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Paul Mundtcad82442006-01-16 22:14:19 -08001menu "Memory management options"
2
Paul Mundt5f8c9902007-05-08 11:55:21 +09003config QUICKLIST
4 def_bool y
5
Paul Mundtcad82442006-01-16 22:14:19 -08006config MMU
7 bool "Support for memory management hardware"
8 depends on !CPU_SH2
9 default y
10 help
11 Some SH processors (such as SH-2/SH-2A) lack an MMU. In order to
12 boot on these systems, this option must not be set.
13
14 On other systems (such as the SH-3 and 4) where an MMU exists,
15 turning this off will boot the kernel on these machines with the
16 MMU implicitly switched off.
17
Paul Mundte7f93a32006-09-27 17:19:13 +090018config PAGE_OFFSET
19 hex
Paul Mundt36763b22007-11-21 15:34:33 +090020 default "0x80000000" if MMU && SUPERH32
21 default "0x20000000" if MMU && SUPERH64
Paul Mundte7f93a32006-09-27 17:19:13 +090022 default "0x00000000"
23
Paul Mundtad3256e2009-05-14 17:40:08 +090024config FORCE_MAX_ZONEORDER
25 int "Maximum zone order"
26 range 9 64 if PAGE_SIZE_16KB
27 default "9" if PAGE_SIZE_16KB
28 range 7 64 if PAGE_SIZE_64KB
29 default "7" if PAGE_SIZE_64KB
30 range 11 64
31 default "14" if !MMU
32 default "11"
33 help
34 The kernel memory allocator divides physically contiguous memory
35 blocks into "zones", where each zone is a power of two number of
36 pages. This option selects the largest power of two that the kernel
37 keeps in the memory allocator. If you need to allocate very large
38 blocks of physically contiguous memory, then you may need to
39 increase this value.
40
41 This config option is actually maximum order plus one. For example,
42 a value of 11 means that the largest free memory block is 2^10 pages.
43
44 The page size is not necessarily 4KB. Keep this in mind when
45 choosing a value for this option.
46
Paul Mundte7f93a32006-09-27 17:19:13 +090047config MEMORY_START
48 hex "Physical memory start address"
49 default "0x08000000"
50 ---help---
51 Computers built with Hitachi SuperH processors always
52 map the ROM starting at address zero. But the processor
53 does not specify the range that RAM takes.
54
55 The physical memory (RAM) start address will be automatically
56 set to 08000000. Other platforms, such as the Solution Engine
57 boards typically map RAM at 0C000000.
58
59 Tweak this only when porting to a new machine which does not
60 already have a defconfig. Changing it from the known correct
61 value on any of the known systems will only lead to disaster.
62
63config MEMORY_SIZE
64 hex "Physical memory size"
Paul Mundt711fe432007-11-21 15:46:07 +090065 default "0x04000000"
Paul Mundte7f93a32006-09-27 17:19:13 +090066 help
67 This sets the default memory size assumed by your SH kernel. It can
68 be overridden as normal by the 'mem=' argument on the kernel command
69 line. If unsure, consult your board specifications or just leave it
Paul Mundt711fe432007-11-21 15:46:07 +090070 as 0x04000000 which was the default value before this became
Paul Mundte7f93a32006-09-27 17:19:13 +090071 configurable.
72
Paul Mundt36bcd392007-11-10 19:16:55 +090073# Physical addressing modes
74
75config 29BIT
76 def_bool !32BIT
77 depends on SUPERH32
Paul Mundtb0f3ae02010-02-12 15:40:00 +090078 select UNCACHED_MAPPING
Paul Mundt36bcd392007-11-10 19:16:55 +090079
Paul Mundtcad82442006-01-16 22:14:19 -080080config 32BIT
Paul Mundt36bcd392007-11-10 19:16:55 +090081 bool
82 default y if CPU_SH5
83
Paul Mundta0ab3662010-01-13 18:31:48 +090084config PMB
Paul Mundtcad82442006-01-16 22:14:19 -080085 bool "Support 32-bit physical addressing through PMB"
Paul Mundtb4e2a2a2010-01-04 11:13:54 +090086 depends on MMU && EXPERIMENTAL && CPU_SH4A && !CPU_SH4AL_DSP
Paul Mundta0ab3662010-01-13 18:31:48 +090087 select 32BIT
Paul Mundtb0f3ae02010-02-12 15:40:00 +090088 select UNCACHED_MAPPING
Paul Mundtcad82442006-01-16 22:14:19 -080089 help
90 If you say Y here, physical addressing will be extended to
91 32-bits through the SH-4A PMB. If this is not set, legacy
92 29-bit physical addressing will be used.
93
Paul Mundt21440cf2006-11-20 14:30:26 +090094config X2TLB
Paul Mundt782bb5a2010-01-13 19:11:14 +090095 def_bool y
96 depends on (CPU_SHX2 || CPU_SHX3) && MMU
Paul Mundt21440cf2006-11-20 14:30:26 +090097
Paul Mundt19f9a342006-09-27 18:33:49 +090098config VSYSCALL
99 bool "Support vsyscall page"
Paul Mundta09063d2007-11-08 18:54:16 +0900100 depends on MMU && (CPU_SH3 || CPU_SH4)
Paul Mundt19f9a342006-09-27 18:33:49 +0900101 default y
102 help
103 This will enable support for the kernel mapping a vDSO page
104 in process space, and subsequently handing down the entry point
105 to the libc through the ELF auxiliary vector.
106
107 From the kernel side this is used for the signal trampoline.
108 For systems with an MMU that can afford to give up a page,
109 (the default value) say Y.
110
Paul Mundtb241cb02007-06-06 17:52:19 +0900111config NUMA
112 bool "Non Uniform Memory Access (NUMA) Support"
Paul Mundt357d5942007-06-11 15:32:07 +0900113 depends on MMU && SYS_SUPPORTS_NUMA && EXPERIMENTAL
Paul Mundtb241cb02007-06-06 17:52:19 +0900114 default n
115 help
116 Some SH systems have many various memories scattered around
117 the address space, each with varying latencies. This enables
118 support for these blocks by binding them to nodes and allowing
119 memory policies to be used for prioritizing and controlling
120 allocation behaviour.
121
Paul Mundt01066622007-03-28 16:38:13 +0900122config NODES_SHIFT
123 int
Paul Mundt99044942007-08-08 16:45:07 +0900124 default "3" if CPU_SUBTYPE_SHX3
Paul Mundt01066622007-03-28 16:38:13 +0900125 default "1"
126 depends on NEED_MULTIPLE_NODES
127
128config ARCH_FLATMEM_ENABLE
129 def_bool y
Paul Mundt357d5942007-06-11 15:32:07 +0900130 depends on !NUMA
Paul Mundt01066622007-03-28 16:38:13 +0900131
Paul Mundtdfbb9042007-05-23 17:48:36 +0900132config ARCH_SPARSEMEM_ENABLE
133 def_bool y
134 select SPARSEMEM_STATIC
135
136config ARCH_SPARSEMEM_DEFAULT
137 def_bool y
138
Paul Mundt1ce7ddd2007-05-09 13:20:52 +0900139config MAX_ACTIVE_REGIONS
140 int
Paul Mundt7da3b8e2007-08-01 17:52:47 +0900141 default "6" if (CPU_SUBTYPE_SHX3 && SPARSEMEM)
Paul Mundtdc47e9d2007-09-27 16:48:00 +0900142 default "2" if SPARSEMEM && (CPU_SUBTYPE_SH7722 || \
143 CPU_SUBTYPE_SH7785)
Paul Mundt1ce7ddd2007-05-09 13:20:52 +0900144 default "1"
145
Paul Mundt01066622007-03-28 16:38:13 +0900146config ARCH_POPULATES_NODE_MAP
147 def_bool y
148
Paul Mundtdfbb9042007-05-23 17:48:36 +0900149config ARCH_SELECT_MEMORY_MODEL
150 def_bool y
151
Paul Mundt33d63bd2007-06-07 11:32:52 +0900152config ARCH_ENABLE_MEMORY_HOTPLUG
153 def_bool y
Paul Mundtb85641b2008-09-17 23:13:27 +0900154 depends on SPARSEMEM && MMU
Paul Mundt33d63bd2007-06-07 11:32:52 +0900155
Paul Mundt3159e7d2008-09-05 15:39:12 +0900156config ARCH_ENABLE_MEMORY_HOTREMOVE
157 def_bool y
Paul Mundtb85641b2008-09-17 23:13:27 +0900158 depends on SPARSEMEM && MMU
Paul Mundt3159e7d2008-09-05 15:39:12 +0900159
Paul Mundt33d63bd2007-06-07 11:32:52 +0900160config ARCH_MEMORY_PROBE
161 def_bool y
162 depends on MEMORY_HOTPLUG
163
Matt Fleming4d35b932009-11-05 07:54:17 +0000164config IOREMAP_FIXED
165 def_bool y
166 depends on X2TLB || SUPERH64
167
Paul Mundtb0f3ae02010-02-12 15:40:00 +0900168config UNCACHED_MAPPING
169 bool
170
Paul Mundtc9934872010-10-15 02:09:00 +0900171config HAVE_SRAM_POOL
172 bool
173 select GENERIC_ALLOCATOR
174
Paul Mundtcad82442006-01-16 22:14:19 -0800175choice
Paul Mundt21440cf2006-11-20 14:30:26 +0900176 prompt "Kernel page size"
177 default PAGE_SIZE_4KB
178
179config PAGE_SIZE_4KB
180 bool "4kB"
181 help
182 This is the default page size used by all SuperH CPUs.
183
184config PAGE_SIZE_8KB
185 bool "8kB"
Matt Fleming3f5ab762009-12-24 20:38:45 +0000186 depends on !MMU || X2TLB
Paul Mundt21440cf2006-11-20 14:30:26 +0900187 help
188 This enables 8kB pages as supported by SH-X2 and later MMUs.
189
Paul Mundt66dfe182008-06-03 18:54:02 +0900190config PAGE_SIZE_16KB
191 bool "16kB"
192 depends on !MMU
193 help
194 This enables 16kB pages on MMU-less SH systems.
195
Paul Mundt21440cf2006-11-20 14:30:26 +0900196config PAGE_SIZE_64KB
197 bool "64kB"
Matt Fleming3f5ab762009-12-24 20:38:45 +0000198 depends on !MMU || CPU_SH4 || CPU_SH5
Paul Mundt21440cf2006-11-20 14:30:26 +0900199 help
200 This enables support for 64kB pages, possible on all SH-4
Paul Mundt4d2cab72007-09-27 10:47:00 +0900201 CPUs and later.
Paul Mundt21440cf2006-11-20 14:30:26 +0900202
203endchoice
204
205choice
Paul Mundtcad82442006-01-16 22:14:19 -0800206 prompt "HugeTLB page size"
Paul Mundtffb4a732009-10-27 07:22:37 +0900207 depends on HUGETLB_PAGE
Paul Mundt68b7c242008-08-06 15:10:49 +0900208 default HUGETLB_PAGE_SIZE_1MB if PAGE_SIZE_64KB
Paul Mundtcad82442006-01-16 22:14:19 -0800209 default HUGETLB_PAGE_SIZE_64K
210
211config HUGETLB_PAGE_SIZE_64K
Paul Mundt21440cf2006-11-20 14:30:26 +0900212 bool "64kB"
Paul Mundt68b7c242008-08-06 15:10:49 +0900213 depends on !PAGE_SIZE_64KB
Paul Mundt21440cf2006-11-20 14:30:26 +0900214
215config HUGETLB_PAGE_SIZE_256K
216 bool "256kB"
217 depends on X2TLB
Paul Mundtcad82442006-01-16 22:14:19 -0800218
219config HUGETLB_PAGE_SIZE_1MB
220 bool "1MB"
221
Paul Mundt21440cf2006-11-20 14:30:26 +0900222config HUGETLB_PAGE_SIZE_4MB
223 bool "4MB"
224 depends on X2TLB
225
226config HUGETLB_PAGE_SIZE_64MB
227 bool "64MB"
228 depends on X2TLB
229
Paul Mundta09063d2007-11-08 18:54:16 +0900230config HUGETLB_PAGE_SIZE_512MB
231 bool "512MB"
232 depends on CPU_SH5
233
Paul Mundtcad82442006-01-16 22:14:19 -0800234endchoice
235
236source "mm/Kconfig"
237
Paul Mundt896f0c02009-10-16 18:00:02 +0900238config SCHED_MC
239 bool "Multi-core scheduler support"
240 depends on SMP
241 default y
242 help
243 Multi-core scheduler support improves the CPU scheduler's decision
244 making when dealing with multi-core CPU chips at a cost of slightly
245 increased overhead in some places. If unsure say N here.
246
Paul Mundtcad82442006-01-16 22:14:19 -0800247endmenu
248
249menu "Cache configuration"
250
251config SH7705_CACHE_32KB
252 bool "Enable 32KB cache size for SH7705"
253 depends on CPU_SUBTYPE_SH7705
254 default y
255
Paul Mundte7bd34a2007-07-31 17:07:28 +0900256choice
257 prompt "Cache mode"
Paul Mundta09063d2007-11-08 18:54:16 +0900258 default CACHE_WRITEBACK if CPU_SH2A || CPU_SH3 || CPU_SH4 || CPU_SH5
Paul Mundte7bd34a2007-07-31 17:07:28 +0900259 default CACHE_WRITETHROUGH if (CPU_SH2 && !CPU_SH2A)
260
261config CACHE_WRITEBACK
262 bool "Write-back"
Paul Mundte7bd34a2007-07-31 17:07:28 +0900263
264config CACHE_WRITETHROUGH
265 bool "Write-through"
Paul Mundtcad82442006-01-16 22:14:19 -0800266 help
267 Selecting this option will configure the caches in write-through
268 mode, as opposed to the default write-back configuration.
269
270 Since there's sill some aliasing issues on SH-4, this option will
271 unfortunately still require the majority of flushing functions to
272 be implemented to deal with aliasing.
273
274 If unsure, say N.
275
Paul Mundte7bd34a2007-07-31 17:07:28 +0900276config CACHE_OFF
277 bool "Off"
278
279endchoice
280
Paul Mundtcad82442006-01-16 22:14:19 -0800281endmenu