David S. Miller | 453e93b | 2007-05-06 22:45:08 -0700 | [diff] [blame] | 1 | /* sunxvr500.c: Sun 3DLABS XVR-500 Expert3D driver for sparc64 systems |
| 2 | * |
| 3 | * Copyright (C) 2007 David S. Miller (davem@davemloft.net) |
| 4 | */ |
| 5 | |
| 6 | #include <linux/module.h> |
| 7 | #include <linux/kernel.h> |
| 8 | #include <linux/slab.h> |
| 9 | #include <linux/fb.h> |
| 10 | #include <linux/pci.h> |
| 11 | #include <linux/init.h> |
Robert Reif | 6cd5a86 | 2008-05-08 21:37:30 -0700 | [diff] [blame] | 12 | #include <linux/of_device.h> |
David S. Miller | 453e93b | 2007-05-06 22:45:08 -0700 | [diff] [blame] | 13 | |
| 14 | #include <asm/io.h> |
David S. Miller | 453e93b | 2007-05-06 22:45:08 -0700 | [diff] [blame] | 15 | |
| 16 | /* XXX This device has a 'dev-comm' property which aparently is |
| 17 | * XXX a pointer into the openfirmware's address space which is |
| 18 | * XXX a shared area the kernel driver can use to keep OBP |
| 19 | * XXX informed about the current resolution setting. The idea |
| 20 | * XXX is that the kernel can change resolutions, and as long |
| 21 | * XXX as the values in the 'dev-comm' area are accurate then |
| 22 | * XXX OBP can still render text properly to the console. |
| 23 | * XXX |
| 24 | * XXX I'm still working out the layout of this and whether there |
| 25 | * XXX are any signatures we need to look for etc. |
| 26 | */ |
| 27 | struct e3d_info { |
| 28 | struct fb_info *info; |
| 29 | struct pci_dev *pdev; |
| 30 | |
| 31 | spinlock_t lock; |
| 32 | |
| 33 | char __iomem *fb_base; |
| 34 | unsigned long fb_base_phys; |
| 35 | |
| 36 | unsigned long fb8_buf_diff; |
| 37 | unsigned long regs_base_phys; |
| 38 | |
| 39 | void __iomem *ramdac; |
| 40 | |
| 41 | struct device_node *of_node; |
| 42 | |
| 43 | unsigned int width; |
| 44 | unsigned int height; |
| 45 | unsigned int depth; |
| 46 | unsigned int fb_size; |
| 47 | |
| 48 | u32 fb_base_reg; |
| 49 | u32 fb8_0_off; |
| 50 | u32 fb8_1_off; |
| 51 | |
Antonino Daplas | e7e8cc5 | 2007-06-05 13:15:26 -0700 | [diff] [blame] | 52 | u32 pseudo_palette[16]; |
David S. Miller | 453e93b | 2007-05-06 22:45:08 -0700 | [diff] [blame] | 53 | }; |
| 54 | |
| 55 | static int __devinit e3d_get_props(struct e3d_info *ep) |
| 56 | { |
| 57 | ep->width = of_getintprop_default(ep->of_node, "width", 0); |
| 58 | ep->height = of_getintprop_default(ep->of_node, "height", 0); |
| 59 | ep->depth = of_getintprop_default(ep->of_node, "depth", 8); |
| 60 | |
| 61 | if (!ep->width || !ep->height) { |
| 62 | printk(KERN_ERR "e3d: Critical properties missing for %s\n", |
| 63 | pci_name(ep->pdev)); |
| 64 | return -EINVAL; |
| 65 | } |
| 66 | |
| 67 | return 0; |
| 68 | } |
| 69 | |
| 70 | /* My XVR-500 comes up, at 1280x768 and a FB base register value of |
| 71 | * 0x04000000, the following video layout register values: |
| 72 | * |
| 73 | * RAMDAC_VID_WH 0x03ff04ff |
| 74 | * RAMDAC_VID_CFG 0x1a0b0088 |
| 75 | * RAMDAC_VID_32FB_0 0x04000000 |
| 76 | * RAMDAC_VID_32FB_1 0x04800000 |
| 77 | * RAMDAC_VID_8FB_0 0x05000000 |
| 78 | * RAMDAC_VID_8FB_1 0x05200000 |
| 79 | * RAMDAC_VID_XXXFB 0x05400000 |
| 80 | * RAMDAC_VID_YYYFB 0x05c00000 |
| 81 | * RAMDAC_VID_ZZZFB 0x05e00000 |
| 82 | */ |
| 83 | /* Video layout registers */ |
| 84 | #define RAMDAC_VID_WH 0x00000070UL /* (height-1)<<16 | (width-1) */ |
| 85 | #define RAMDAC_VID_CFG 0x00000074UL /* 0x1a000088|(linesz_log2<<16) */ |
| 86 | #define RAMDAC_VID_32FB_0 0x00000078UL /* PCI base 32bpp FB buffer 0 */ |
| 87 | #define RAMDAC_VID_32FB_1 0x0000007cUL /* PCI base 32bpp FB buffer 1 */ |
| 88 | #define RAMDAC_VID_8FB_0 0x00000080UL /* PCI base 8bpp FB buffer 0 */ |
| 89 | #define RAMDAC_VID_8FB_1 0x00000084UL /* PCI base 8bpp FB buffer 1 */ |
| 90 | #define RAMDAC_VID_XXXFB 0x00000088UL /* PCI base of XXX FB */ |
| 91 | #define RAMDAC_VID_YYYFB 0x0000008cUL /* PCI base of YYY FB */ |
| 92 | #define RAMDAC_VID_ZZZFB 0x00000090UL /* PCI base of ZZZ FB */ |
| 93 | |
| 94 | /* CLUT registers */ |
| 95 | #define RAMDAC_INDEX 0x000000bcUL |
| 96 | #define RAMDAC_DATA 0x000000c0UL |
| 97 | |
| 98 | static void e3d_clut_write(struct e3d_info *ep, int index, u32 val) |
| 99 | { |
| 100 | void __iomem *ramdac = ep->ramdac; |
| 101 | unsigned long flags; |
| 102 | |
| 103 | spin_lock_irqsave(&ep->lock, flags); |
| 104 | |
| 105 | writel(index, ramdac + RAMDAC_INDEX); |
| 106 | writel(val, ramdac + RAMDAC_DATA); |
| 107 | |
| 108 | spin_unlock_irqrestore(&ep->lock, flags); |
| 109 | } |
| 110 | |
| 111 | static int e3d_setcolreg(unsigned regno, |
| 112 | unsigned red, unsigned green, unsigned blue, |
| 113 | unsigned transp, struct fb_info *info) |
| 114 | { |
| 115 | struct e3d_info *ep = info->par; |
| 116 | u32 red_8, green_8, blue_8; |
| 117 | u32 red_10, green_10, blue_10; |
| 118 | u32 value; |
| 119 | |
| 120 | if (regno >= 256) |
| 121 | return 1; |
| 122 | |
| 123 | red_8 = red >> 8; |
| 124 | green_8 = green >> 8; |
| 125 | blue_8 = blue >> 8; |
| 126 | |
| 127 | value = (blue_8 << 24) | (green_8 << 16) | (red_8 << 8); |
Antonino Daplas | e7e8cc5 | 2007-06-05 13:15:26 -0700 | [diff] [blame] | 128 | |
| 129 | if (info->fix.visual == FB_VISUAL_TRUECOLOR && regno < 16) |
| 130 | ((u32 *)info->pseudo_palette)[regno] = value; |
David S. Miller | 453e93b | 2007-05-06 22:45:08 -0700 | [diff] [blame] | 131 | |
| 132 | |
| 133 | red_10 = red >> 6; |
| 134 | green_10 = green >> 6; |
| 135 | blue_10 = blue >> 6; |
| 136 | |
| 137 | value = (blue_10 << 20) | (green_10 << 10) | (red_10 << 0); |
| 138 | e3d_clut_write(ep, regno, value); |
| 139 | |
| 140 | return 0; |
| 141 | } |
| 142 | |
| 143 | /* XXX This is a bit of a hack. I can't figure out exactly how the |
| 144 | * XXX two 8bpp areas of the framebuffer work. I imagine there is |
| 145 | * XXX a WID attribute somewhere else in the framebuffer which tells |
| 146 | * XXX the ramdac which of the two 8bpp framebuffer regions to take |
| 147 | * XXX the pixel from. So, for now, render into both regions to make |
| 148 | * XXX sure the pixel shows up. |
| 149 | */ |
| 150 | static void e3d_imageblit(struct fb_info *info, const struct fb_image *image) |
| 151 | { |
| 152 | struct e3d_info *ep = info->par; |
| 153 | unsigned long flags; |
| 154 | |
| 155 | spin_lock_irqsave(&ep->lock, flags); |
| 156 | cfb_imageblit(info, image); |
| 157 | info->screen_base += ep->fb8_buf_diff; |
| 158 | cfb_imageblit(info, image); |
| 159 | info->screen_base -= ep->fb8_buf_diff; |
| 160 | spin_unlock_irqrestore(&ep->lock, flags); |
| 161 | } |
| 162 | |
| 163 | static void e3d_fillrect(struct fb_info *info, const struct fb_fillrect *rect) |
| 164 | { |
| 165 | struct e3d_info *ep = info->par; |
| 166 | unsigned long flags; |
| 167 | |
| 168 | spin_lock_irqsave(&ep->lock, flags); |
| 169 | cfb_fillrect(info, rect); |
| 170 | info->screen_base += ep->fb8_buf_diff; |
| 171 | cfb_fillrect(info, rect); |
| 172 | info->screen_base -= ep->fb8_buf_diff; |
| 173 | spin_unlock_irqrestore(&ep->lock, flags); |
| 174 | } |
| 175 | |
| 176 | static void e3d_copyarea(struct fb_info *info, const struct fb_copyarea *area) |
| 177 | { |
| 178 | struct e3d_info *ep = info->par; |
| 179 | unsigned long flags; |
| 180 | |
| 181 | spin_lock_irqsave(&ep->lock, flags); |
| 182 | cfb_copyarea(info, area); |
| 183 | info->screen_base += ep->fb8_buf_diff; |
| 184 | cfb_copyarea(info, area); |
| 185 | info->screen_base -= ep->fb8_buf_diff; |
| 186 | spin_unlock_irqrestore(&ep->lock, flags); |
| 187 | } |
| 188 | |
| 189 | static struct fb_ops e3d_ops = { |
| 190 | .owner = THIS_MODULE, |
| 191 | .fb_setcolreg = e3d_setcolreg, |
| 192 | .fb_fillrect = e3d_fillrect, |
| 193 | .fb_copyarea = e3d_copyarea, |
| 194 | .fb_imageblit = e3d_imageblit, |
| 195 | }; |
| 196 | |
| 197 | static int __devinit e3d_set_fbinfo(struct e3d_info *ep) |
| 198 | { |
| 199 | struct fb_info *info = ep->info; |
| 200 | struct fb_var_screeninfo *var = &info->var; |
| 201 | |
| 202 | info->flags = FBINFO_DEFAULT; |
| 203 | info->fbops = &e3d_ops; |
| 204 | info->screen_base = ep->fb_base; |
| 205 | info->screen_size = ep->fb_size; |
| 206 | |
| 207 | info->pseudo_palette = ep->pseudo_palette; |
| 208 | |
| 209 | /* Fill fix common fields */ |
| 210 | strlcpy(info->fix.id, "e3d", sizeof(info->fix.id)); |
| 211 | info->fix.smem_start = ep->fb_base_phys; |
| 212 | info->fix.smem_len = ep->fb_size; |
| 213 | info->fix.type = FB_TYPE_PACKED_PIXELS; |
| 214 | if (ep->depth == 32 || ep->depth == 24) |
| 215 | info->fix.visual = FB_VISUAL_TRUECOLOR; |
| 216 | else |
| 217 | info->fix.visual = FB_VISUAL_PSEUDOCOLOR; |
| 218 | |
| 219 | var->xres = ep->width; |
| 220 | var->yres = ep->height; |
| 221 | var->xres_virtual = var->xres; |
| 222 | var->yres_virtual = var->yres; |
| 223 | var->bits_per_pixel = ep->depth; |
| 224 | |
| 225 | var->red.offset = 8; |
| 226 | var->red.length = 8; |
| 227 | var->green.offset = 16; |
| 228 | var->green.length = 8; |
| 229 | var->blue.offset = 24; |
| 230 | var->blue.length = 8; |
| 231 | var->transp.offset = 0; |
| 232 | var->transp.length = 0; |
| 233 | |
| 234 | if (fb_alloc_cmap(&info->cmap, 256, 0)) { |
| 235 | printk(KERN_ERR "e3d: Cannot allocate color map.\n"); |
| 236 | return -ENOMEM; |
| 237 | } |
| 238 | |
| 239 | return 0; |
| 240 | } |
| 241 | |
| 242 | static int __devinit e3d_pci_register(struct pci_dev *pdev, |
| 243 | const struct pci_device_id *ent) |
| 244 | { |
| 245 | struct fb_info *info; |
| 246 | struct e3d_info *ep; |
| 247 | unsigned int line_length; |
| 248 | int err; |
| 249 | |
| 250 | err = pci_enable_device(pdev); |
| 251 | if (err < 0) { |
| 252 | printk(KERN_ERR "e3d: Cannot enable PCI device %s\n", |
| 253 | pci_name(pdev)); |
| 254 | goto err_out; |
| 255 | } |
| 256 | |
| 257 | info = framebuffer_alloc(sizeof(struct e3d_info), &pdev->dev); |
| 258 | if (!info) { |
| 259 | printk(KERN_ERR "e3d: Cannot allocate fb_info\n"); |
| 260 | err = -ENOMEM; |
| 261 | goto err_disable; |
| 262 | } |
| 263 | |
| 264 | ep = info->par; |
| 265 | ep->info = info; |
| 266 | ep->pdev = pdev; |
| 267 | spin_lock_init(&ep->lock); |
| 268 | ep->of_node = pci_device_to_OF_node(pdev); |
| 269 | if (!ep->of_node) { |
| 270 | printk(KERN_ERR "e3d: Cannot find OF node of %s\n", |
| 271 | pci_name(pdev)); |
| 272 | err = -ENODEV; |
| 273 | goto err_release_fb; |
| 274 | } |
| 275 | |
| 276 | /* Read the PCI base register of the frame buffer, which we |
| 277 | * need in order to interpret the RAMDAC_VID_*FB* values in |
| 278 | * the ramdac correctly. |
| 279 | */ |
| 280 | pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0, |
| 281 | &ep->fb_base_reg); |
| 282 | ep->fb_base_reg &= PCI_BASE_ADDRESS_MEM_MASK; |
| 283 | |
| 284 | ep->regs_base_phys = pci_resource_start (pdev, 1); |
| 285 | err = pci_request_region(pdev, 1, "e3d regs"); |
| 286 | if (err < 0) { |
| 287 | printk("e3d: Cannot request region 1 for %s\n", |
| 288 | pci_name(pdev)); |
| 289 | goto err_release_fb; |
| 290 | } |
| 291 | ep->ramdac = ioremap(ep->regs_base_phys + 0x8000, 0x1000); |
| 292 | if (!ep->ramdac) |
| 293 | goto err_release_pci1; |
| 294 | |
| 295 | ep->fb8_0_off = readl(ep->ramdac + RAMDAC_VID_8FB_0); |
| 296 | ep->fb8_0_off -= ep->fb_base_reg; |
| 297 | |
| 298 | ep->fb8_1_off = readl(ep->ramdac + RAMDAC_VID_8FB_1); |
| 299 | ep->fb8_1_off -= ep->fb_base_reg; |
| 300 | |
| 301 | ep->fb8_buf_diff = ep->fb8_1_off - ep->fb8_0_off; |
| 302 | |
| 303 | ep->fb_base_phys = pci_resource_start (pdev, 0); |
| 304 | ep->fb_base_phys += ep->fb8_0_off; |
| 305 | |
| 306 | err = pci_request_region(pdev, 0, "e3d framebuffer"); |
| 307 | if (err < 0) { |
| 308 | printk("e3d: Cannot request region 0 for %s\n", |
| 309 | pci_name(pdev)); |
| 310 | goto err_unmap_ramdac; |
| 311 | } |
| 312 | |
| 313 | err = e3d_get_props(ep); |
| 314 | if (err) |
| 315 | goto err_release_pci0; |
| 316 | |
| 317 | line_length = (readl(ep->ramdac + RAMDAC_VID_CFG) >> 16) & 0xff; |
| 318 | line_length = 1 << line_length; |
| 319 | |
| 320 | switch (ep->depth) { |
| 321 | case 8: |
| 322 | info->fix.line_length = line_length; |
| 323 | break; |
| 324 | case 16: |
| 325 | info->fix.line_length = line_length * 2; |
| 326 | break; |
| 327 | case 24: |
| 328 | info->fix.line_length = line_length * 3; |
| 329 | break; |
| 330 | case 32: |
| 331 | info->fix.line_length = line_length * 4; |
| 332 | break; |
| 333 | } |
| 334 | ep->fb_size = info->fix.line_length * ep->height; |
| 335 | |
| 336 | ep->fb_base = ioremap(ep->fb_base_phys, ep->fb_size); |
| 337 | if (!ep->fb_base) |
| 338 | goto err_release_pci0; |
| 339 | |
| 340 | err = e3d_set_fbinfo(ep); |
| 341 | if (err) |
| 342 | goto err_unmap_fb; |
| 343 | |
| 344 | pci_set_drvdata(pdev, info); |
| 345 | |
| 346 | printk("e3d: Found device at %s\n", pci_name(pdev)); |
| 347 | |
| 348 | err = register_framebuffer(info); |
| 349 | if (err < 0) { |
| 350 | printk(KERN_ERR "e3d: Could not register framebuffer %s\n", |
| 351 | pci_name(pdev)); |
Andres Salomon | cc880a7 | 2009-03-31 15:25:27 -0700 | [diff] [blame^] | 352 | goto err_free_cmap; |
David S. Miller | 453e93b | 2007-05-06 22:45:08 -0700 | [diff] [blame] | 353 | } |
| 354 | |
| 355 | return 0; |
| 356 | |
Andres Salomon | cc880a7 | 2009-03-31 15:25:27 -0700 | [diff] [blame^] | 357 | err_free_cmap: |
| 358 | fb_dealloc_cmap(&info->cmap); |
| 359 | |
David S. Miller | 453e93b | 2007-05-06 22:45:08 -0700 | [diff] [blame] | 360 | err_unmap_fb: |
| 361 | iounmap(ep->fb_base); |
| 362 | |
| 363 | err_release_pci0: |
| 364 | pci_release_region(pdev, 0); |
| 365 | |
| 366 | err_unmap_ramdac: |
| 367 | iounmap(ep->ramdac); |
| 368 | |
| 369 | err_release_pci1: |
| 370 | pci_release_region(pdev, 1); |
| 371 | |
| 372 | err_release_fb: |
| 373 | framebuffer_release(info); |
| 374 | |
| 375 | err_disable: |
| 376 | pci_disable_device(pdev); |
| 377 | |
| 378 | err_out: |
| 379 | return err; |
| 380 | } |
| 381 | |
| 382 | static void __devexit e3d_pci_unregister(struct pci_dev *pdev) |
| 383 | { |
| 384 | struct fb_info *info = pci_get_drvdata(pdev); |
| 385 | struct e3d_info *ep = info->par; |
| 386 | |
| 387 | unregister_framebuffer(info); |
| 388 | |
| 389 | iounmap(ep->ramdac); |
| 390 | iounmap(ep->fb_base); |
| 391 | |
| 392 | pci_release_region(pdev, 0); |
| 393 | pci_release_region(pdev, 1); |
| 394 | |
Andres Salomon | cc880a7 | 2009-03-31 15:25:27 -0700 | [diff] [blame^] | 395 | fb_dealloc_cmap(&info->cmap); |
David S. Miller | 453e93b | 2007-05-06 22:45:08 -0700 | [diff] [blame] | 396 | framebuffer_release(info); |
| 397 | |
| 398 | pci_disable_device(pdev); |
| 399 | } |
| 400 | |
| 401 | static struct pci_device_id e3d_pci_table[] = { |
| 402 | { PCI_DEVICE(PCI_VENDOR_ID_3DLABS, 0x7a0), }, |
| 403 | { PCI_DEVICE(PCI_VENDOR_ID_3DLABS, 0x7a2), }, |
| 404 | { .vendor = PCI_VENDOR_ID_3DLABS, |
| 405 | .device = PCI_ANY_ID, |
| 406 | .subvendor = PCI_VENDOR_ID_3DLABS, |
| 407 | .subdevice = 0x0108, |
| 408 | }, |
| 409 | { .vendor = PCI_VENDOR_ID_3DLABS, |
| 410 | .device = PCI_ANY_ID, |
| 411 | .subvendor = PCI_VENDOR_ID_3DLABS, |
| 412 | .subdevice = 0x0140, |
| 413 | }, |
| 414 | { .vendor = PCI_VENDOR_ID_3DLABS, |
| 415 | .device = PCI_ANY_ID, |
| 416 | .subvendor = PCI_VENDOR_ID_3DLABS, |
| 417 | .subdevice = 0x1024, |
| 418 | }, |
| 419 | { 0, } |
| 420 | }; |
| 421 | |
| 422 | static struct pci_driver e3d_driver = { |
| 423 | .name = "e3d", |
| 424 | .id_table = e3d_pci_table, |
| 425 | .probe = e3d_pci_register, |
| 426 | .remove = __devexit_p(e3d_pci_unregister), |
| 427 | }; |
| 428 | |
| 429 | static int __init e3d_init(void) |
| 430 | { |
| 431 | if (fb_get_options("e3d", NULL)) |
| 432 | return -ENODEV; |
| 433 | |
| 434 | return pci_register_driver(&e3d_driver); |
| 435 | } |
| 436 | |
| 437 | static void __exit e3d_exit(void) |
| 438 | { |
| 439 | pci_unregister_driver(&e3d_driver); |
| 440 | } |
| 441 | |
| 442 | module_init(e3d_init); |
| 443 | module_exit(e3d_exit); |
| 444 | |
| 445 | MODULE_DESCRIPTION("framebuffer driver for Sun XVR-500 graphics"); |
| 446 | MODULE_AUTHOR("David S. Miller <davem@davemloft.net>"); |
| 447 | MODULE_VERSION("1.0"); |
| 448 | MODULE_LICENSE("GPL"); |