Yong Shen | 5e428d5 | 2010-12-14 14:00:55 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Regulator Driver for Freescale MC13892 PMIC |
| 3 | * |
| 4 | * Copyright 2010 Yong Shen <yong.shen@linaro.org> |
| 5 | * |
| 6 | * Based on draft driver from Arnaud Patard <arnaud.patard@rtp-net.org> |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License version 2 as |
| 10 | * published by the Free Software Foundation. |
| 11 | */ |
| 12 | |
| 13 | #include <linux/mfd/mc13892.h> |
| 14 | #include <linux/regulator/machine.h> |
| 15 | #include <linux/regulator/driver.h> |
| 16 | #include <linux/platform_device.h> |
| 17 | #include <linux/kernel.h> |
| 18 | #include <linux/slab.h> |
| 19 | #include <linux/init.h> |
| 20 | #include <linux/err.h> |
Paul Gortmaker | 65602c3 | 2011-07-17 16:28:23 -0400 | [diff] [blame] | 21 | #include <linux/module.h> |
Yong Shen | 5e428d5 | 2010-12-14 14:00:55 +0800 | [diff] [blame] | 22 | #include "mc13xxx.h" |
| 23 | |
| 24 | #define MC13892_REVISION 7 |
| 25 | |
| 26 | #define MC13892_POWERCTL0 13 |
| 27 | #define MC13892_POWERCTL0_USEROFFSPI 3 |
| 28 | #define MC13892_POWERCTL0_VCOINCELLVSEL 20 |
| 29 | #define MC13892_POWERCTL0_VCOINCELLVSEL_M (7<<20) |
| 30 | #define MC13892_POWERCTL0_VCOINCELLEN (1<<23) |
| 31 | |
| 32 | #define MC13892_SWITCHERS0_SWxHI (1<<23) |
| 33 | |
| 34 | #define MC13892_SWITCHERS0 24 |
| 35 | #define MC13892_SWITCHERS0_SW1VSEL 0 |
| 36 | #define MC13892_SWITCHERS0_SW1VSEL_M (0x1f<<0) |
| 37 | #define MC13892_SWITCHERS0_SW1HI (1<<23) |
| 38 | #define MC13892_SWITCHERS0_SW1EN 0 |
| 39 | |
| 40 | #define MC13892_SWITCHERS1 25 |
| 41 | #define MC13892_SWITCHERS1_SW2VSEL 0 |
| 42 | #define MC13892_SWITCHERS1_SW2VSEL_M (0x1f<<0) |
| 43 | #define MC13892_SWITCHERS1_SW2HI (1<<23) |
| 44 | #define MC13892_SWITCHERS1_SW2EN 0 |
| 45 | |
| 46 | #define MC13892_SWITCHERS2 26 |
| 47 | #define MC13892_SWITCHERS2_SW3VSEL 0 |
| 48 | #define MC13892_SWITCHERS2_SW3VSEL_M (0x1f<<0) |
| 49 | #define MC13892_SWITCHERS2_SW3HI (1<<23) |
| 50 | #define MC13892_SWITCHERS2_SW3EN 0 |
| 51 | |
| 52 | #define MC13892_SWITCHERS3 27 |
| 53 | #define MC13892_SWITCHERS3_SW4VSEL 0 |
| 54 | #define MC13892_SWITCHERS3_SW4VSEL_M (0x1f<<0) |
| 55 | #define MC13892_SWITCHERS3_SW4HI (1<<23) |
| 56 | #define MC13892_SWITCHERS3_SW4EN 0 |
| 57 | |
| 58 | #define MC13892_SWITCHERS4 28 |
| 59 | #define MC13892_SWITCHERS4_SW1MODE 0 |
| 60 | #define MC13892_SWITCHERS4_SW1MODE_AUTO (8<<0) |
| 61 | #define MC13892_SWITCHERS4_SW1MODE_M (0xf<<0) |
| 62 | #define MC13892_SWITCHERS4_SW2MODE 10 |
| 63 | #define MC13892_SWITCHERS4_SW2MODE_AUTO (8<<10) |
| 64 | #define MC13892_SWITCHERS4_SW2MODE_M (0xf<<10) |
| 65 | |
| 66 | #define MC13892_SWITCHERS5 29 |
| 67 | #define MC13892_SWITCHERS5_SW3MODE 0 |
| 68 | #define MC13892_SWITCHERS5_SW3MODE_AUTO (8<<0) |
| 69 | #define MC13892_SWITCHERS5_SW3MODE_M (0xf<<0) |
| 70 | #define MC13892_SWITCHERS5_SW4MODE 8 |
| 71 | #define MC13892_SWITCHERS5_SW4MODE_AUTO (8<<8) |
| 72 | #define MC13892_SWITCHERS5_SW4MODE_M (0xf<<8) |
| 73 | #define MC13892_SWITCHERS5_SWBSTEN (1<<20) |
| 74 | |
| 75 | #define MC13892_REGULATORSETTING0 30 |
| 76 | #define MC13892_REGULATORSETTING0_VGEN1VSEL 0 |
| 77 | #define MC13892_REGULATORSETTING0_VDIGVSEL 4 |
| 78 | #define MC13892_REGULATORSETTING0_VGEN2VSEL 6 |
| 79 | #define MC13892_REGULATORSETTING0_VPLLVSEL 9 |
| 80 | #define MC13892_REGULATORSETTING0_VUSB2VSEL 11 |
| 81 | #define MC13892_REGULATORSETTING0_VGEN3VSEL 14 |
| 82 | #define MC13892_REGULATORSETTING0_VCAMVSEL 16 |
| 83 | |
| 84 | #define MC13892_REGULATORSETTING0_VGEN1VSEL_M (3<<0) |
| 85 | #define MC13892_REGULATORSETTING0_VDIGVSEL_M (3<<4) |
| 86 | #define MC13892_REGULATORSETTING0_VGEN2VSEL_M (7<<6) |
| 87 | #define MC13892_REGULATORSETTING0_VPLLVSEL_M (3<<9) |
| 88 | #define MC13892_REGULATORSETTING0_VUSB2VSEL_M (3<<11) |
| 89 | #define MC13892_REGULATORSETTING0_VGEN3VSEL_M (1<<14) |
| 90 | #define MC13892_REGULATORSETTING0_VCAMVSEL_M (3<<16) |
| 91 | |
| 92 | #define MC13892_REGULATORSETTING1 31 |
| 93 | #define MC13892_REGULATORSETTING1_VVIDEOVSEL 2 |
| 94 | #define MC13892_REGULATORSETTING1_VAUDIOVSEL 4 |
| 95 | #define MC13892_REGULATORSETTING1_VSDVSEL 6 |
| 96 | |
| 97 | #define MC13892_REGULATORSETTING1_VVIDEOVSEL_M (3<<2) |
| 98 | #define MC13892_REGULATORSETTING1_VAUDIOVSEL_M (3<<4) |
| 99 | #define MC13892_REGULATORSETTING1_VSDVSEL_M (7<<6) |
| 100 | |
| 101 | #define MC13892_REGULATORMODE0 32 |
| 102 | #define MC13892_REGULATORMODE0_VGEN1EN (1<<0) |
| 103 | #define MC13892_REGULATORMODE0_VGEN1STDBY (1<<1) |
| 104 | #define MC13892_REGULATORMODE0_VGEN1MODE (1<<2) |
| 105 | #define MC13892_REGULATORMODE0_VIOHIEN (1<<3) |
| 106 | #define MC13892_REGULATORMODE0_VIOHISTDBY (1<<4) |
| 107 | #define MC13892_REGULATORMODE0_VIOHIMODE (1<<5) |
| 108 | #define MC13892_REGULATORMODE0_VDIGEN (1<<9) |
| 109 | #define MC13892_REGULATORMODE0_VDIGSTDBY (1<<10) |
| 110 | #define MC13892_REGULATORMODE0_VDIGMODE (1<<11) |
| 111 | #define MC13892_REGULATORMODE0_VGEN2EN (1<<12) |
| 112 | #define MC13892_REGULATORMODE0_VGEN2STDBY (1<<13) |
| 113 | #define MC13892_REGULATORMODE0_VGEN2MODE (1<<14) |
| 114 | #define MC13892_REGULATORMODE0_VPLLEN (1<<15) |
| 115 | #define MC13892_REGULATORMODE0_VPLLSTDBY (1<<16) |
| 116 | #define MC13892_REGULATORMODE0_VPLLMODE (1<<17) |
| 117 | #define MC13892_REGULATORMODE0_VUSB2EN (1<<18) |
| 118 | #define MC13892_REGULATORMODE0_VUSB2STDBY (1<<19) |
| 119 | #define MC13892_REGULATORMODE0_VUSB2MODE (1<<20) |
| 120 | |
| 121 | #define MC13892_REGULATORMODE1 33 |
| 122 | #define MC13892_REGULATORMODE1_VGEN3EN (1<<0) |
| 123 | #define MC13892_REGULATORMODE1_VGEN3STDBY (1<<1) |
| 124 | #define MC13892_REGULATORMODE1_VGEN3MODE (1<<2) |
| 125 | #define MC13892_REGULATORMODE1_VCAMEN (1<<6) |
| 126 | #define MC13892_REGULATORMODE1_VCAMSTDBY (1<<7) |
| 127 | #define MC13892_REGULATORMODE1_VCAMMODE (1<<8) |
| 128 | #define MC13892_REGULATORMODE1_VCAMCONFIGEN (1<<9) |
| 129 | #define MC13892_REGULATORMODE1_VVIDEOEN (1<<12) |
| 130 | #define MC13892_REGULATORMODE1_VVIDEOSTDBY (1<<13) |
| 131 | #define MC13892_REGULATORMODE1_VVIDEOMODE (1<<14) |
| 132 | #define MC13892_REGULATORMODE1_VAUDIOEN (1<<15) |
| 133 | #define MC13892_REGULATORMODE1_VAUDIOSTDBY (1<<16) |
| 134 | #define MC13892_REGULATORMODE1_VAUDIOMODE (1<<17) |
| 135 | #define MC13892_REGULATORMODE1_VSDEN (1<<18) |
| 136 | #define MC13892_REGULATORMODE1_VSDSTDBY (1<<19) |
| 137 | #define MC13892_REGULATORMODE1_VSDMODE (1<<20) |
| 138 | |
| 139 | #define MC13892_POWERMISC 34 |
| 140 | #define MC13892_POWERMISC_GPO1EN (1<<6) |
| 141 | #define MC13892_POWERMISC_GPO2EN (1<<8) |
| 142 | #define MC13892_POWERMISC_GPO3EN (1<<10) |
| 143 | #define MC13892_POWERMISC_GPO4EN (1<<12) |
| 144 | #define MC13892_POWERMISC_PWGT1SPIEN (1<<15) |
| 145 | #define MC13892_POWERMISC_PWGT2SPIEN (1<<16) |
| 146 | #define MC13892_POWERMISC_GPO4ADINEN (1<<21) |
| 147 | |
| 148 | #define MC13892_POWERMISC_PWGTSPI_M (3 << 15) |
| 149 | |
| 150 | #define MC13892_USB1 50 |
| 151 | #define MC13892_USB1_VUSBEN (1<<3) |
| 152 | |
| 153 | static const int mc13892_vcoincell[] = { |
| 154 | 2500000, 2700000, 2800000, 2900000, 3000000, 3100000, |
| 155 | 3200000, 3300000, |
| 156 | }; |
| 157 | |
| 158 | static const int mc13892_sw1[] = { |
| 159 | 600000, 625000, 650000, 675000, 700000, 725000, |
| 160 | 750000, 775000, 800000, 825000, 850000, 875000, |
| 161 | 900000, 925000, 950000, 975000, 1000000, 1025000, |
| 162 | 1050000, 1075000, 1100000, 1125000, 1150000, 1175000, |
| 163 | 1200000, 1225000, 1250000, 1275000, 1300000, 1325000, |
| 164 | 1350000, 1375000 |
| 165 | }; |
| 166 | |
| 167 | static const int mc13892_sw[] = { |
| 168 | 600000, 625000, 650000, 675000, 700000, 725000, |
| 169 | 750000, 775000, 800000, 825000, 850000, 875000, |
| 170 | 900000, 925000, 950000, 975000, 1000000, 1025000, |
| 171 | 1050000, 1075000, 1100000, 1125000, 1150000, 1175000, |
| 172 | 1200000, 1225000, 1250000, 1275000, 1300000, 1325000, |
| 173 | 1350000, 1375000, 1400000, 1425000, 1450000, 1475000, |
| 174 | 1500000, 1525000, 1550000, 1575000, 1600000, 1625000, |
| 175 | 1650000, 1675000, 1700000, 1725000, 1750000, 1775000, |
| 176 | 1800000, 1825000, 1850000, 1875000 |
| 177 | }; |
| 178 | |
| 179 | static const int mc13892_swbst[] = { |
| 180 | 5000000, |
| 181 | }; |
| 182 | |
| 183 | static const int mc13892_viohi[] = { |
| 184 | 2775000, |
| 185 | }; |
| 186 | |
| 187 | static const int mc13892_vpll[] = { |
| 188 | 1050000, 1250000, 1650000, 1800000, |
| 189 | }; |
| 190 | |
| 191 | static const int mc13892_vdig[] = { |
| 192 | 1050000, 1250000, 1650000, 1800000, |
| 193 | }; |
| 194 | |
| 195 | static const int mc13892_vsd[] = { |
| 196 | 1800000, 2000000, 2600000, 2700000, |
| 197 | 2800000, 2900000, 3000000, 3150000, |
| 198 | }; |
| 199 | |
| 200 | static const int mc13892_vusb2[] = { |
| 201 | 2400000, 2600000, 2700000, 2775000, |
| 202 | }; |
| 203 | |
| 204 | static const int mc13892_vvideo[] = { |
| 205 | 2700000, 2775000, 2500000, 2600000, |
| 206 | }; |
| 207 | |
| 208 | static const int mc13892_vaudio[] = { |
| 209 | 2300000, 2500000, 2775000, 3000000, |
| 210 | }; |
| 211 | |
| 212 | static const int mc13892_vcam[] = { |
| 213 | 2500000, 2600000, 2750000, 3000000, |
| 214 | }; |
| 215 | |
| 216 | static const int mc13892_vgen1[] = { |
| 217 | 1200000, 1500000, 2775000, 3150000, |
| 218 | }; |
| 219 | |
| 220 | static const int mc13892_vgen2[] = { |
| 221 | 1200000, 1500000, 1600000, 1800000, |
| 222 | 2700000, 2800000, 3000000, 3150000, |
| 223 | }; |
| 224 | |
| 225 | static const int mc13892_vgen3[] = { |
| 226 | 1800000, 2900000, |
| 227 | }; |
| 228 | |
| 229 | static const int mc13892_vusb[] = { |
| 230 | 3300000, |
| 231 | }; |
| 232 | |
| 233 | static const int mc13892_gpo[] = { |
| 234 | 2750000, |
| 235 | }; |
| 236 | |
| 237 | static const int mc13892_pwgtdrv[] = { |
| 238 | 5000000, |
| 239 | }; |
| 240 | |
| 241 | static struct regulator_ops mc13892_gpo_regulator_ops; |
| 242 | /* sw regulators need special care due to the "hi bit" */ |
| 243 | static struct regulator_ops mc13892_sw_regulator_ops; |
| 244 | |
| 245 | |
| 246 | #define MC13892_FIXED_DEFINE(name, reg, voltages) \ |
| 247 | MC13xxx_FIXED_DEFINE(MC13892_, name, reg, voltages, \ |
| 248 | mc13xxx_fixed_regulator_ops) |
| 249 | |
| 250 | #define MC13892_GPO_DEFINE(name, reg, voltages) \ |
| 251 | MC13xxx_GPO_DEFINE(MC13892_, name, reg, voltages, \ |
| 252 | mc13892_gpo_regulator_ops) |
| 253 | |
| 254 | #define MC13892_SW_DEFINE(name, reg, vsel_reg, voltages) \ |
| 255 | MC13xxx_DEFINE(MC13892_, name, reg, vsel_reg, voltages, \ |
| 256 | mc13892_sw_regulator_ops) |
| 257 | |
| 258 | #define MC13892_DEFINE_REGU(name, reg, vsel_reg, voltages) \ |
| 259 | MC13xxx_DEFINE(MC13892_, name, reg, vsel_reg, voltages, \ |
| 260 | mc13xxx_regulator_ops) |
| 261 | |
| 262 | static struct mc13xxx_regulator mc13892_regulators[] = { |
Axel Lin | 327e15a | 2011-05-10 19:10:36 +0800 | [diff] [blame] | 263 | MC13892_DEFINE_REGU(VCOINCELL, POWERCTL0, POWERCTL0, mc13892_vcoincell), |
Yong Shen | 5e428d5 | 2010-12-14 14:00:55 +0800 | [diff] [blame] | 264 | MC13892_SW_DEFINE(SW1, SWITCHERS0, SWITCHERS0, mc13892_sw1), |
| 265 | MC13892_SW_DEFINE(SW2, SWITCHERS1, SWITCHERS1, mc13892_sw), |
| 266 | MC13892_SW_DEFINE(SW3, SWITCHERS2, SWITCHERS2, mc13892_sw), |
| 267 | MC13892_SW_DEFINE(SW4, SWITCHERS3, SWITCHERS3, mc13892_sw), |
| 268 | MC13892_FIXED_DEFINE(SWBST, SWITCHERS5, mc13892_swbst), |
| 269 | MC13892_FIXED_DEFINE(VIOHI, REGULATORMODE0, mc13892_viohi), |
| 270 | MC13892_DEFINE_REGU(VPLL, REGULATORMODE0, REGULATORSETTING0, \ |
| 271 | mc13892_vpll), |
| 272 | MC13892_DEFINE_REGU(VDIG, REGULATORMODE0, REGULATORSETTING0, \ |
| 273 | mc13892_vdig), |
| 274 | MC13892_DEFINE_REGU(VSD, REGULATORMODE1, REGULATORSETTING1, \ |
| 275 | mc13892_vsd), |
| 276 | MC13892_DEFINE_REGU(VUSB2, REGULATORMODE0, REGULATORSETTING0, \ |
| 277 | mc13892_vusb2), |
| 278 | MC13892_DEFINE_REGU(VVIDEO, REGULATORMODE1, REGULATORSETTING1, \ |
| 279 | mc13892_vvideo), |
| 280 | MC13892_DEFINE_REGU(VAUDIO, REGULATORMODE1, REGULATORSETTING1, \ |
| 281 | mc13892_vaudio), |
| 282 | MC13892_DEFINE_REGU(VCAM, REGULATORMODE1, REGULATORSETTING0, \ |
| 283 | mc13892_vcam), |
| 284 | MC13892_DEFINE_REGU(VGEN1, REGULATORMODE0, REGULATORSETTING0, \ |
| 285 | mc13892_vgen1), |
| 286 | MC13892_DEFINE_REGU(VGEN2, REGULATORMODE0, REGULATORSETTING0, \ |
| 287 | mc13892_vgen2), |
| 288 | MC13892_DEFINE_REGU(VGEN3, REGULATORMODE1, REGULATORSETTING0, \ |
| 289 | mc13892_vgen3), |
| 290 | MC13892_FIXED_DEFINE(VUSB, USB1, mc13892_vusb), |
| 291 | MC13892_GPO_DEFINE(GPO1, POWERMISC, mc13892_gpo), |
| 292 | MC13892_GPO_DEFINE(GPO2, POWERMISC, mc13892_gpo), |
| 293 | MC13892_GPO_DEFINE(GPO3, POWERMISC, mc13892_gpo), |
| 294 | MC13892_GPO_DEFINE(GPO4, POWERMISC, mc13892_gpo), |
| 295 | MC13892_GPO_DEFINE(PWGT1SPI, POWERMISC, mc13892_pwgtdrv), |
| 296 | MC13892_GPO_DEFINE(PWGT2SPI, POWERMISC, mc13892_pwgtdrv), |
| 297 | }; |
| 298 | |
Mark Brown | 27315cf | 2010-12-16 15:29:56 +0000 | [diff] [blame] | 299 | static int mc13892_powermisc_rmw(struct mc13xxx_regulator_priv *priv, u32 mask, |
| 300 | u32 val) |
Yong Shen | 5e428d5 | 2010-12-14 14:00:55 +0800 | [diff] [blame] | 301 | { |
| 302 | struct mc13xxx *mc13892 = priv->mc13xxx; |
| 303 | int ret; |
| 304 | u32 valread; |
| 305 | |
| 306 | BUG_ON(val & ~mask); |
| 307 | |
| 308 | ret = mc13xxx_reg_read(mc13892, MC13892_POWERMISC, &valread); |
| 309 | if (ret) |
| 310 | return ret; |
| 311 | |
| 312 | /* Update the stored state for Power Gates. */ |
| 313 | priv->powermisc_pwgt_state = |
| 314 | (priv->powermisc_pwgt_state & ~mask) | val; |
| 315 | priv->powermisc_pwgt_state &= MC13892_POWERMISC_PWGTSPI_M; |
| 316 | |
| 317 | /* Construct the new register value */ |
| 318 | valread = (valread & ~mask) | val; |
| 319 | /* Overwrite the PWGTxEN with the stored version */ |
| 320 | valread = (valread & ~MC13892_POWERMISC_PWGTSPI_M) | |
| 321 | priv->powermisc_pwgt_state; |
| 322 | |
| 323 | return mc13xxx_reg_write(mc13892, MC13892_POWERMISC, valread); |
| 324 | } |
| 325 | |
| 326 | static int mc13892_gpo_regulator_enable(struct regulator_dev *rdev) |
| 327 | { |
| 328 | struct mc13xxx_regulator_priv *priv = rdev_get_drvdata(rdev); |
| 329 | int id = rdev_get_id(rdev); |
| 330 | int ret; |
| 331 | u32 en_val = mc13892_regulators[id].enable_bit; |
| 332 | u32 mask = mc13892_regulators[id].enable_bit; |
| 333 | |
| 334 | dev_dbg(rdev_get_dev(rdev), "%s id: %d\n", __func__, id); |
| 335 | |
| 336 | /* Power Gate enable value is 0 */ |
| 337 | if (id == MC13892_PWGT1SPI || id == MC13892_PWGT2SPI) |
| 338 | en_val = 0; |
| 339 | |
| 340 | if (id == MC13892_GPO4) |
| 341 | mask |= MC13892_POWERMISC_GPO4ADINEN; |
| 342 | |
| 343 | mc13xxx_lock(priv->mc13xxx); |
| 344 | ret = mc13892_powermisc_rmw(priv, mask, en_val); |
| 345 | mc13xxx_unlock(priv->mc13xxx); |
| 346 | |
| 347 | return ret; |
| 348 | } |
| 349 | |
| 350 | static int mc13892_gpo_regulator_disable(struct regulator_dev *rdev) |
| 351 | { |
| 352 | struct mc13xxx_regulator_priv *priv = rdev_get_drvdata(rdev); |
| 353 | int id = rdev_get_id(rdev); |
| 354 | int ret; |
| 355 | u32 dis_val = 0; |
| 356 | |
| 357 | dev_dbg(rdev_get_dev(rdev), "%s id: %d\n", __func__, id); |
| 358 | |
| 359 | /* Power Gate disable value is 1 */ |
| 360 | if (id == MC13892_PWGT1SPI || id == MC13892_PWGT2SPI) |
| 361 | dis_val = mc13892_regulators[id].enable_bit; |
| 362 | |
| 363 | mc13xxx_lock(priv->mc13xxx); |
| 364 | ret = mc13892_powermisc_rmw(priv, mc13892_regulators[id].enable_bit, |
| 365 | dis_val); |
| 366 | mc13xxx_unlock(priv->mc13xxx); |
| 367 | |
| 368 | return ret; |
| 369 | } |
| 370 | |
| 371 | static int mc13892_gpo_regulator_is_enabled(struct regulator_dev *rdev) |
| 372 | { |
| 373 | struct mc13xxx_regulator_priv *priv = rdev_get_drvdata(rdev); |
| 374 | int ret, id = rdev_get_id(rdev); |
| 375 | unsigned int val; |
| 376 | |
| 377 | mc13xxx_lock(priv->mc13xxx); |
| 378 | ret = mc13xxx_reg_read(priv->mc13xxx, mc13892_regulators[id].reg, &val); |
| 379 | mc13xxx_unlock(priv->mc13xxx); |
| 380 | |
| 381 | if (ret) |
| 382 | return ret; |
| 383 | |
| 384 | /* Power Gates state is stored in powermisc_pwgt_state |
| 385 | * where the meaning of bits is negated */ |
| 386 | val = (val & ~MC13892_POWERMISC_PWGTSPI_M) | |
| 387 | (priv->powermisc_pwgt_state ^ MC13892_POWERMISC_PWGTSPI_M); |
| 388 | |
| 389 | return (val & mc13892_regulators[id].enable_bit) != 0; |
| 390 | } |
| 391 | |
| 392 | |
| 393 | static struct regulator_ops mc13892_gpo_regulator_ops = { |
| 394 | .enable = mc13892_gpo_regulator_enable, |
| 395 | .disable = mc13892_gpo_regulator_disable, |
| 396 | .is_enabled = mc13892_gpo_regulator_is_enabled, |
| 397 | .list_voltage = mc13xxx_regulator_list_voltage, |
| 398 | .set_voltage = mc13xxx_fixed_regulator_set_voltage, |
| 399 | .get_voltage = mc13xxx_fixed_regulator_get_voltage, |
| 400 | }; |
| 401 | |
| 402 | static int mc13892_sw_regulator_get_voltage(struct regulator_dev *rdev) |
| 403 | { |
| 404 | struct mc13xxx_regulator_priv *priv = rdev_get_drvdata(rdev); |
| 405 | int ret, id = rdev_get_id(rdev); |
| 406 | unsigned int val, hi; |
| 407 | |
| 408 | dev_dbg(rdev_get_dev(rdev), "%s id: %d\n", __func__, id); |
| 409 | |
| 410 | mc13xxx_lock(priv->mc13xxx); |
| 411 | ret = mc13xxx_reg_read(priv->mc13xxx, |
| 412 | mc13892_regulators[id].vsel_reg, &val); |
| 413 | mc13xxx_unlock(priv->mc13xxx); |
| 414 | if (ret) |
| 415 | return ret; |
| 416 | |
| 417 | hi = val & MC13892_SWITCHERS0_SWxHI; |
| 418 | val = (val & mc13892_regulators[id].vsel_mask) |
| 419 | >> mc13892_regulators[id].vsel_shift; |
| 420 | |
| 421 | dev_dbg(rdev_get_dev(rdev), "%s id: %d val: %d\n", __func__, id, val); |
| 422 | |
| 423 | if (hi) |
| 424 | val = (25000 * val) + 1100000; |
| 425 | else |
| 426 | val = (25000 * val) + 600000; |
| 427 | |
| 428 | return val; |
| 429 | } |
| 430 | |
| 431 | static int mc13892_sw_regulator_set_voltage(struct regulator_dev *rdev, |
| 432 | int min_uV, int max_uV, unsigned *selector) |
| 433 | { |
| 434 | struct mc13xxx_regulator_priv *priv = rdev_get_drvdata(rdev); |
Axel Lin | 98ea5c2 | 2011-05-09 17:49:40 +0800 | [diff] [blame] | 435 | int hi, value, mask, id = rdev_get_id(rdev); |
| 436 | u32 valread; |
Yong Shen | 5e428d5 | 2010-12-14 14:00:55 +0800 | [diff] [blame] | 437 | int ret; |
| 438 | |
| 439 | dev_dbg(rdev_get_dev(rdev), "%s id: %d min_uV: %d max_uV: %d\n", |
| 440 | __func__, id, min_uV, max_uV); |
| 441 | |
| 442 | /* Find the best index */ |
| 443 | value = mc13xxx_get_best_voltage_index(rdev, min_uV, max_uV); |
| 444 | dev_dbg(rdev_get_dev(rdev), "%s best value: %d\n", __func__, value); |
| 445 | if (value < 0) |
| 446 | return value; |
| 447 | |
| 448 | value = mc13892_regulators[id].voltages[value]; |
| 449 | |
| 450 | mc13xxx_lock(priv->mc13xxx); |
| 451 | ret = mc13xxx_reg_read(priv->mc13xxx, |
Axel Lin | 98ea5c2 | 2011-05-09 17:49:40 +0800 | [diff] [blame] | 452 | mc13892_regulators[id].vsel_reg, &valread); |
Yong Shen | 5e428d5 | 2010-12-14 14:00:55 +0800 | [diff] [blame] | 453 | if (ret) |
| 454 | goto err; |
| 455 | |
Fabio Estevam | 6dc4efc | 2011-05-16 10:54:27 -0300 | [diff] [blame] | 456 | if (value > 1375000) |
Yong Shen | 5e428d5 | 2010-12-14 14:00:55 +0800 | [diff] [blame] | 457 | hi = 1; |
Fabio Estevam | 6dc4efc | 2011-05-16 10:54:27 -0300 | [diff] [blame] | 458 | else if (value < 1100000) |
Yong Shen | 5e428d5 | 2010-12-14 14:00:55 +0800 | [diff] [blame] | 459 | hi = 0; |
Axel Lin | 98ea5c2 | 2011-05-09 17:49:40 +0800 | [diff] [blame] | 460 | else |
| 461 | hi = valread & MC13892_SWITCHERS0_SWxHI; |
Yong Shen | 5e428d5 | 2010-12-14 14:00:55 +0800 | [diff] [blame] | 462 | |
| 463 | if (hi) { |
| 464 | value = (value - 1100000) / 25000; |
| 465 | value |= MC13892_SWITCHERS0_SWxHI; |
| 466 | } else |
| 467 | value = (value - 600000) / 25000; |
| 468 | |
| 469 | mask = mc13892_regulators[id].vsel_mask | MC13892_SWITCHERS0_SWxHI; |
Axel Lin | 98ea5c2 | 2011-05-09 17:49:40 +0800 | [diff] [blame] | 470 | valread = (valread & ~mask) | |
| 471 | (value << mc13892_regulators[id].vsel_shift); |
| 472 | ret = mc13xxx_reg_write(priv->mc13xxx, mc13892_regulators[id].vsel_reg, |
| 473 | valread); |
Yong Shen | 5e428d5 | 2010-12-14 14:00:55 +0800 | [diff] [blame] | 474 | err: |
| 475 | mc13xxx_unlock(priv->mc13xxx); |
| 476 | |
| 477 | return ret; |
| 478 | } |
| 479 | |
| 480 | static struct regulator_ops mc13892_sw_regulator_ops = { |
| 481 | .is_enabled = mc13xxx_sw_regulator_is_enabled, |
| 482 | .list_voltage = mc13xxx_regulator_list_voltage, |
| 483 | .set_voltage = mc13892_sw_regulator_set_voltage, |
| 484 | .get_voltage = mc13892_sw_regulator_get_voltage, |
| 485 | }; |
| 486 | |
| 487 | static int mc13892_vcam_set_mode(struct regulator_dev *rdev, unsigned int mode) |
| 488 | { |
| 489 | unsigned int en_val = 0; |
| 490 | struct mc13xxx_regulator_priv *priv = rdev_get_drvdata(rdev); |
| 491 | int ret, id = rdev_get_id(rdev); |
| 492 | |
| 493 | if (mode == REGULATOR_MODE_FAST) |
| 494 | en_val = MC13892_REGULATORMODE1_VCAMCONFIGEN; |
| 495 | |
| 496 | mc13xxx_lock(priv->mc13xxx); |
| 497 | ret = mc13xxx_reg_rmw(priv->mc13xxx, mc13892_regulators[id].reg, |
| 498 | MC13892_REGULATORMODE1_VCAMCONFIGEN, en_val); |
| 499 | mc13xxx_unlock(priv->mc13xxx); |
| 500 | |
| 501 | return ret; |
| 502 | } |
| 503 | |
Mark Brown | 27315cf | 2010-12-16 15:29:56 +0000 | [diff] [blame] | 504 | static unsigned int mc13892_vcam_get_mode(struct regulator_dev *rdev) |
Yong Shen | 5e428d5 | 2010-12-14 14:00:55 +0800 | [diff] [blame] | 505 | { |
| 506 | struct mc13xxx_regulator_priv *priv = rdev_get_drvdata(rdev); |
| 507 | int ret, id = rdev_get_id(rdev); |
| 508 | unsigned int val; |
| 509 | |
| 510 | mc13xxx_lock(priv->mc13xxx); |
| 511 | ret = mc13xxx_reg_read(priv->mc13xxx, mc13892_regulators[id].reg, &val); |
| 512 | mc13xxx_unlock(priv->mc13xxx); |
| 513 | |
| 514 | if (ret) |
| 515 | return ret; |
| 516 | |
| 517 | if (val & MC13892_REGULATORMODE1_VCAMCONFIGEN) |
| 518 | return REGULATOR_MODE_FAST; |
| 519 | |
| 520 | return REGULATOR_MODE_NORMAL; |
| 521 | } |
| 522 | |
| 523 | |
| 524 | static int __devinit mc13892_regulator_probe(struct platform_device *pdev) |
| 525 | { |
| 526 | struct mc13xxx_regulator_priv *priv; |
| 527 | struct mc13xxx *mc13892 = dev_get_drvdata(pdev->dev.parent); |
Samuel Ortiz | c8a03c9 | 2011-04-08 01:55:01 +0200 | [diff] [blame] | 528 | struct mc13xxx_regulator_platform_data *pdata = |
| 529 | dev_get_platdata(&pdev->dev); |
Shawn Guo | 93bcb23 | 2011-12-21 23:00:46 +0800 | [diff] [blame] | 530 | struct mc13xxx_regulator_init_data *mc13xxx_data; |
Yong Shen | 5e428d5 | 2010-12-14 14:00:55 +0800 | [diff] [blame] | 531 | int i, ret; |
Shawn Guo | 93bcb23 | 2011-12-21 23:00:46 +0800 | [diff] [blame] | 532 | int num_regulators = 0; |
Yong Shen | 5e428d5 | 2010-12-14 14:00:55 +0800 | [diff] [blame] | 533 | u32 val; |
| 534 | |
Shawn Guo | 93bcb23 | 2011-12-21 23:00:46 +0800 | [diff] [blame] | 535 | num_regulators = mc13xxx_get_num_regulators_dt(pdev); |
| 536 | if (num_regulators <= 0 && pdata) |
| 537 | num_regulators = pdata->num_regulators; |
| 538 | if (num_regulators <= 0) |
| 539 | return -EINVAL; |
| 540 | |
Fabio Estevam | 4fef21e | 2011-12-29 20:05:00 -0200 | [diff] [blame] | 541 | priv = devm_kzalloc(&pdev->dev, sizeof(*priv) + |
Shawn Guo | 93bcb23 | 2011-12-21 23:00:46 +0800 | [diff] [blame] | 542 | num_regulators * sizeof(priv->regulators[0]), |
Yong Shen | 5e428d5 | 2010-12-14 14:00:55 +0800 | [diff] [blame] | 543 | GFP_KERNEL); |
| 544 | if (!priv) |
| 545 | return -ENOMEM; |
| 546 | |
Shawn Guo | 93bcb23 | 2011-12-21 23:00:46 +0800 | [diff] [blame] | 547 | priv->num_regulators = num_regulators; |
Yong Shen | 5e428d5 | 2010-12-14 14:00:55 +0800 | [diff] [blame] | 548 | priv->mc13xxx_regulators = mc13892_regulators; |
| 549 | priv->mc13xxx = mc13892; |
Shawn Guo | 93bcb23 | 2011-12-21 23:00:46 +0800 | [diff] [blame] | 550 | platform_set_drvdata(pdev, priv); |
Yong Shen | 5e428d5 | 2010-12-14 14:00:55 +0800 | [diff] [blame] | 551 | |
| 552 | mc13xxx_lock(mc13892); |
| 553 | ret = mc13xxx_reg_read(mc13892, MC13892_REVISION, &val); |
| 554 | if (ret) |
Axel Lin | 5777d9b | 2012-03-15 12:49:09 +0800 | [diff] [blame] | 555 | goto err_unlock; |
Yong Shen | 5e428d5 | 2010-12-14 14:00:55 +0800 | [diff] [blame] | 556 | |
| 557 | /* enable switch auto mode */ |
| 558 | if ((val & 0x0000FFFF) == 0x45d0) { |
| 559 | ret = mc13xxx_reg_rmw(mc13892, MC13892_SWITCHERS4, |
| 560 | MC13892_SWITCHERS4_SW1MODE_M | |
| 561 | MC13892_SWITCHERS4_SW2MODE_M, |
| 562 | MC13892_SWITCHERS4_SW1MODE_AUTO | |
| 563 | MC13892_SWITCHERS4_SW2MODE_AUTO); |
| 564 | if (ret) |
Axel Lin | 5777d9b | 2012-03-15 12:49:09 +0800 | [diff] [blame] | 565 | goto err_unlock; |
Yong Shen | 5e428d5 | 2010-12-14 14:00:55 +0800 | [diff] [blame] | 566 | |
Axel Lin | 923430c | 2011-01-03 23:57:38 +0800 | [diff] [blame] | 567 | ret = mc13xxx_reg_rmw(mc13892, MC13892_SWITCHERS5, |
Yong Shen | 5e428d5 | 2010-12-14 14:00:55 +0800 | [diff] [blame] | 568 | MC13892_SWITCHERS5_SW3MODE_M | |
| 569 | MC13892_SWITCHERS5_SW4MODE_M, |
| 570 | MC13892_SWITCHERS5_SW3MODE_AUTO | |
| 571 | MC13892_SWITCHERS5_SW4MODE_AUTO); |
| 572 | if (ret) |
Axel Lin | 5777d9b | 2012-03-15 12:49:09 +0800 | [diff] [blame] | 573 | goto err_unlock; |
Yong Shen | 5e428d5 | 2010-12-14 14:00:55 +0800 | [diff] [blame] | 574 | } |
| 575 | mc13xxx_unlock(mc13892); |
| 576 | |
| 577 | mc13892_regulators[MC13892_VCAM].desc.ops->set_mode |
| 578 | = mc13892_vcam_set_mode; |
| 579 | mc13892_regulators[MC13892_VCAM].desc.ops->get_mode |
| 580 | = mc13892_vcam_get_mode; |
Shawn Guo | 93bcb23 | 2011-12-21 23:00:46 +0800 | [diff] [blame] | 581 | |
| 582 | mc13xxx_data = mc13xxx_parse_regulators_dt(pdev, mc13892_regulators, |
| 583 | ARRAY_SIZE(mc13892_regulators)); |
| 584 | for (i = 0; i < num_regulators; i++) { |
| 585 | struct regulator_init_data *init_data; |
| 586 | struct regulator_desc *desc; |
| 587 | struct device_node *node = NULL; |
| 588 | int id; |
| 589 | |
| 590 | if (mc13xxx_data) { |
| 591 | id = mc13xxx_data[i].id; |
| 592 | init_data = mc13xxx_data[i].init_data; |
| 593 | node = mc13xxx_data[i].node; |
| 594 | } else { |
| 595 | id = pdata->regulators[i].id; |
| 596 | init_data = pdata->regulators[i].init_data; |
| 597 | } |
| 598 | desc = &mc13892_regulators[id].desc; |
| 599 | |
Yong Shen | 5e428d5 | 2010-12-14 14:00:55 +0800 | [diff] [blame] | 600 | priv->regulators[i] = regulator_register( |
Shawn Guo | 93bcb23 | 2011-12-21 23:00:46 +0800 | [diff] [blame] | 601 | desc, &pdev->dev, init_data, priv, node); |
Yong Shen | 5e428d5 | 2010-12-14 14:00:55 +0800 | [diff] [blame] | 602 | |
| 603 | if (IS_ERR(priv->regulators[i])) { |
| 604 | dev_err(&pdev->dev, "failed to register regulator %s\n", |
| 605 | mc13892_regulators[i].desc.name); |
| 606 | ret = PTR_ERR(priv->regulators[i]); |
| 607 | goto err; |
| 608 | } |
| 609 | } |
| 610 | |
Yong Shen | 5e428d5 | 2010-12-14 14:00:55 +0800 | [diff] [blame] | 611 | return 0; |
| 612 | err: |
| 613 | while (--i >= 0) |
| 614 | regulator_unregister(priv->regulators[i]); |
Axel Lin | 5777d9b | 2012-03-15 12:49:09 +0800 | [diff] [blame] | 615 | return ret; |
Yong Shen | 5e428d5 | 2010-12-14 14:00:55 +0800 | [diff] [blame] | 616 | |
Axel Lin | 5777d9b | 2012-03-15 12:49:09 +0800 | [diff] [blame] | 617 | err_unlock: |
Yong Shen | 5e428d5 | 2010-12-14 14:00:55 +0800 | [diff] [blame] | 618 | mc13xxx_unlock(mc13892); |
Yong Shen | 5e428d5 | 2010-12-14 14:00:55 +0800 | [diff] [blame] | 619 | return ret; |
| 620 | } |
| 621 | |
| 622 | static int __devexit mc13892_regulator_remove(struct platform_device *pdev) |
| 623 | { |
| 624 | struct mc13xxx_regulator_priv *priv = platform_get_drvdata(pdev); |
Yong Shen | 5e428d5 | 2010-12-14 14:00:55 +0800 | [diff] [blame] | 625 | int i; |
| 626 | |
| 627 | platform_set_drvdata(pdev, NULL); |
| 628 | |
Shawn Guo | 93bcb23 | 2011-12-21 23:00:46 +0800 | [diff] [blame] | 629 | for (i = 0; i < priv->num_regulators; i++) |
Yong Shen | 5e428d5 | 2010-12-14 14:00:55 +0800 | [diff] [blame] | 630 | regulator_unregister(priv->regulators[i]); |
| 631 | |
Yong Shen | 5e428d5 | 2010-12-14 14:00:55 +0800 | [diff] [blame] | 632 | return 0; |
| 633 | } |
| 634 | |
| 635 | static struct platform_driver mc13892_regulator_driver = { |
| 636 | .driver = { |
| 637 | .name = "mc13892-regulator", |
| 638 | .owner = THIS_MODULE, |
| 639 | }, |
| 640 | .remove = __devexit_p(mc13892_regulator_remove), |
| 641 | .probe = mc13892_regulator_probe, |
| 642 | }; |
| 643 | |
| 644 | static int __init mc13892_regulator_init(void) |
| 645 | { |
| 646 | return platform_driver_register(&mc13892_regulator_driver); |
| 647 | } |
| 648 | subsys_initcall(mc13892_regulator_init); |
| 649 | |
| 650 | static void __exit mc13892_regulator_exit(void) |
| 651 | { |
| 652 | platform_driver_unregister(&mc13892_regulator_driver); |
| 653 | } |
| 654 | module_exit(mc13892_regulator_exit); |
| 655 | |
| 656 | MODULE_LICENSE("GPL v2"); |
| 657 | MODULE_AUTHOR("Yong Shen <yong.shen@linaro.org>"); |
| 658 | MODULE_DESCRIPTION("Regulator Driver for Freescale MC13892 PMIC"); |
| 659 | MODULE_ALIAS("platform:mc13892-regulator"); |