Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1 | /* |
Sujith | cee075a | 2009-03-13 09:07:23 +0530 | [diff] [blame] | 2 | * Copyright (c) 2008-2009 Atheros Communications Inc. |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3 | * |
| 4 | * Permission to use, copy, modify, and/or distribute this software for any |
| 5 | * purpose with or without fee is hereby granted, provided that the above |
| 6 | * copyright notice and this permission notice appear in all copies. |
| 7 | * |
| 8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
| 9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
| 10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
| 11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
| 12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
| 13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
| 14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
| 15 | */ |
| 16 | |
Sujith | 394cf0a | 2009-02-09 13:26:54 +0530 | [diff] [blame] | 17 | #include "ath9k.h" |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 18 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 19 | /* We can tune this as we go by monitoring really low values */ |
| 20 | #define ATH9K_NF_TOO_LOW -60 |
| 21 | |
| 22 | /* AR5416 may return very high value (like -31 dBm), in those cases the nf |
| 23 | * is incorrect and we should use the static NF value. Later we can try to |
| 24 | * find out why they are reporting these values */ |
| 25 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 26 | static bool ath9k_hw_nf_in_range(struct ath_hw *ah, s16 nf) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 27 | { |
| 28 | if (nf > ATH9K_NF_TOO_LOW) { |
Sujith | 04bd463 | 2008-11-28 22:18:05 +0530 | [diff] [blame] | 29 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, |
| 30 | "noise floor value detected (%d) is " |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 31 | "lower than what we think is a " |
| 32 | "reasonable value (%d)\n", |
Sujith | 04bd463 | 2008-11-28 22:18:05 +0530 | [diff] [blame] | 33 | nf, ATH9K_NF_TOO_LOW); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 34 | return false; |
| 35 | } |
| 36 | return true; |
| 37 | } |
| 38 | |
| 39 | static int16_t ath9k_hw_get_nf_hist_mid(int16_t *nfCalBuffer) |
| 40 | { |
| 41 | int16_t nfval; |
| 42 | int16_t sort[ATH9K_NF_CAL_HIST_MAX]; |
| 43 | int i, j; |
| 44 | |
| 45 | for (i = 0; i < ATH9K_NF_CAL_HIST_MAX; i++) |
| 46 | sort[i] = nfCalBuffer[i]; |
| 47 | |
| 48 | for (i = 0; i < ATH9K_NF_CAL_HIST_MAX - 1; i++) { |
| 49 | for (j = 1; j < ATH9K_NF_CAL_HIST_MAX - i; j++) { |
| 50 | if (sort[j] > sort[j - 1]) { |
| 51 | nfval = sort[j]; |
| 52 | sort[j] = sort[j - 1]; |
| 53 | sort[j - 1] = nfval; |
| 54 | } |
| 55 | } |
| 56 | } |
| 57 | nfval = sort[(ATH9K_NF_CAL_HIST_MAX - 1) >> 1]; |
| 58 | |
| 59 | return nfval; |
| 60 | } |
| 61 | |
| 62 | static void ath9k_hw_update_nfcal_hist_buffer(struct ath9k_nfcal_hist *h, |
| 63 | int16_t *nfarray) |
| 64 | { |
| 65 | int i; |
| 66 | |
| 67 | for (i = 0; i < NUM_NF_READINGS; i++) { |
| 68 | h[i].nfCalBuffer[h[i].currIndex] = nfarray[i]; |
| 69 | |
| 70 | if (++h[i].currIndex >= ATH9K_NF_CAL_HIST_MAX) |
| 71 | h[i].currIndex = 0; |
| 72 | |
| 73 | if (h[i].invalidNFcount > 0) { |
| 74 | if (nfarray[i] < AR_PHY_CCA_MIN_BAD_VALUE || |
| 75 | nfarray[i] > AR_PHY_CCA_MAX_HIGH_VALUE) { |
| 76 | h[i].invalidNFcount = ATH9K_NF_CAL_HIST_MAX; |
| 77 | } else { |
| 78 | h[i].invalidNFcount--; |
| 79 | h[i].privNF = nfarray[i]; |
| 80 | } |
| 81 | } else { |
| 82 | h[i].privNF = |
| 83 | ath9k_hw_get_nf_hist_mid(h[i].nfCalBuffer); |
| 84 | } |
| 85 | } |
| 86 | return; |
| 87 | } |
| 88 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 89 | static void ath9k_hw_do_getnf(struct ath_hw *ah, |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 90 | int16_t nfarray[NUM_NF_READINGS]) |
| 91 | { |
| 92 | int16_t nf; |
| 93 | |
| 94 | if (AR_SREV_9280_10_OR_LATER(ah)) |
| 95 | nf = MS(REG_READ(ah, AR_PHY_CCA), AR9280_PHY_MINCCA_PWR); |
| 96 | else |
| 97 | nf = MS(REG_READ(ah, AR_PHY_CCA), AR_PHY_MINCCA_PWR); |
| 98 | |
| 99 | if (nf & 0x100) |
| 100 | nf = 0 - ((nf ^ 0x1ff) + 1); |
| 101 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, |
| 102 | "NF calibrated [ctl] [chain 0] is %d\n", nf); |
| 103 | nfarray[0] = nf; |
| 104 | |
Senthil Balasubramanian | 793c592 | 2009-01-26 20:28:14 +0530 | [diff] [blame] | 105 | if (!AR_SREV_9285(ah)) { |
| 106 | if (AR_SREV_9280_10_OR_LATER(ah)) |
| 107 | nf = MS(REG_READ(ah, AR_PHY_CH1_CCA), |
| 108 | AR9280_PHY_CH1_MINCCA_PWR); |
| 109 | else |
| 110 | nf = MS(REG_READ(ah, AR_PHY_CH1_CCA), |
| 111 | AR_PHY_CH1_MINCCA_PWR); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 112 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 113 | if (nf & 0x100) |
| 114 | nf = 0 - ((nf ^ 0x1ff) + 1); |
Sujith | 04bd463 | 2008-11-28 22:18:05 +0530 | [diff] [blame] | 115 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, |
Senthil Balasubramanian | 793c592 | 2009-01-26 20:28:14 +0530 | [diff] [blame] | 116 | "NF calibrated [ctl] [chain 1] is %d\n", nf); |
| 117 | nfarray[1] = nf; |
| 118 | |
Vivek Natarajan | ac88b6e | 2009-07-23 10:59:57 +0530 | [diff] [blame] | 119 | if (!AR_SREV_9280(ah) && !AR_SREV_9287(ah)) { |
Senthil Balasubramanian | 793c592 | 2009-01-26 20:28:14 +0530 | [diff] [blame] | 120 | nf = MS(REG_READ(ah, AR_PHY_CH2_CCA), |
| 121 | AR_PHY_CH2_MINCCA_PWR); |
| 122 | if (nf & 0x100) |
| 123 | nf = 0 - ((nf ^ 0x1ff) + 1); |
| 124 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, |
| 125 | "NF calibrated [ctl] [chain 2] is %d\n", nf); |
| 126 | nfarray[2] = nf; |
| 127 | } |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 128 | } |
| 129 | |
| 130 | if (AR_SREV_9280_10_OR_LATER(ah)) |
| 131 | nf = MS(REG_READ(ah, AR_PHY_EXT_CCA), |
| 132 | AR9280_PHY_EXT_MINCCA_PWR); |
| 133 | else |
| 134 | nf = MS(REG_READ(ah, AR_PHY_EXT_CCA), |
| 135 | AR_PHY_EXT_MINCCA_PWR); |
| 136 | |
| 137 | if (nf & 0x100) |
| 138 | nf = 0 - ((nf ^ 0x1ff) + 1); |
Sujith | 04bd463 | 2008-11-28 22:18:05 +0530 | [diff] [blame] | 139 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 140 | "NF calibrated [ext] [chain 0] is %d\n", nf); |
| 141 | nfarray[3] = nf; |
| 142 | |
Senthil Balasubramanian | 793c592 | 2009-01-26 20:28:14 +0530 | [diff] [blame] | 143 | if (!AR_SREV_9285(ah)) { |
| 144 | if (AR_SREV_9280_10_OR_LATER(ah)) |
| 145 | nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA), |
| 146 | AR9280_PHY_CH1_EXT_MINCCA_PWR); |
| 147 | else |
| 148 | nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA), |
| 149 | AR_PHY_CH1_EXT_MINCCA_PWR); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 150 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 151 | if (nf & 0x100) |
| 152 | nf = 0 - ((nf ^ 0x1ff) + 1); |
Sujith | 04bd463 | 2008-11-28 22:18:05 +0530 | [diff] [blame] | 153 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, |
Senthil Balasubramanian | 793c592 | 2009-01-26 20:28:14 +0530 | [diff] [blame] | 154 | "NF calibrated [ext] [chain 1] is %d\n", nf); |
| 155 | nfarray[4] = nf; |
| 156 | |
Vivek Natarajan | ac88b6e | 2009-07-23 10:59:57 +0530 | [diff] [blame] | 157 | if (!AR_SREV_9280(ah) && !AR_SREV_9287(ah)) { |
Senthil Balasubramanian | 793c592 | 2009-01-26 20:28:14 +0530 | [diff] [blame] | 158 | nf = MS(REG_READ(ah, AR_PHY_CH2_EXT_CCA), |
| 159 | AR_PHY_CH2_EXT_MINCCA_PWR); |
| 160 | if (nf & 0x100) |
| 161 | nf = 0 - ((nf ^ 0x1ff) + 1); |
| 162 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, |
| 163 | "NF calibrated [ext] [chain 2] is %d\n", nf); |
| 164 | nfarray[5] = nf; |
| 165 | } |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 166 | } |
| 167 | } |
| 168 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 169 | static bool getNoiseFloorThresh(struct ath_hw *ah, |
Luis R. Rodriguez | 76061ab | 2008-12-23 15:58:41 -0800 | [diff] [blame] | 170 | enum ieee80211_band band, |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 171 | int16_t *nft) |
| 172 | { |
Luis R. Rodriguez | 76061ab | 2008-12-23 15:58:41 -0800 | [diff] [blame] | 173 | switch (band) { |
| 174 | case IEEE80211_BAND_5GHZ: |
Sujith | f74df6f | 2009-02-09 13:27:24 +0530 | [diff] [blame] | 175 | *nft = (int8_t)ah->eep_ops->get_eeprom(ah, EEP_NFTHRESH_5); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 176 | break; |
Luis R. Rodriguez | 76061ab | 2008-12-23 15:58:41 -0800 | [diff] [blame] | 177 | case IEEE80211_BAND_2GHZ: |
Sujith | f74df6f | 2009-02-09 13:27:24 +0530 | [diff] [blame] | 178 | *nft = (int8_t)ah->eep_ops->get_eeprom(ah, EEP_NFTHRESH_2); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 179 | break; |
| 180 | default: |
Luis R. Rodriguez | 76061ab | 2008-12-23 15:58:41 -0800 | [diff] [blame] | 181 | BUG_ON(1); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 182 | return false; |
| 183 | } |
| 184 | |
| 185 | return true; |
| 186 | } |
| 187 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 188 | static void ath9k_hw_setup_calibration(struct ath_hw *ah, |
Sujith | cbfe946 | 2009-04-13 21:56:56 +0530 | [diff] [blame] | 189 | struct ath9k_cal_list *currCal) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 190 | { |
| 191 | REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(0), |
| 192 | AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX, |
| 193 | currCal->calData->calCountMax); |
| 194 | |
| 195 | switch (currCal->calData->calType) { |
| 196 | case IQ_MISMATCH_CAL: |
| 197 | REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ); |
| 198 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, |
Sujith | 04bd463 | 2008-11-28 22:18:05 +0530 | [diff] [blame] | 199 | "starting IQ Mismatch Calibration\n"); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 200 | break; |
| 201 | case ADC_GAIN_CAL: |
| 202 | REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_GAIN); |
| 203 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, |
Sujith | 04bd463 | 2008-11-28 22:18:05 +0530 | [diff] [blame] | 204 | "starting ADC Gain Calibration\n"); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 205 | break; |
| 206 | case ADC_DC_CAL: |
| 207 | REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_PER); |
| 208 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, |
Sujith | 04bd463 | 2008-11-28 22:18:05 +0530 | [diff] [blame] | 209 | "starting ADC DC Calibration\n"); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 210 | break; |
| 211 | case ADC_DC_INIT_CAL: |
| 212 | REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_INIT); |
| 213 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, |
Sujith | 04bd463 | 2008-11-28 22:18:05 +0530 | [diff] [blame] | 214 | "starting Init ADC DC Calibration\n"); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 215 | break; |
| 216 | } |
| 217 | |
| 218 | REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0), |
| 219 | AR_PHY_TIMING_CTRL4_DO_CAL); |
| 220 | } |
| 221 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 222 | static void ath9k_hw_reset_calibration(struct ath_hw *ah, |
Sujith | cbfe946 | 2009-04-13 21:56:56 +0530 | [diff] [blame] | 223 | struct ath9k_cal_list *currCal) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 224 | { |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 225 | int i; |
| 226 | |
| 227 | ath9k_hw_setup_calibration(ah, currCal); |
| 228 | |
| 229 | currCal->calState = CAL_RUNNING; |
| 230 | |
| 231 | for (i = 0; i < AR5416_MAX_CHAINS; i++) { |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 232 | ah->meas0.sign[i] = 0; |
| 233 | ah->meas1.sign[i] = 0; |
| 234 | ah->meas2.sign[i] = 0; |
| 235 | ah->meas3.sign[i] = 0; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 236 | } |
| 237 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 238 | ah->cal_samples = 0; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 239 | } |
| 240 | |
Sujith | 379f044 | 2009-04-13 21:56:48 +0530 | [diff] [blame] | 241 | static bool ath9k_hw_per_calibration(struct ath_hw *ah, |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 242 | struct ath9k_channel *ichan, |
| 243 | u8 rxchainmask, |
Sujith | cbfe946 | 2009-04-13 21:56:56 +0530 | [diff] [blame] | 244 | struct ath9k_cal_list *currCal) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 245 | { |
Sujith | 379f044 | 2009-04-13 21:56:48 +0530 | [diff] [blame] | 246 | bool iscaldone = false; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 247 | |
| 248 | if (currCal->calState == CAL_RUNNING) { |
| 249 | if (!(REG_READ(ah, AR_PHY_TIMING_CTRL4(0)) & |
| 250 | AR_PHY_TIMING_CTRL4_DO_CAL)) { |
| 251 | |
| 252 | currCal->calData->calCollect(ah); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 253 | ah->cal_samples++; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 254 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 255 | if (ah->cal_samples >= currCal->calData->calNumSamples) { |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 256 | int i, numChains = 0; |
| 257 | for (i = 0; i < AR5416_MAX_CHAINS; i++) { |
| 258 | if (rxchainmask & (1 << i)) |
| 259 | numChains++; |
| 260 | } |
| 261 | |
| 262 | currCal->calData->calPostProc(ah, numChains); |
| 263 | ichan->CalValid |= currCal->calData->calType; |
| 264 | currCal->calState = CAL_DONE; |
Sujith | 379f044 | 2009-04-13 21:56:48 +0530 | [diff] [blame] | 265 | iscaldone = true; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 266 | } else { |
| 267 | ath9k_hw_setup_calibration(ah, currCal); |
| 268 | } |
| 269 | } |
| 270 | } else if (!(ichan->CalValid & currCal->calData->calType)) { |
| 271 | ath9k_hw_reset_calibration(ah, currCal); |
| 272 | } |
Sujith | 379f044 | 2009-04-13 21:56:48 +0530 | [diff] [blame] | 273 | |
| 274 | return iscaldone; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 275 | } |
| 276 | |
Luis R. Rodriguez | c9e27d9 | 2008-12-23 15:58:42 -0800 | [diff] [blame] | 277 | /* Assumes you are talking about the currently configured channel */ |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 278 | static bool ath9k_hw_iscal_supported(struct ath_hw *ah, |
Sujith | cbfe946 | 2009-04-13 21:56:56 +0530 | [diff] [blame] | 279 | enum ath9k_cal_types calType) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 280 | { |
Luis R. Rodriguez | c9e27d9 | 2008-12-23 15:58:42 -0800 | [diff] [blame] | 281 | struct ieee80211_conf *conf = &ah->ah_sc->hw->conf; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 282 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 283 | switch (calType & ah->supp_cals) { |
Luis R. Rodriguez | c9e27d9 | 2008-12-23 15:58:42 -0800 | [diff] [blame] | 284 | case IQ_MISMATCH_CAL: /* Both 2 GHz and 5 GHz support OFDM */ |
| 285 | return true; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 286 | case ADC_GAIN_CAL: |
| 287 | case ADC_DC_CAL: |
Sujith | a451aa6 | 2009-04-13 21:56:43 +0530 | [diff] [blame] | 288 | if (!(conf->channel->band == IEEE80211_BAND_2GHZ && |
| 289 | conf_is_ht20(conf))) |
Luis R. Rodriguez | c9e27d9 | 2008-12-23 15:58:42 -0800 | [diff] [blame] | 290 | return true; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 291 | break; |
| 292 | } |
Luis R. Rodriguez | c9e27d9 | 2008-12-23 15:58:42 -0800 | [diff] [blame] | 293 | return false; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 294 | } |
| 295 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 296 | static void ath9k_hw_iqcal_collect(struct ath_hw *ah) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 297 | { |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 298 | int i; |
| 299 | |
| 300 | for (i = 0; i < AR5416_MAX_CHAINS; i++) { |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 301 | ah->totalPowerMeasI[i] += |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 302 | REG_READ(ah, AR_PHY_CAL_MEAS_0(i)); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 303 | ah->totalPowerMeasQ[i] += |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 304 | REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 305 | ah->totalIqCorrMeas[i] += |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 306 | (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i)); |
| 307 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, |
| 308 | "%d: Chn %d pmi=0x%08x;pmq=0x%08x;iqcm=0x%08x;\n", |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 309 | ah->cal_samples, i, ah->totalPowerMeasI[i], |
| 310 | ah->totalPowerMeasQ[i], |
| 311 | ah->totalIqCorrMeas[i]); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 312 | } |
| 313 | } |
| 314 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 315 | static void ath9k_hw_adc_gaincal_collect(struct ath_hw *ah) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 316 | { |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 317 | int i; |
| 318 | |
| 319 | for (i = 0; i < AR5416_MAX_CHAINS; i++) { |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 320 | ah->totalAdcIOddPhase[i] += |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 321 | REG_READ(ah, AR_PHY_CAL_MEAS_0(i)); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 322 | ah->totalAdcIEvenPhase[i] += |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 323 | REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 324 | ah->totalAdcQOddPhase[i] += |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 325 | REG_READ(ah, AR_PHY_CAL_MEAS_2(i)); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 326 | ah->totalAdcQEvenPhase[i] += |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 327 | REG_READ(ah, AR_PHY_CAL_MEAS_3(i)); |
| 328 | |
| 329 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, |
| 330 | "%d: Chn %d oddi=0x%08x; eveni=0x%08x; " |
| 331 | "oddq=0x%08x; evenq=0x%08x;\n", |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 332 | ah->cal_samples, i, |
| 333 | ah->totalAdcIOddPhase[i], |
| 334 | ah->totalAdcIEvenPhase[i], |
| 335 | ah->totalAdcQOddPhase[i], |
| 336 | ah->totalAdcQEvenPhase[i]); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 337 | } |
| 338 | } |
| 339 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 340 | static void ath9k_hw_adc_dccal_collect(struct ath_hw *ah) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 341 | { |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 342 | int i; |
| 343 | |
| 344 | for (i = 0; i < AR5416_MAX_CHAINS; i++) { |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 345 | ah->totalAdcDcOffsetIOddPhase[i] += |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 346 | (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_0(i)); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 347 | ah->totalAdcDcOffsetIEvenPhase[i] += |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 348 | (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 349 | ah->totalAdcDcOffsetQOddPhase[i] += |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 350 | (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i)); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 351 | ah->totalAdcDcOffsetQEvenPhase[i] += |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 352 | (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_3(i)); |
| 353 | |
| 354 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, |
| 355 | "%d: Chn %d oddi=0x%08x; eveni=0x%08x; " |
| 356 | "oddq=0x%08x; evenq=0x%08x;\n", |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 357 | ah->cal_samples, i, |
| 358 | ah->totalAdcDcOffsetIOddPhase[i], |
| 359 | ah->totalAdcDcOffsetIEvenPhase[i], |
| 360 | ah->totalAdcDcOffsetQOddPhase[i], |
| 361 | ah->totalAdcDcOffsetQEvenPhase[i]); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 362 | } |
| 363 | } |
| 364 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 365 | static void ath9k_hw_iqcalibrate(struct ath_hw *ah, u8 numChains) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 366 | { |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 367 | u32 powerMeasQ, powerMeasI, iqCorrMeas; |
| 368 | u32 qCoffDenom, iCoffDenom; |
| 369 | int32_t qCoff, iCoff; |
| 370 | int iqCorrNeg, i; |
| 371 | |
| 372 | for (i = 0; i < numChains; i++) { |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 373 | powerMeasI = ah->totalPowerMeasI[i]; |
| 374 | powerMeasQ = ah->totalPowerMeasQ[i]; |
| 375 | iqCorrMeas = ah->totalIqCorrMeas[i]; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 376 | |
| 377 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, |
| 378 | "Starting IQ Cal and Correction for Chain %d\n", |
| 379 | i); |
| 380 | |
| 381 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, |
| 382 | "Orignal: Chn %diq_corr_meas = 0x%08x\n", |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 383 | i, ah->totalIqCorrMeas[i]); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 384 | |
| 385 | iqCorrNeg = 0; |
| 386 | |
| 387 | if (iqCorrMeas > 0x80000000) { |
| 388 | iqCorrMeas = (0xffffffff - iqCorrMeas) + 1; |
| 389 | iqCorrNeg = 1; |
| 390 | } |
| 391 | |
| 392 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, |
| 393 | "Chn %d pwr_meas_i = 0x%08x\n", i, powerMeasI); |
| 394 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, |
| 395 | "Chn %d pwr_meas_q = 0x%08x\n", i, powerMeasQ); |
| 396 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, "iqCorrNeg is 0x%08x\n", |
| 397 | iqCorrNeg); |
| 398 | |
| 399 | iCoffDenom = (powerMeasI / 2 + powerMeasQ / 2) / 128; |
| 400 | qCoffDenom = powerMeasQ / 64; |
| 401 | |
| 402 | if (powerMeasQ != 0) { |
| 403 | iCoff = iqCorrMeas / iCoffDenom; |
| 404 | qCoff = powerMeasI / qCoffDenom - 64; |
| 405 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, |
| 406 | "Chn %d iCoff = 0x%08x\n", i, iCoff); |
| 407 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, |
| 408 | "Chn %d qCoff = 0x%08x\n", i, qCoff); |
| 409 | |
| 410 | iCoff = iCoff & 0x3f; |
| 411 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, |
| 412 | "New: Chn %d iCoff = 0x%08x\n", i, iCoff); |
| 413 | if (iqCorrNeg == 0x0) |
| 414 | iCoff = 0x40 - iCoff; |
| 415 | |
| 416 | if (qCoff > 15) |
| 417 | qCoff = 15; |
| 418 | else if (qCoff <= -16) |
| 419 | qCoff = 16; |
| 420 | |
| 421 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, |
| 422 | "Chn %d : iCoff = 0x%x qCoff = 0x%x\n", |
| 423 | i, iCoff, qCoff); |
| 424 | |
| 425 | REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i), |
| 426 | AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF, |
| 427 | iCoff); |
| 428 | REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i), |
| 429 | AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF, |
| 430 | qCoff); |
| 431 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, |
| 432 | "IQ Cal and Correction done for Chain %d\n", |
| 433 | i); |
| 434 | } |
| 435 | } |
| 436 | |
| 437 | REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0), |
| 438 | AR_PHY_TIMING_CTRL4_IQCORR_ENABLE); |
| 439 | } |
| 440 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 441 | static void ath9k_hw_adc_gaincal_calibrate(struct ath_hw *ah, u8 numChains) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 442 | { |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 443 | u32 iOddMeasOffset, iEvenMeasOffset, qOddMeasOffset, qEvenMeasOffset; |
| 444 | u32 qGainMismatch, iGainMismatch, val, i; |
| 445 | |
| 446 | for (i = 0; i < numChains; i++) { |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 447 | iOddMeasOffset = ah->totalAdcIOddPhase[i]; |
| 448 | iEvenMeasOffset = ah->totalAdcIEvenPhase[i]; |
| 449 | qOddMeasOffset = ah->totalAdcQOddPhase[i]; |
| 450 | qEvenMeasOffset = ah->totalAdcQEvenPhase[i]; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 451 | |
| 452 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, |
| 453 | "Starting ADC Gain Cal for Chain %d\n", i); |
| 454 | |
| 455 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, |
| 456 | "Chn %d pwr_meas_odd_i = 0x%08x\n", i, |
| 457 | iOddMeasOffset); |
| 458 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, |
| 459 | "Chn %d pwr_meas_even_i = 0x%08x\n", i, |
| 460 | iEvenMeasOffset); |
| 461 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, |
| 462 | "Chn %d pwr_meas_odd_q = 0x%08x\n", i, |
| 463 | qOddMeasOffset); |
| 464 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, |
| 465 | "Chn %d pwr_meas_even_q = 0x%08x\n", i, |
| 466 | qEvenMeasOffset); |
| 467 | |
| 468 | if (iOddMeasOffset != 0 && qEvenMeasOffset != 0) { |
| 469 | iGainMismatch = |
| 470 | ((iEvenMeasOffset * 32) / |
| 471 | iOddMeasOffset) & 0x3f; |
| 472 | qGainMismatch = |
| 473 | ((qOddMeasOffset * 32) / |
| 474 | qEvenMeasOffset) & 0x3f; |
| 475 | |
| 476 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, |
| 477 | "Chn %d gain_mismatch_i = 0x%08x\n", i, |
| 478 | iGainMismatch); |
| 479 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, |
| 480 | "Chn %d gain_mismatch_q = 0x%08x\n", i, |
| 481 | qGainMismatch); |
| 482 | |
| 483 | val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i)); |
| 484 | val &= 0xfffff000; |
| 485 | val |= (qGainMismatch) | (iGainMismatch << 6); |
| 486 | REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val); |
| 487 | |
| 488 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, |
| 489 | "ADC Gain Cal done for Chain %d\n", i); |
| 490 | } |
| 491 | } |
| 492 | |
| 493 | REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0), |
| 494 | REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0)) | |
| 495 | AR_PHY_NEW_ADC_GAIN_CORR_ENABLE); |
| 496 | } |
| 497 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 498 | static void ath9k_hw_adc_dccal_calibrate(struct ath_hw *ah, u8 numChains) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 499 | { |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 500 | u32 iOddMeasOffset, iEvenMeasOffset, val, i; |
| 501 | int32_t qOddMeasOffset, qEvenMeasOffset, qDcMismatch, iDcMismatch; |
Sujith | cbfe946 | 2009-04-13 21:56:56 +0530 | [diff] [blame] | 502 | const struct ath9k_percal_data *calData = |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 503 | ah->cal_list_curr->calData; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 504 | u32 numSamples = |
| 505 | (1 << (calData->calCountMax + 5)) * calData->calNumSamples; |
| 506 | |
| 507 | for (i = 0; i < numChains; i++) { |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 508 | iOddMeasOffset = ah->totalAdcDcOffsetIOddPhase[i]; |
| 509 | iEvenMeasOffset = ah->totalAdcDcOffsetIEvenPhase[i]; |
| 510 | qOddMeasOffset = ah->totalAdcDcOffsetQOddPhase[i]; |
| 511 | qEvenMeasOffset = ah->totalAdcDcOffsetQEvenPhase[i]; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 512 | |
| 513 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, |
| 514 | "Starting ADC DC Offset Cal for Chain %d\n", i); |
| 515 | |
| 516 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, |
| 517 | "Chn %d pwr_meas_odd_i = %d\n", i, |
| 518 | iOddMeasOffset); |
| 519 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, |
| 520 | "Chn %d pwr_meas_even_i = %d\n", i, |
| 521 | iEvenMeasOffset); |
| 522 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, |
| 523 | "Chn %d pwr_meas_odd_q = %d\n", i, |
| 524 | qOddMeasOffset); |
| 525 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, |
| 526 | "Chn %d pwr_meas_even_q = %d\n", i, |
| 527 | qEvenMeasOffset); |
| 528 | |
| 529 | iDcMismatch = (((iEvenMeasOffset - iOddMeasOffset) * 2) / |
| 530 | numSamples) & 0x1ff; |
| 531 | qDcMismatch = (((qOddMeasOffset - qEvenMeasOffset) * 2) / |
| 532 | numSamples) & 0x1ff; |
| 533 | |
| 534 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, |
| 535 | "Chn %d dc_offset_mismatch_i = 0x%08x\n", i, |
| 536 | iDcMismatch); |
| 537 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, |
| 538 | "Chn %d dc_offset_mismatch_q = 0x%08x\n", i, |
| 539 | qDcMismatch); |
| 540 | |
| 541 | val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i)); |
| 542 | val &= 0xc0000fff; |
| 543 | val |= (qDcMismatch << 12) | (iDcMismatch << 21); |
| 544 | REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val); |
| 545 | |
| 546 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, |
| 547 | "ADC DC Offset Cal done for Chain %d\n", i); |
| 548 | } |
| 549 | |
| 550 | REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0), |
| 551 | REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0)) | |
| 552 | AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE); |
| 553 | } |
| 554 | |
Luis R. Rodriguez | c9e27d9 | 2008-12-23 15:58:42 -0800 | [diff] [blame] | 555 | /* This is done for the currently configured channel */ |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 556 | bool ath9k_hw_reset_calvalid(struct ath_hw *ah) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 557 | { |
Luis R. Rodriguez | c9e27d9 | 2008-12-23 15:58:42 -0800 | [diff] [blame] | 558 | struct ieee80211_conf *conf = &ah->ah_sc->hw->conf; |
Sujith | cbfe946 | 2009-04-13 21:56:56 +0530 | [diff] [blame] | 559 | struct ath9k_cal_list *currCal = ah->cal_list_curr; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 560 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 561 | if (!ah->curchan) |
Luis R. Rodriguez | c9e27d9 | 2008-12-23 15:58:42 -0800 | [diff] [blame] | 562 | return true; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 563 | |
| 564 | if (!AR_SREV_9100(ah) && !AR_SREV_9160_10_OR_LATER(ah)) |
Luis R. Rodriguez | c9e27d9 | 2008-12-23 15:58:42 -0800 | [diff] [blame] | 565 | return true; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 566 | |
| 567 | if (currCal == NULL) |
Luis R. Rodriguez | c9e27d9 | 2008-12-23 15:58:42 -0800 | [diff] [blame] | 568 | return true; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 569 | |
| 570 | if (currCal->calState != CAL_DONE) { |
| 571 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, |
Sujith | 04bd463 | 2008-11-28 22:18:05 +0530 | [diff] [blame] | 572 | "Calibration state incorrect, %d\n", |
| 573 | currCal->calState); |
Luis R. Rodriguez | c9e27d9 | 2008-12-23 15:58:42 -0800 | [diff] [blame] | 574 | return true; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 575 | } |
| 576 | |
Luis R. Rodriguez | c9e27d9 | 2008-12-23 15:58:42 -0800 | [diff] [blame] | 577 | if (!ath9k_hw_iscal_supported(ah, currCal->calData->calType)) |
| 578 | return true; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 579 | |
| 580 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, |
Luis R. Rodriguez | c9e27d9 | 2008-12-23 15:58:42 -0800 | [diff] [blame] | 581 | "Resetting Cal %d state for channel %u\n", |
| 582 | currCal->calData->calType, conf->channel->center_freq); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 583 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 584 | ah->curchan->CalValid &= ~currCal->calData->calType; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 585 | currCal->calState = CAL_WAITING; |
| 586 | |
Luis R. Rodriguez | c9e27d9 | 2008-12-23 15:58:42 -0800 | [diff] [blame] | 587 | return false; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 588 | } |
| 589 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 590 | void ath9k_hw_start_nfcal(struct ath_hw *ah) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 591 | { |
| 592 | REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, |
| 593 | AR_PHY_AGC_CONTROL_ENABLE_NF); |
| 594 | REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, |
| 595 | AR_PHY_AGC_CONTROL_NO_UPDATE_NF); |
| 596 | REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF); |
| 597 | } |
| 598 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 599 | void ath9k_hw_loadnf(struct ath_hw *ah, struct ath9k_channel *chan) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 600 | { |
| 601 | struct ath9k_nfcal_hist *h; |
| 602 | int i, j; |
| 603 | int32_t val; |
| 604 | const u32 ar5416_cca_regs[6] = { |
| 605 | AR_PHY_CCA, |
| 606 | AR_PHY_CH1_CCA, |
| 607 | AR_PHY_CH2_CCA, |
| 608 | AR_PHY_EXT_CCA, |
| 609 | AR_PHY_CH1_EXT_CCA, |
| 610 | AR_PHY_CH2_EXT_CCA |
| 611 | }; |
Senthil Balasubramanian | ce143bb | 2009-09-17 09:27:33 +0530 | [diff] [blame^] | 612 | u8 chainmask, rx_chain_status; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 613 | |
Senthil Balasubramanian | ce143bb | 2009-09-17 09:27:33 +0530 | [diff] [blame^] | 614 | rx_chain_status = REG_READ(ah, AR_PHY_RX_CHAINMASK); |
Sujith | 5dad40c | 2009-01-23 11:20:55 +0530 | [diff] [blame] | 615 | if (AR_SREV_9285(ah)) |
| 616 | chainmask = 0x9; |
Senthil Balasubramanian | ce143bb | 2009-09-17 09:27:33 +0530 | [diff] [blame^] | 617 | else if (AR_SREV_9280(ah) || AR_SREV_9287(ah)) { |
| 618 | if ((rx_chain_status & 0x2) || (rx_chain_status & 0x4)) |
| 619 | chainmask = 0x1B; |
| 620 | else |
| 621 | chainmask = 0x09; |
| 622 | } else { |
| 623 | if (rx_chain_status & 0x4) |
| 624 | chainmask = 0x3F; |
| 625 | else if (rx_chain_status & 0x2) |
| 626 | chainmask = 0x1B; |
| 627 | else |
| 628 | chainmask = 0x09; |
| 629 | } |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 630 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 631 | h = ah->nfCalHist; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 632 | |
| 633 | for (i = 0; i < NUM_NF_READINGS; i++) { |
| 634 | if (chainmask & (1 << i)) { |
| 635 | val = REG_READ(ah, ar5416_cca_regs[i]); |
| 636 | val &= 0xFFFFFE00; |
| 637 | val |= (((u32) (h[i].privNF) << 1) & 0x1ff); |
| 638 | REG_WRITE(ah, ar5416_cca_regs[i], val); |
| 639 | } |
| 640 | } |
| 641 | |
| 642 | REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, |
| 643 | AR_PHY_AGC_CONTROL_ENABLE_NF); |
| 644 | REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, |
| 645 | AR_PHY_AGC_CONTROL_NO_UPDATE_NF); |
| 646 | REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF); |
| 647 | |
| 648 | for (j = 0; j < 1000; j++) { |
| 649 | if ((REG_READ(ah, AR_PHY_AGC_CONTROL) & |
| 650 | AR_PHY_AGC_CONTROL_NF) == 0) |
| 651 | break; |
| 652 | udelay(10); |
| 653 | } |
| 654 | |
| 655 | for (i = 0; i < NUM_NF_READINGS; i++) { |
| 656 | if (chainmask & (1 << i)) { |
| 657 | val = REG_READ(ah, ar5416_cca_regs[i]); |
| 658 | val &= 0xFFFFFE00; |
| 659 | val |= (((u32) (-50) << 1) & 0x1ff); |
| 660 | REG_WRITE(ah, ar5416_cca_regs[i], val); |
| 661 | } |
| 662 | } |
| 663 | } |
| 664 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 665 | int16_t ath9k_hw_getnf(struct ath_hw *ah, |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 666 | struct ath9k_channel *chan) |
| 667 | { |
| 668 | int16_t nf, nfThresh; |
| 669 | int16_t nfarray[NUM_NF_READINGS] = { 0 }; |
| 670 | struct ath9k_nfcal_hist *h; |
Luis R. Rodriguez | 76061ab | 2008-12-23 15:58:41 -0800 | [diff] [blame] | 671 | struct ieee80211_channel *c = chan->chan; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 672 | |
| 673 | chan->channelFlags &= (~CHANNEL_CW_INT); |
| 674 | if (REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) { |
| 675 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, |
Sujith | 04bd463 | 2008-11-28 22:18:05 +0530 | [diff] [blame] | 676 | "NF did not complete in calibration window\n"); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 677 | nf = 0; |
| 678 | chan->rawNoiseFloor = nf; |
| 679 | return chan->rawNoiseFloor; |
| 680 | } else { |
| 681 | ath9k_hw_do_getnf(ah, nfarray); |
| 682 | nf = nfarray[0]; |
Luis R. Rodriguez | 76061ab | 2008-12-23 15:58:41 -0800 | [diff] [blame] | 683 | if (getNoiseFloorThresh(ah, c->band, &nfThresh) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 684 | && nf > nfThresh) { |
| 685 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, |
Sujith | 04bd463 | 2008-11-28 22:18:05 +0530 | [diff] [blame] | 686 | "noise floor failed detected; " |
| 687 | "detected %d, threshold %d\n", |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 688 | nf, nfThresh); |
| 689 | chan->channelFlags |= CHANNEL_CW_INT; |
| 690 | } |
| 691 | } |
| 692 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 693 | h = ah->nfCalHist; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 694 | |
| 695 | ath9k_hw_update_nfcal_hist_buffer(h, nfarray); |
| 696 | chan->rawNoiseFloor = h[0].privNF; |
| 697 | |
| 698 | return chan->rawNoiseFloor; |
| 699 | } |
| 700 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 701 | void ath9k_init_nfcal_hist_buffer(struct ath_hw *ah) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 702 | { |
| 703 | int i, j; |
Senthil Balasubramanian | a59b5a5 | 2009-07-14 20:17:07 -0400 | [diff] [blame] | 704 | s16 noise_floor; |
| 705 | |
| 706 | if (AR_SREV_9280(ah)) |
| 707 | noise_floor = AR_PHY_CCA_MAX_AR9280_GOOD_VALUE; |
| 708 | else if (AR_SREV_9285(ah)) |
| 709 | noise_floor = AR_PHY_CCA_MAX_AR9285_GOOD_VALUE; |
Vivek Natarajan | 6170cd5 | 2009-09-17 09:24:24 +0530 | [diff] [blame] | 710 | else if (AR_SREV_9287(ah)) |
| 711 | noise_floor = AR_PHY_CCA_MAX_AR9287_GOOD_VALUE; |
Senthil Balasubramanian | a59b5a5 | 2009-07-14 20:17:07 -0400 | [diff] [blame] | 712 | else |
| 713 | noise_floor = AR_PHY_CCA_MAX_AR5416_GOOD_VALUE; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 714 | |
| 715 | for (i = 0; i < NUM_NF_READINGS; i++) { |
| 716 | ah->nfCalHist[i].currIndex = 0; |
Senthil Balasubramanian | a59b5a5 | 2009-07-14 20:17:07 -0400 | [diff] [blame] | 717 | ah->nfCalHist[i].privNF = noise_floor; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 718 | ah->nfCalHist[i].invalidNFcount = |
| 719 | AR_PHY_CCA_FILTERWINDOW_LENGTH; |
| 720 | for (j = 0; j < ATH9K_NF_CAL_HIST_MAX; j++) { |
Senthil Balasubramanian | a59b5a5 | 2009-07-14 20:17:07 -0400 | [diff] [blame] | 721 | ah->nfCalHist[i].nfCalBuffer[j] = noise_floor; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 722 | } |
| 723 | } |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 724 | } |
| 725 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 726 | s16 ath9k_hw_getchan_noise(struct ath_hw *ah, struct ath9k_channel *chan) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 727 | { |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 728 | s16 nf; |
| 729 | |
Luis R. Rodriguez | 5f8e077 | 2009-01-22 15:16:48 -0800 | [diff] [blame] | 730 | if (chan->rawNoiseFloor == 0) |
Luis R. Rodriguez | e56db71 | 2008-12-23 15:58:47 -0800 | [diff] [blame] | 731 | nf = -96; |
| 732 | else |
Luis R. Rodriguez | 5f8e077 | 2009-01-22 15:16:48 -0800 | [diff] [blame] | 733 | nf = chan->rawNoiseFloor; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 734 | |
| 735 | if (!ath9k_hw_nf_in_range(ah, nf)) |
| 736 | nf = ATH_DEFAULT_NOISE_FLOOR; |
| 737 | |
| 738 | return nf; |
| 739 | } |
| 740 | |
Senthil Balasubramanian | 8bd1d07 | 2009-02-12 13:57:03 +0530 | [diff] [blame] | 741 | static void ath9k_olc_temp_compensation(struct ath_hw *ah) |
| 742 | { |
| 743 | u32 rddata, i; |
Vivek Natarajan | db91f2e | 2009-08-14 11:27:16 +0530 | [diff] [blame] | 744 | int delta, currPDADC, regval, slope; |
Senthil Balasubramanian | 8bd1d07 | 2009-02-12 13:57:03 +0530 | [diff] [blame] | 745 | |
| 746 | rddata = REG_READ(ah, AR_PHY_TX_PWRCTRL4); |
Senthil Balasubramanian | 8bd1d07 | 2009-02-12 13:57:03 +0530 | [diff] [blame] | 747 | currPDADC = MS(rddata, AR_PHY_TX_PWRCTRL_PD_AVG_OUT); |
| 748 | |
Senthil Balasubramanian | 8bd1d07 | 2009-02-12 13:57:03 +0530 | [diff] [blame] | 749 | |
Vivek Natarajan | db91f2e | 2009-08-14 11:27:16 +0530 | [diff] [blame] | 750 | if (OLC_FOR_AR9287_10_LATER) { |
| 751 | if (ah->initPDADC == 0 || currPDADC == 0) { |
| 752 | return; |
| 753 | } else { |
| 754 | slope = ah->eep_ops->get_eeprom(ah, EEP_TEMPSENSE_SLOPE); |
| 755 | if (slope == 0) |
| 756 | delta = 0; |
| 757 | else |
| 758 | delta = ((currPDADC - ah->initPDADC)*4) / slope; |
| 759 | REG_RMW_FIELD(ah, AR_PHY_CH0_TX_PWRCTRL11, |
| 760 | AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP, delta); |
| 761 | REG_RMW_FIELD(ah, AR_PHY_CH1_TX_PWRCTRL11, |
| 762 | AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP, delta); |
| 763 | } |
| 764 | } else { |
| 765 | if (ah->eep_ops->get_eeprom(ah, EEP_DAC_HPWR_5G)) |
| 766 | delta = (currPDADC - ah->initPDADC + 4) / 8; |
| 767 | else |
| 768 | delta = (currPDADC - ah->initPDADC + 5) / 10; |
Senthil Balasubramanian | 8bd1d07 | 2009-02-12 13:57:03 +0530 | [diff] [blame] | 769 | |
Vivek Natarajan | db91f2e | 2009-08-14 11:27:16 +0530 | [diff] [blame] | 770 | if (delta != ah->PDADCdelta) { |
| 771 | ah->PDADCdelta = delta; |
| 772 | for (i = 1; i < AR9280_TX_GAIN_TABLE_SIZE; i++) { |
| 773 | regval = ah->originalGain[i] - delta; |
| 774 | if (regval < 0) |
| 775 | regval = 0; |
| 776 | |
| 777 | REG_RMW_FIELD(ah, AR_PHY_TX_GAIN_TBL1 + i * 4, |
| 778 | AR_PHY_TX_GAIN, regval); |
| 779 | } |
Senthil Balasubramanian | 8bd1d07 | 2009-02-12 13:57:03 +0530 | [diff] [blame] | 780 | } |
| 781 | } |
| 782 | } |
| 783 | |
Luis R. Rodriguez | d7e7d22 | 2009-08-03 23:14:12 -0400 | [diff] [blame] | 784 | static void ath9k_hw_9271_pa_cal(struct ath_hw *ah) |
| 785 | { |
| 786 | u32 regVal; |
| 787 | unsigned int i; |
| 788 | u32 regList [][2] = { |
| 789 | { 0x786c, 0 }, |
| 790 | { 0x7854, 0 }, |
| 791 | { 0x7820, 0 }, |
| 792 | { 0x7824, 0 }, |
| 793 | { 0x7868, 0 }, |
| 794 | { 0x783c, 0 }, |
| 795 | { 0x7838, 0 } , |
| 796 | { 0x7828, 0 } , |
| 797 | }; |
| 798 | |
| 799 | for (i = 0; i < ARRAY_SIZE(regList); i++) |
| 800 | regList[i][1] = REG_READ(ah, regList[i][0]); |
| 801 | |
| 802 | regVal = REG_READ(ah, 0x7834); |
| 803 | regVal &= (~(0x1)); |
| 804 | REG_WRITE(ah, 0x7834, regVal); |
| 805 | regVal = REG_READ(ah, 0x9808); |
| 806 | regVal |= (0x1 << 27); |
| 807 | REG_WRITE(ah, 0x9808, regVal); |
| 808 | |
| 809 | /* 786c,b23,1, pwddac=1 */ |
| 810 | REG_RMW_FIELD(ah, AR9285_AN_TOP3, AR9285_AN_TOP3_PWDDAC, 1); |
| 811 | /* 7854, b5,1, pdrxtxbb=1 */ |
| 812 | REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDRXTXBB1, 1); |
| 813 | /* 7854, b7,1, pdv2i=1 */ |
| 814 | REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDV2I, 1); |
| 815 | /* 7854, b8,1, pddacinterface=1 */ |
| 816 | REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDDACIF, 1); |
| 817 | /* 7824,b12,0, offcal=0 */ |
| 818 | REG_RMW_FIELD(ah, AR9285_AN_RF2G2, AR9285_AN_RF2G2_OFFCAL, 0); |
| 819 | /* 7838, b1,0, pwddb=0 */ |
| 820 | REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PWDDB, 0); |
| 821 | /* 7820,b11,0, enpacal=0 */ |
| 822 | REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_ENPACAL, 0); |
| 823 | /* 7820,b25,1, pdpadrv1=0 */ |
| 824 | REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV1, 0); |
| 825 | /* 7820,b24,0, pdpadrv2=0 */ |
| 826 | REG_RMW_FIELD(ah, AR9285_AN_RF2G1,AR9285_AN_RF2G1_PDPADRV2,0); |
| 827 | /* 7820,b23,0, pdpaout=0 */ |
| 828 | REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPAOUT, 0); |
| 829 | /* 783c,b14-16,7, padrvgn2tab_0=7 */ |
| 830 | REG_RMW_FIELD(ah, AR9285_AN_RF2G8,AR9285_AN_RF2G8_PADRVGN2TAB0, 7); |
| 831 | /* |
| 832 | * 7838,b29-31,0, padrvgn1tab_0=0 |
| 833 | * does not matter since we turn it off |
| 834 | */ |
| 835 | REG_RMW_FIELD(ah, AR9285_AN_RF2G7,AR9285_AN_RF2G7_PADRVGN2TAB0, 0); |
| 836 | |
| 837 | REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9271_AN_RF2G3_CCOMP, 0xfff); |
| 838 | |
| 839 | /* Set: |
| 840 | * localmode=1,bmode=1,bmoderxtx=1,synthon=1, |
| 841 | * txon=1,paon=1,oscon=1,synthon_force=1 |
| 842 | */ |
| 843 | REG_WRITE(ah, AR9285_AN_TOP2, 0xca0358a0); |
| 844 | udelay(30); |
| 845 | REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9271_AN_RF2G6_OFFS, 0); |
| 846 | |
| 847 | /* find off_6_1; */ |
| 848 | for (i = 6; i >= 0; i--) { |
| 849 | regVal = REG_READ(ah, 0x7834); |
| 850 | regVal |= (1 << (20 + i)); |
| 851 | REG_WRITE(ah, 0x7834, regVal); |
| 852 | udelay(1); |
| 853 | //regVal = REG_READ(ah, 0x7834); |
| 854 | regVal &= (~(0x1 << (20 + i))); |
| 855 | regVal |= (MS(REG_READ(ah, 0x7840), AR9285_AN_RXTXBB1_SPARE9) |
| 856 | << (20 + i)); |
| 857 | REG_WRITE(ah, 0x7834, regVal); |
| 858 | } |
| 859 | |
| 860 | /* Empirical offset correction */ |
| 861 | #if 0 |
| 862 | REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9271_AN_RF2G6_OFFS, 0x20); |
| 863 | #endif |
| 864 | |
| 865 | regVal = REG_READ(ah, 0x7834); |
| 866 | regVal |= 0x1; |
| 867 | REG_WRITE(ah, 0x7834, regVal); |
| 868 | regVal = REG_READ(ah, 0x9808); |
| 869 | regVal &= (~(0x1 << 27)); |
| 870 | REG_WRITE(ah, 0x9808, regVal); |
| 871 | |
| 872 | for (i = 0; i < ARRAY_SIZE(regList); i++) |
| 873 | REG_WRITE(ah, regList[i][0], regList[i][1]); |
| 874 | } |
| 875 | |
Sujith | a13883b | 2009-08-26 08:39:40 +0530 | [diff] [blame] | 876 | static inline void ath9k_hw_9285_pa_cal(struct ath_hw *ah, bool is_reset) |
Senthil Balasubramanian | e759407 | 2008-12-08 19:43:48 +0530 | [diff] [blame] | 877 | { |
| 878 | |
| 879 | u32 regVal; |
| 880 | int i, offset, offs_6_1, offs_0; |
| 881 | u32 ccomp_org, reg_field; |
| 882 | u32 regList[][2] = { |
| 883 | { 0x786c, 0 }, |
| 884 | { 0x7854, 0 }, |
| 885 | { 0x7820, 0 }, |
| 886 | { 0x7824, 0 }, |
| 887 | { 0x7868, 0 }, |
| 888 | { 0x783c, 0 }, |
| 889 | { 0x7838, 0 }, |
| 890 | }; |
| 891 | |
Sujith | a13883b | 2009-08-26 08:39:40 +0530 | [diff] [blame] | 892 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, "Running PA Calibration\n"); |
| 893 | |
Sujith | 20caf0d | 2009-08-26 08:39:52 +0530 | [diff] [blame] | 894 | /* PA CAL is not needed for high power solution */ |
| 895 | if (ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE) == |
| 896 | AR5416_EEP_TXGAIN_HIGH_POWER) |
| 897 | return; |
| 898 | |
Senthil Balasubramanian | e759407 | 2008-12-08 19:43:48 +0530 | [diff] [blame] | 899 | if (AR_SREV_9285_11(ah)) { |
| 900 | REG_WRITE(ah, AR9285_AN_TOP4, (AR9285_AN_TOP4_DEFAULT | 0x14)); |
| 901 | udelay(10); |
| 902 | } |
| 903 | |
| 904 | for (i = 0; i < ARRAY_SIZE(regList); i++) |
| 905 | regList[i][1] = REG_READ(ah, regList[i][0]); |
| 906 | |
| 907 | regVal = REG_READ(ah, 0x7834); |
| 908 | regVal &= (~(0x1)); |
| 909 | REG_WRITE(ah, 0x7834, regVal); |
| 910 | regVal = REG_READ(ah, 0x9808); |
| 911 | regVal |= (0x1 << 27); |
| 912 | REG_WRITE(ah, 0x9808, regVal); |
| 913 | |
| 914 | REG_RMW_FIELD(ah, AR9285_AN_TOP3, AR9285_AN_TOP3_PWDDAC, 1); |
| 915 | REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDRXTXBB1, 1); |
| 916 | REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDV2I, 1); |
| 917 | REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDDACIF, 1); |
| 918 | REG_RMW_FIELD(ah, AR9285_AN_RF2G2, AR9285_AN_RF2G2_OFFCAL, 0); |
| 919 | REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PWDDB, 0); |
| 920 | REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_ENPACAL, 0); |
Sujith | 0abb096 | 2009-08-26 08:39:50 +0530 | [diff] [blame] | 921 | REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV1, 0); |
Senthil Balasubramanian | e759407 | 2008-12-08 19:43:48 +0530 | [diff] [blame] | 922 | REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV2, 0); |
| 923 | REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPAOUT, 0); |
| 924 | REG_RMW_FIELD(ah, AR9285_AN_RF2G8, AR9285_AN_RF2G8_PADRVGN2TAB0, 7); |
| 925 | REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PADRVGN2TAB0, 0); |
| 926 | ccomp_org = MS(REG_READ(ah, AR9285_AN_RF2G6), AR9285_AN_RF2G6_CCOMP); |
Sujith | 0abb096 | 2009-08-26 08:39:50 +0530 | [diff] [blame] | 927 | REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_CCOMP, 0xf); |
Senthil Balasubramanian | e759407 | 2008-12-08 19:43:48 +0530 | [diff] [blame] | 928 | |
| 929 | REG_WRITE(ah, AR9285_AN_TOP2, 0xca0358a0); |
| 930 | udelay(30); |
| 931 | REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_OFFS, 0); |
| 932 | REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, 0); |
| 933 | |
| 934 | for (i = 6; i > 0; i--) { |
| 935 | regVal = REG_READ(ah, 0x7834); |
| 936 | regVal |= (1 << (19 + i)); |
| 937 | REG_WRITE(ah, 0x7834, regVal); |
| 938 | udelay(1); |
Senthil Balasubramanian | e759407 | 2008-12-08 19:43:48 +0530 | [diff] [blame] | 939 | regVal &= (~(0x1 << (19 + i))); |
| 940 | reg_field = MS(REG_READ(ah, 0x7840), AR9285_AN_RXTXBB1_SPARE9); |
| 941 | regVal |= (reg_field << (19 + i)); |
| 942 | REG_WRITE(ah, 0x7834, regVal); |
| 943 | } |
| 944 | |
| 945 | REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, 1); |
| 946 | udelay(1); |
| 947 | reg_field = MS(REG_READ(ah, AR9285_AN_RF2G9), AR9285_AN_RXTXBB1_SPARE9); |
| 948 | REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, reg_field); |
| 949 | offs_6_1 = MS(REG_READ(ah, AR9285_AN_RF2G6), AR9285_AN_RF2G6_OFFS); |
| 950 | offs_0 = MS(REG_READ(ah, AR9285_AN_RF2G3), AR9285_AN_RF2G3_PDVCCOMP); |
| 951 | |
| 952 | offset = (offs_6_1<<1) | offs_0; |
| 953 | offset = offset - 0; |
| 954 | offs_6_1 = offset>>1; |
| 955 | offs_0 = offset & 1; |
| 956 | |
Sujith | a13883b | 2009-08-26 08:39:40 +0530 | [diff] [blame] | 957 | if ((!is_reset) && (ah->pacal_info.prev_offset == offset)) { |
| 958 | if (ah->pacal_info.max_skipcount < MAX_PACAL_SKIPCOUNT) |
| 959 | ah->pacal_info.max_skipcount = |
| 960 | 2 * ah->pacal_info.max_skipcount; |
| 961 | ah->pacal_info.skipcount = ah->pacal_info.max_skipcount; |
| 962 | } else { |
| 963 | ah->pacal_info.max_skipcount = 1; |
| 964 | ah->pacal_info.skipcount = 0; |
| 965 | ah->pacal_info.prev_offset = offset; |
| 966 | } |
| 967 | |
Senthil Balasubramanian | e759407 | 2008-12-08 19:43:48 +0530 | [diff] [blame] | 968 | REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_OFFS, offs_6_1); |
| 969 | REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, offs_0); |
| 970 | |
| 971 | regVal = REG_READ(ah, 0x7834); |
| 972 | regVal |= 0x1; |
| 973 | REG_WRITE(ah, 0x7834, regVal); |
| 974 | regVal = REG_READ(ah, 0x9808); |
| 975 | regVal &= (~(0x1 << 27)); |
| 976 | REG_WRITE(ah, 0x9808, regVal); |
| 977 | |
| 978 | for (i = 0; i < ARRAY_SIZE(regList); i++) |
| 979 | REG_WRITE(ah, regList[i][0], regList[i][1]); |
| 980 | |
| 981 | REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_CCOMP, ccomp_org); |
| 982 | |
| 983 | if (AR_SREV_9285_11(ah)) |
| 984 | REG_WRITE(ah, AR9285_AN_TOP4, AR9285_AN_TOP4_DEFAULT); |
| 985 | |
| 986 | } |
| 987 | |
Senthil Balasubramanian | 4e84516 | 2009-03-06 11:24:10 +0530 | [diff] [blame] | 988 | bool ath9k_hw_calibrate(struct ath_hw *ah, struct ath9k_channel *chan, |
Sujith | 379f044 | 2009-04-13 21:56:48 +0530 | [diff] [blame] | 989 | u8 rxchainmask, bool longcal) |
Senthil Balasubramanian | 4e84516 | 2009-03-06 11:24:10 +0530 | [diff] [blame] | 990 | { |
Sujith | 379f044 | 2009-04-13 21:56:48 +0530 | [diff] [blame] | 991 | bool iscaldone = true; |
Sujith | cbfe946 | 2009-04-13 21:56:56 +0530 | [diff] [blame] | 992 | struct ath9k_cal_list *currCal = ah->cal_list_curr; |
Senthil Balasubramanian | 4e84516 | 2009-03-06 11:24:10 +0530 | [diff] [blame] | 993 | |
Senthil Balasubramanian | 4e84516 | 2009-03-06 11:24:10 +0530 | [diff] [blame] | 994 | if (currCal && |
| 995 | (currCal->calState == CAL_RUNNING || |
| 996 | currCal->calState == CAL_WAITING)) { |
Sujith | 379f044 | 2009-04-13 21:56:48 +0530 | [diff] [blame] | 997 | iscaldone = ath9k_hw_per_calibration(ah, chan, |
| 998 | rxchainmask, currCal); |
| 999 | if (iscaldone) { |
Senthil Balasubramanian | 4e84516 | 2009-03-06 11:24:10 +0530 | [diff] [blame] | 1000 | ah->cal_list_curr = currCal = currCal->calNext; |
| 1001 | |
| 1002 | if (currCal->calState == CAL_WAITING) { |
Sujith | 379f044 | 2009-04-13 21:56:48 +0530 | [diff] [blame] | 1003 | iscaldone = false; |
Senthil Balasubramanian | 4e84516 | 2009-03-06 11:24:10 +0530 | [diff] [blame] | 1004 | ath9k_hw_reset_calibration(ah, currCal); |
| 1005 | } |
| 1006 | } |
| 1007 | } |
| 1008 | |
Luis R. Rodriguez | d7e7d22 | 2009-08-03 23:14:12 -0400 | [diff] [blame] | 1009 | /* Do NF cal only at longer intervals */ |
Senthil Balasubramanian | 4e84516 | 2009-03-06 11:24:10 +0530 | [diff] [blame] | 1010 | if (longcal) { |
Luis R. Rodriguez | d7e7d22 | 2009-08-03 23:14:12 -0400 | [diff] [blame] | 1011 | /* Do periodic PAOffset Cal */ |
| 1012 | if (AR_SREV_9271(ah)) |
| 1013 | ath9k_hw_9271_pa_cal(ah); |
Sujith | a13883b | 2009-08-26 08:39:40 +0530 | [diff] [blame] | 1014 | else if (AR_SREV_9285_11_OR_LATER(ah)) { |
| 1015 | if (!ah->pacal_info.skipcount) |
| 1016 | ath9k_hw_9285_pa_cal(ah, false); |
| 1017 | else |
| 1018 | ah->pacal_info.skipcount--; |
| 1019 | } |
Senthil Balasubramanian | 4e84516 | 2009-03-06 11:24:10 +0530 | [diff] [blame] | 1020 | |
Vivek Natarajan | ac88b6e | 2009-07-23 10:59:57 +0530 | [diff] [blame] | 1021 | if (OLC_FOR_AR9280_20_LATER || OLC_FOR_AR9287_10_LATER) |
Senthil Balasubramanian | 4e84516 | 2009-03-06 11:24:10 +0530 | [diff] [blame] | 1022 | ath9k_olc_temp_compensation(ah); |
Luis R. Rodriguez | d7e7d22 | 2009-08-03 23:14:12 -0400 | [diff] [blame] | 1023 | |
| 1024 | /* Get the value from the previous NF cal and update history buffer */ |
Senthil Balasubramanian | 4e84516 | 2009-03-06 11:24:10 +0530 | [diff] [blame] | 1025 | ath9k_hw_getnf(ah, chan); |
Luis R. Rodriguez | d7e7d22 | 2009-08-03 23:14:12 -0400 | [diff] [blame] | 1026 | |
| 1027 | /* |
| 1028 | * Load the NF from history buffer of the current channel. |
| 1029 | * NF is slow time-variant, so it is OK to use a historical value. |
| 1030 | */ |
Senthil Balasubramanian | 4e84516 | 2009-03-06 11:24:10 +0530 | [diff] [blame] | 1031 | ath9k_hw_loadnf(ah, ah->curchan); |
Luis R. Rodriguez | d7e7d22 | 2009-08-03 23:14:12 -0400 | [diff] [blame] | 1032 | |
Senthil Balasubramanian | 4e84516 | 2009-03-06 11:24:10 +0530 | [diff] [blame] | 1033 | ath9k_hw_start_nfcal(ah); |
Senthil Balasubramanian | 4e84516 | 2009-03-06 11:24:10 +0530 | [diff] [blame] | 1034 | } |
| 1035 | |
Sujith | 379f044 | 2009-04-13 21:56:48 +0530 | [diff] [blame] | 1036 | return iscaldone; |
Senthil Balasubramanian | 4e84516 | 2009-03-06 11:24:10 +0530 | [diff] [blame] | 1037 | } |
| 1038 | |
Luis R. Rodriguez | 15cc0f1 | 2009-03-09 22:09:42 -0400 | [diff] [blame] | 1039 | static bool ar9285_clc(struct ath_hw *ah, struct ath9k_channel *chan) |
Senthil Balasubramanian | 4e84516 | 2009-03-06 11:24:10 +0530 | [diff] [blame] | 1040 | { |
| 1041 | REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE); |
Sujith | db2f63f | 2009-04-13 21:56:41 +0530 | [diff] [blame] | 1042 | if (IS_CHAN_HT20(chan)) { |
Senthil Balasubramanian | 4e84516 | 2009-03-06 11:24:10 +0530 | [diff] [blame] | 1043 | REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_PARALLEL_CAL_ENABLE); |
| 1044 | REG_SET_BIT(ah, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN); |
| 1045 | REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, |
| 1046 | AR_PHY_AGC_CONTROL_FLTR_CAL); |
| 1047 | REG_CLR_BIT(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_CAL_ENABLE); |
| 1048 | REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL); |
| 1049 | if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, |
| 1050 | AR_PHY_AGC_CONTROL_CAL, 0, AH_WAIT_TIMEOUT)) { |
| 1051 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, "offset " |
| 1052 | "calibration failed to complete in " |
| 1053 | "1ms; noisy ??\n"); |
| 1054 | return false; |
| 1055 | } |
| 1056 | REG_CLR_BIT(ah, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN); |
| 1057 | REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_PARALLEL_CAL_ENABLE); |
| 1058 | REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE); |
| 1059 | } |
| 1060 | REG_CLR_BIT(ah, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC); |
| 1061 | REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL); |
| 1062 | REG_SET_BIT(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_CAL_ENABLE); |
| 1063 | REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL); |
| 1064 | if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL, |
| 1065 | 0, AH_WAIT_TIMEOUT)) { |
| 1066 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, "offset calibration " |
| 1067 | "failed to complete in 1ms; noisy ??\n"); |
| 1068 | return false; |
| 1069 | } |
| 1070 | |
| 1071 | REG_SET_BIT(ah, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC); |
| 1072 | REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE); |
| 1073 | REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL); |
| 1074 | |
| 1075 | return true; |
| 1076 | } |
| 1077 | |
Sujith | 04d19dd | 2009-04-13 21:56:59 +0530 | [diff] [blame] | 1078 | bool ath9k_hw_init_cal(struct ath_hw *ah, struct ath9k_channel *chan) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1079 | { |
Gabor Juhos | f9dd6b5 | 2009-05-06 09:47:30 +0200 | [diff] [blame] | 1080 | if (AR_SREV_9285_12_OR_LATER(ah)) { |
Senthil Balasubramanian | 4e84516 | 2009-03-06 11:24:10 +0530 | [diff] [blame] | 1081 | if (!ar9285_clc(ah, chan)) |
| 1082 | return false; |
Sujith | 04d19dd | 2009-04-13 21:56:59 +0530 | [diff] [blame] | 1083 | } else { |
| 1084 | if (AR_SREV_9280_10_OR_LATER(ah)) { |
Vivek Natarajan | ac88b6e | 2009-07-23 10:59:57 +0530 | [diff] [blame] | 1085 | if (!AR_SREV_9287_10_OR_LATER(ah)) |
| 1086 | REG_CLR_BIT(ah, AR_PHY_ADC_CTL, |
| 1087 | AR_PHY_ADC_CTL_OFF_PWDADC); |
| 1088 | REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, |
| 1089 | AR_PHY_AGC_CONTROL_FLTR_CAL); |
Sujith | 04d19dd | 2009-04-13 21:56:59 +0530 | [diff] [blame] | 1090 | } |
Sujith | edf7c06 | 2009-02-12 10:06:49 +0530 | [diff] [blame] | 1091 | |
Sujith | 04d19dd | 2009-04-13 21:56:59 +0530 | [diff] [blame] | 1092 | /* Calibrate the AGC */ |
Sujith | edf7c06 | 2009-02-12 10:06:49 +0530 | [diff] [blame] | 1093 | REG_WRITE(ah, AR_PHY_AGC_CONTROL, |
Sujith | 04d19dd | 2009-04-13 21:56:59 +0530 | [diff] [blame] | 1094 | REG_READ(ah, AR_PHY_AGC_CONTROL) | |
| 1095 | AR_PHY_AGC_CONTROL_CAL); |
Sujith | edf7c06 | 2009-02-12 10:06:49 +0530 | [diff] [blame] | 1096 | |
Sujith | 04d19dd | 2009-04-13 21:56:59 +0530 | [diff] [blame] | 1097 | /* Poll for offset calibration complete */ |
| 1098 | if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL, |
| 1099 | 0, AH_WAIT_TIMEOUT)) { |
Sujith | edf7c06 | 2009-02-12 10:06:49 +0530 | [diff] [blame] | 1100 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, |
| 1101 | "offset calibration failed to complete in 1ms; " |
| 1102 | "noisy environment?\n"); |
| 1103 | return false; |
| 1104 | } |
| 1105 | |
Sujith | 04d19dd | 2009-04-13 21:56:59 +0530 | [diff] [blame] | 1106 | if (AR_SREV_9280_10_OR_LATER(ah)) { |
Vivek Natarajan | ac88b6e | 2009-07-23 10:59:57 +0530 | [diff] [blame] | 1107 | if (!AR_SREV_9287_10_OR_LATER(ah)) |
| 1108 | REG_SET_BIT(ah, AR_PHY_ADC_CTL, |
| 1109 | AR_PHY_ADC_CTL_OFF_PWDADC); |
| 1110 | REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, |
| 1111 | AR_PHY_AGC_CONTROL_FLTR_CAL); |
Sujith | 04d19dd | 2009-04-13 21:56:59 +0530 | [diff] [blame] | 1112 | } |
Sujith | edf7c06 | 2009-02-12 10:06:49 +0530 | [diff] [blame] | 1113 | } |
| 1114 | |
| 1115 | /* Do PA Calibration */ |
Gabor Juhos | f9dd6b5 | 2009-05-06 09:47:30 +0200 | [diff] [blame] | 1116 | if (AR_SREV_9285_11_OR_LATER(ah)) |
Sujith | a13883b | 2009-08-26 08:39:40 +0530 | [diff] [blame] | 1117 | ath9k_hw_9285_pa_cal(ah, true); |
Senthil Balasubramanian | e759407 | 2008-12-08 19:43:48 +0530 | [diff] [blame] | 1118 | |
Sujith | 04d19dd | 2009-04-13 21:56:59 +0530 | [diff] [blame] | 1119 | /* Do NF Calibration after DC offset and other calibrations */ |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1120 | REG_WRITE(ah, AR_PHY_AGC_CONTROL, |
Sujith | 04d19dd | 2009-04-13 21:56:59 +0530 | [diff] [blame] | 1121 | REG_READ(ah, AR_PHY_AGC_CONTROL) | AR_PHY_AGC_CONTROL_NF); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1122 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1123 | ah->cal_list = ah->cal_list_last = ah->cal_list_curr = NULL; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1124 | |
Sujith | 04d19dd | 2009-04-13 21:56:59 +0530 | [diff] [blame] | 1125 | /* Enable IQ, ADC Gain and ADC DC offset CALs */ |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1126 | if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah)) { |
Luis R. Rodriguez | c9e27d9 | 2008-12-23 15:58:42 -0800 | [diff] [blame] | 1127 | if (ath9k_hw_iscal_supported(ah, ADC_GAIN_CAL)) { |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1128 | INIT_CAL(&ah->adcgain_caldata); |
| 1129 | INSERT_CAL(ah, &ah->adcgain_caldata); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1130 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, |
Sujith | 04d19dd | 2009-04-13 21:56:59 +0530 | [diff] [blame] | 1131 | "enabling ADC Gain Calibration.\n"); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1132 | } |
Luis R. Rodriguez | c9e27d9 | 2008-12-23 15:58:42 -0800 | [diff] [blame] | 1133 | if (ath9k_hw_iscal_supported(ah, ADC_DC_CAL)) { |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1134 | INIT_CAL(&ah->adcdc_caldata); |
| 1135 | INSERT_CAL(ah, &ah->adcdc_caldata); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1136 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, |
Sujith | 04d19dd | 2009-04-13 21:56:59 +0530 | [diff] [blame] | 1137 | "enabling ADC DC Calibration.\n"); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1138 | } |
Luis R. Rodriguez | c9e27d9 | 2008-12-23 15:58:42 -0800 | [diff] [blame] | 1139 | if (ath9k_hw_iscal_supported(ah, IQ_MISMATCH_CAL)) { |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1140 | INIT_CAL(&ah->iq_caldata); |
| 1141 | INSERT_CAL(ah, &ah->iq_caldata); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1142 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, |
Sujith | 04d19dd | 2009-04-13 21:56:59 +0530 | [diff] [blame] | 1143 | "enabling IQ Calibration.\n"); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1144 | } |
| 1145 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1146 | ah->cal_list_curr = ah->cal_list; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1147 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1148 | if (ah->cal_list_curr) |
| 1149 | ath9k_hw_reset_calibration(ah, ah->cal_list_curr); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1150 | } |
| 1151 | |
Luis R. Rodriguez | 5f8e077 | 2009-01-22 15:16:48 -0800 | [diff] [blame] | 1152 | chan->CalValid = 0; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1153 | |
| 1154 | return true; |
| 1155 | } |
| 1156 | |
Sujith | cbfe946 | 2009-04-13 21:56:56 +0530 | [diff] [blame] | 1157 | const struct ath9k_percal_data iq_cal_multi_sample = { |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1158 | IQ_MISMATCH_CAL, |
| 1159 | MAX_CAL_SAMPLES, |
| 1160 | PER_MIN_LOG_COUNT, |
| 1161 | ath9k_hw_iqcal_collect, |
| 1162 | ath9k_hw_iqcalibrate |
| 1163 | }; |
Sujith | cbfe946 | 2009-04-13 21:56:56 +0530 | [diff] [blame] | 1164 | const struct ath9k_percal_data iq_cal_single_sample = { |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1165 | IQ_MISMATCH_CAL, |
| 1166 | MIN_CAL_SAMPLES, |
| 1167 | PER_MAX_LOG_COUNT, |
| 1168 | ath9k_hw_iqcal_collect, |
| 1169 | ath9k_hw_iqcalibrate |
| 1170 | }; |
Sujith | cbfe946 | 2009-04-13 21:56:56 +0530 | [diff] [blame] | 1171 | const struct ath9k_percal_data adc_gain_cal_multi_sample = { |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1172 | ADC_GAIN_CAL, |
| 1173 | MAX_CAL_SAMPLES, |
| 1174 | PER_MIN_LOG_COUNT, |
| 1175 | ath9k_hw_adc_gaincal_collect, |
| 1176 | ath9k_hw_adc_gaincal_calibrate |
| 1177 | }; |
Sujith | cbfe946 | 2009-04-13 21:56:56 +0530 | [diff] [blame] | 1178 | const struct ath9k_percal_data adc_gain_cal_single_sample = { |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1179 | ADC_GAIN_CAL, |
| 1180 | MIN_CAL_SAMPLES, |
| 1181 | PER_MAX_LOG_COUNT, |
| 1182 | ath9k_hw_adc_gaincal_collect, |
| 1183 | ath9k_hw_adc_gaincal_calibrate |
| 1184 | }; |
Sujith | cbfe946 | 2009-04-13 21:56:56 +0530 | [diff] [blame] | 1185 | const struct ath9k_percal_data adc_dc_cal_multi_sample = { |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1186 | ADC_DC_CAL, |
| 1187 | MAX_CAL_SAMPLES, |
| 1188 | PER_MIN_LOG_COUNT, |
| 1189 | ath9k_hw_adc_dccal_collect, |
| 1190 | ath9k_hw_adc_dccal_calibrate |
| 1191 | }; |
Sujith | cbfe946 | 2009-04-13 21:56:56 +0530 | [diff] [blame] | 1192 | const struct ath9k_percal_data adc_dc_cal_single_sample = { |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1193 | ADC_DC_CAL, |
| 1194 | MIN_CAL_SAMPLES, |
| 1195 | PER_MAX_LOG_COUNT, |
| 1196 | ath9k_hw_adc_dccal_collect, |
| 1197 | ath9k_hw_adc_dccal_calibrate |
| 1198 | }; |
Sujith | cbfe946 | 2009-04-13 21:56:56 +0530 | [diff] [blame] | 1199 | const struct ath9k_percal_data adc_init_dc_cal = { |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1200 | ADC_DC_INIT_CAL, |
| 1201 | MIN_CAL_SAMPLES, |
| 1202 | INIT_LOG_COUNT, |
| 1203 | ath9k_hw_adc_dccal_collect, |
| 1204 | ath9k_hw_adc_dccal_calibrate |
| 1205 | }; |