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Rabin Vincent62579262010-05-19 11:39:02 +02001/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * License Terms: GNU General Public License v2
5 * Author: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
6 */
7#ifndef MFD_AB8500_H
8#define MFD_AB8500_H
9
10#include <linux/device.h>
11
12/*
Mattias Wallin47c16972010-09-10 17:47:56 +020013 * AB8500 bank addresses
14 */
15#define AB8500_SYS_CTRL1_BLOCK 0x1
16#define AB8500_SYS_CTRL2_BLOCK 0x2
17#define AB8500_REGU_CTRL1 0x3
18#define AB8500_REGU_CTRL2 0x4
19#define AB8500_USB 0x5
20#define AB8500_TVOUT 0x6
21#define AB8500_DBI 0x7
22#define AB8500_ECI_AV_ACC 0x8
23#define AB8500_RESERVED 0x9
24#define AB8500_GPADC 0xA
25#define AB8500_CHARGER 0xB
26#define AB8500_GAS_GAUGE 0xC
27#define AB8500_AUDIO 0xD
28#define AB8500_INTERRUPT 0xE
29#define AB8500_RTC 0xF
30#define AB8500_MISC 0x10
31#define AB8500_DEBUG 0x12
32#define AB8500_PROD_TEST 0x13
33#define AB8500_OTP_EMUL 0x15
34
35/*
Rabin Vincent62579262010-05-19 11:39:02 +020036 * Interrupts
37 */
38
39#define AB8500_INT_MAIN_EXT_CH_NOT_OK 0
40#define AB8500_INT_UN_PLUG_TV_DET 1
41#define AB8500_INT_PLUG_TV_DET 2
42#define AB8500_INT_TEMP_WARM 3
43#define AB8500_INT_PON_KEY2DB_F 4
44#define AB8500_INT_PON_KEY2DB_R 5
45#define AB8500_INT_PON_KEY1DB_F 6
46#define AB8500_INT_PON_KEY1DB_R 7
47#define AB8500_INT_BATT_OVV 8
48#define AB8500_INT_MAIN_CH_UNPLUG_DET 10
49#define AB8500_INT_MAIN_CH_PLUG_DET 11
50#define AB8500_INT_USB_ID_DET_F 12
51#define AB8500_INT_USB_ID_DET_R 13
52#define AB8500_INT_VBUS_DET_F 14
53#define AB8500_INT_VBUS_DET_R 15
54#define AB8500_INT_VBUS_CH_DROP_END 16
55#define AB8500_INT_RTC_60S 17
56#define AB8500_INT_RTC_ALARM 18
57#define AB8500_INT_BAT_CTRL_INDB 20
58#define AB8500_INT_CH_WD_EXP 21
59#define AB8500_INT_VBUS_OVV 22
60#define AB8500_INT_MAIN_CH_DROP_END 23
61#define AB8500_INT_CCN_CONV_ACC 24
62#define AB8500_INT_INT_AUD 25
63#define AB8500_INT_CCEOC 26
64#define AB8500_INT_CC_INT_CALIB 27
65#define AB8500_INT_LOW_BAT_F 28
66#define AB8500_INT_LOW_BAT_R 29
67#define AB8500_INT_BUP_CHG_NOT_OK 30
68#define AB8500_INT_BUP_CHG_OK 31
69#define AB8500_INT_GP_HW_ADC_CONV_END 32
70#define AB8500_INT_ACC_DETECT_1DB_F 33
71#define AB8500_INT_ACC_DETECT_1DB_R 34
72#define AB8500_INT_ACC_DETECT_22DB_F 35
73#define AB8500_INT_ACC_DETECT_22DB_R 36
74#define AB8500_INT_ACC_DETECT_21DB_F 37
75#define AB8500_INT_ACC_DETECT_21DB_R 38
76#define AB8500_INT_GP_SW_ADC_CONV_END 39
Bibek Basu0cb3fcd2011-02-09 11:02:35 +053077#define AB8500_INT_ACC_DETECT_1DB_F 33
78#define AB8500_INT_ACC_DETECT_1DB_R 34
79#define AB8500_INT_ACC_DETECT_22DB_F 35
80#define AB8500_INT_ACC_DETECT_22DB_R 36
81#define AB8500_INT_ACC_DETECT_21DB_F 37
82#define AB8500_INT_ACC_DETECT_21DB_R 38
83#define AB8500_INT_GP_SW_ADC_CONV_END 39
84#define AB8500_INT_GPIO6R 40
85#define AB8500_INT_GPIO7R 41
86#define AB8500_INT_GPIO8R 42
87#define AB8500_INT_GPIO9R 43
88#define AB8500_INT_GPIO10R 44
89#define AB8500_INT_GPIO11R 45
90#define AB8500_INT_GPIO12R 46
91#define AB8500_INT_GPIO13R 47
92#define AB8500_INT_GPIO24R 48
93#define AB8500_INT_GPIO25R 49
94#define AB8500_INT_GPIO36R 50
95#define AB8500_INT_GPIO37R 51
96#define AB8500_INT_GPIO38R 52
97#define AB8500_INT_GPIO39R 53
98#define AB8500_INT_GPIO40R 54
99#define AB8500_INT_GPIO41R 55
100#define AB8500_INT_GPIO6F 56
101#define AB8500_INT_GPIO7F 57
102#define AB8500_INT_GPIO8F 58
103#define AB8500_INT_GPIO9F 59
104#define AB8500_INT_GPIO10F 60
105#define AB8500_INT_GPIO11F 61
106#define AB8500_INT_GPIO12F 62
107#define AB8500_INT_GPIO13F 63
108#define AB8500_INT_GPIO24F 64
109#define AB8500_INT_GPIO25F 65
110#define AB8500_INT_GPIO36F 66
111#define AB8500_INT_GPIO37F 67
112#define AB8500_INT_GPIO38F 68
113#define AB8500_INT_GPIO39F 69
114#define AB8500_INT_GPIO40F 70
115#define AB8500_INT_GPIO41F 71
Mattias Wallin92d50a42010-12-07 11:20:47 +0100116#define AB8500_INT_ADP_SOURCE_ERROR 72
117#define AB8500_INT_ADP_SINK_ERROR 73
118#define AB8500_INT_ADP_PROBE_PLUG 74
119#define AB8500_INT_ADP_PROBE_UNPLUG 75
120#define AB8500_INT_ADP_SENSE_OFF 76
121#define AB8500_INT_USB_PHY_POWER_ERR 78
122#define AB8500_INT_USB_LINK_STATUS 79
123#define AB8500_INT_BTEMP_LOW 80
124#define AB8500_INT_BTEMP_LOW_MEDIUM 81
125#define AB8500_INT_BTEMP_MEDIUM_HIGH 82
126#define AB8500_INT_BTEMP_HIGH 83
127#define AB8500_INT_USB_CHARGER_NOT_OK 89
128#define AB8500_INT_ID_WAKEUP_R 90
129#define AB8500_INT_ID_DET_R1R 92
130#define AB8500_INT_ID_DET_R2R 93
131#define AB8500_INT_ID_DET_R3R 94
132#define AB8500_INT_ID_DET_R4R 95
133#define AB8500_INT_ID_WAKEUP_F 96
134#define AB8500_INT_ID_DET_R1F 98
135#define AB8500_INT_ID_DET_R2F 99
136#define AB8500_INT_ID_DET_R3F 100
137#define AB8500_INT_ID_DET_R4F 101
138#define AB8500_INT_USB_CHG_DET_DONE 102
139#define AB8500_INT_USB_CH_TH_PROT_F 104
140#define AB8500_INT_USB_CH_TH_PROT_R 105
141#define AB8500_INT_MAIN_CH_TH_PROT_F 106
142#define AB8500_INT_MAIN_CH_TH_PROT_R 107
143#define AB8500_INT_USB_CHARGER_NOT_OKF 111
Rabin Vincent62579262010-05-19 11:39:02 +0200144
Mattias Wallin92d50a42010-12-07 11:20:47 +0100145#define AB8500_NR_IRQS 112
146#define AB8500_NUM_IRQ_REGS 14
Rabin Vincent62579262010-05-19 11:39:02 +0200147
148/**
149 * struct ab8500 - ab8500 internal structure
150 * @dev: parent device
151 * @lock: read/write operations lock
152 * @irq_lock: genirq bus lock
Rabin Vincent62579262010-05-19 11:39:02 +0200153 * @irq: irq line
Mattias Wallinadceed62011-03-02 11:51:11 +0100154 * @chip_id: chip revision id
Rabin Vincent62579262010-05-19 11:39:02 +0200155 * @write: register write
156 * @read: register read
157 * @rx_buf: rx buf for SPI
158 * @tx_buf: tx buf for SPI
159 * @mask: cache of IRQ regs for bus lock
160 * @oldmask: cache of previous IRQ regs for bus lock
161 */
162struct ab8500 {
163 struct device *dev;
164 struct mutex lock;
165 struct mutex irq_lock;
Mattias Wallinadceed62011-03-02 11:51:11 +0100166
Rabin Vincent62579262010-05-19 11:39:02 +0200167 int irq_base;
168 int irq;
Mattias Wallin47c16972010-09-10 17:47:56 +0200169 u8 chip_id;
Rabin Vincent62579262010-05-19 11:39:02 +0200170
171 int (*write) (struct ab8500 *a8500, u16 addr, u8 data);
172 int (*read) (struct ab8500 *a8500, u16 addr);
173
174 unsigned long tx_buf[4];
175 unsigned long rx_buf[4];
176
177 u8 mask[AB8500_NUM_IRQ_REGS];
178 u8 oldmask[AB8500_NUM_IRQ_REGS];
179};
180
Bengt Jonsson79568b92011-03-11 11:54:46 +0100181struct regulator_reg_init;
Sundar R Iyer549931f2010-07-13 11:51:28 +0530182struct regulator_init_data;
Bibek Basu0cb3fcd2011-02-09 11:02:35 +0530183struct ab8500_gpio_platform_data;
Sundar R Iyer549931f2010-07-13 11:51:28 +0530184
Rabin Vincent62579262010-05-19 11:39:02 +0200185/**
186 * struct ab8500_platform_data - AB8500 platform data
187 * @irq_base: start of AB8500 IRQs, AB8500_NR_IRQS will be used
188 * @init: board-specific initialization after detection of ab8500
Bengt Jonsson79568b92011-03-11 11:54:46 +0100189 * @num_regulator_reg_init: number of regulator init registers
190 * @regulator_reg_init: regulator init registers
191 * @num_regulator: number of regulators
Sundar R Iyer549931f2010-07-13 11:51:28 +0530192 * @regulator: machine-specific constraints for regulators
Rabin Vincent62579262010-05-19 11:39:02 +0200193 */
194struct ab8500_platform_data {
195 int irq_base;
196 void (*init) (struct ab8500 *);
Bengt Jonsson79568b92011-03-11 11:54:46 +0100197 int num_regulator_reg_init;
198 struct ab8500_regulator_reg_init *regulator_reg_init;
Bengt Jonssoncb189b02010-12-10 11:08:40 +0100199 int num_regulator;
200 struct regulator_init_data *regulator;
Bibek Basu0cb3fcd2011-02-09 11:02:35 +0530201 struct ab8500_gpio_platform_data *gpio;
Rabin Vincent62579262010-05-19 11:39:02 +0200202};
203
Rabin Vincent62579262010-05-19 11:39:02 +0200204extern int __devinit ab8500_init(struct ab8500 *ab8500);
205extern int __devexit ab8500_exit(struct ab8500 *ab8500);
206
207#endif /* MFD_AB8500_H */