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Dmitry Baryshkovf024ff12008-06-27 10:37:57 +01001#ifndef MFD_TMIO_H
2#define MFD_TMIO_H
3
Dmitry Baryshkovb53cde32008-10-15 22:03:55 -07004#include <linux/fb.h>
Ian Molton64e88672010-01-06 13:51:48 +01005#include <linux/io.h>
6#include <linux/platform_device.h>
Guennadi Liakhovetski7311bef2011-05-11 16:51:11 +00007#include <linux/pm_runtime.h>
Dmitry Baryshkovb53cde32008-10-15 22:03:55 -07008
Ian Moltond3a2f712008-07-31 20:44:28 +02009#define tmio_ioread8(addr) readb(addr)
10#define tmio_ioread16(addr) readw(addr)
11#define tmio_ioread16_rep(r, b, l) readsw(r, b, l)
12#define tmio_ioread32(addr) \
13 (((u32) readw((addr))) | (((u32) readw((addr) + 2)) << 16))
14
15#define tmio_iowrite8(val, addr) writeb((val), (addr))
16#define tmio_iowrite16(val, addr) writew((val), (addr))
17#define tmio_iowrite16_rep(r, b, l) writesw(r, b, l)
18#define tmio_iowrite32(val, addr) \
19 do { \
20 writew((val), (addr)); \
21 writew((val) >> 16, (addr) + 2); \
22 } while (0)
23
Ian Molton64e88672010-01-06 13:51:48 +010024#define CNF_CMD 0x04
25#define CNF_CTL_BASE 0x10
26#define CNF_INT_PIN 0x3d
27#define CNF_STOP_CLK_CTL 0x40
28#define CNF_GCLK_CTL 0x41
29#define CNF_SD_CLK_MODE 0x42
30#define CNF_PIN_STATUS 0x44
31#define CNF_PWR_CTL_1 0x48
32#define CNF_PWR_CTL_2 0x49
33#define CNF_PWR_CTL_3 0x4a
34#define CNF_CARD_DETECT_MODE 0x4c
35#define CNF_SD_SLOT 0x50
36#define CNF_EXT_GCLK_CTL_1 0xf0
37#define CNF_EXT_GCLK_CTL_2 0xf1
38#define CNF_EXT_GCLK_CTL_3 0xf9
39#define CNF_SD_LED_EN_1 0xfa
40#define CNF_SD_LED_EN_2 0xfe
41
42#define SDCREN 0x2 /* Enable access to MMC CTL regs. (flag in COMMAND_REG)*/
43
44#define sd_config_write8(base, shift, reg, val) \
45 tmio_iowrite8((val), (base) + ((reg) << (shift)))
46#define sd_config_write16(base, shift, reg, val) \
47 tmio_iowrite16((val), (base) + ((reg) << (shift)))
48#define sd_config_write32(base, shift, reg, val) \
49 do { \
50 tmio_iowrite16((val), (base) + ((reg) << (shift))); \
51 tmio_iowrite16((val) >> 16, (base) + ((reg + 2) << (shift))); \
52 } while (0)
53
Guennadi Liakhovetskiac8fb3e2010-05-19 18:36:02 +000054/* tmio MMC platform flags */
55#define TMIO_MMC_WRPROTECT_DISABLE (1 << 0)
Yusuke Godaf1334fb2010-08-30 11:50:19 +010056/*
57 * Some controllers can support a 2-byte block size when the bus width
58 * is configured in 4-bit mode.
59 */
60#define TMIO_MMC_BLKSZ_2BYTES (1 << 1)
Arnd Hannemann845ecd22010-12-28 23:22:31 +010061/*
62 * Some controllers can support SDIO IRQ signalling.
63 */
64#define TMIO_MMC_SDIO_IRQ (1 << 2)
Guennadi Liakhovetski7311bef2011-05-11 16:51:11 +000065/*
66 * Some platforms can detect card insertion events with controller powered
67 * down, in which case they have to call tmio_mmc_cd_wakeup() to power up the
68 * controller and report the event to the driver.
69 */
70#define TMIO_MMC_HAS_COLD_CD (1 << 3)
Simon Horman973ed3a2011-06-21 08:00:10 +090071/*
72 * Some controllers require waiting for the SD bus to become
73 * idle before writing to some registers.
74 */
75#define TMIO_MMC_HAS_IDLE_WAIT (1 << 4)
Guennadi Liakhovetskiac8fb3e2010-05-19 18:36:02 +000076
Ian Molton64e88672010-01-06 13:51:48 +010077int tmio_core_mmc_enable(void __iomem *cnf, int shift, unsigned long base);
78int tmio_core_mmc_resume(void __iomem *cnf, int shift, unsigned long base);
79void tmio_core_mmc_pwr(void __iomem *cnf, int shift, int state);
80void tmio_core_mmc_clk_div(void __iomem *cnf, int shift, int state);
81
Guennadi Liakhovetski42a45332010-05-19 18:34:11 +000082struct tmio_mmc_dma {
83 void *chan_priv_tx;
84 void *chan_priv_rx;
Guennadi Liakhovetski93173052010-12-22 12:02:15 +010085 int alignment_shift;
Guennadi Liakhovetski42a45332010-05-19 18:34:11 +000086};
87
Simon Horman973ed3a2011-06-21 08:00:10 +090088struct tmio_mmc_host;
89
Dmitry Baryshkovf024ff12008-06-27 10:37:57 +010090/*
Philipp Zabelf0e46cc2009-06-04 20:12:31 +020091 * data for the MMC controller
92 */
93struct tmio_mmc_data {
Magnus Damm707f0b22010-02-17 16:38:14 +090094 unsigned int hclk;
Yusuke Godab741d442010-02-17 16:37:55 +090095 unsigned long capabilities;
Guennadi Liakhovetskiac8fb3e2010-05-19 18:36:02 +000096 unsigned long flags;
Guennadi Liakhovetskia2b14dc2010-05-19 18:37:25 +000097 u32 ocr_mask; /* available voltages */
Guennadi Liakhovetski42a45332010-05-19 18:34:11 +000098 struct tmio_mmc_dma *dma;
Guennadi Liakhovetski7311bef2011-05-11 16:51:11 +000099 struct device *dev;
100 bool power;
Ian Molton64e88672010-01-06 13:51:48 +0100101 void (*set_pwr)(struct platform_device *host, int state);
102 void (*set_clk_div)(struct platform_device *host, int state);
Arnd Hannemann19ca7502010-08-24 17:26:59 +0200103 int (*get_cd)(struct platform_device *host);
Simon Horman973ed3a2011-06-21 08:00:10 +0900104 int (*write16_hook)(struct tmio_mmc_host *host, int addr);
Philipp Zabelf0e46cc2009-06-04 20:12:31 +0200105};
106
Guennadi Liakhovetski7311bef2011-05-11 16:51:11 +0000107static inline void tmio_mmc_cd_wakeup(struct tmio_mmc_data *pdata)
108{
109 if (pdata && !pdata->power) {
110 pdata->power = true;
111 pm_runtime_get(pdata->dev);
112 }
113}
114
Philipp Zabelf0e46cc2009-06-04 20:12:31 +0200115/*
Dmitry Baryshkovf024ff12008-06-27 10:37:57 +0100116 * data for the NAND controller
117 */
118struct tmio_nand_data {
119 struct nand_bbt_descr *badblock_pattern;
120 struct mtd_partition *partition;
121 unsigned int num_partitions;
122};
123
Dmitry Baryshkovb53cde32008-10-15 22:03:55 -0700124#define FBIO_TMIO_ACC_WRITE 0x7C639300
125#define FBIO_TMIO_ACC_SYNC 0x7C639301
126
127struct tmio_fb_data {
128 int (*lcd_set_power)(struct platform_device *fb_dev,
129 bool on);
130 int (*lcd_mode)(struct platform_device *fb_dev,
131 const struct fb_videomode *mode);
132 int num_modes;
133 struct fb_videomode *modes;
134
135 /* in mm: size of screen */
136 int height;
137 int width;
138};
139
140
Dmitry Baryshkovf024ff12008-06-27 10:37:57 +0100141#endif