Kevin Wells | c4a0208 | 2010-02-26 15:53:41 -0800 | [diff] [blame] | 1 | /* |
| 2 | * arch/arm/mach-lpc32xx/timer.c |
| 3 | * |
| 4 | * Author: Kevin Wells <kevin.wells@nxp.com> |
| 5 | * |
| 6 | * Copyright (C) 2009 - 2010 NXP Semiconductors |
| 7 | * Copyright (C) 2009 Fontys University of Applied Sciences, Eindhoven |
| 8 | * Ed Schouten <e.schouten@fontys.nl> |
| 9 | * Laurens Timmermans <l.timmermans@fontys.nl> |
| 10 | * |
| 11 | * This program is free software; you can redistribute it and/or modify |
| 12 | * it under the terms of the GNU General Public License as published by |
| 13 | * the Free Software Foundation; either version 2 of the License, or |
| 14 | * (at your option) any later version. |
| 15 | * |
| 16 | * This program is distributed in the hope that it will be useful, |
| 17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 19 | * GNU General Public License for more details. |
| 20 | */ |
| 21 | |
| 22 | #include <linux/interrupt.h> |
| 23 | #include <linux/irq.h> |
| 24 | #include <linux/time.h> |
| 25 | #include <linux/err.h> |
| 26 | #include <linux/clockchips.h> |
| 27 | |
| 28 | #include <asm/mach/time.h> |
| 29 | |
| 30 | #include <mach/hardware.h> |
| 31 | #include <mach/platform.h> |
| 32 | #include "common.h" |
| 33 | |
Kevin Wells | c4a0208 | 2010-02-26 15:53:41 -0800 | [diff] [blame] | 34 | static int lpc32xx_clkevt_next_event(unsigned long delta, |
| 35 | struct clock_event_device *dev) |
| 36 | { |
Roland Stigge | cfac337 | 2012-02-27 17:31:24 +0100 | [diff] [blame^] | 37 | __raw_writel(LPC32XX_TIMER_CNTR_TCR_RESET, |
| 38 | LPC32XX_TIMER_TCR(LPC32XX_TIMER0_BASE)); |
| 39 | __raw_writel(delta, LPC32XX_TIMER_PR(LPC32XX_TIMER0_BASE)); |
| 40 | __raw_writel(LPC32XX_TIMER_CNTR_TCR_EN, |
| 41 | LPC32XX_TIMER_TCR(LPC32XX_TIMER0_BASE)); |
Kevin Wells | c4a0208 | 2010-02-26 15:53:41 -0800 | [diff] [blame] | 42 | |
| 43 | return 0; |
| 44 | } |
| 45 | |
| 46 | static void lpc32xx_clkevt_mode(enum clock_event_mode mode, |
| 47 | struct clock_event_device *dev) |
| 48 | { |
| 49 | switch (mode) { |
| 50 | case CLOCK_EVT_MODE_PERIODIC: |
| 51 | WARN_ON(1); |
| 52 | break; |
| 53 | |
| 54 | case CLOCK_EVT_MODE_ONESHOT: |
| 55 | case CLOCK_EVT_MODE_SHUTDOWN: |
| 56 | /* |
| 57 | * Disable the timer. When using oneshot, we must also |
| 58 | * disable the timer to wait for the first call to |
| 59 | * set_next_event(). |
| 60 | */ |
Roland Stigge | cfac337 | 2012-02-27 17:31:24 +0100 | [diff] [blame^] | 61 | __raw_writel(0, LPC32XX_TIMER_TCR(LPC32XX_TIMER0_BASE)); |
Kevin Wells | c4a0208 | 2010-02-26 15:53:41 -0800 | [diff] [blame] | 62 | break; |
| 63 | |
| 64 | case CLOCK_EVT_MODE_UNUSED: |
| 65 | case CLOCK_EVT_MODE_RESUME: |
| 66 | break; |
| 67 | } |
| 68 | } |
| 69 | |
| 70 | static struct clock_event_device lpc32xx_clkevt = { |
| 71 | .name = "lpc32xx_clkevt", |
| 72 | .features = CLOCK_EVT_FEAT_ONESHOT, |
| 73 | .shift = 32, |
| 74 | .rating = 300, |
| 75 | .set_next_event = lpc32xx_clkevt_next_event, |
| 76 | .set_mode = lpc32xx_clkevt_mode, |
| 77 | }; |
| 78 | |
| 79 | static irqreturn_t lpc32xx_timer_interrupt(int irq, void *dev_id) |
| 80 | { |
| 81 | struct clock_event_device *evt = &lpc32xx_clkevt; |
| 82 | |
| 83 | /* Clear match */ |
Roland Stigge | cfac337 | 2012-02-27 17:31:24 +0100 | [diff] [blame^] | 84 | __raw_writel(LPC32XX_TIMER_CNTR_MTCH_BIT(0), |
| 85 | LPC32XX_TIMER_IR(LPC32XX_TIMER0_BASE)); |
Kevin Wells | c4a0208 | 2010-02-26 15:53:41 -0800 | [diff] [blame] | 86 | |
| 87 | evt->event_handler(evt); |
| 88 | |
| 89 | return IRQ_HANDLED; |
| 90 | } |
| 91 | |
| 92 | static struct irqaction lpc32xx_timer_irq = { |
| 93 | .name = "LPC32XX Timer Tick", |
| 94 | .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, |
| 95 | .handler = lpc32xx_timer_interrupt, |
| 96 | }; |
| 97 | |
| 98 | /* |
| 99 | * The clock management driver isn't initialized at this point, so the |
| 100 | * clocks need to be enabled here manually and then tagged as used in |
| 101 | * the clock driver initialization |
| 102 | */ |
| 103 | static void __init lpc32xx_timer_init(void) |
| 104 | { |
| 105 | u32 clkrate, pllreg; |
| 106 | |
| 107 | /* Enable timer clock */ |
| 108 | __raw_writel(LPC32XX_CLKPWR_TMRPWMCLK_TIMER0_EN | |
| 109 | LPC32XX_CLKPWR_TMRPWMCLK_TIMER1_EN, |
| 110 | LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1); |
| 111 | |
| 112 | /* |
| 113 | * The clock driver isn't initialized at this point. So determine if |
| 114 | * the SYSCLK is driven from the PLL397 or main oscillator and then use |
| 115 | * it to compute the PLL frequency and the PCLK divider to get the base |
| 116 | * timer rates. This rate is needed to compute the tick rate. |
| 117 | */ |
| 118 | if (clk_is_sysclk_mainosc() != 0) |
| 119 | clkrate = LPC32XX_MAIN_OSC_FREQ; |
| 120 | else |
| 121 | clkrate = 397 * LPC32XX_CLOCK_OSC_FREQ; |
| 122 | |
| 123 | /* Get ARM HCLKPLL register and convert it into a frequency */ |
| 124 | pllreg = __raw_readl(LPC32XX_CLKPWR_HCLKPLL_CTRL) & 0x1FFFF; |
| 125 | clkrate = clk_get_pllrate_from_reg(clkrate, pllreg); |
| 126 | |
| 127 | /* Get PCLK divider and divide ARM PLL clock by it to get timer rate */ |
| 128 | clkrate = clkrate / clk_get_pclk_div(); |
| 129 | |
| 130 | /* Initial timer setup */ |
Roland Stigge | cfac337 | 2012-02-27 17:31:24 +0100 | [diff] [blame^] | 131 | __raw_writel(0, LPC32XX_TIMER_TCR(LPC32XX_TIMER0_BASE)); |
| 132 | __raw_writel(LPC32XX_TIMER_CNTR_MTCH_BIT(0), |
| 133 | LPC32XX_TIMER_IR(LPC32XX_TIMER0_BASE)); |
| 134 | __raw_writel(1, LPC32XX_TIMER_MR0(LPC32XX_TIMER0_BASE)); |
| 135 | __raw_writel(LPC32XX_TIMER_CNTR_MCR_MTCH(0) | |
| 136 | LPC32XX_TIMER_CNTR_MCR_STOP(0) | |
| 137 | LPC32XX_TIMER_CNTR_MCR_RESET(0), |
| 138 | LPC32XX_TIMER_MCR(LPC32XX_TIMER0_BASE)); |
Kevin Wells | c4a0208 | 2010-02-26 15:53:41 -0800 | [diff] [blame] | 139 | |
| 140 | /* Setup tick interrupt */ |
| 141 | setup_irq(IRQ_LPC32XX_TIMER0, &lpc32xx_timer_irq); |
| 142 | |
| 143 | /* Setup the clockevent structure. */ |
| 144 | lpc32xx_clkevt.mult = div_sc(clkrate, NSEC_PER_SEC, |
| 145 | lpc32xx_clkevt.shift); |
| 146 | lpc32xx_clkevt.max_delta_ns = clockevent_delta2ns(-1, |
| 147 | &lpc32xx_clkevt); |
| 148 | lpc32xx_clkevt.min_delta_ns = clockevent_delta2ns(1, |
| 149 | &lpc32xx_clkevt) + 1; |
| 150 | lpc32xx_clkevt.cpumask = cpumask_of(0); |
| 151 | clockevents_register_device(&lpc32xx_clkevt); |
| 152 | |
| 153 | /* Use timer1 as clock source. */ |
Roland Stigge | cfac337 | 2012-02-27 17:31:24 +0100 | [diff] [blame^] | 154 | __raw_writel(LPC32XX_TIMER_CNTR_TCR_RESET, |
| 155 | LPC32XX_TIMER_TCR(LPC32XX_TIMER1_BASE)); |
| 156 | __raw_writel(0, LPC32XX_TIMER_PR(LPC32XX_TIMER1_BASE)); |
| 157 | __raw_writel(0, LPC32XX_TIMER_MCR(LPC32XX_TIMER1_BASE)); |
| 158 | __raw_writel(LPC32XX_TIMER_CNTR_TCR_EN, |
| 159 | LPC32XX_TIMER_TCR(LPC32XX_TIMER1_BASE)); |
Russell King | 234b6ce | 2011-05-08 14:09:47 +0100 | [diff] [blame] | 160 | |
Roland Stigge | cfac337 | 2012-02-27 17:31:24 +0100 | [diff] [blame^] | 161 | clocksource_mmio_init(LPC32XX_TIMER_TC(LPC32XX_TIMER1_BASE), |
Russell King | 234b6ce | 2011-05-08 14:09:47 +0100 | [diff] [blame] | 162 | "lpc32xx_clksrc", clkrate, 300, 32, clocksource_mmio_readl_up); |
Kevin Wells | c4a0208 | 2010-02-26 15:53:41 -0800 | [diff] [blame] | 163 | } |
| 164 | |
| 165 | struct sys_timer lpc32xx_timer = { |
| 166 | .init = &lpc32xx_timer_init, |
| 167 | }; |
| 168 | |