blob: 6fe948c10e7283e350010e7707ed3e777c85fecd [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * drivers/net/mv643xx_eth.c - Driver for MV643XX ethernet ports
3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
4 *
5 * Based on the 64360 driver from:
6 * Copyright (C) 2002 rabeeh@galileo.co.il
7 *
8 * Copyright (C) 2003 PMC-Sierra, Inc.,
9 * written by Manish Lachwani (lachwani@pmc-sierra.com)
10 *
11 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
12 *
13 * Copyright (C) 2004-2005 MontaVista Software, Inc.
14 * Dale Farnsworth <dale@farnsworth.org>
15 *
16 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
17 * <sjhill@realitydiluted.com>
18 *
19 * This program is free software; you can redistribute it and/or
20 * modify it under the terms of the GNU General Public License
21 * as published by the Free Software Foundation; either version 2
22 * of the License, or (at your option) any later version.
23 *
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 * GNU General Public License for more details.
28 *
29 * You should have received a copy of the GNU General Public License
30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
32 */
33#include <linux/init.h>
34#include <linux/dma-mapping.h>
35#include <linux/tcp.h>
36#include <linux/udp.h>
37#include <linux/etherdevice.h>
38
39#include <linux/bitops.h>
40#include <linux/delay.h>
41#include <linux/ethtool.h>
Russell Kingd052d1b2005-10-29 19:07:23 +010042#include <linux/platform_device.h>
43
Linus Torvalds1da177e2005-04-16 15:20:36 -070044#include <asm/io.h>
45#include <asm/types.h>
46#include <asm/pgtable.h>
47#include <asm/system.h>
48#include <asm/delay.h>
49#include "mv643xx_eth.h"
50
51/*
52 * The first part is the high level driver of the gigE ethernet ports.
53 */
54
55/* Constants */
56#define VLAN_HLEN 4
57#define FCS_LEN 4
58#define WRAP NET_IP_ALIGN + ETH_HLEN + VLAN_HLEN + FCS_LEN
59#define RX_SKB_SIZE ((dev->mtu + WRAP + 7) & ~0x7)
60
61#define INT_CAUSE_UNMASK_ALL 0x0007ffff
62#define INT_CAUSE_UNMASK_ALL_EXT 0x0011ffff
Linus Torvalds1da177e2005-04-16 15:20:36 -070063#define INT_CAUSE_MASK_ALL 0x00000000
Dale Farnsworth63c9e542005-09-02 13:49:10 -070064#define INT_CAUSE_MASK_ALL_EXT 0x00000000
Linus Torvalds1da177e2005-04-16 15:20:36 -070065#define INT_CAUSE_CHECK_BITS INT_CAUSE_UNMASK_ALL
66#define INT_CAUSE_CHECK_BITS_EXT INT_CAUSE_UNMASK_ALL_EXT
Linus Torvalds1da177e2005-04-16 15:20:36 -070067
68#ifdef MV643XX_CHECKSUM_OFFLOAD_TX
69#define MAX_DESCS_PER_SKB (MAX_SKB_FRAGS + 1)
70#else
71#define MAX_DESCS_PER_SKB 1
72#endif
73
74#define PHY_WAIT_ITERATIONS 1000 /* 1000 iterations * 10uS = 10mS max */
75#define PHY_WAIT_MICRO_SECONDS 10
76
77/* Static function declarations */
78static int eth_port_link_is_up(unsigned int eth_port_num);
79static void eth_port_uc_addr_get(struct net_device *dev,
80 unsigned char *MacAddr);
81static int mv643xx_eth_real_open(struct net_device *);
82static int mv643xx_eth_real_stop(struct net_device *);
83static int mv643xx_eth_change_mtu(struct net_device *, int);
84static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *);
85static void eth_port_init_mac_tables(unsigned int eth_port_num);
86#ifdef MV643XX_NAPI
87static int mv643xx_poll(struct net_device *dev, int *budget);
88#endif
89static void ethernet_phy_set(unsigned int eth_port_num, int phy_addr);
90static int ethernet_phy_detect(unsigned int eth_port_num);
91static struct ethtool_ops mv643xx_ethtool_ops;
92
93static char mv643xx_driver_name[] = "mv643xx_eth";
94static char mv643xx_driver_version[] = "1.0";
95
96static void __iomem *mv643xx_eth_shared_base;
97
98/* used to protect MV643XX_ETH_SMI_REG, which is shared across ports */
Ingo Molnara9f6a0d2005-09-09 13:10:41 -070099static DEFINE_SPINLOCK(mv643xx_eth_phy_lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700100
101static inline u32 mv_read(int offset)
102{
Al Virodc074a82005-04-25 07:55:58 -0700103 void __iomem *reg_base;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700104
105 reg_base = mv643xx_eth_shared_base - MV643XX_ETH_SHARED_REGS;
106
107 return readl(reg_base + offset);
108}
109
110static inline void mv_write(int offset, u32 data)
111{
Al Virodc074a82005-04-25 07:55:58 -0700112 void __iomem *reg_base;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700113
114 reg_base = mv643xx_eth_shared_base - MV643XX_ETH_SHARED_REGS;
115 writel(data, reg_base + offset);
116}
117
118/*
119 * Changes MTU (maximum transfer unit) of the gigabit ethenret port
120 *
121 * Input : pointer to ethernet interface network device structure
122 * new mtu size
123 * Output : 0 upon success, -EINVAL upon failure
124 */
125static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
126{
127 struct mv643xx_private *mp = netdev_priv(dev);
128 unsigned long flags;
129
130 spin_lock_irqsave(&mp->lock, flags);
131
132 if ((new_mtu > 9500) || (new_mtu < 64)) {
133 spin_unlock_irqrestore(&mp->lock, flags);
134 return -EINVAL;
135 }
136
137 dev->mtu = new_mtu;
138 /*
139 * Stop then re-open the interface. This will allocate RX skb's with
140 * the new MTU.
141 * There is a possible danger that the open will not successed, due
142 * to memory is full, which might fail the open function.
143 */
144 if (netif_running(dev)) {
145 if (mv643xx_eth_real_stop(dev))
146 printk(KERN_ERR
147 "%s: Fatal error on stopping device\n",
148 dev->name);
149 if (mv643xx_eth_real_open(dev))
150 printk(KERN_ERR
151 "%s: Fatal error on opening device\n",
152 dev->name);
153 }
154
155 spin_unlock_irqrestore(&mp->lock, flags);
156 return 0;
157}
158
159/*
160 * mv643xx_eth_rx_task
161 *
162 * Fills / refills RX queue on a certain gigabit ethernet port
163 *
164 * Input : pointer to ethernet interface network device structure
165 * Output : N/A
166 */
167static void mv643xx_eth_rx_task(void *data)
168{
169 struct net_device *dev = (struct net_device *)data;
170 struct mv643xx_private *mp = netdev_priv(dev);
171 struct pkt_info pkt_info;
172 struct sk_buff *skb;
173
174 if (test_and_set_bit(0, &mp->rx_task_busy))
175 panic("%s: Error in test_set_bit / clear_bit", dev->name);
176
177 while (mp->rx_ring_skbs < (mp->rx_ring_size - 5)) {
178 skb = dev_alloc_skb(RX_SKB_SIZE);
179 if (!skb)
180 break;
181 mp->rx_ring_skbs++;
182 pkt_info.cmd_sts = ETH_RX_ENABLE_INTERRUPT;
183 pkt_info.byte_cnt = RX_SKB_SIZE;
184 pkt_info.buf_ptr = dma_map_single(NULL, skb->data, RX_SKB_SIZE,
185 DMA_FROM_DEVICE);
186 pkt_info.return_info = skb;
187 if (eth_rx_return_buff(mp, &pkt_info) != ETH_OK) {
188 printk(KERN_ERR
189 "%s: Error allocating RX Ring\n", dev->name);
190 break;
191 }
192 skb_reserve(skb, 2);
193 }
194 clear_bit(0, &mp->rx_task_busy);
195 /*
196 * If RX ring is empty of SKB, set a timer to try allocating
197 * again in a later time .
198 */
199 if ((mp->rx_ring_skbs == 0) && (mp->rx_timer_flag == 0)) {
200 printk(KERN_INFO "%s: Rx ring is empty\n", dev->name);
201 /* After 100mSec */
202 mp->timeout.expires = jiffies + (HZ / 10);
203 add_timer(&mp->timeout);
204 mp->rx_timer_flag = 1;
205 }
206#ifdef MV643XX_RX_QUEUE_FILL_ON_TASK
207 else {
208 /* Return interrupts */
209 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(mp->port_num),
210 INT_CAUSE_UNMASK_ALL);
211 }
212#endif
213}
214
215/*
216 * mv643xx_eth_rx_task_timer_wrapper
217 *
218 * Timer routine to wake up RX queue filling task. This function is
219 * used only in case the RX queue is empty, and all alloc_skb has
220 * failed (due to out of memory event).
221 *
222 * Input : pointer to ethernet interface network device structure
223 * Output : N/A
224 */
225static void mv643xx_eth_rx_task_timer_wrapper(unsigned long data)
226{
227 struct net_device *dev = (struct net_device *)data;
228 struct mv643xx_private *mp = netdev_priv(dev);
229
230 mp->rx_timer_flag = 0;
231 mv643xx_eth_rx_task((void *)data);
232}
233
234/*
235 * mv643xx_eth_update_mac_address
236 *
237 * Update the MAC address of the port in the address table
238 *
239 * Input : pointer to ethernet interface network device structure
240 * Output : N/A
241 */
242static void mv643xx_eth_update_mac_address(struct net_device *dev)
243{
244 struct mv643xx_private *mp = netdev_priv(dev);
245 unsigned int port_num = mp->port_num;
246
247 eth_port_init_mac_tables(port_num);
248 memcpy(mp->port_mac_addr, dev->dev_addr, 6);
249 eth_port_uc_addr_set(port_num, mp->port_mac_addr);
250}
251
252/*
253 * mv643xx_eth_set_rx_mode
254 *
255 * Change from promiscuos to regular rx mode
256 *
257 * Input : pointer to ethernet interface network device structure
258 * Output : N/A
259 */
260static void mv643xx_eth_set_rx_mode(struct net_device *dev)
261{
262 struct mv643xx_private *mp = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700263
Linus Torvalds1da177e2005-04-16 15:20:36 -0700264 if (dev->flags & IFF_PROMISC)
Dale Farnsworth7342cd82005-09-02 12:36:48 -0700265 mp->port_config |= (u32) MV643XX_ETH_UNICAST_PROMISCUOUS_MODE;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700266 else
Dale Farnsworth7342cd82005-09-02 12:36:48 -0700267 mp->port_config &= ~(u32) MV643XX_ETH_UNICAST_PROMISCUOUS_MODE;
268
269 mv_write(MV643XX_ETH_PORT_CONFIG_REG(mp->port_num), mp->port_config);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700270}
271
272/*
273 * mv643xx_eth_set_mac_address
274 *
275 * Change the interface's mac address.
276 * No special hardware thing should be done because interface is always
277 * put in promiscuous mode.
278 *
279 * Input : pointer to ethernet interface network device structure and
280 * a pointer to the designated entry to be added to the cache.
281 * Output : zero upon success, negative upon failure
282 */
283static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
284{
285 int i;
286
287 for (i = 0; i < 6; i++)
288 /* +2 is for the offset of the HW addr type */
289 dev->dev_addr[i] = ((unsigned char *)addr)[i + 2];
290 mv643xx_eth_update_mac_address(dev);
291 return 0;
292}
293
294/*
295 * mv643xx_eth_tx_timeout
296 *
297 * Called upon a timeout on transmitting a packet
298 *
299 * Input : pointer to ethernet interface network device structure.
300 * Output : N/A
301 */
302static void mv643xx_eth_tx_timeout(struct net_device *dev)
303{
304 struct mv643xx_private *mp = netdev_priv(dev);
305
306 printk(KERN_INFO "%s: TX timeout ", dev->name);
307
308 /* Do the reset outside of interrupt context */
309 schedule_work(&mp->tx_timeout_task);
310}
311
312/*
313 * mv643xx_eth_tx_timeout_task
314 *
315 * Actual routine to reset the adapter when a timeout on Tx has occurred
316 */
317static void mv643xx_eth_tx_timeout_task(struct net_device *dev)
318{
319 struct mv643xx_private *mp = netdev_priv(dev);
320
321 netif_device_detach(dev);
322 eth_port_reset(mp->port_num);
323 eth_port_start(mp);
324 netif_device_attach(dev);
325}
326
327/*
328 * mv643xx_eth_free_tx_queue
329 *
330 * Input : dev - a pointer to the required interface
331 *
332 * Output : 0 if was able to release skb , nonzero otherwise
333 */
334static int mv643xx_eth_free_tx_queue(struct net_device *dev,
335 unsigned int eth_int_cause_ext)
336{
337 struct mv643xx_private *mp = netdev_priv(dev);
338 struct net_device_stats *stats = &mp->stats;
339 struct pkt_info pkt_info;
340 int released = 1;
341
342 if (!(eth_int_cause_ext & (BIT0 | BIT8)))
343 return released;
344
345 spin_lock(&mp->lock);
346
347 /* Check only queue 0 */
348 while (eth_tx_return_desc(mp, &pkt_info) == ETH_OK) {
349 if (pkt_info.cmd_sts & BIT0) {
350 printk("%s: Error in TX\n", dev->name);
351 stats->tx_errors++;
352 }
353
354 /*
355 * If return_info is different than 0, release the skb.
356 * The case where return_info is not 0 is only in case
357 * when transmitted a scatter/gather packet, where only
358 * last skb releases the whole chain.
359 */
360 if (pkt_info.return_info) {
361 if (skb_shinfo(pkt_info.return_info)->nr_frags)
362 dma_unmap_page(NULL, pkt_info.buf_ptr,
363 pkt_info.byte_cnt,
364 DMA_TO_DEVICE);
365 else
366 dma_unmap_single(NULL, pkt_info.buf_ptr,
367 pkt_info.byte_cnt,
368 DMA_TO_DEVICE);
369
370 dev_kfree_skb_irq(pkt_info.return_info);
371 released = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700372 } else
373 dma_unmap_page(NULL, pkt_info.buf_ptr,
374 pkt_info.byte_cnt, DMA_TO_DEVICE);
375 }
376
377 spin_unlock(&mp->lock);
378
379 return released;
380}
381
382/*
383 * mv643xx_eth_receive
384 *
385 * This function is forward packets that are received from the port's
386 * queues toward kernel core or FastRoute them to another interface.
387 *
388 * Input : dev - a pointer to the required interface
389 * max - maximum number to receive (0 means unlimted)
390 *
391 * Output : number of served packets
392 */
393#ifdef MV643XX_NAPI
394static int mv643xx_eth_receive_queue(struct net_device *dev, int budget)
395#else
396static int mv643xx_eth_receive_queue(struct net_device *dev)
397#endif
398{
399 struct mv643xx_private *mp = netdev_priv(dev);
400 struct net_device_stats *stats = &mp->stats;
401 unsigned int received_packets = 0;
402 struct sk_buff *skb;
403 struct pkt_info pkt_info;
404
405#ifdef MV643XX_NAPI
Dale Farnsworthb1dd9ca2005-09-01 09:59:23 -0700406 while (budget-- > 0 && eth_port_receive(mp, &pkt_info) == ETH_OK) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700407#else
408 while (eth_port_receive(mp, &pkt_info) == ETH_OK) {
409#endif
410 mp->rx_ring_skbs--;
411 received_packets++;
Dale Farnsworthb1dd9ca2005-09-01 09:59:23 -0700412
Linus Torvalds1da177e2005-04-16 15:20:36 -0700413 /* Update statistics. Note byte count includes 4 byte CRC count */
414 stats->rx_packets++;
415 stats->rx_bytes += pkt_info.byte_cnt;
416 skb = pkt_info.return_info;
417 /*
418 * In case received a packet without first / last bits on OR
419 * the error summary bit is on, the packets needs to be dropeed.
420 */
421 if (((pkt_info.cmd_sts
422 & (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) !=
423 (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC))
424 || (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)) {
425 stats->rx_dropped++;
426 if ((pkt_info.cmd_sts & (ETH_RX_FIRST_DESC |
427 ETH_RX_LAST_DESC)) !=
428 (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) {
429 if (net_ratelimit())
430 printk(KERN_ERR
431 "%s: Received packet spread "
432 "on multiple descriptors\n",
433 dev->name);
434 }
435 if (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)
436 stats->rx_errors++;
437
438 dev_kfree_skb_irq(skb);
439 } else {
440 /*
441 * The -4 is for the CRC in the trailer of the
442 * received packet
443 */
444 skb_put(skb, pkt_info.byte_cnt - 4);
445 skb->dev = dev;
446
447 if (pkt_info.cmd_sts & ETH_LAYER_4_CHECKSUM_OK) {
448 skb->ip_summed = CHECKSUM_UNNECESSARY;
449 skb->csum = htons(
450 (pkt_info.cmd_sts & 0x0007fff8) >> 3);
451 }
452 skb->protocol = eth_type_trans(skb, dev);
453#ifdef MV643XX_NAPI
454 netif_receive_skb(skb);
455#else
456 netif_rx(skb);
457#endif
458 }
459 }
460
461 return received_packets;
462}
463
464/*
465 * mv643xx_eth_int_handler
466 *
467 * Main interrupt handler for the gigbit ethernet ports
468 *
469 * Input : irq - irq number (not used)
470 * dev_id - a pointer to the required interface's data structure
471 * regs - not used
472 * Output : N/A
473 */
474
475static irqreturn_t mv643xx_eth_int_handler(int irq, void *dev_id,
476 struct pt_regs *regs)
477{
478 struct net_device *dev = (struct net_device *)dev_id;
479 struct mv643xx_private *mp = netdev_priv(dev);
480 u32 eth_int_cause, eth_int_cause_ext = 0;
481 unsigned int port_num = mp->port_num;
482
483 /* Read interrupt cause registers */
484 eth_int_cause = mv_read(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num)) &
485 INT_CAUSE_UNMASK_ALL;
486
487 if (eth_int_cause & BIT1)
488 eth_int_cause_ext = mv_read(
489 MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num)) &
490 INT_CAUSE_UNMASK_ALL_EXT;
491
492#ifdef MV643XX_NAPI
493 if (!(eth_int_cause & 0x0007fffd)) {
494 /* Dont ack the Rx interrupt */
495#endif
496 /*
497 * Clear specific ethernet port intrerrupt registers by
498 * acknowleding relevant bits.
499 */
500 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num),
501 ~eth_int_cause);
502 if (eth_int_cause_ext != 0x0)
503 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG
504 (port_num), ~eth_int_cause_ext);
505
506 /* UDP change : We may need this */
507 if ((eth_int_cause_ext & 0x0000ffff) &&
508 (mv643xx_eth_free_tx_queue(dev, eth_int_cause_ext) == 0) &&
509 (mp->tx_ring_size > mp->tx_ring_skbs + MAX_DESCS_PER_SKB))
510 netif_wake_queue(dev);
511#ifdef MV643XX_NAPI
512 } else {
513 if (netif_rx_schedule_prep(dev)) {
514 /* Mask all the interrupts */
515 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), 0);
516 mv_write(MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG
517 (port_num), 0);
518 __netif_rx_schedule(dev);
519 }
520#else
521 if (eth_int_cause & (BIT2 | BIT11))
522 mv643xx_eth_receive_queue(dev, 0);
523
524 /*
525 * After forwarded received packets to upper layer, add a task
526 * in an interrupts enabled context that refills the RX ring
527 * with skb's.
528 */
529#ifdef MV643XX_RX_QUEUE_FILL_ON_TASK
530 /* Unmask all interrupts on ethernet port */
531 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num),
532 INT_CAUSE_MASK_ALL);
533 queue_task(&mp->rx_task, &tq_immediate);
534 mark_bh(IMMEDIATE_BH);
535#else
536 mp->rx_task.func(dev);
537#endif
538#endif
539 }
540 /* PHY status changed */
541 if (eth_int_cause_ext & (BIT16 | BIT20)) {
542 if (eth_port_link_is_up(port_num)) {
543 netif_carrier_on(dev);
544 netif_wake_queue(dev);
545 /* Start TX queue */
546 mv_write(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG
547 (port_num), 1);
548 } else {
549 netif_carrier_off(dev);
550 netif_stop_queue(dev);
551 }
552 }
553
554 /*
555 * If no real interrupt occured, exit.
556 * This can happen when using gigE interrupt coalescing mechanism.
557 */
558 if ((eth_int_cause == 0x0) && (eth_int_cause_ext == 0x0))
559 return IRQ_NONE;
560
561 return IRQ_HANDLED;
562}
563
564#ifdef MV643XX_COAL
565
566/*
567 * eth_port_set_rx_coal - Sets coalescing interrupt mechanism on RX path
568 *
569 * DESCRIPTION:
570 * This routine sets the RX coalescing interrupt mechanism parameter.
571 * This parameter is a timeout counter, that counts in 64 t_clk
572 * chunks ; that when timeout event occurs a maskable interrupt
573 * occurs.
574 * The parameter is calculated using the tClk of the MV-643xx chip
575 * , and the required delay of the interrupt in usec.
576 *
577 * INPUT:
578 * unsigned int eth_port_num Ethernet port number
579 * unsigned int t_clk t_clk of the MV-643xx chip in HZ units
580 * unsigned int delay Delay in usec
581 *
582 * OUTPUT:
583 * Interrupt coalescing mechanism value is set in MV-643xx chip.
584 *
585 * RETURN:
586 * The interrupt coalescing value set in the gigE port.
587 *
588 */
589static unsigned int eth_port_set_rx_coal(unsigned int eth_port_num,
590 unsigned int t_clk, unsigned int delay)
591{
592 unsigned int coal = ((t_clk / 1000000) * delay) / 64;
593
594 /* Set RX Coalescing mechanism */
595 mv_write(MV643XX_ETH_SDMA_CONFIG_REG(eth_port_num),
596 ((coal & 0x3fff) << 8) |
597 (mv_read(MV643XX_ETH_SDMA_CONFIG_REG(eth_port_num))
598 & 0xffc000ff));
599
600 return coal;
601}
602#endif
603
604/*
605 * eth_port_set_tx_coal - Sets coalescing interrupt mechanism on TX path
606 *
607 * DESCRIPTION:
608 * This routine sets the TX coalescing interrupt mechanism parameter.
609 * This parameter is a timeout counter, that counts in 64 t_clk
610 * chunks ; that when timeout event occurs a maskable interrupt
611 * occurs.
612 * The parameter is calculated using the t_cLK frequency of the
613 * MV-643xx chip and the required delay in the interrupt in uSec
614 *
615 * INPUT:
616 * unsigned int eth_port_num Ethernet port number
617 * unsigned int t_clk t_clk of the MV-643xx chip in HZ units
618 * unsigned int delay Delay in uSeconds
619 *
620 * OUTPUT:
621 * Interrupt coalescing mechanism value is set in MV-643xx chip.
622 *
623 * RETURN:
624 * The interrupt coalescing value set in the gigE port.
625 *
626 */
627static unsigned int eth_port_set_tx_coal(unsigned int eth_port_num,
628 unsigned int t_clk, unsigned int delay)
629{
630 unsigned int coal;
631 coal = ((t_clk / 1000000) * delay) / 64;
632 /* Set TX Coalescing mechanism */
633 mv_write(MV643XX_ETH_TX_FIFO_URGENT_THRESHOLD_REG(eth_port_num),
634 coal << 4);
635 return coal;
636}
637
638/*
639 * mv643xx_eth_open
640 *
641 * This function is called when openning the network device. The function
642 * should initialize all the hardware, initialize cyclic Rx/Tx
643 * descriptors chain and buffers and allocate an IRQ to the network
644 * device.
645 *
646 * Input : a pointer to the network device structure
647 *
648 * Output : zero of success , nonzero if fails.
649 */
650
651static int mv643xx_eth_open(struct net_device *dev)
652{
653 struct mv643xx_private *mp = netdev_priv(dev);
654 unsigned int port_num = mp->port_num;
655 int err;
656
657 spin_lock_irq(&mp->lock);
658
659 err = request_irq(dev->irq, mv643xx_eth_int_handler,
Benjamin Herrenschmidt16b81752005-04-16 15:24:30 -0700660 SA_SHIRQ | SA_SAMPLE_RANDOM, dev->name, dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700661
662 if (err) {
663 printk(KERN_ERR "Can not assign IRQ number to MV643XX_eth%d\n",
664 port_num);
665 err = -EAGAIN;
666 goto out;
667 }
668
669 if (mv643xx_eth_real_open(dev)) {
670 printk("%s: Error opening interface\n", dev->name);
671 err = -EBUSY;
672 goto out_free;
673 }
674
675 spin_unlock_irq(&mp->lock);
676
677 return 0;
678
679out_free:
680 free_irq(dev->irq, dev);
681
682out:
683 spin_unlock_irq(&mp->lock);
684
685 return err;
686}
687
688/*
689 * ether_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory.
690 *
691 * DESCRIPTION:
692 * This function prepares a Rx chained list of descriptors and packet
693 * buffers in a form of a ring. The routine must be called after port
694 * initialization routine and before port start routine.
695 * The Ethernet SDMA engine uses CPU bus addresses to access the various
696 * devices in the system (i.e. DRAM). This function uses the ethernet
697 * struct 'virtual to physical' routine (set by the user) to set the ring
698 * with physical addresses.
699 *
700 * INPUT:
701 * struct mv643xx_private *mp Ethernet Port Control srtuct.
702 *
703 * OUTPUT:
704 * The routine updates the Ethernet port control struct with information
705 * regarding the Rx descriptors and buffers.
706 *
707 * RETURN:
708 * None.
709 */
710static void ether_init_rx_desc_ring(struct mv643xx_private *mp)
711{
712 volatile struct eth_rx_desc *p_rx_desc;
713 int rx_desc_num = mp->rx_ring_size;
714 int i;
715
716 /* initialize the next_desc_ptr links in the Rx descriptors ring */
717 p_rx_desc = (struct eth_rx_desc *)mp->p_rx_desc_area;
718 for (i = 0; i < rx_desc_num; i++) {
719 p_rx_desc[i].next_desc_ptr = mp->rx_desc_dma +
720 ((i + 1) % rx_desc_num) * sizeof(struct eth_rx_desc);
721 }
722
723 /* Save Rx desc pointer to driver struct. */
724 mp->rx_curr_desc_q = 0;
725 mp->rx_used_desc_q = 0;
726
727 mp->rx_desc_area_size = rx_desc_num * sizeof(struct eth_rx_desc);
728
729 /* Add the queue to the list of RX queues of this port */
730 mp->port_rx_queue_command |= 1;
731}
732
733/*
734 * ether_init_tx_desc_ring - Curve a Tx chain desc list and buffer in memory.
735 *
736 * DESCRIPTION:
737 * This function prepares a Tx chained list of descriptors and packet
738 * buffers in a form of a ring. The routine must be called after port
739 * initialization routine and before port start routine.
740 * The Ethernet SDMA engine uses CPU bus addresses to access the various
741 * devices in the system (i.e. DRAM). This function uses the ethernet
742 * struct 'virtual to physical' routine (set by the user) to set the ring
743 * with physical addresses.
744 *
745 * INPUT:
746 * struct mv643xx_private *mp Ethernet Port Control srtuct.
747 *
748 * OUTPUT:
749 * The routine updates the Ethernet port control struct with information
750 * regarding the Tx descriptors and buffers.
751 *
752 * RETURN:
753 * None.
754 */
755static void ether_init_tx_desc_ring(struct mv643xx_private *mp)
756{
757 int tx_desc_num = mp->tx_ring_size;
758 struct eth_tx_desc *p_tx_desc;
759 int i;
760
761 /* Initialize the next_desc_ptr links in the Tx descriptors ring */
762 p_tx_desc = (struct eth_tx_desc *)mp->p_tx_desc_area;
763 for (i = 0; i < tx_desc_num; i++) {
764 p_tx_desc[i].next_desc_ptr = mp->tx_desc_dma +
765 ((i + 1) % tx_desc_num) * sizeof(struct eth_tx_desc);
766 }
767
768 mp->tx_curr_desc_q = 0;
769 mp->tx_used_desc_q = 0;
770#ifdef MV643XX_CHECKSUM_OFFLOAD_TX
771 mp->tx_first_desc_q = 0;
772#endif
773
774 mp->tx_desc_area_size = tx_desc_num * sizeof(struct eth_tx_desc);
775
776 /* Add the queue to the list of Tx queues of this port */
777 mp->port_tx_queue_command |= 1;
778}
779
780/* Helper function for mv643xx_eth_open */
781static int mv643xx_eth_real_open(struct net_device *dev)
782{
783 struct mv643xx_private *mp = netdev_priv(dev);
784 unsigned int port_num = mp->port_num;
785 unsigned int size;
786
787 /* Stop RX Queues */
788 mv_write(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num), 0x0000ff00);
789
790 /* Clear the ethernet port interrupts */
791 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num), 0);
792 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num), 0);
793
794 /* Unmask RX buffer and TX end interrupt */
795 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num),
796 INT_CAUSE_UNMASK_ALL);
797
798 /* Unmask phy and link status changes interrupts */
799 mv_write(MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG(port_num),
800 INT_CAUSE_UNMASK_ALL_EXT);
801
802 /* Set the MAC Address */
803 memcpy(mp->port_mac_addr, dev->dev_addr, 6);
804
805 eth_port_init(mp);
806
807 INIT_WORK(&mp->rx_task, (void (*)(void *))mv643xx_eth_rx_task, dev);
808
809 memset(&mp->timeout, 0, sizeof(struct timer_list));
810 mp->timeout.function = mv643xx_eth_rx_task_timer_wrapper;
811 mp->timeout.data = (unsigned long)dev;
812
813 mp->rx_task_busy = 0;
814 mp->rx_timer_flag = 0;
815
816 /* Allocate RX and TX skb rings */
817 mp->rx_skb = kmalloc(sizeof(*mp->rx_skb) * mp->rx_ring_size,
818 GFP_KERNEL);
819 if (!mp->rx_skb) {
820 printk(KERN_ERR "%s: Cannot allocate Rx skb ring\n", dev->name);
821 return -ENOMEM;
822 }
823 mp->tx_skb = kmalloc(sizeof(*mp->tx_skb) * mp->tx_ring_size,
824 GFP_KERNEL);
825 if (!mp->tx_skb) {
826 printk(KERN_ERR "%s: Cannot allocate Tx skb ring\n", dev->name);
827 kfree(mp->rx_skb);
828 return -ENOMEM;
829 }
830
831 /* Allocate TX ring */
832 mp->tx_ring_skbs = 0;
833 size = mp->tx_ring_size * sizeof(struct eth_tx_desc);
834 mp->tx_desc_area_size = size;
835
836 if (mp->tx_sram_size) {
837 mp->p_tx_desc_area = ioremap(mp->tx_sram_addr,
838 mp->tx_sram_size);
839 mp->tx_desc_dma = mp->tx_sram_addr;
840 } else
841 mp->p_tx_desc_area = dma_alloc_coherent(NULL, size,
842 &mp->tx_desc_dma,
843 GFP_KERNEL);
844
845 if (!mp->p_tx_desc_area) {
846 printk(KERN_ERR "%s: Cannot allocate Tx Ring (size %d bytes)\n",
847 dev->name, size);
848 kfree(mp->rx_skb);
849 kfree(mp->tx_skb);
850 return -ENOMEM;
851 }
852 BUG_ON((u32) mp->p_tx_desc_area & 0xf); /* check 16-byte alignment */
853 memset((void *)mp->p_tx_desc_area, 0, mp->tx_desc_area_size);
854
855 ether_init_tx_desc_ring(mp);
856
857 /* Allocate RX ring */
858 mp->rx_ring_skbs = 0;
859 size = mp->rx_ring_size * sizeof(struct eth_rx_desc);
860 mp->rx_desc_area_size = size;
861
862 if (mp->rx_sram_size) {
863 mp->p_rx_desc_area = ioremap(mp->rx_sram_addr,
864 mp->rx_sram_size);
865 mp->rx_desc_dma = mp->rx_sram_addr;
866 } else
867 mp->p_rx_desc_area = dma_alloc_coherent(NULL, size,
868 &mp->rx_desc_dma,
869 GFP_KERNEL);
870
871 if (!mp->p_rx_desc_area) {
872 printk(KERN_ERR "%s: Cannot allocate Rx ring (size %d bytes)\n",
873 dev->name, size);
874 printk(KERN_ERR "%s: Freeing previously allocated TX queues...",
875 dev->name);
876 if (mp->rx_sram_size)
877 iounmap(mp->p_rx_desc_area);
878 else
879 dma_free_coherent(NULL, mp->tx_desc_area_size,
880 mp->p_tx_desc_area, mp->tx_desc_dma);
881 kfree(mp->rx_skb);
882 kfree(mp->tx_skb);
883 return -ENOMEM;
884 }
885 memset((void *)mp->p_rx_desc_area, 0, size);
886
887 ether_init_rx_desc_ring(mp);
888
889 mv643xx_eth_rx_task(dev); /* Fill RX ring with skb's */
890
891 eth_port_start(mp);
892
893 /* Interrupt Coalescing */
894
895#ifdef MV643XX_COAL
896 mp->rx_int_coal =
897 eth_port_set_rx_coal(port_num, 133000000, MV643XX_RX_COAL);
898#endif
899
900 mp->tx_int_coal =
901 eth_port_set_tx_coal(port_num, 133000000, MV643XX_TX_COAL);
902
903 netif_start_queue(dev);
904
905 return 0;
906}
907
908static void mv643xx_eth_free_tx_rings(struct net_device *dev)
909{
910 struct mv643xx_private *mp = netdev_priv(dev);
911 unsigned int port_num = mp->port_num;
912 unsigned int curr;
913
914 /* Stop Tx Queues */
915 mv_write(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num), 0x0000ff00);
916
917 /* Free outstanding skb's on TX rings */
918 for (curr = 0; mp->tx_ring_skbs && curr < mp->tx_ring_size; curr++) {
919 if (mp->tx_skb[curr]) {
920 dev_kfree_skb(mp->tx_skb[curr]);
921 mp->tx_ring_skbs--;
922 }
923 }
924 if (mp->tx_ring_skbs)
925 printk("%s: Error on Tx descriptor free - could not free %d"
926 " descriptors\n", dev->name, mp->tx_ring_skbs);
927
928 /* Free TX ring */
929 if (mp->tx_sram_size)
930 iounmap(mp->p_tx_desc_area);
931 else
932 dma_free_coherent(NULL, mp->tx_desc_area_size,
933 mp->p_tx_desc_area, mp->tx_desc_dma);
934}
935
936static void mv643xx_eth_free_rx_rings(struct net_device *dev)
937{
938 struct mv643xx_private *mp = netdev_priv(dev);
939 unsigned int port_num = mp->port_num;
940 int curr;
941
942 /* Stop RX Queues */
943 mv_write(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num), 0x0000ff00);
944
945 /* Free preallocated skb's on RX rings */
946 for (curr = 0; mp->rx_ring_skbs && curr < mp->rx_ring_size; curr++) {
947 if (mp->rx_skb[curr]) {
948 dev_kfree_skb(mp->rx_skb[curr]);
949 mp->rx_ring_skbs--;
950 }
951 }
952
953 if (mp->rx_ring_skbs)
954 printk(KERN_ERR
955 "%s: Error in freeing Rx Ring. %d skb's still"
956 " stuck in RX Ring - ignoring them\n", dev->name,
957 mp->rx_ring_skbs);
958 /* Free RX ring */
959 if (mp->rx_sram_size)
960 iounmap(mp->p_rx_desc_area);
961 else
962 dma_free_coherent(NULL, mp->rx_desc_area_size,
963 mp->p_rx_desc_area, mp->rx_desc_dma);
964}
965
966/*
967 * mv643xx_eth_stop
968 *
969 * This function is used when closing the network device.
970 * It updates the hardware,
971 * release all memory that holds buffers and descriptors and release the IRQ.
972 * Input : a pointer to the device structure
973 * Output : zero if success , nonzero if fails
974 */
975
976/* Helper function for mv643xx_eth_stop */
977
978static int mv643xx_eth_real_stop(struct net_device *dev)
979{
980 struct mv643xx_private *mp = netdev_priv(dev);
981 unsigned int port_num = mp->port_num;
982
983 netif_carrier_off(dev);
984 netif_stop_queue(dev);
985
986 mv643xx_eth_free_tx_rings(dev);
987 mv643xx_eth_free_rx_rings(dev);
988
989 eth_port_reset(mp->port_num);
990
991 /* Disable ethernet port interrupts */
992 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num), 0);
993 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num), 0);
994
995 /* Mask RX buffer and TX end interrupt */
996 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), 0);
997
998 /* Mask phy and link status changes interrupts */
999 mv_write(MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG(port_num), 0);
1000
1001 return 0;
1002}
1003
1004static int mv643xx_eth_stop(struct net_device *dev)
1005{
1006 struct mv643xx_private *mp = netdev_priv(dev);
1007
1008 spin_lock_irq(&mp->lock);
1009
1010 mv643xx_eth_real_stop(dev);
1011
1012 free_irq(dev->irq, dev);
1013 spin_unlock_irq(&mp->lock);
1014
1015 return 0;
1016}
1017
1018#ifdef MV643XX_NAPI
1019static void mv643xx_tx(struct net_device *dev)
1020{
1021 struct mv643xx_private *mp = netdev_priv(dev);
1022 struct pkt_info pkt_info;
1023
1024 while (eth_tx_return_desc(mp, &pkt_info) == ETH_OK) {
1025 if (pkt_info.return_info) {
1026 if (skb_shinfo(pkt_info.return_info)->nr_frags)
1027 dma_unmap_page(NULL, pkt_info.buf_ptr,
1028 pkt_info.byte_cnt,
1029 DMA_TO_DEVICE);
1030 else
1031 dma_unmap_single(NULL, pkt_info.buf_ptr,
1032 pkt_info.byte_cnt,
1033 DMA_TO_DEVICE);
1034
1035 dev_kfree_skb_irq(pkt_info.return_info);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001036 } else
1037 dma_unmap_page(NULL, pkt_info.buf_ptr,
1038 pkt_info.byte_cnt, DMA_TO_DEVICE);
1039 }
1040
1041 if (netif_queue_stopped(dev) &&
1042 mp->tx_ring_size > mp->tx_ring_skbs + MAX_DESCS_PER_SKB)
1043 netif_wake_queue(dev);
1044}
1045
1046/*
1047 * mv643xx_poll
1048 *
1049 * This function is used in case of NAPI
1050 */
1051static int mv643xx_poll(struct net_device *dev, int *budget)
1052{
1053 struct mv643xx_private *mp = netdev_priv(dev);
1054 int done = 1, orig_budget, work_done;
1055 unsigned int port_num = mp->port_num;
1056 unsigned long flags;
1057
1058#ifdef MV643XX_TX_FAST_REFILL
1059 if (++mp->tx_clean_threshold > 5) {
1060 spin_lock_irqsave(&mp->lock, flags);
1061 mv643xx_tx(dev);
1062 mp->tx_clean_threshold = 0;
1063 spin_unlock_irqrestore(&mp->lock, flags);
1064 }
1065#endif
1066
1067 if ((mv_read(MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port_num)))
1068 != (u32) mp->rx_used_desc_q) {
1069 orig_budget = *budget;
1070 if (orig_budget > dev->quota)
1071 orig_budget = dev->quota;
1072 work_done = mv643xx_eth_receive_queue(dev, orig_budget);
1073 mp->rx_task.func(dev);
1074 *budget -= work_done;
1075 dev->quota -= work_done;
1076 if (work_done >= orig_budget)
1077 done = 0;
1078 }
1079
1080 if (done) {
1081 spin_lock_irqsave(&mp->lock, flags);
1082 __netif_rx_complete(dev);
1083 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num), 0);
1084 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num), 0);
1085 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num),
1086 INT_CAUSE_UNMASK_ALL);
1087 mv_write(MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG(port_num),
1088 INT_CAUSE_UNMASK_ALL_EXT);
1089 spin_unlock_irqrestore(&mp->lock, flags);
1090 }
1091
1092 return done ? 0 : 1;
1093}
1094#endif
1095
1096/*
1097 * mv643xx_eth_start_xmit
1098 *
1099 * This function is queues a packet in the Tx descriptor for
1100 * required port.
1101 *
1102 * Input : skb - a pointer to socket buffer
1103 * dev - a pointer to the required port
1104 *
1105 * Output : zero upon success
1106 */
1107static int mv643xx_eth_start_xmit(struct sk_buff *skb, struct net_device *dev)
1108{
1109 struct mv643xx_private *mp = netdev_priv(dev);
1110 struct net_device_stats *stats = &mp->stats;
1111 ETH_FUNC_RET_STATUS status;
1112 unsigned long flags;
1113 struct pkt_info pkt_info;
1114
1115 if (netif_queue_stopped(dev)) {
1116 printk(KERN_ERR
1117 "%s: Tried sending packet when interface is stopped\n",
1118 dev->name);
1119 return 1;
1120 }
1121
1122 /* This is a hard error, log it. */
1123 if ((mp->tx_ring_size - mp->tx_ring_skbs) <=
1124 (skb_shinfo(skb)->nr_frags + 1)) {
1125 netif_stop_queue(dev);
1126 printk(KERN_ERR
1127 "%s: Bug in mv643xx_eth - Trying to transmit when"
1128 " queue full !\n", dev->name);
1129 return 1;
1130 }
1131
1132 /* Paranoid check - this shouldn't happen */
1133 if (skb == NULL) {
1134 stats->tx_dropped++;
1135 printk(KERN_ERR "mv64320_eth paranoid check failed\n");
1136 return 1;
1137 }
1138
1139 spin_lock_irqsave(&mp->lock, flags);
1140
1141 /* Update packet info data structure -- DMA owned, first last */
1142#ifdef MV643XX_CHECKSUM_OFFLOAD_TX
1143 if (!skb_shinfo(skb)->nr_frags) {
1144linear:
1145 if (skb->ip_summed != CHECKSUM_HW) {
Dale Farnsworth26006362005-08-22 15:53:29 -07001146 /* Errata BTS #50, IHL must be 5 if no HW checksum */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001147 pkt_info.cmd_sts = ETH_TX_ENABLE_INTERRUPT |
Dale Farnsworth26006362005-08-22 15:53:29 -07001148 ETH_TX_FIRST_DESC |
1149 ETH_TX_LAST_DESC |
1150 5 << ETH_TX_IHL_SHIFT;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001151 pkt_info.l4i_chk = 0;
1152 } else {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001153
1154 pkt_info.cmd_sts = ETH_TX_ENABLE_INTERRUPT |
Dale Farnsworth26006362005-08-22 15:53:29 -07001155 ETH_TX_FIRST_DESC |
1156 ETH_TX_LAST_DESC |
1157 ETH_GEN_TCP_UDP_CHECKSUM |
1158 ETH_GEN_IP_V_4_CHECKSUM |
1159 skb->nh.iph->ihl << ETH_TX_IHL_SHIFT;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001160 /* CPU already calculated pseudo header checksum. */
1161 if (skb->nh.iph->protocol == IPPROTO_UDP) {
1162 pkt_info.cmd_sts |= ETH_UDP_FRAME;
1163 pkt_info.l4i_chk = skb->h.uh->check;
1164 } else if (skb->nh.iph->protocol == IPPROTO_TCP)
1165 pkt_info.l4i_chk = skb->h.th->check;
1166 else {
1167 printk(KERN_ERR
1168 "%s: chksum proto != TCP or UDP\n",
1169 dev->name);
1170 spin_unlock_irqrestore(&mp->lock, flags);
1171 return 1;
1172 }
1173 }
1174 pkt_info.byte_cnt = skb->len;
1175 pkt_info.buf_ptr = dma_map_single(NULL, skb->data, skb->len,
1176 DMA_TO_DEVICE);
1177 pkt_info.return_info = skb;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001178 status = eth_port_send(mp, &pkt_info);
1179 if ((status == ETH_ERROR) || (status == ETH_QUEUE_FULL))
1180 printk(KERN_ERR "%s: Error on transmitting packet\n",
1181 dev->name);
1182 stats->tx_bytes += pkt_info.byte_cnt;
1183 } else {
1184 unsigned int frag;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001185
1186 /* Since hardware can't handle unaligned fragments smaller
1187 * than 9 bytes, if we find any, we linearize the skb
1188 * and start again. When I've seen it, it's always been
1189 * the first frag (probably near the end of the page),
1190 * but we check all frags to be safe.
1191 */
1192 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
1193 skb_frag_t *fragp;
1194
1195 fragp = &skb_shinfo(skb)->frags[frag];
1196 if (fragp->size <= 8 && fragp->page_offset & 0x7) {
1197 skb_linearize(skb, GFP_ATOMIC);
1198 printk(KERN_DEBUG "%s: unaligned tiny fragment"
1199 "%d of %d, fixed\n",
1200 dev->name, frag,
1201 skb_shinfo(skb)->nr_frags);
1202 goto linear;
1203 }
1204 }
1205
1206 /* first frag which is skb header */
1207 pkt_info.byte_cnt = skb_headlen(skb);
1208 pkt_info.buf_ptr = dma_map_single(NULL, skb->data,
1209 skb_headlen(skb),
1210 DMA_TO_DEVICE);
1211 pkt_info.l4i_chk = 0;
1212 pkt_info.return_info = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001213
Dale Farnsworth26006362005-08-22 15:53:29 -07001214 if (skb->ip_summed != CHECKSUM_HW)
1215 /* Errata BTS #50, IHL must be 5 if no HW checksum */
1216 pkt_info.cmd_sts = ETH_TX_FIRST_DESC |
1217 5 << ETH_TX_IHL_SHIFT;
1218 else {
1219 pkt_info.cmd_sts = ETH_TX_FIRST_DESC |
1220 ETH_GEN_TCP_UDP_CHECKSUM |
1221 ETH_GEN_IP_V_4_CHECKSUM |
1222 skb->nh.iph->ihl << ETH_TX_IHL_SHIFT;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001223 /* CPU already calculated pseudo header checksum. */
1224 if (skb->nh.iph->protocol == IPPROTO_UDP) {
1225 pkt_info.cmd_sts |= ETH_UDP_FRAME;
1226 pkt_info.l4i_chk = skb->h.uh->check;
1227 } else if (skb->nh.iph->protocol == IPPROTO_TCP)
1228 pkt_info.l4i_chk = skb->h.th->check;
1229 else {
1230 printk(KERN_ERR
1231 "%s: chksum proto != TCP or UDP\n",
1232 dev->name);
1233 spin_unlock_irqrestore(&mp->lock, flags);
1234 return 1;
1235 }
1236 }
1237
1238 status = eth_port_send(mp, &pkt_info);
1239 if (status != ETH_OK) {
1240 if ((status == ETH_ERROR))
1241 printk(KERN_ERR
1242 "%s: Error on transmitting packet\n",
1243 dev->name);
1244 if (status == ETH_QUEUE_FULL)
1245 printk("Error on Queue Full \n");
1246 if (status == ETH_QUEUE_LAST_RESOURCE)
1247 printk("Tx resource error \n");
1248 }
1249 stats->tx_bytes += pkt_info.byte_cnt;
1250
1251 /* Check for the remaining frags */
1252 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
1253 skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
1254 pkt_info.l4i_chk = 0x0000;
1255 pkt_info.cmd_sts = 0x00000000;
1256
1257 /* Last Frag enables interrupt and frees the skb */
1258 if (frag == (skb_shinfo(skb)->nr_frags - 1)) {
1259 pkt_info.cmd_sts |= ETH_TX_ENABLE_INTERRUPT |
1260 ETH_TX_LAST_DESC;
1261 pkt_info.return_info = skb;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001262 } else {
1263 pkt_info.return_info = 0;
1264 }
1265 pkt_info.l4i_chk = 0;
1266 pkt_info.byte_cnt = this_frag->size;
1267
1268 pkt_info.buf_ptr = dma_map_page(NULL, this_frag->page,
1269 this_frag->page_offset,
1270 this_frag->size,
1271 DMA_TO_DEVICE);
1272
1273 status = eth_port_send(mp, &pkt_info);
1274
1275 if (status != ETH_OK) {
1276 if ((status == ETH_ERROR))
1277 printk(KERN_ERR "%s: Error on "
1278 "transmitting packet\n",
1279 dev->name);
1280
1281 if (status == ETH_QUEUE_LAST_RESOURCE)
1282 printk("Tx resource error \n");
1283
1284 if (status == ETH_QUEUE_FULL)
1285 printk("Queue is full \n");
1286 }
1287 stats->tx_bytes += pkt_info.byte_cnt;
1288 }
1289 }
1290#else
1291 pkt_info.cmd_sts = ETH_TX_ENABLE_INTERRUPT | ETH_TX_FIRST_DESC |
1292 ETH_TX_LAST_DESC;
1293 pkt_info.l4i_chk = 0;
1294 pkt_info.byte_cnt = skb->len;
1295 pkt_info.buf_ptr = dma_map_single(NULL, skb->data, skb->len,
1296 DMA_TO_DEVICE);
1297 pkt_info.return_info = skb;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001298 status = eth_port_send(mp, &pkt_info);
1299 if ((status == ETH_ERROR) || (status == ETH_QUEUE_FULL))
1300 printk(KERN_ERR "%s: Error on transmitting packet\n",
1301 dev->name);
1302 stats->tx_bytes += pkt_info.byte_cnt;
1303#endif
1304
1305 /* Check if TX queue can handle another skb. If not, then
1306 * signal higher layers to stop requesting TX
1307 */
1308 if (mp->tx_ring_size <= (mp->tx_ring_skbs + MAX_DESCS_PER_SKB))
1309 /*
1310 * Stop getting skb's from upper layers.
1311 * Getting skb's from upper layers will be enabled again after
1312 * packets are released.
1313 */
1314 netif_stop_queue(dev);
1315
1316 /* Update statistics and start of transmittion time */
1317 stats->tx_packets++;
1318 dev->trans_start = jiffies;
1319
1320 spin_unlock_irqrestore(&mp->lock, flags);
1321
1322 return 0; /* success */
1323}
1324
1325/*
1326 * mv643xx_eth_get_stats
1327 *
1328 * Returns a pointer to the interface statistics.
1329 *
1330 * Input : dev - a pointer to the required interface
1331 *
1332 * Output : a pointer to the interface's statistics
1333 */
1334
1335static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *dev)
1336{
1337 struct mv643xx_private *mp = netdev_priv(dev);
1338
1339 return &mp->stats;
1340}
1341
Dale Farnsworth63c9e542005-09-02 13:49:10 -07001342#ifdef CONFIG_NET_POLL_CONTROLLER
1343static inline void mv643xx_enable_irq(struct mv643xx_private *mp)
1344{
1345 int port_num = mp->port_num;
1346 unsigned long flags;
1347
1348 spin_lock_irqsave(&mp->lock, flags);
1349 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num),
1350 INT_CAUSE_UNMASK_ALL);
1351 mv_write(MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG(port_num),
1352 INT_CAUSE_UNMASK_ALL_EXT);
1353 spin_unlock_irqrestore(&mp->lock, flags);
1354}
1355
1356static inline void mv643xx_disable_irq(struct mv643xx_private *mp)
1357{
1358 int port_num = mp->port_num;
1359 unsigned long flags;
1360
1361 spin_lock_irqsave(&mp->lock, flags);
1362 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num),
1363 INT_CAUSE_MASK_ALL);
1364 mv_write(MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG(port_num),
1365 INT_CAUSE_MASK_ALL_EXT);
1366 spin_unlock_irqrestore(&mp->lock, flags);
1367}
1368
1369static void mv643xx_netpoll(struct net_device *netdev)
1370{
1371 struct mv643xx_private *mp = netdev_priv(netdev);
1372
1373 mv643xx_disable_irq(mp);
1374 mv643xx_eth_int_handler(netdev->irq, netdev, NULL);
1375 mv643xx_enable_irq(mp);
1376}
1377#endif
1378
Linus Torvalds1da177e2005-04-16 15:20:36 -07001379/*/
1380 * mv643xx_eth_probe
1381 *
1382 * First function called after registering the network device.
1383 * It's purpose is to initialize the device as an ethernet device,
1384 * fill the ethernet device structure with pointers * to functions,
1385 * and set the MAC address of the interface
1386 *
1387 * Input : struct device *
1388 * Output : -ENOMEM if failed , 0 if success
1389 */
1390static int mv643xx_eth_probe(struct device *ddev)
1391{
1392 struct platform_device *pdev = to_platform_device(ddev);
1393 struct mv643xx_eth_platform_data *pd;
1394 int port_num = pdev->id;
1395 struct mv643xx_private *mp;
1396 struct net_device *dev;
1397 u8 *p;
1398 struct resource *res;
1399 int err;
1400
1401 dev = alloc_etherdev(sizeof(struct mv643xx_private));
1402 if (!dev)
1403 return -ENOMEM;
1404
1405 dev_set_drvdata(ddev, dev);
1406
1407 mp = netdev_priv(dev);
1408
1409 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1410 BUG_ON(!res);
1411 dev->irq = res->start;
1412
1413 mp->port_num = port_num;
1414
1415 dev->open = mv643xx_eth_open;
1416 dev->stop = mv643xx_eth_stop;
1417 dev->hard_start_xmit = mv643xx_eth_start_xmit;
1418 dev->get_stats = mv643xx_eth_get_stats;
1419 dev->set_mac_address = mv643xx_eth_set_mac_address;
1420 dev->set_multicast_list = mv643xx_eth_set_rx_mode;
1421
1422 /* No need to Tx Timeout */
1423 dev->tx_timeout = mv643xx_eth_tx_timeout;
1424#ifdef MV643XX_NAPI
1425 dev->poll = mv643xx_poll;
1426 dev->weight = 64;
1427#endif
1428
Dale Farnsworth63c9e542005-09-02 13:49:10 -07001429#ifdef CONFIG_NET_POLL_CONTROLLER
1430 dev->poll_controller = mv643xx_netpoll;
1431#endif
1432
Linus Torvalds1da177e2005-04-16 15:20:36 -07001433 dev->watchdog_timeo = 2 * HZ;
1434 dev->tx_queue_len = mp->tx_ring_size;
1435 dev->base_addr = 0;
1436 dev->change_mtu = mv643xx_eth_change_mtu;
1437 SET_ETHTOOL_OPS(dev, &mv643xx_ethtool_ops);
1438
1439#ifdef MV643XX_CHECKSUM_OFFLOAD_TX
1440#ifdef MAX_SKB_FRAGS
1441 /*
1442 * Zero copy can only work if we use Discovery II memory. Else, we will
1443 * have to map the buffers to ISA memory which is only 16 MB
1444 */
1445 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_HW_CSUM;
1446#endif
1447#endif
1448
1449 /* Configure the timeout task */
1450 INIT_WORK(&mp->tx_timeout_task,
1451 (void (*)(void *))mv643xx_eth_tx_timeout_task, dev);
1452
1453 spin_lock_init(&mp->lock);
1454
1455 /* set default config values */
1456 eth_port_uc_addr_get(dev, dev->dev_addr);
1457 mp->port_config = MV643XX_ETH_PORT_CONFIG_DEFAULT_VALUE;
1458 mp->port_config_extend = MV643XX_ETH_PORT_CONFIG_EXTEND_DEFAULT_VALUE;
1459 mp->port_sdma_config = MV643XX_ETH_PORT_SDMA_CONFIG_DEFAULT_VALUE;
1460 mp->port_serial_control = MV643XX_ETH_PORT_SERIAL_CONTROL_DEFAULT_VALUE;
1461 mp->rx_ring_size = MV643XX_ETH_PORT_DEFAULT_RECEIVE_QUEUE_SIZE;
1462 mp->tx_ring_size = MV643XX_ETH_PORT_DEFAULT_TRANSMIT_QUEUE_SIZE;
1463
1464 pd = pdev->dev.platform_data;
1465 if (pd) {
1466 if (pd->mac_addr != NULL)
1467 memcpy(dev->dev_addr, pd->mac_addr, 6);
1468
1469 if (pd->phy_addr || pd->force_phy_addr)
1470 ethernet_phy_set(port_num, pd->phy_addr);
1471
1472 if (pd->port_config || pd->force_port_config)
1473 mp->port_config = pd->port_config;
1474
1475 if (pd->port_config_extend || pd->force_port_config_extend)
1476 mp->port_config_extend = pd->port_config_extend;
1477
1478 if (pd->port_sdma_config || pd->force_port_sdma_config)
1479 mp->port_sdma_config = pd->port_sdma_config;
1480
1481 if (pd->port_serial_control || pd->force_port_serial_control)
1482 mp->port_serial_control = pd->port_serial_control;
1483
1484 if (pd->rx_queue_size)
1485 mp->rx_ring_size = pd->rx_queue_size;
1486
1487 if (pd->tx_queue_size)
1488 mp->tx_ring_size = pd->tx_queue_size;
1489
1490 if (pd->tx_sram_size) {
1491 mp->tx_sram_size = pd->tx_sram_size;
1492 mp->tx_sram_addr = pd->tx_sram_addr;
1493 }
1494
1495 if (pd->rx_sram_size) {
1496 mp->rx_sram_size = pd->rx_sram_size;
1497 mp->rx_sram_addr = pd->rx_sram_addr;
1498 }
1499 }
1500
1501 err = ethernet_phy_detect(port_num);
1502 if (err) {
1503 pr_debug("MV643xx ethernet port %d: "
1504 "No PHY detected at addr %d\n",
1505 port_num, ethernet_phy_get(port_num));
1506 return err;
1507 }
1508
1509 err = register_netdev(dev);
1510 if (err)
1511 goto out;
1512
1513 p = dev->dev_addr;
1514 printk(KERN_NOTICE
1515 "%s: port %d with MAC address %02x:%02x:%02x:%02x:%02x:%02x\n",
1516 dev->name, port_num, p[0], p[1], p[2], p[3], p[4], p[5]);
1517
1518 if (dev->features & NETIF_F_SG)
1519 printk(KERN_NOTICE "%s: Scatter Gather Enabled\n", dev->name);
1520
1521 if (dev->features & NETIF_F_IP_CSUM)
1522 printk(KERN_NOTICE "%s: TX TCP/IP Checksumming Supported\n",
1523 dev->name);
1524
1525#ifdef MV643XX_CHECKSUM_OFFLOAD_TX
1526 printk(KERN_NOTICE "%s: RX TCP/UDP Checksum Offload ON \n", dev->name);
1527#endif
1528
1529#ifdef MV643XX_COAL
1530 printk(KERN_NOTICE "%s: TX and RX Interrupt Coalescing ON \n",
1531 dev->name);
1532#endif
1533
1534#ifdef MV643XX_NAPI
1535 printk(KERN_NOTICE "%s: RX NAPI Enabled \n", dev->name);
1536#endif
1537
1538 return 0;
1539
1540out:
1541 free_netdev(dev);
1542
1543 return err;
1544}
1545
1546static int mv643xx_eth_remove(struct device *ddev)
1547{
1548 struct net_device *dev = dev_get_drvdata(ddev);
1549
1550 unregister_netdev(dev);
1551 flush_scheduled_work();
1552
1553 free_netdev(dev);
1554 dev_set_drvdata(ddev, NULL);
1555 return 0;
1556}
1557
1558static int mv643xx_eth_shared_probe(struct device *ddev)
1559{
1560 struct platform_device *pdev = to_platform_device(ddev);
1561 struct resource *res;
1562
1563 printk(KERN_NOTICE "MV-643xx 10/100/1000 Ethernet Driver\n");
1564
1565 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1566 if (res == NULL)
1567 return -ENODEV;
1568
1569 mv643xx_eth_shared_base = ioremap(res->start,
1570 MV643XX_ETH_SHARED_REGS_SIZE);
1571 if (mv643xx_eth_shared_base == NULL)
1572 return -ENOMEM;
1573
1574 return 0;
1575
1576}
1577
1578static int mv643xx_eth_shared_remove(struct device *ddev)
1579{
1580 iounmap(mv643xx_eth_shared_base);
1581 mv643xx_eth_shared_base = NULL;
1582
1583 return 0;
1584}
1585
1586static struct device_driver mv643xx_eth_driver = {
1587 .name = MV643XX_ETH_NAME,
1588 .bus = &platform_bus_type,
1589 .probe = mv643xx_eth_probe,
1590 .remove = mv643xx_eth_remove,
1591};
1592
1593static struct device_driver mv643xx_eth_shared_driver = {
1594 .name = MV643XX_ETH_SHARED_NAME,
1595 .bus = &platform_bus_type,
1596 .probe = mv643xx_eth_shared_probe,
1597 .remove = mv643xx_eth_shared_remove,
1598};
1599
1600/*
1601 * mv643xx_init_module
1602 *
1603 * Registers the network drivers into the Linux kernel
1604 *
1605 * Input : N/A
1606 *
1607 * Output : N/A
1608 */
1609static int __init mv643xx_init_module(void)
1610{
1611 int rc;
1612
1613 rc = driver_register(&mv643xx_eth_shared_driver);
1614 if (!rc) {
1615 rc = driver_register(&mv643xx_eth_driver);
1616 if (rc)
1617 driver_unregister(&mv643xx_eth_shared_driver);
1618 }
1619 return rc;
1620}
1621
1622/*
1623 * mv643xx_cleanup_module
1624 *
1625 * Registers the network drivers into the Linux kernel
1626 *
1627 * Input : N/A
1628 *
1629 * Output : N/A
1630 */
1631static void __exit mv643xx_cleanup_module(void)
1632{
1633 driver_unregister(&mv643xx_eth_driver);
1634 driver_unregister(&mv643xx_eth_shared_driver);
1635}
1636
1637module_init(mv643xx_init_module);
1638module_exit(mv643xx_cleanup_module);
1639
1640MODULE_LICENSE("GPL");
1641MODULE_AUTHOR( "Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, Manish Lachwani"
1642 " and Dale Farnsworth");
1643MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
1644
1645/*
1646 * The second part is the low level driver of the gigE ethernet ports.
1647 */
1648
1649/*
1650 * Marvell's Gigabit Ethernet controller low level driver
1651 *
1652 * DESCRIPTION:
1653 * This file introduce low level API to Marvell's Gigabit Ethernet
1654 * controller. This Gigabit Ethernet Controller driver API controls
1655 * 1) Operations (i.e. port init, start, reset etc').
1656 * 2) Data flow (i.e. port send, receive etc').
1657 * Each Gigabit Ethernet port is controlled via
1658 * struct mv643xx_private.
1659 * This struct includes user configuration information as well as
1660 * driver internal data needed for its operations.
1661 *
1662 * Supported Features:
1663 * - This low level driver is OS independent. Allocating memory for
1664 * the descriptor rings and buffers are not within the scope of
1665 * this driver.
1666 * - The user is free from Rx/Tx queue managing.
1667 * - This low level driver introduce functionality API that enable
1668 * the to operate Marvell's Gigabit Ethernet Controller in a
1669 * convenient way.
1670 * - Simple Gigabit Ethernet port operation API.
1671 * - Simple Gigabit Ethernet port data flow API.
1672 * - Data flow and operation API support per queue functionality.
1673 * - Support cached descriptors for better performance.
1674 * - Enable access to all four DRAM banks and internal SRAM memory
1675 * spaces.
1676 * - PHY access and control API.
1677 * - Port control register configuration API.
1678 * - Full control over Unicast and Multicast MAC configurations.
1679 *
1680 * Operation flow:
1681 *
1682 * Initialization phase
1683 * This phase complete the initialization of the the
1684 * mv643xx_private struct.
1685 * User information regarding port configuration has to be set
1686 * prior to calling the port initialization routine.
1687 *
1688 * In this phase any port Tx/Rx activity is halted, MIB counters
1689 * are cleared, PHY address is set according to user parameter and
1690 * access to DRAM and internal SRAM memory spaces.
1691 *
1692 * Driver ring initialization
1693 * Allocating memory for the descriptor rings and buffers is not
1694 * within the scope of this driver. Thus, the user is required to
1695 * allocate memory for the descriptors ring and buffers. Those
1696 * memory parameters are used by the Rx and Tx ring initialization
1697 * routines in order to curve the descriptor linked list in a form
1698 * of a ring.
1699 * Note: Pay special attention to alignment issues when using
1700 * cached descriptors/buffers. In this phase the driver store
1701 * information in the mv643xx_private struct regarding each queue
1702 * ring.
1703 *
1704 * Driver start
1705 * This phase prepares the Ethernet port for Rx and Tx activity.
1706 * It uses the information stored in the mv643xx_private struct to
1707 * initialize the various port registers.
1708 *
1709 * Data flow:
1710 * All packet references to/from the driver are done using
1711 * struct pkt_info.
1712 * This struct is a unified struct used with Rx and Tx operations.
1713 * This way the user is not required to be familiar with neither
1714 * Tx nor Rx descriptors structures.
1715 * The driver's descriptors rings are management by indexes.
1716 * Those indexes controls the ring resources and used to indicate
1717 * a SW resource error:
1718 * 'current'
1719 * This index points to the current available resource for use. For
1720 * example in Rx process this index will point to the descriptor
1721 * that will be passed to the user upon calling the receive
1722 * routine. In Tx process, this index will point to the descriptor
1723 * that will be assigned with the user packet info and transmitted.
1724 * 'used'
1725 * This index points to the descriptor that need to restore its
1726 * resources. For example in Rx process, using the Rx buffer return
1727 * API will attach the buffer returned in packet info to the
1728 * descriptor pointed by 'used'. In Tx process, using the Tx
1729 * descriptor return will merely return the user packet info with
1730 * the command status of the transmitted buffer pointed by the
1731 * 'used' index. Nevertheless, it is essential to use this routine
1732 * to update the 'used' index.
1733 * 'first'
1734 * This index supports Tx Scatter-Gather. It points to the first
1735 * descriptor of a packet assembled of multiple buffers. For
1736 * example when in middle of Such packet we have a Tx resource
1737 * error the 'curr' index get the value of 'first' to indicate
1738 * that the ring returned to its state before trying to transmit
1739 * this packet.
1740 *
1741 * Receive operation:
1742 * The eth_port_receive API set the packet information struct,
1743 * passed by the caller, with received information from the
1744 * 'current' SDMA descriptor.
1745 * It is the user responsibility to return this resource back
1746 * to the Rx descriptor ring to enable the reuse of this source.
1747 * Return Rx resource is done using the eth_rx_return_buff API.
1748 *
1749 * Transmit operation:
1750 * The eth_port_send API supports Scatter-Gather which enables to
1751 * send a packet spanned over multiple buffers. This means that
1752 * for each packet info structure given by the user and put into
1753 * the Tx descriptors ring, will be transmitted only if the 'LAST'
1754 * bit will be set in the packet info command status field. This
1755 * API also consider restriction regarding buffer alignments and
1756 * sizes.
1757 * The user must return a Tx resource after ensuring the buffer
1758 * has been transmitted to enable the Tx ring indexes to update.
1759 *
1760 * BOARD LAYOUT
1761 * This device is on-board. No jumper diagram is necessary.
1762 *
1763 * EXTERNAL INTERFACE
1764 *
1765 * Prior to calling the initialization routine eth_port_init() the user
1766 * must set the following fields under mv643xx_private struct:
1767 * port_num User Ethernet port number.
1768 * port_mac_addr[6] User defined port MAC address.
1769 * port_config User port configuration value.
1770 * port_config_extend User port config extend value.
1771 * port_sdma_config User port SDMA config value.
1772 * port_serial_control User port serial control value.
1773 *
1774 * This driver data flow is done using the struct pkt_info which
1775 * is a unified struct for Rx and Tx operations:
1776 *
1777 * byte_cnt Tx/Rx descriptor buffer byte count.
1778 * l4i_chk CPU provided TCP Checksum. For Tx operation
1779 * only.
1780 * cmd_sts Tx/Rx descriptor command status.
1781 * buf_ptr Tx/Rx descriptor buffer pointer.
1782 * return_info Tx/Rx user resource return information.
1783 */
1784
1785/* defines */
1786/* SDMA command macros */
1787#define ETH_ENABLE_TX_QUEUE(eth_port) \
1788 mv_write(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port), 1)
1789
1790/* locals */
1791
1792/* PHY routines */
1793static int ethernet_phy_get(unsigned int eth_port_num);
1794static void ethernet_phy_set(unsigned int eth_port_num, int phy_addr);
1795
1796/* Ethernet Port routines */
1797static int eth_port_uc_addr(unsigned int eth_port_num, unsigned char uc_nibble,
1798 int option);
1799
1800/*
1801 * eth_port_init - Initialize the Ethernet port driver
1802 *
1803 * DESCRIPTION:
1804 * This function prepares the ethernet port to start its activity:
1805 * 1) Completes the ethernet port driver struct initialization toward port
1806 * start routine.
1807 * 2) Resets the device to a quiescent state in case of warm reboot.
1808 * 3) Enable SDMA access to all four DRAM banks as well as internal SRAM.
1809 * 4) Clean MAC tables. The reset status of those tables is unknown.
1810 * 5) Set PHY address.
1811 * Note: Call this routine prior to eth_port_start routine and after
1812 * setting user values in the user fields of Ethernet port control
1813 * struct.
1814 *
1815 * INPUT:
1816 * struct mv643xx_private *mp Ethernet port control struct
1817 *
1818 * OUTPUT:
1819 * See description.
1820 *
1821 * RETURN:
1822 * None.
1823 */
1824static void eth_port_init(struct mv643xx_private *mp)
1825{
1826 mp->port_rx_queue_command = 0;
1827 mp->port_tx_queue_command = 0;
1828
1829 mp->rx_resource_err = 0;
1830 mp->tx_resource_err = 0;
1831
1832 eth_port_reset(mp->port_num);
1833
1834 eth_port_init_mac_tables(mp->port_num);
1835
1836 ethernet_phy_reset(mp->port_num);
1837}
1838
1839/*
1840 * eth_port_start - Start the Ethernet port activity.
1841 *
1842 * DESCRIPTION:
1843 * This routine prepares the Ethernet port for Rx and Tx activity:
1844 * 1. Initialize Tx and Rx Current Descriptor Pointer for each queue that
1845 * has been initialized a descriptor's ring (using
1846 * ether_init_tx_desc_ring for Tx and ether_init_rx_desc_ring for Rx)
1847 * 2. Initialize and enable the Ethernet configuration port by writing to
1848 * the port's configuration and command registers.
1849 * 3. Initialize and enable the SDMA by writing to the SDMA's
1850 * configuration and command registers. After completing these steps,
1851 * the ethernet port SDMA can starts to perform Rx and Tx activities.
1852 *
1853 * Note: Each Rx and Tx queue descriptor's list must be initialized prior
1854 * to calling this function (use ether_init_tx_desc_ring for Tx queues
1855 * and ether_init_rx_desc_ring for Rx queues).
1856 *
1857 * INPUT:
1858 * struct mv643xx_private *mp Ethernet port control struct
1859 *
1860 * OUTPUT:
1861 * Ethernet port is ready to receive and transmit.
1862 *
1863 * RETURN:
1864 * None.
1865 */
1866static void eth_port_start(struct mv643xx_private *mp)
1867{
1868 unsigned int port_num = mp->port_num;
1869 int tx_curr_desc, rx_curr_desc;
1870
1871 /* Assignment of Tx CTRP of given queue */
1872 tx_curr_desc = mp->tx_curr_desc_q;
1873 mv_write(MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port_num),
1874 (u32)((struct eth_tx_desc *)mp->tx_desc_dma + tx_curr_desc));
1875
1876 /* Assignment of Rx CRDP of given queue */
1877 rx_curr_desc = mp->rx_curr_desc_q;
1878 mv_write(MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port_num),
1879 (u32)((struct eth_rx_desc *)mp->rx_desc_dma + rx_curr_desc));
1880
1881 /* Add the assigned Ethernet address to the port's address table */
1882 eth_port_uc_addr_set(port_num, mp->port_mac_addr);
1883
1884 /* Assign port configuration and command. */
1885 mv_write(MV643XX_ETH_PORT_CONFIG_REG(port_num), mp->port_config);
1886
1887 mv_write(MV643XX_ETH_PORT_CONFIG_EXTEND_REG(port_num),
1888 mp->port_config_extend);
1889
1890
1891 /* Increase the Rx side buffer size if supporting GigE */
1892 if (mp->port_serial_control & MV643XX_ETH_SET_GMII_SPEED_TO_1000)
1893 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num),
1894 (mp->port_serial_control & 0xfff1ffff) | (0x5 << 17));
1895 else
1896 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num),
1897 mp->port_serial_control);
1898
1899 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num),
1900 mv_read(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num)) |
1901 MV643XX_ETH_SERIAL_PORT_ENABLE);
1902
1903 /* Assign port SDMA configuration */
1904 mv_write(MV643XX_ETH_SDMA_CONFIG_REG(port_num),
1905 mp->port_sdma_config);
1906
1907 /* Enable port Rx. */
1908 mv_write(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num),
1909 mp->port_rx_queue_command);
Dale Farnsworth8f543712005-09-02 12:34:35 -07001910
1911 /* Disable port bandwidth limits by clearing MTU register */
1912 mv_write(MV643XX_ETH_MAXIMUM_TRANSMIT_UNIT(port_num), 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001913}
1914
1915/*
1916 * eth_port_uc_addr_set - This function Set the port Unicast address.
1917 *
1918 * DESCRIPTION:
1919 * This function Set the port Ethernet MAC address.
1920 *
1921 * INPUT:
1922 * unsigned int eth_port_num Port number.
1923 * char * p_addr Address to be set
1924 *
1925 * OUTPUT:
1926 * Set MAC address low and high registers. also calls eth_port_uc_addr()
1927 * To set the unicast table with the proper information.
1928 *
1929 * RETURN:
1930 * N/A.
1931 *
1932 */
1933static void eth_port_uc_addr_set(unsigned int eth_port_num,
1934 unsigned char *p_addr)
1935{
1936 unsigned int mac_h;
1937 unsigned int mac_l;
1938
1939 mac_l = (p_addr[4] << 8) | (p_addr[5]);
1940 mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) | (p_addr[2] << 8) |
1941 (p_addr[3] << 0);
1942
1943 mv_write(MV643XX_ETH_MAC_ADDR_LOW(eth_port_num), mac_l);
1944 mv_write(MV643XX_ETH_MAC_ADDR_HIGH(eth_port_num), mac_h);
1945
1946 /* Accept frames of this address */
1947 eth_port_uc_addr(eth_port_num, p_addr[5], ACCEPT_MAC_ADDR);
1948
1949 return;
1950}
1951
1952/*
1953 * eth_port_uc_addr_get - This function retrieves the port Unicast address
1954 * (MAC address) from the ethernet hw registers.
1955 *
1956 * DESCRIPTION:
1957 * This function retrieves the port Ethernet MAC address.
1958 *
1959 * INPUT:
1960 * unsigned int eth_port_num Port number.
1961 * char *MacAddr pointer where the MAC address is stored
1962 *
1963 * OUTPUT:
1964 * Copy the MAC address to the location pointed to by MacAddr
1965 *
1966 * RETURN:
1967 * N/A.
1968 *
1969 */
1970static void eth_port_uc_addr_get(struct net_device *dev, unsigned char *p_addr)
1971{
1972 struct mv643xx_private *mp = netdev_priv(dev);
1973 unsigned int mac_h;
1974 unsigned int mac_l;
1975
1976 mac_h = mv_read(MV643XX_ETH_MAC_ADDR_HIGH(mp->port_num));
1977 mac_l = mv_read(MV643XX_ETH_MAC_ADDR_LOW(mp->port_num));
1978
1979 p_addr[0] = (mac_h >> 24) & 0xff;
1980 p_addr[1] = (mac_h >> 16) & 0xff;
1981 p_addr[2] = (mac_h >> 8) & 0xff;
1982 p_addr[3] = mac_h & 0xff;
1983 p_addr[4] = (mac_l >> 8) & 0xff;
1984 p_addr[5] = mac_l & 0xff;
1985}
1986
1987/*
1988 * eth_port_uc_addr - This function Set the port unicast address table
1989 *
1990 * DESCRIPTION:
1991 * This function locates the proper entry in the Unicast table for the
1992 * specified MAC nibble and sets its properties according to function
1993 * parameters.
1994 *
1995 * INPUT:
1996 * unsigned int eth_port_num Port number.
1997 * unsigned char uc_nibble Unicast MAC Address last nibble.
1998 * int option 0 = Add, 1 = remove address.
1999 *
2000 * OUTPUT:
2001 * This function add/removes MAC addresses from the port unicast address
2002 * table.
2003 *
2004 * RETURN:
2005 * true is output succeeded.
2006 * false if option parameter is invalid.
2007 *
2008 */
2009static int eth_port_uc_addr(unsigned int eth_port_num, unsigned char uc_nibble,
2010 int option)
2011{
2012 unsigned int unicast_reg;
2013 unsigned int tbl_offset;
2014 unsigned int reg_offset;
2015
2016 /* Locate the Unicast table entry */
2017 uc_nibble = (0xf & uc_nibble);
2018 tbl_offset = (uc_nibble / 4) * 4; /* Register offset from unicast table base */
2019 reg_offset = uc_nibble % 4; /* Entry offset within the above register */
2020
2021 switch (option) {
2022 case REJECT_MAC_ADDR:
2023 /* Clear accepts frame bit at given unicast DA table entry */
2024 unicast_reg = mv_read((MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE
2025 (eth_port_num) + tbl_offset));
2026
2027 unicast_reg &= (0x0E << (8 * reg_offset));
2028
2029 mv_write((MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE
2030 (eth_port_num) + tbl_offset), unicast_reg);
2031 break;
2032
2033 case ACCEPT_MAC_ADDR:
2034 /* Set accepts frame bit at unicast DA filter table entry */
2035 unicast_reg =
2036 mv_read((MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE
2037 (eth_port_num) + tbl_offset));
2038
2039 unicast_reg |= (0x01 << (8 * reg_offset));
2040
2041 mv_write((MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE
2042 (eth_port_num) + tbl_offset), unicast_reg);
2043
2044 break;
2045
2046 default:
2047 return 0;
2048 }
2049
2050 return 1;
2051}
2052
2053/*
2054 * eth_port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables
2055 *
2056 * DESCRIPTION:
2057 * Go through all the DA filter tables (Unicast, Special Multicast &
2058 * Other Multicast) and set each entry to 0.
2059 *
2060 * INPUT:
2061 * unsigned int eth_port_num Ethernet Port number.
2062 *
2063 * OUTPUT:
2064 * Multicast and Unicast packets are rejected.
2065 *
2066 * RETURN:
2067 * None.
2068 */
2069static void eth_port_init_mac_tables(unsigned int eth_port_num)
2070{
2071 int table_index;
2072
2073 /* Clear DA filter unicast table (Ex_dFUT) */
2074 for (table_index = 0; table_index <= 0xC; table_index += 4)
2075 mv_write((MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE
2076 (eth_port_num) + table_index), 0);
2077
2078 for (table_index = 0; table_index <= 0xFC; table_index += 4) {
2079 /* Clear DA filter special multicast table (Ex_dFSMT) */
2080 mv_write((MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE
2081 (eth_port_num) + table_index), 0);
2082 /* Clear DA filter other multicast table (Ex_dFOMT) */
2083 mv_write((MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE
2084 (eth_port_num) + table_index), 0);
2085 }
2086}
2087
2088/*
2089 * eth_clear_mib_counters - Clear all MIB counters
2090 *
2091 * DESCRIPTION:
2092 * This function clears all MIB counters of a specific ethernet port.
2093 * A read from the MIB counter will reset the counter.
2094 *
2095 * INPUT:
2096 * unsigned int eth_port_num Ethernet Port number.
2097 *
2098 * OUTPUT:
2099 * After reading all MIB counters, the counters resets.
2100 *
2101 * RETURN:
2102 * MIB counter value.
2103 *
2104 */
2105static void eth_clear_mib_counters(unsigned int eth_port_num)
2106{
2107 int i;
2108
2109 /* Perform dummy reads from MIB counters */
2110 for (i = ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i < ETH_MIB_LATE_COLLISION;
2111 i += 4)
2112 mv_read(MV643XX_ETH_MIB_COUNTERS_BASE(eth_port_num) + i);
2113}
2114
2115static inline u32 read_mib(struct mv643xx_private *mp, int offset)
2116{
2117 return mv_read(MV643XX_ETH_MIB_COUNTERS_BASE(mp->port_num) + offset);
2118}
2119
2120static void eth_update_mib_counters(struct mv643xx_private *mp)
2121{
2122 struct mv643xx_mib_counters *p = &mp->mib_counters;
2123 int offset;
2124
2125 p->good_octets_received +=
2126 read_mib(mp, ETH_MIB_GOOD_OCTETS_RECEIVED_LOW);
2127 p->good_octets_received +=
2128 (u64)read_mib(mp, ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH) << 32;
2129
2130 for (offset = ETH_MIB_BAD_OCTETS_RECEIVED;
2131 offset <= ETH_MIB_FRAMES_1024_TO_MAX_OCTETS;
2132 offset += 4)
2133 *(u32 *)((char *)p + offset) = read_mib(mp, offset);
2134
2135 p->good_octets_sent += read_mib(mp, ETH_MIB_GOOD_OCTETS_SENT_LOW);
2136 p->good_octets_sent +=
2137 (u64)read_mib(mp, ETH_MIB_GOOD_OCTETS_SENT_HIGH) << 32;
2138
2139 for (offset = ETH_MIB_GOOD_FRAMES_SENT;
2140 offset <= ETH_MIB_LATE_COLLISION;
2141 offset += 4)
2142 *(u32 *)((char *)p + offset) = read_mib(mp, offset);
2143}
2144
2145/*
2146 * ethernet_phy_detect - Detect whether a phy is present
2147 *
2148 * DESCRIPTION:
2149 * This function tests whether there is a PHY present on
2150 * the specified port.
2151 *
2152 * INPUT:
2153 * unsigned int eth_port_num Ethernet Port number.
2154 *
2155 * OUTPUT:
2156 * None
2157 *
2158 * RETURN:
2159 * 0 on success
2160 * -ENODEV on failure
2161 *
2162 */
2163static int ethernet_phy_detect(unsigned int port_num)
2164{
2165 unsigned int phy_reg_data0;
2166 int auto_neg;
2167
2168 eth_port_read_smi_reg(port_num, 0, &phy_reg_data0);
2169 auto_neg = phy_reg_data0 & 0x1000;
2170 phy_reg_data0 ^= 0x1000; /* invert auto_neg */
2171 eth_port_write_smi_reg(port_num, 0, phy_reg_data0);
2172
2173 eth_port_read_smi_reg(port_num, 0, &phy_reg_data0);
2174 if ((phy_reg_data0 & 0x1000) == auto_neg)
2175 return -ENODEV; /* change didn't take */
2176
2177 phy_reg_data0 ^= 0x1000;
2178 eth_port_write_smi_reg(port_num, 0, phy_reg_data0);
2179 return 0;
2180}
2181
2182/*
2183 * ethernet_phy_get - Get the ethernet port PHY address.
2184 *
2185 * DESCRIPTION:
2186 * This routine returns the given ethernet port PHY address.
2187 *
2188 * INPUT:
2189 * unsigned int eth_port_num Ethernet Port number.
2190 *
2191 * OUTPUT:
2192 * None.
2193 *
2194 * RETURN:
2195 * PHY address.
2196 *
2197 */
2198static int ethernet_phy_get(unsigned int eth_port_num)
2199{
2200 unsigned int reg_data;
2201
2202 reg_data = mv_read(MV643XX_ETH_PHY_ADDR_REG);
2203
2204 return ((reg_data >> (5 * eth_port_num)) & 0x1f);
2205}
2206
2207/*
2208 * ethernet_phy_set - Set the ethernet port PHY address.
2209 *
2210 * DESCRIPTION:
2211 * This routine sets the given ethernet port PHY address.
2212 *
2213 * INPUT:
2214 * unsigned int eth_port_num Ethernet Port number.
2215 * int phy_addr PHY address.
2216 *
2217 * OUTPUT:
2218 * None.
2219 *
2220 * RETURN:
2221 * None.
2222 *
2223 */
2224static void ethernet_phy_set(unsigned int eth_port_num, int phy_addr)
2225{
2226 u32 reg_data;
2227 int addr_shift = 5 * eth_port_num;
2228
2229 reg_data = mv_read(MV643XX_ETH_PHY_ADDR_REG);
2230 reg_data &= ~(0x1f << addr_shift);
2231 reg_data |= (phy_addr & 0x1f) << addr_shift;
2232 mv_write(MV643XX_ETH_PHY_ADDR_REG, reg_data);
2233}
2234
2235/*
2236 * ethernet_phy_reset - Reset Ethernet port PHY.
2237 *
2238 * DESCRIPTION:
2239 * This routine utilizes the SMI interface to reset the ethernet port PHY.
2240 *
2241 * INPUT:
2242 * unsigned int eth_port_num Ethernet Port number.
2243 *
2244 * OUTPUT:
2245 * The PHY is reset.
2246 *
2247 * RETURN:
2248 * None.
2249 *
2250 */
2251static void ethernet_phy_reset(unsigned int eth_port_num)
2252{
2253 unsigned int phy_reg_data;
2254
2255 /* Reset the PHY */
2256 eth_port_read_smi_reg(eth_port_num, 0, &phy_reg_data);
2257 phy_reg_data |= 0x8000; /* Set bit 15 to reset the PHY */
2258 eth_port_write_smi_reg(eth_port_num, 0, phy_reg_data);
2259}
2260
2261/*
2262 * eth_port_reset - Reset Ethernet port
2263 *
2264 * DESCRIPTION:
2265 * This routine resets the chip by aborting any SDMA engine activity and
2266 * clearing the MIB counters. The Receiver and the Transmit unit are in
2267 * idle state after this command is performed and the port is disabled.
2268 *
2269 * INPUT:
2270 * unsigned int eth_port_num Ethernet Port number.
2271 *
2272 * OUTPUT:
2273 * Channel activity is halted.
2274 *
2275 * RETURN:
2276 * None.
2277 *
2278 */
2279static void eth_port_reset(unsigned int port_num)
2280{
2281 unsigned int reg_data;
2282
2283 /* Stop Tx port activity. Check port Tx activity. */
2284 reg_data = mv_read(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num));
2285
2286 if (reg_data & 0xFF) {
2287 /* Issue stop command for active channels only */
2288 mv_write(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num),
2289 (reg_data << 8));
2290
2291 /* Wait for all Tx activity to terminate. */
2292 /* Check port cause register that all Tx queues are stopped */
2293 while (mv_read(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num))
2294 & 0xFF)
2295 udelay(10);
2296 }
2297
2298 /* Stop Rx port activity. Check port Rx activity. */
2299 reg_data = mv_read(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num));
2300
2301 if (reg_data & 0xFF) {
2302 /* Issue stop command for active channels only */
2303 mv_write(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num),
2304 (reg_data << 8));
2305
2306 /* Wait for all Rx activity to terminate. */
2307 /* Check port cause register that all Rx queues are stopped */
2308 while (mv_read(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num))
2309 & 0xFF)
2310 udelay(10);
2311 }
2312
2313 /* Clear all MIB counters */
2314 eth_clear_mib_counters(port_num);
2315
2316 /* Reset the Enable bit in the Configuration Register */
2317 reg_data = mv_read(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num));
2318 reg_data &= ~MV643XX_ETH_SERIAL_PORT_ENABLE;
2319 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num), reg_data);
2320}
2321
Linus Torvalds1da177e2005-04-16 15:20:36 -07002322
2323static int eth_port_autoneg_supported(unsigned int eth_port_num)
2324{
2325 unsigned int phy_reg_data0;
2326
2327 eth_port_read_smi_reg(eth_port_num, 0, &phy_reg_data0);
2328
2329 return phy_reg_data0 & 0x1000;
2330}
2331
2332static int eth_port_link_is_up(unsigned int eth_port_num)
2333{
2334 unsigned int phy_reg_data1;
2335
2336 eth_port_read_smi_reg(eth_port_num, 1, &phy_reg_data1);
2337
2338 if (eth_port_autoneg_supported(eth_port_num)) {
2339 if (phy_reg_data1 & 0x20) /* auto-neg complete */
2340 return 1;
2341 } else if (phy_reg_data1 & 0x4) /* link up */
2342 return 1;
2343
2344 return 0;
2345}
2346
2347/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07002348 * eth_port_read_smi_reg - Read PHY registers
2349 *
2350 * DESCRIPTION:
2351 * This routine utilize the SMI interface to interact with the PHY in
2352 * order to perform PHY register read.
2353 *
2354 * INPUT:
2355 * unsigned int port_num Ethernet Port number.
2356 * unsigned int phy_reg PHY register address offset.
2357 * unsigned int *value Register value buffer.
2358 *
2359 * OUTPUT:
2360 * Write the value of a specified PHY register into given buffer.
2361 *
2362 * RETURN:
2363 * false if the PHY is busy or read data is not in valid state.
2364 * true otherwise.
2365 *
2366 */
2367static void eth_port_read_smi_reg(unsigned int port_num,
2368 unsigned int phy_reg, unsigned int *value)
2369{
2370 int phy_addr = ethernet_phy_get(port_num);
2371 unsigned long flags;
2372 int i;
2373
2374 /* the SMI register is a shared resource */
2375 spin_lock_irqsave(&mv643xx_eth_phy_lock, flags);
2376
2377 /* wait for the SMI register to become available */
2378 for (i = 0; mv_read(MV643XX_ETH_SMI_REG) & ETH_SMI_BUSY; i++) {
2379 if (i == PHY_WAIT_ITERATIONS) {
2380 printk("mv643xx PHY busy timeout, port %d\n", port_num);
2381 goto out;
2382 }
2383 udelay(PHY_WAIT_MICRO_SECONDS);
2384 }
2385
2386 mv_write(MV643XX_ETH_SMI_REG,
2387 (phy_addr << 16) | (phy_reg << 21) | ETH_SMI_OPCODE_READ);
2388
2389 /* now wait for the data to be valid */
2390 for (i = 0; !(mv_read(MV643XX_ETH_SMI_REG) & ETH_SMI_READ_VALID); i++) {
2391 if (i == PHY_WAIT_ITERATIONS) {
2392 printk("mv643xx PHY read timeout, port %d\n", port_num);
2393 goto out;
2394 }
2395 udelay(PHY_WAIT_MICRO_SECONDS);
2396 }
2397
2398 *value = mv_read(MV643XX_ETH_SMI_REG) & 0xffff;
2399out:
2400 spin_unlock_irqrestore(&mv643xx_eth_phy_lock, flags);
2401}
2402
2403/*
2404 * eth_port_write_smi_reg - Write to PHY registers
2405 *
2406 * DESCRIPTION:
2407 * This routine utilize the SMI interface to interact with the PHY in
2408 * order to perform writes to PHY registers.
2409 *
2410 * INPUT:
2411 * unsigned int eth_port_num Ethernet Port number.
2412 * unsigned int phy_reg PHY register address offset.
2413 * unsigned int value Register value.
2414 *
2415 * OUTPUT:
2416 * Write the given value to the specified PHY register.
2417 *
2418 * RETURN:
2419 * false if the PHY is busy.
2420 * true otherwise.
2421 *
2422 */
2423static void eth_port_write_smi_reg(unsigned int eth_port_num,
2424 unsigned int phy_reg, unsigned int value)
2425{
2426 int phy_addr;
2427 int i;
2428 unsigned long flags;
2429
2430 phy_addr = ethernet_phy_get(eth_port_num);
2431
2432 /* the SMI register is a shared resource */
2433 spin_lock_irqsave(&mv643xx_eth_phy_lock, flags);
2434
2435 /* wait for the SMI register to become available */
2436 for (i = 0; mv_read(MV643XX_ETH_SMI_REG) & ETH_SMI_BUSY; i++) {
2437 if (i == PHY_WAIT_ITERATIONS) {
2438 printk("mv643xx PHY busy timeout, port %d\n",
2439 eth_port_num);
2440 goto out;
2441 }
2442 udelay(PHY_WAIT_MICRO_SECONDS);
2443 }
2444
2445 mv_write(MV643XX_ETH_SMI_REG, (phy_addr << 16) | (phy_reg << 21) |
2446 ETH_SMI_OPCODE_WRITE | (value & 0xffff));
2447out:
2448 spin_unlock_irqrestore(&mv643xx_eth_phy_lock, flags);
2449}
2450
2451/*
2452 * eth_port_send - Send an Ethernet packet
2453 *
2454 * DESCRIPTION:
2455 * This routine send a given packet described by p_pktinfo parameter. It
2456 * supports transmitting of a packet spaned over multiple buffers. The
2457 * routine updates 'curr' and 'first' indexes according to the packet
2458 * segment passed to the routine. In case the packet segment is first,
2459 * the 'first' index is update. In any case, the 'curr' index is updated.
2460 * If the routine get into Tx resource error it assigns 'curr' index as
2461 * 'first'. This way the function can abort Tx process of multiple
2462 * descriptors per packet.
2463 *
2464 * INPUT:
2465 * struct mv643xx_private *mp Ethernet Port Control srtuct.
2466 * struct pkt_info *p_pkt_info User packet buffer.
2467 *
2468 * OUTPUT:
2469 * Tx ring 'curr' and 'first' indexes are updated.
2470 *
2471 * RETURN:
2472 * ETH_QUEUE_FULL in case of Tx resource error.
2473 * ETH_ERROR in case the routine can not access Tx desc ring.
2474 * ETH_QUEUE_LAST_RESOURCE if the routine uses the last Tx resource.
2475 * ETH_OK otherwise.
2476 *
2477 */
2478#ifdef MV643XX_CHECKSUM_OFFLOAD_TX
2479/*
2480 * Modified to include the first descriptor pointer in case of SG
2481 */
2482static ETH_FUNC_RET_STATUS eth_port_send(struct mv643xx_private *mp,
2483 struct pkt_info *p_pkt_info)
2484{
2485 int tx_desc_curr, tx_desc_used, tx_first_desc, tx_next_desc;
2486 struct eth_tx_desc *current_descriptor;
2487 struct eth_tx_desc *first_descriptor;
2488 u32 command;
2489
2490 /* Do not process Tx ring in case of Tx ring resource error */
2491 if (mp->tx_resource_err)
2492 return ETH_QUEUE_FULL;
2493
2494 /*
2495 * The hardware requires that each buffer that is <= 8 bytes
2496 * in length must be aligned on an 8 byte boundary.
2497 */
2498 if (p_pkt_info->byte_cnt <= 8 && p_pkt_info->buf_ptr & 0x7) {
2499 printk(KERN_ERR
2500 "mv643xx_eth port %d: packet size <= 8 problem\n",
2501 mp->port_num);
2502 return ETH_ERROR;
2503 }
2504
Dale Farnsworthb111ceb2005-09-02 10:25:24 -07002505 mp->tx_ring_skbs++;
2506 BUG_ON(mp->tx_ring_skbs > mp->tx_ring_size);
2507
Linus Torvalds1da177e2005-04-16 15:20:36 -07002508 /* Get the Tx Desc ring indexes */
2509 tx_desc_curr = mp->tx_curr_desc_q;
2510 tx_desc_used = mp->tx_used_desc_q;
2511
2512 current_descriptor = &mp->p_tx_desc_area[tx_desc_curr];
2513
2514 tx_next_desc = (tx_desc_curr + 1) % mp->tx_ring_size;
2515
2516 current_descriptor->buf_ptr = p_pkt_info->buf_ptr;
2517 current_descriptor->byte_cnt = p_pkt_info->byte_cnt;
2518 current_descriptor->l4i_chk = p_pkt_info->l4i_chk;
2519 mp->tx_skb[tx_desc_curr] = p_pkt_info->return_info;
2520
2521 command = p_pkt_info->cmd_sts | ETH_ZERO_PADDING | ETH_GEN_CRC |
2522 ETH_BUFFER_OWNED_BY_DMA;
2523 if (command & ETH_TX_FIRST_DESC) {
2524 tx_first_desc = tx_desc_curr;
2525 mp->tx_first_desc_q = tx_first_desc;
2526 first_descriptor = current_descriptor;
2527 mp->tx_first_command = command;
2528 } else {
2529 tx_first_desc = mp->tx_first_desc_q;
2530 first_descriptor = &mp->p_tx_desc_area[tx_first_desc];
2531 BUG_ON(first_descriptor == NULL);
2532 current_descriptor->cmd_sts = command;
2533 }
2534
2535 if (command & ETH_TX_LAST_DESC) {
2536 wmb();
2537 first_descriptor->cmd_sts = mp->tx_first_command;
2538
2539 wmb();
2540 ETH_ENABLE_TX_QUEUE(mp->port_num);
2541
2542 /*
2543 * Finish Tx packet. Update first desc in case of Tx resource
2544 * error */
2545 tx_first_desc = tx_next_desc;
2546 mp->tx_first_desc_q = tx_first_desc;
2547 }
2548
2549 /* Check for ring index overlap in the Tx desc ring */
2550 if (tx_next_desc == tx_desc_used) {
2551 mp->tx_resource_err = 1;
2552 mp->tx_curr_desc_q = tx_first_desc;
2553
2554 return ETH_QUEUE_LAST_RESOURCE;
2555 }
2556
2557 mp->tx_curr_desc_q = tx_next_desc;
2558
2559 return ETH_OK;
2560}
2561#else
2562static ETH_FUNC_RET_STATUS eth_port_send(struct mv643xx_private *mp,
2563 struct pkt_info *p_pkt_info)
2564{
2565 int tx_desc_curr;
2566 int tx_desc_used;
2567 struct eth_tx_desc *current_descriptor;
2568 unsigned int command_status;
2569
2570 /* Do not process Tx ring in case of Tx ring resource error */
2571 if (mp->tx_resource_err)
2572 return ETH_QUEUE_FULL;
2573
Dale Farnsworthb111ceb2005-09-02 10:25:24 -07002574 mp->tx_ring_skbs++;
2575 BUG_ON(mp->tx_ring_skbs > mp->tx_ring_size);
2576
Linus Torvalds1da177e2005-04-16 15:20:36 -07002577 /* Get the Tx Desc ring indexes */
2578 tx_desc_curr = mp->tx_curr_desc_q;
2579 tx_desc_used = mp->tx_used_desc_q;
2580 current_descriptor = &mp->p_tx_desc_area[tx_desc_curr];
2581
2582 command_status = p_pkt_info->cmd_sts | ETH_ZERO_PADDING | ETH_GEN_CRC;
2583 current_descriptor->buf_ptr = p_pkt_info->buf_ptr;
2584 current_descriptor->byte_cnt = p_pkt_info->byte_cnt;
2585 mp->tx_skb[tx_desc_curr] = p_pkt_info->return_info;
2586
2587 /* Set last desc with DMA ownership and interrupt enable. */
2588 wmb();
2589 current_descriptor->cmd_sts = command_status |
2590 ETH_BUFFER_OWNED_BY_DMA | ETH_TX_ENABLE_INTERRUPT;
2591
2592 wmb();
2593 ETH_ENABLE_TX_QUEUE(mp->port_num);
2594
2595 /* Finish Tx packet. Update first desc in case of Tx resource error */
2596 tx_desc_curr = (tx_desc_curr + 1) % mp->tx_ring_size;
2597
2598 /* Update the current descriptor */
2599 mp->tx_curr_desc_q = tx_desc_curr;
2600
2601 /* Check for ring index overlap in the Tx desc ring */
2602 if (tx_desc_curr == tx_desc_used) {
2603 mp->tx_resource_err = 1;
2604 return ETH_QUEUE_LAST_RESOURCE;
2605 }
2606
2607 return ETH_OK;
2608}
2609#endif
2610
2611/*
2612 * eth_tx_return_desc - Free all used Tx descriptors
2613 *
2614 * DESCRIPTION:
2615 * This routine returns the transmitted packet information to the caller.
2616 * It uses the 'first' index to support Tx desc return in case a transmit
2617 * of a packet spanned over multiple buffer still in process.
2618 * In case the Tx queue was in "resource error" condition, where there are
2619 * no available Tx resources, the function resets the resource error flag.
2620 *
2621 * INPUT:
2622 * struct mv643xx_private *mp Ethernet Port Control srtuct.
2623 * struct pkt_info *p_pkt_info User packet buffer.
2624 *
2625 * OUTPUT:
2626 * Tx ring 'first' and 'used' indexes are updated.
2627 *
2628 * RETURN:
2629 * ETH_ERROR in case the routine can not access Tx desc ring.
2630 * ETH_RETRY in case there is transmission in process.
2631 * ETH_END_OF_JOB if the routine has nothing to release.
2632 * ETH_OK otherwise.
2633 *
2634 */
2635static ETH_FUNC_RET_STATUS eth_tx_return_desc(struct mv643xx_private *mp,
2636 struct pkt_info *p_pkt_info)
2637{
2638 int tx_desc_used;
2639#ifdef MV643XX_CHECKSUM_OFFLOAD_TX
2640 int tx_busy_desc = mp->tx_first_desc_q;
2641#else
2642 int tx_busy_desc = mp->tx_curr_desc_q;
2643#endif
2644 struct eth_tx_desc *p_tx_desc_used;
2645 unsigned int command_status;
2646
2647 /* Get the Tx Desc ring indexes */
2648 tx_desc_used = mp->tx_used_desc_q;
2649
2650 p_tx_desc_used = &mp->p_tx_desc_area[tx_desc_used];
2651
2652 /* Sanity check */
2653 if (p_tx_desc_used == NULL)
2654 return ETH_ERROR;
2655
2656 /* Stop release. About to overlap the current available Tx descriptor */
2657 if (tx_desc_used == tx_busy_desc && !mp->tx_resource_err)
2658 return ETH_END_OF_JOB;
2659
2660 command_status = p_tx_desc_used->cmd_sts;
2661
2662 /* Still transmitting... */
2663 if (command_status & (ETH_BUFFER_OWNED_BY_DMA))
2664 return ETH_RETRY;
2665
2666 /* Pass the packet information to the caller */
2667 p_pkt_info->cmd_sts = command_status;
2668 p_pkt_info->return_info = mp->tx_skb[tx_desc_used];
2669 mp->tx_skb[tx_desc_used] = NULL;
2670
2671 /* Update the next descriptor to release. */
2672 mp->tx_used_desc_q = (tx_desc_used + 1) % mp->tx_ring_size;
2673
2674 /* Any Tx return cancels the Tx resource error status */
2675 mp->tx_resource_err = 0;
2676
Dale Farnsworthb111ceb2005-09-02 10:25:24 -07002677 BUG_ON(mp->tx_ring_skbs == 0);
2678 mp->tx_ring_skbs--;
2679
Linus Torvalds1da177e2005-04-16 15:20:36 -07002680 return ETH_OK;
2681}
2682
2683/*
2684 * eth_port_receive - Get received information from Rx ring.
2685 *
2686 * DESCRIPTION:
2687 * This routine returns the received data to the caller. There is no
2688 * data copying during routine operation. All information is returned
2689 * using pointer to packet information struct passed from the caller.
2690 * If the routine exhausts Rx ring resources then the resource error flag
2691 * is set.
2692 *
2693 * INPUT:
2694 * struct mv643xx_private *mp Ethernet Port Control srtuct.
2695 * struct pkt_info *p_pkt_info User packet buffer.
2696 *
2697 * OUTPUT:
2698 * Rx ring current and used indexes are updated.
2699 *
2700 * RETURN:
2701 * ETH_ERROR in case the routine can not access Rx desc ring.
2702 * ETH_QUEUE_FULL if Rx ring resources are exhausted.
2703 * ETH_END_OF_JOB if there is no received data.
2704 * ETH_OK otherwise.
2705 */
2706static ETH_FUNC_RET_STATUS eth_port_receive(struct mv643xx_private *mp,
2707 struct pkt_info *p_pkt_info)
2708{
2709 int rx_next_curr_desc, rx_curr_desc, rx_used_desc;
2710 volatile struct eth_rx_desc *p_rx_desc;
2711 unsigned int command_status;
2712
2713 /* Do not process Rx ring in case of Rx ring resource error */
2714 if (mp->rx_resource_err)
2715 return ETH_QUEUE_FULL;
2716
2717 /* Get the Rx Desc ring 'curr and 'used' indexes */
2718 rx_curr_desc = mp->rx_curr_desc_q;
2719 rx_used_desc = mp->rx_used_desc_q;
2720
2721 p_rx_desc = &mp->p_rx_desc_area[rx_curr_desc];
2722
2723 /* The following parameters are used to save readings from memory */
2724 command_status = p_rx_desc->cmd_sts;
2725 rmb();
2726
2727 /* Nothing to receive... */
2728 if (command_status & (ETH_BUFFER_OWNED_BY_DMA))
2729 return ETH_END_OF_JOB;
2730
2731 p_pkt_info->byte_cnt = (p_rx_desc->byte_cnt) - RX_BUF_OFFSET;
2732 p_pkt_info->cmd_sts = command_status;
2733 p_pkt_info->buf_ptr = (p_rx_desc->buf_ptr) + RX_BUF_OFFSET;
2734 p_pkt_info->return_info = mp->rx_skb[rx_curr_desc];
2735 p_pkt_info->l4i_chk = p_rx_desc->buf_size;
2736
2737 /* Clean the return info field to indicate that the packet has been */
2738 /* moved to the upper layers */
2739 mp->rx_skb[rx_curr_desc] = NULL;
2740
2741 /* Update current index in data structure */
2742 rx_next_curr_desc = (rx_curr_desc + 1) % mp->rx_ring_size;
2743 mp->rx_curr_desc_q = rx_next_curr_desc;
2744
2745 /* Rx descriptors exhausted. Set the Rx ring resource error flag */
2746 if (rx_next_curr_desc == rx_used_desc)
2747 mp->rx_resource_err = 1;
2748
2749 return ETH_OK;
2750}
2751
2752/*
2753 * eth_rx_return_buff - Returns a Rx buffer back to the Rx ring.
2754 *
2755 * DESCRIPTION:
2756 * This routine returns a Rx buffer back to the Rx ring. It retrieves the
2757 * next 'used' descriptor and attached the returned buffer to it.
2758 * In case the Rx ring was in "resource error" condition, where there are
2759 * no available Rx resources, the function resets the resource error flag.
2760 *
2761 * INPUT:
2762 * struct mv643xx_private *mp Ethernet Port Control srtuct.
2763 * struct pkt_info *p_pkt_info Information on returned buffer.
2764 *
2765 * OUTPUT:
2766 * New available Rx resource in Rx descriptor ring.
2767 *
2768 * RETURN:
2769 * ETH_ERROR in case the routine can not access Rx desc ring.
2770 * ETH_OK otherwise.
2771 */
2772static ETH_FUNC_RET_STATUS eth_rx_return_buff(struct mv643xx_private *mp,
2773 struct pkt_info *p_pkt_info)
2774{
2775 int used_rx_desc; /* Where to return Rx resource */
2776 volatile struct eth_rx_desc *p_used_rx_desc;
2777
2778 /* Get 'used' Rx descriptor */
2779 used_rx_desc = mp->rx_used_desc_q;
2780 p_used_rx_desc = &mp->p_rx_desc_area[used_rx_desc];
2781
2782 p_used_rx_desc->buf_ptr = p_pkt_info->buf_ptr;
2783 p_used_rx_desc->buf_size = p_pkt_info->byte_cnt;
2784 mp->rx_skb[used_rx_desc] = p_pkt_info->return_info;
2785
2786 /* Flush the write pipe */
2787
2788 /* Return the descriptor to DMA ownership */
2789 wmb();
2790 p_used_rx_desc->cmd_sts =
2791 ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT;
2792 wmb();
2793
2794 /* Move the used descriptor pointer to the next descriptor */
2795 mp->rx_used_desc_q = (used_rx_desc + 1) % mp->rx_ring_size;
2796
2797 /* Any Rx return cancels the Rx resource error status */
2798 mp->rx_resource_err = 0;
2799
2800 return ETH_OK;
2801}
2802
2803/************* Begin ethtool support *************************/
2804
2805struct mv643xx_stats {
2806 char stat_string[ETH_GSTRING_LEN];
2807 int sizeof_stat;
2808 int stat_offset;
2809};
2810
2811#define MV643XX_STAT(m) sizeof(((struct mv643xx_private *)0)->m), \
2812 offsetof(struct mv643xx_private, m)
2813
2814static const struct mv643xx_stats mv643xx_gstrings_stats[] = {
2815 { "rx_packets", MV643XX_STAT(stats.rx_packets) },
2816 { "tx_packets", MV643XX_STAT(stats.tx_packets) },
2817 { "rx_bytes", MV643XX_STAT(stats.rx_bytes) },
2818 { "tx_bytes", MV643XX_STAT(stats.tx_bytes) },
2819 { "rx_errors", MV643XX_STAT(stats.rx_errors) },
2820 { "tx_errors", MV643XX_STAT(stats.tx_errors) },
2821 { "rx_dropped", MV643XX_STAT(stats.rx_dropped) },
2822 { "tx_dropped", MV643XX_STAT(stats.tx_dropped) },
2823 { "good_octets_received", MV643XX_STAT(mib_counters.good_octets_received) },
2824 { "bad_octets_received", MV643XX_STAT(mib_counters.bad_octets_received) },
2825 { "internal_mac_transmit_err", MV643XX_STAT(mib_counters.internal_mac_transmit_err) },
2826 { "good_frames_received", MV643XX_STAT(mib_counters.good_frames_received) },
2827 { "bad_frames_received", MV643XX_STAT(mib_counters.bad_frames_received) },
2828 { "broadcast_frames_received", MV643XX_STAT(mib_counters.broadcast_frames_received) },
2829 { "multicast_frames_received", MV643XX_STAT(mib_counters.multicast_frames_received) },
2830 { "frames_64_octets", MV643XX_STAT(mib_counters.frames_64_octets) },
2831 { "frames_65_to_127_octets", MV643XX_STAT(mib_counters.frames_65_to_127_octets) },
2832 { "frames_128_to_255_octets", MV643XX_STAT(mib_counters.frames_128_to_255_octets) },
2833 { "frames_256_to_511_octets", MV643XX_STAT(mib_counters.frames_256_to_511_octets) },
2834 { "frames_512_to_1023_octets", MV643XX_STAT(mib_counters.frames_512_to_1023_octets) },
2835 { "frames_1024_to_max_octets", MV643XX_STAT(mib_counters.frames_1024_to_max_octets) },
2836 { "good_octets_sent", MV643XX_STAT(mib_counters.good_octets_sent) },
2837 { "good_frames_sent", MV643XX_STAT(mib_counters.good_frames_sent) },
2838 { "excessive_collision", MV643XX_STAT(mib_counters.excessive_collision) },
2839 { "multicast_frames_sent", MV643XX_STAT(mib_counters.multicast_frames_sent) },
2840 { "broadcast_frames_sent", MV643XX_STAT(mib_counters.broadcast_frames_sent) },
2841 { "unrec_mac_control_received", MV643XX_STAT(mib_counters.unrec_mac_control_received) },
2842 { "fc_sent", MV643XX_STAT(mib_counters.fc_sent) },
2843 { "good_fc_received", MV643XX_STAT(mib_counters.good_fc_received) },
2844 { "bad_fc_received", MV643XX_STAT(mib_counters.bad_fc_received) },
2845 { "undersize_received", MV643XX_STAT(mib_counters.undersize_received) },
2846 { "fragments_received", MV643XX_STAT(mib_counters.fragments_received) },
2847 { "oversize_received", MV643XX_STAT(mib_counters.oversize_received) },
2848 { "jabber_received", MV643XX_STAT(mib_counters.jabber_received) },
2849 { "mac_receive_error", MV643XX_STAT(mib_counters.mac_receive_error) },
2850 { "bad_crc_event", MV643XX_STAT(mib_counters.bad_crc_event) },
2851 { "collision", MV643XX_STAT(mib_counters.collision) },
2852 { "late_collision", MV643XX_STAT(mib_counters.late_collision) },
2853};
2854
2855#define MV643XX_STATS_LEN \
2856 sizeof(mv643xx_gstrings_stats) / sizeof(struct mv643xx_stats)
2857
2858static int
2859mv643xx_get_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
2860{
2861 struct mv643xx_private *mp = netdev->priv;
2862 int port_num = mp->port_num;
2863 int autoneg = eth_port_autoneg_supported(port_num);
2864 int mode_10_bit;
2865 int auto_duplex;
2866 int half_duplex = 0;
2867 int full_duplex = 0;
2868 int auto_speed;
2869 int speed_10 = 0;
2870 int speed_100 = 0;
2871 int speed_1000 = 0;
2872
2873 u32 pcs = mv_read(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num));
2874 u32 psr = mv_read(MV643XX_ETH_PORT_STATUS_REG(port_num));
2875
2876 mode_10_bit = psr & MV643XX_ETH_PORT_STATUS_MODE_10_BIT;
2877
2878 if (mode_10_bit) {
2879 ecmd->supported = SUPPORTED_10baseT_Half;
2880 } else {
2881 ecmd->supported = (SUPPORTED_10baseT_Half |
2882 SUPPORTED_10baseT_Full |
2883 SUPPORTED_100baseT_Half |
2884 SUPPORTED_100baseT_Full |
2885 SUPPORTED_1000baseT_Full |
2886 (autoneg ? SUPPORTED_Autoneg : 0) |
2887 SUPPORTED_TP);
2888
2889 auto_duplex = !(pcs & MV643XX_ETH_DISABLE_AUTO_NEG_FOR_DUPLX);
2890 auto_speed = !(pcs & MV643XX_ETH_DISABLE_AUTO_NEG_SPEED_GMII);
2891
2892 ecmd->advertising = ADVERTISED_TP;
2893
2894 if (autoneg) {
2895 ecmd->advertising |= ADVERTISED_Autoneg;
2896
2897 if (auto_duplex) {
2898 half_duplex = 1;
2899 full_duplex = 1;
2900 } else {
2901 if (pcs & MV643XX_ETH_SET_FULL_DUPLEX_MODE)
2902 full_duplex = 1;
2903 else
2904 half_duplex = 1;
2905 }
2906
2907 if (auto_speed) {
2908 speed_10 = 1;
2909 speed_100 = 1;
2910 speed_1000 = 1;
2911 } else {
2912 if (pcs & MV643XX_ETH_SET_GMII_SPEED_TO_1000)
2913 speed_1000 = 1;
2914 else if (pcs & MV643XX_ETH_SET_MII_SPEED_TO_100)
2915 speed_100 = 1;
2916 else
2917 speed_10 = 1;
2918 }
2919
2920 if (speed_10 & half_duplex)
2921 ecmd->advertising |= ADVERTISED_10baseT_Half;
2922 if (speed_10 & full_duplex)
2923 ecmd->advertising |= ADVERTISED_10baseT_Full;
2924 if (speed_100 & half_duplex)
2925 ecmd->advertising |= ADVERTISED_100baseT_Half;
2926 if (speed_100 & full_duplex)
2927 ecmd->advertising |= ADVERTISED_100baseT_Full;
2928 if (speed_1000)
2929 ecmd->advertising |= ADVERTISED_1000baseT_Full;
2930 }
2931 }
2932
2933 ecmd->port = PORT_TP;
2934 ecmd->phy_address = ethernet_phy_get(port_num);
2935
2936 ecmd->transceiver = XCVR_EXTERNAL;
2937
2938 if (netif_carrier_ok(netdev)) {
2939 if (mode_10_bit)
2940 ecmd->speed = SPEED_10;
2941 else {
2942 if (psr & MV643XX_ETH_PORT_STATUS_GMII_1000)
2943 ecmd->speed = SPEED_1000;
2944 else if (psr & MV643XX_ETH_PORT_STATUS_MII_100)
2945 ecmd->speed = SPEED_100;
2946 else
2947 ecmd->speed = SPEED_10;
2948 }
2949
2950 if (psr & MV643XX_ETH_PORT_STATUS_FULL_DUPLEX)
2951 ecmd->duplex = DUPLEX_FULL;
2952 else
2953 ecmd->duplex = DUPLEX_HALF;
2954 } else {
2955 ecmd->speed = -1;
2956 ecmd->duplex = -1;
2957 }
2958
2959 ecmd->autoneg = autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE;
2960 return 0;
2961}
2962
2963static void
2964mv643xx_get_drvinfo(struct net_device *netdev,
2965 struct ethtool_drvinfo *drvinfo)
2966{
2967 strncpy(drvinfo->driver, mv643xx_driver_name, 32);
2968 strncpy(drvinfo->version, mv643xx_driver_version, 32);
2969 strncpy(drvinfo->fw_version, "N/A", 32);
2970 strncpy(drvinfo->bus_info, "mv643xx", 32);
2971 drvinfo->n_stats = MV643XX_STATS_LEN;
2972}
2973
2974static int
2975mv643xx_get_stats_count(struct net_device *netdev)
2976{
2977 return MV643XX_STATS_LEN;
2978}
2979
2980static void
2981mv643xx_get_ethtool_stats(struct net_device *netdev,
2982 struct ethtool_stats *stats, uint64_t *data)
2983{
2984 struct mv643xx_private *mp = netdev->priv;
2985 int i;
2986
2987 eth_update_mib_counters(mp);
2988
2989 for(i = 0; i < MV643XX_STATS_LEN; i++) {
2990 char *p = (char *)mp+mv643xx_gstrings_stats[i].stat_offset;
2991 data[i] = (mv643xx_gstrings_stats[i].sizeof_stat ==
2992 sizeof(uint64_t)) ? *(uint64_t *)p : *(uint32_t *)p;
2993 }
2994}
2995
2996static void
2997mv643xx_get_strings(struct net_device *netdev, uint32_t stringset, uint8_t *data)
2998{
2999 int i;
3000
3001 switch(stringset) {
3002 case ETH_SS_STATS:
3003 for (i=0; i < MV643XX_STATS_LEN; i++) {
3004 memcpy(data + i * ETH_GSTRING_LEN,
3005 mv643xx_gstrings_stats[i].stat_string,
3006 ETH_GSTRING_LEN);
3007 }
3008 break;
3009 }
3010}
3011
3012static struct ethtool_ops mv643xx_ethtool_ops = {
3013 .get_settings = mv643xx_get_settings,
3014 .get_drvinfo = mv643xx_get_drvinfo,
3015 .get_link = ethtool_op_get_link,
3016 .get_sg = ethtool_op_get_sg,
3017 .set_sg = ethtool_op_set_sg,
3018 .get_strings = mv643xx_get_strings,
3019 .get_stats_count = mv643xx_get_stats_count,
3020 .get_ethtool_stats = mv643xx_get_ethtool_stats,
3021};
3022
3023/************* End ethtool support *************************/