jack wang | dbf9bfe | 2009-10-14 16:19:21 +0800 | [diff] [blame] | 1 | /* |
| 2 | * PMC-Sierra SPC 8001 SAS/SATA based host adapters driver |
| 3 | * |
| 4 | * Copyright (c) 2008-2009 USI Co., Ltd. |
| 5 | * All rights reserved. |
| 6 | * |
| 7 | * Redistribution and use in source and binary forms, with or without |
| 8 | * modification, are permitted provided that the following conditions |
| 9 | * are met: |
| 10 | * 1. Redistributions of source code must retain the above copyright |
| 11 | * notice, this list of conditions, and the following disclaimer, |
| 12 | * without modification. |
| 13 | * 2. Redistributions in binary form must reproduce at minimum a disclaimer |
| 14 | * substantially similar to the "NO WARRANTY" disclaimer below |
| 15 | * ("Disclaimer") and any redistribution must be conditioned upon |
| 16 | * including a substantially similar Disclaimer requirement for further |
| 17 | * binary redistribution. |
| 18 | * 3. Neither the names of the above-listed copyright holders nor the names |
| 19 | * of any contributors may be used to endorse or promote products derived |
| 20 | * from this software without specific prior written permission. |
| 21 | * |
| 22 | * Alternatively, this software may be distributed under the terms of the |
| 23 | * GNU General Public License ("GPL") version 2 as published by the Free |
| 24 | * Software Foundation. |
| 25 | * |
| 26 | * NO WARRANTY |
| 27 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
| 28 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
| 29 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR |
| 30 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT |
| 31 | * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| 32 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
| 33 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
| 34 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, |
| 35 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING |
| 36 | * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 37 | * POSSIBILITY OF SUCH DAMAGES. |
| 38 | * |
| 39 | */ |
| 40 | #ifndef _PMC8001_REG_H_ |
| 41 | #define _PMC8001_REG_H_ |
| 42 | |
| 43 | #include <linux/types.h> |
| 44 | #include <scsi/libsas.h> |
| 45 | |
| 46 | |
| 47 | /* for Request Opcode of IOMB */ |
| 48 | #define OPC_INB_ECHO 1 /* 0x000 */ |
| 49 | #define OPC_INB_PHYSTART 4 /* 0x004 */ |
| 50 | #define OPC_INB_PHYSTOP 5 /* 0x005 */ |
| 51 | #define OPC_INB_SSPINIIOSTART 6 /* 0x006 */ |
| 52 | #define OPC_INB_SSPINITMSTART 7 /* 0x007 */ |
| 53 | #define OPC_INB_SSPINIEXTIOSTART 8 /* 0x008 */ |
| 54 | #define OPC_INB_DEV_HANDLE_ACCEPT 9 /* 0x009 */ |
| 55 | #define OPC_INB_SSPTGTIOSTART 10 /* 0x00A */ |
| 56 | #define OPC_INB_SSPTGTRSPSTART 11 /* 0x00B */ |
| 57 | #define OPC_INB_SSPINIEDCIOSTART 12 /* 0x00C */ |
| 58 | #define OPC_INB_SSPINIEXTEDCIOSTART 13 /* 0x00D */ |
| 59 | #define OPC_INB_SSPTGTEDCIOSTART 14 /* 0x00E */ |
| 60 | #define OPC_INB_SSP_ABORT 15 /* 0x00F */ |
| 61 | #define OPC_INB_DEREG_DEV_HANDLE 16 /* 0x010 */ |
| 62 | #define OPC_INB_GET_DEV_HANDLE 17 /* 0x011 */ |
| 63 | #define OPC_INB_SMP_REQUEST 18 /* 0x012 */ |
| 64 | /* SMP_RESPONSE is removed */ |
| 65 | #define OPC_INB_SMP_RESPONSE 19 /* 0x013 */ |
| 66 | #define OPC_INB_SMP_ABORT 20 /* 0x014 */ |
| 67 | #define OPC_INB_REG_DEV 22 /* 0x016 */ |
| 68 | #define OPC_INB_SATA_HOST_OPSTART 23 /* 0x017 */ |
| 69 | #define OPC_INB_SATA_ABORT 24 /* 0x018 */ |
| 70 | #define OPC_INB_LOCAL_PHY_CONTROL 25 /* 0x019 */ |
| 71 | #define OPC_INB_GET_DEV_INFO 26 /* 0x01A */ |
| 72 | #define OPC_INB_FW_FLASH_UPDATE 32 /* 0x020 */ |
| 73 | #define OPC_INB_GPIO 34 /* 0x022 */ |
| 74 | #define OPC_INB_SAS_DIAG_MODE_START_END 35 /* 0x023 */ |
| 75 | #define OPC_INB_SAS_DIAG_EXECUTE 36 /* 0x024 */ |
| 76 | #define OPC_INB_SAS_HW_EVENT_ACK 37 /* 0x025 */ |
| 77 | #define OPC_INB_GET_TIME_STAMP 38 /* 0x026 */ |
| 78 | #define OPC_INB_PORT_CONTROL 39 /* 0x027 */ |
| 79 | #define OPC_INB_GET_NVMD_DATA 40 /* 0x028 */ |
| 80 | #define OPC_INB_SET_NVMD_DATA 41 /* 0x029 */ |
| 81 | #define OPC_INB_SET_DEVICE_STATE 42 /* 0x02A */ |
| 82 | #define OPC_INB_GET_DEVICE_STATE 43 /* 0x02B */ |
| 83 | #define OPC_INB_SET_DEV_INFO 44 /* 0x02C */ |
| 84 | #define OPC_INB_SAS_RE_INITIALIZE 45 /* 0x02D */ |
| 85 | |
| 86 | /* for Response Opcode of IOMB */ |
| 87 | #define OPC_OUB_ECHO 1 /* 0x001 */ |
| 88 | #define OPC_OUB_HW_EVENT 4 /* 0x004 */ |
| 89 | #define OPC_OUB_SSP_COMP 5 /* 0x005 */ |
| 90 | #define OPC_OUB_SMP_COMP 6 /* 0x006 */ |
| 91 | #define OPC_OUB_LOCAL_PHY_CNTRL 7 /* 0x007 */ |
| 92 | #define OPC_OUB_DEV_REGIST 10 /* 0x00A */ |
| 93 | #define OPC_OUB_DEREG_DEV 11 /* 0x00B */ |
| 94 | #define OPC_OUB_GET_DEV_HANDLE 12 /* 0x00C */ |
| 95 | #define OPC_OUB_SATA_COMP 13 /* 0x00D */ |
| 96 | #define OPC_OUB_SATA_EVENT 14 /* 0x00E */ |
| 97 | #define OPC_OUB_SSP_EVENT 15 /* 0x00F */ |
| 98 | #define OPC_OUB_DEV_HANDLE_ARRIV 16 /* 0x010 */ |
| 99 | /* SMP_RECEIVED Notification is removed */ |
| 100 | #define OPC_OUB_SMP_RECV_EVENT 17 /* 0x011 */ |
| 101 | #define OPC_OUB_SSP_RECV_EVENT 18 /* 0x012 */ |
| 102 | #define OPC_OUB_DEV_INFO 19 /* 0x013 */ |
| 103 | #define OPC_OUB_FW_FLASH_UPDATE 20 /* 0x014 */ |
| 104 | #define OPC_OUB_GPIO_RESPONSE 22 /* 0x016 */ |
| 105 | #define OPC_OUB_GPIO_EVENT 23 /* 0x017 */ |
| 106 | #define OPC_OUB_GENERAL_EVENT 24 /* 0x018 */ |
| 107 | #define OPC_OUB_SSP_ABORT_RSP 26 /* 0x01A */ |
| 108 | #define OPC_OUB_SATA_ABORT_RSP 27 /* 0x01B */ |
| 109 | #define OPC_OUB_SAS_DIAG_MODE_START_END 28 /* 0x01C */ |
| 110 | #define OPC_OUB_SAS_DIAG_EXECUTE 29 /* 0x01D */ |
| 111 | #define OPC_OUB_GET_TIME_STAMP 30 /* 0x01E */ |
| 112 | #define OPC_OUB_SAS_HW_EVENT_ACK 31 /* 0x01F */ |
| 113 | #define OPC_OUB_PORT_CONTROL 32 /* 0x020 */ |
| 114 | #define OPC_OUB_SKIP_ENTRY 33 /* 0x021 */ |
| 115 | #define OPC_OUB_SMP_ABORT_RSP 34 /* 0x022 */ |
| 116 | #define OPC_OUB_GET_NVMD_DATA 35 /* 0x023 */ |
| 117 | #define OPC_OUB_SET_NVMD_DATA 36 /* 0x024 */ |
| 118 | #define OPC_OUB_DEVICE_HANDLE_REMOVAL 37 /* 0x025 */ |
| 119 | #define OPC_OUB_SET_DEVICE_STATE 38 /* 0x026 */ |
| 120 | #define OPC_OUB_GET_DEVICE_STATE 39 /* 0x027 */ |
| 121 | #define OPC_OUB_SET_DEV_INFO 40 /* 0x028 */ |
| 122 | #define OPC_OUB_SAS_RE_INITIALIZE 41 /* 0x029 */ |
| 123 | |
| 124 | /* for phy start*/ |
| 125 | #define SPINHOLD_DISABLE (0x00 << 14) |
| 126 | #define SPINHOLD_ENABLE (0x01 << 14) |
| 127 | #define LINKMODE_SAS (0x01 << 12) |
| 128 | #define LINKMODE_DSATA (0x02 << 12) |
| 129 | #define LINKMODE_AUTO (0x03 << 12) |
| 130 | #define LINKRATE_15 (0x01 << 8) |
| 131 | #define LINKRATE_30 (0x02 << 8) |
| 132 | #define LINKRATE_60 (0x04 << 8) |
| 133 | |
| 134 | struct mpi_msg_hdr{ |
| 135 | __le32 header; /* Bits [11:0] - Message operation code */ |
| 136 | /* Bits [15:12] - Message Category */ |
| 137 | /* Bits [21:16] - Outboundqueue ID for the |
| 138 | operation completion message */ |
| 139 | /* Bits [23:22] - Reserved */ |
| 140 | /* Bits [28:24] - Buffer Count, indicates how |
| 141 | many buffer are allocated for the massage */ |
| 142 | /* Bits [30:29] - Reserved */ |
| 143 | /* Bits [31] - Message Valid bit */ |
| 144 | } __attribute__((packed, aligned(4))); |
| 145 | |
| 146 | |
| 147 | /* |
| 148 | * brief the data structure of PHY Start Command |
| 149 | * use to describe enable the phy (64 bytes) |
| 150 | */ |
| 151 | struct phy_start_req { |
| 152 | __le32 tag; |
| 153 | __le32 ase_sh_lm_slr_phyid; |
| 154 | struct sas_identify_frame sas_identify; |
| 155 | u32 reserved[5]; |
| 156 | } __attribute__((packed, aligned(4))); |
| 157 | |
| 158 | |
| 159 | /* |
| 160 | * brief the data structure of PHY Start Command |
| 161 | * use to disable the phy (64 bytes) |
| 162 | */ |
| 163 | struct phy_stop_req { |
| 164 | __le32 tag; |
| 165 | __le32 phy_id; |
| 166 | u32 reserved[13]; |
| 167 | } __attribute__((packed, aligned(4))); |
| 168 | |
| 169 | |
| 170 | /* set device bits fis - device to host */ |
| 171 | struct set_dev_bits_fis { |
| 172 | u8 fis_type; /* 0xA1*/ |
| 173 | u8 n_i_pmport; |
| 174 | /* b7 : n Bit. Notification bit. If set device needs attention. */ |
| 175 | /* b6 : i Bit. Interrupt Bit */ |
| 176 | /* b5-b4: reserved2 */ |
| 177 | /* b3-b0: PM Port */ |
| 178 | u8 status; |
| 179 | u8 error; |
| 180 | u32 _r_a; |
| 181 | } __attribute__ ((packed)); |
| 182 | /* PIO setup FIS - device to host */ |
| 183 | struct pio_setup_fis { |
| 184 | u8 fis_type; /* 0x5f */ |
| 185 | u8 i_d_pmPort; |
| 186 | /* b7 : reserved */ |
| 187 | /* b6 : i bit. Interrupt bit */ |
| 188 | /* b5 : d bit. data transfer direction. set to 1 for device to host |
| 189 | xfer */ |
| 190 | /* b4 : reserved */ |
| 191 | /* b3-b0: PM Port */ |
| 192 | u8 status; |
| 193 | u8 error; |
| 194 | u8 lbal; |
| 195 | u8 lbam; |
| 196 | u8 lbah; |
| 197 | u8 device; |
| 198 | u8 lbal_exp; |
| 199 | u8 lbam_exp; |
| 200 | u8 lbah_exp; |
| 201 | u8 _r_a; |
| 202 | u8 sector_count; |
| 203 | u8 sector_count_exp; |
| 204 | u8 _r_b; |
| 205 | u8 e_status; |
| 206 | u8 _r_c[2]; |
| 207 | u8 transfer_count; |
| 208 | } __attribute__ ((packed)); |
| 209 | |
| 210 | /* |
| 211 | * brief the data structure of SATA Completion Response |
| 212 | * use to discribe the sata task response (64 bytes) |
| 213 | */ |
| 214 | struct sata_completion_resp { |
| 215 | __le32 tag; |
| 216 | __le32 status; |
| 217 | __le32 param; |
| 218 | u32 sata_resp[12]; |
| 219 | } __attribute__((packed, aligned(4))); |
| 220 | |
| 221 | |
| 222 | /* |
| 223 | * brief the data structure of SAS HW Event Notification |
| 224 | * use to alert the host about the hardware event(64 bytes) |
| 225 | */ |
| 226 | struct hw_event_resp { |
| 227 | __le32 lr_evt_status_phyid_portid; |
| 228 | __le32 evt_param; |
| 229 | __le32 npip_portstate; |
| 230 | struct sas_identify_frame sas_identify; |
| 231 | struct dev_to_host_fis sata_fis; |
| 232 | } __attribute__((packed, aligned(4))); |
| 233 | |
| 234 | |
| 235 | /* |
| 236 | * brief the data structure of REGISTER DEVICE Command |
| 237 | * use to describe MPI REGISTER DEVICE Command (64 bytes) |
| 238 | */ |
| 239 | |
| 240 | struct reg_dev_req { |
| 241 | __le32 tag; |
| 242 | __le32 phyid_portid; |
| 243 | __le32 dtype_dlr_retry; |
| 244 | __le32 firstburstsize_ITNexustimeout; |
| 245 | u32 sas_addr_hi; |
| 246 | u32 sas_addr_low; |
| 247 | __le32 upper_device_id; |
| 248 | u32 reserved[8]; |
| 249 | } __attribute__((packed, aligned(4))); |
| 250 | |
| 251 | |
| 252 | /* |
| 253 | * brief the data structure of DEREGISTER DEVICE Command |
| 254 | * use to request spc to remove all internal resources associated |
| 255 | * with the device id (64 bytes) |
| 256 | */ |
| 257 | |
| 258 | struct dereg_dev_req { |
| 259 | __le32 tag; |
| 260 | __le32 device_id; |
| 261 | u32 reserved[13]; |
| 262 | } __attribute__((packed, aligned(4))); |
| 263 | |
| 264 | |
| 265 | /* |
| 266 | * brief the data structure of DEVICE_REGISTRATION Response |
| 267 | * use to notify the completion of the device registration (64 bytes) |
| 268 | */ |
| 269 | |
| 270 | struct dev_reg_resp { |
| 271 | __le32 tag; |
| 272 | __le32 status; |
| 273 | __le32 device_id; |
| 274 | u32 reserved[12]; |
| 275 | } __attribute__((packed, aligned(4))); |
| 276 | |
| 277 | |
| 278 | /* |
| 279 | * brief the data structure of Local PHY Control Command |
| 280 | * use to issue PHY CONTROL to local phy (64 bytes) |
| 281 | */ |
| 282 | struct local_phy_ctl_req { |
| 283 | __le32 tag; |
| 284 | __le32 phyop_phyid; |
| 285 | u32 reserved1[13]; |
| 286 | } __attribute__((packed, aligned(4))); |
| 287 | |
| 288 | |
| 289 | /** |
| 290 | * brief the data structure of Local Phy Control Response |
| 291 | * use to describe MPI Local Phy Control Response (64 bytes) |
| 292 | */ |
| 293 | struct local_phy_ctl_resp { |
| 294 | __le32 tag; |
| 295 | __le32 phyop_phyid; |
| 296 | __le32 status; |
| 297 | u32 reserved[12]; |
| 298 | } __attribute__((packed, aligned(4))); |
| 299 | |
| 300 | |
| 301 | #define OP_BITS 0x0000FF00 |
| 302 | #define ID_BITS 0x0000000F |
| 303 | |
| 304 | /* |
| 305 | * brief the data structure of PORT Control Command |
| 306 | * use to control port properties (64 bytes) |
| 307 | */ |
| 308 | |
| 309 | struct port_ctl_req { |
| 310 | __le32 tag; |
| 311 | __le32 portop_portid; |
| 312 | __le32 param0; |
| 313 | __le32 param1; |
| 314 | u32 reserved1[11]; |
| 315 | } __attribute__((packed, aligned(4))); |
| 316 | |
| 317 | |
| 318 | /* |
| 319 | * brief the data structure of HW Event Ack Command |
| 320 | * use to acknowledge receive HW event (64 bytes) |
| 321 | */ |
| 322 | |
| 323 | struct hw_event_ack_req { |
| 324 | __le32 tag; |
| 325 | __le32 sea_phyid_portid; |
| 326 | __le32 param0; |
| 327 | __le32 param1; |
| 328 | u32 reserved1[11]; |
| 329 | } __attribute__((packed, aligned(4))); |
| 330 | |
| 331 | |
| 332 | /* |
| 333 | * brief the data structure of SSP Completion Response |
| 334 | * use to indicate a SSP Completion (n bytes) |
| 335 | */ |
| 336 | struct ssp_completion_resp { |
| 337 | __le32 tag; |
| 338 | __le32 status; |
| 339 | __le32 param; |
| 340 | __le32 ssptag_rescv_rescpad; |
| 341 | struct ssp_response_iu ssp_resp_iu; |
| 342 | __le32 residual_count; |
| 343 | } __attribute__((packed, aligned(4))); |
| 344 | |
| 345 | |
| 346 | #define SSP_RESCV_BIT 0x00010000 |
| 347 | |
| 348 | /* |
| 349 | * brief the data structure of SATA EVNET esponse |
| 350 | * use to indicate a SATA Completion (64 bytes) |
| 351 | */ |
| 352 | |
| 353 | struct sata_event_resp { |
| 354 | __le32 tag; |
| 355 | __le32 event; |
| 356 | __le32 port_id; |
| 357 | __le32 device_id; |
| 358 | u32 reserved[11]; |
| 359 | } __attribute__((packed, aligned(4))); |
| 360 | |
| 361 | /* |
| 362 | * brief the data structure of SSP EVNET esponse |
| 363 | * use to indicate a SSP Completion (64 bytes) |
| 364 | */ |
| 365 | |
| 366 | struct ssp_event_resp { |
| 367 | __le32 tag; |
| 368 | __le32 event; |
| 369 | __le32 port_id; |
| 370 | __le32 device_id; |
| 371 | u32 reserved[11]; |
| 372 | } __attribute__((packed, aligned(4))); |
| 373 | |
| 374 | /** |
| 375 | * brief the data structure of General Event Notification Response |
| 376 | * use to describe MPI General Event Notification Response (64 bytes) |
| 377 | */ |
| 378 | struct general_event_resp { |
| 379 | __le32 status; |
| 380 | __le32 inb_IOMB_payload[14]; |
| 381 | } __attribute__((packed, aligned(4))); |
| 382 | |
| 383 | |
| 384 | #define GENERAL_EVENT_PAYLOAD 14 |
| 385 | #define OPCODE_BITS 0x00000fff |
| 386 | |
| 387 | /* |
| 388 | * brief the data structure of SMP Request Command |
| 389 | * use to describe MPI SMP REQUEST Command (64 bytes) |
| 390 | */ |
| 391 | struct smp_req { |
| 392 | __le32 tag; |
| 393 | __le32 device_id; |
| 394 | __le32 len_ip_ir; |
| 395 | /* Bits [0] - Indirect response */ |
| 396 | /* Bits [1] - Indirect Payload */ |
| 397 | /* Bits [15:2] - Reserved */ |
| 398 | /* Bits [23:16] - direct payload Len */ |
| 399 | /* Bits [31:24] - Reserved */ |
| 400 | u8 smp_req16[16]; |
| 401 | union { |
| 402 | u8 smp_req[32]; |
| 403 | struct { |
| 404 | __le64 long_req_addr;/* sg dma address, LE */ |
| 405 | __le32 long_req_size;/* LE */ |
| 406 | u32 _r_a; |
| 407 | __le64 long_resp_addr;/* sg dma address, LE */ |
| 408 | __le32 long_resp_size;/* LE */ |
| 409 | u32 _r_b; |
| 410 | } long_smp_req;/* sequencer extension */ |
| 411 | }; |
| 412 | } __attribute__((packed, aligned(4))); |
| 413 | /* |
| 414 | * brief the data structure of SMP Completion Response |
| 415 | * use to describe MPI SMP Completion Response (64 bytes) |
| 416 | */ |
| 417 | struct smp_completion_resp { |
| 418 | __le32 tag; |
| 419 | __le32 status; |
| 420 | __le32 param; |
| 421 | __le32 _r_a[12]; |
| 422 | } __attribute__((packed, aligned(4))); |
| 423 | |
| 424 | /* |
| 425 | *brief the data structure of SSP SMP SATA Abort Command |
| 426 | * use to describe MPI SSP SMP & SATA Abort Command (64 bytes) |
| 427 | */ |
| 428 | struct task_abort_req { |
| 429 | __le32 tag; |
| 430 | __le32 device_id; |
| 431 | __le32 tag_to_abort; |
| 432 | __le32 abort_all; |
| 433 | u32 reserved[11]; |
| 434 | } __attribute__((packed, aligned(4))); |
| 435 | |
| 436 | /* These flags used for SSP SMP & SATA Abort */ |
| 437 | #define ABORT_MASK 0x3 |
| 438 | #define ABORT_SINGLE 0x0 |
| 439 | #define ABORT_ALL 0x1 |
| 440 | |
| 441 | /** |
| 442 | * brief the data structure of SSP SATA SMP Abort Response |
| 443 | * use to describe SSP SMP & SATA Abort Response ( 64 bytes) |
| 444 | */ |
| 445 | struct task_abort_resp { |
| 446 | __le32 tag; |
| 447 | __le32 status; |
| 448 | __le32 scp; |
| 449 | u32 reserved[12]; |
| 450 | } __attribute__((packed, aligned(4))); |
| 451 | |
| 452 | |
| 453 | /** |
| 454 | * brief the data structure of SAS Diagnostic Start/End Command |
| 455 | * use to describe MPI SAS Diagnostic Start/End Command (64 bytes) |
| 456 | */ |
| 457 | struct sas_diag_start_end_req { |
| 458 | __le32 tag; |
| 459 | __le32 operation_phyid; |
| 460 | u32 reserved[13]; |
| 461 | } __attribute__((packed, aligned(4))); |
| 462 | |
| 463 | |
| 464 | /** |
| 465 | * brief the data structure of SAS Diagnostic Execute Command |
| 466 | * use to describe MPI SAS Diagnostic Execute Command (64 bytes) |
| 467 | */ |
| 468 | struct sas_diag_execute_req{ |
| 469 | __le32 tag; |
| 470 | __le32 cmdtype_cmddesc_phyid; |
| 471 | __le32 pat1_pat2; |
| 472 | __le32 threshold; |
| 473 | __le32 codepat_errmsk; |
| 474 | __le32 pmon; |
| 475 | __le32 pERF1CTL; |
| 476 | u32 reserved[8]; |
| 477 | } __attribute__((packed, aligned(4))); |
| 478 | |
| 479 | |
| 480 | #define SAS_DIAG_PARAM_BYTES 24 |
| 481 | |
| 482 | /* |
| 483 | * brief the data structure of Set Device State Command |
| 484 | * use to describe MPI Set Device State Command (64 bytes) |
| 485 | */ |
| 486 | struct set_dev_state_req { |
| 487 | __le32 tag; |
| 488 | __le32 device_id; |
| 489 | __le32 nds; |
| 490 | u32 reserved[12]; |
| 491 | } __attribute__((packed, aligned(4))); |
| 492 | |
| 493 | |
| 494 | /* |
| 495 | * brief the data structure of SATA Start Command |
| 496 | * use to describe MPI SATA IO Start Command (64 bytes) |
| 497 | */ |
| 498 | |
| 499 | struct sata_start_req { |
| 500 | __le32 tag; |
| 501 | __le32 device_id; |
| 502 | __le32 data_len; |
| 503 | __le32 ncqtag_atap_dir_m; |
| 504 | struct host_to_dev_fis sata_fis; |
| 505 | u32 reserved1; |
| 506 | u32 reserved2; |
| 507 | u32 addr_low; |
| 508 | u32 addr_high; |
| 509 | __le32 len; |
| 510 | __le32 esgl; |
| 511 | } __attribute__((packed, aligned(4))); |
| 512 | |
| 513 | /** |
| 514 | * brief the data structure of SSP INI TM Start Command |
| 515 | * use to describe MPI SSP INI TM Start Command (64 bytes) |
| 516 | */ |
| 517 | struct ssp_ini_tm_start_req { |
| 518 | __le32 tag; |
| 519 | __le32 device_id; |
| 520 | __le32 relate_tag; |
| 521 | __le32 tmf; |
| 522 | u8 lun[8]; |
| 523 | __le32 ds_ads_m; |
| 524 | u32 reserved[8]; |
| 525 | } __attribute__((packed, aligned(4))); |
| 526 | |
| 527 | |
| 528 | struct ssp_info_unit { |
| 529 | u8 lun[8];/* SCSI Logical Unit Number */ |
| 530 | u8 reserved1;/* reserved */ |
| 531 | u8 efb_prio_attr; |
| 532 | /* B7 : enabledFirstBurst */ |
| 533 | /* B6-3 : taskPriority */ |
| 534 | /* B2-0 : taskAttribute */ |
| 535 | u8 reserved2; /* reserved */ |
| 536 | u8 additional_cdb_len; |
| 537 | /* B7-2 : additional_cdb_len */ |
| 538 | /* B1-0 : reserved */ |
| 539 | u8 cdb[16];/* The SCSI CDB up to 16 bytes length */ |
| 540 | } __attribute__((packed, aligned(4))); |
| 541 | |
| 542 | |
| 543 | /** |
| 544 | * brief the data structure of SSP INI IO Start Command |
| 545 | * use to describe MPI SSP INI IO Start Command (64 bytes) |
| 546 | */ |
| 547 | struct ssp_ini_io_start_req { |
| 548 | __le32 tag; |
| 549 | __le32 device_id; |
| 550 | __le32 data_len; |
| 551 | __le32 dir_m_tlr; |
| 552 | struct ssp_info_unit ssp_iu; |
| 553 | __le32 addr_low; |
| 554 | __le32 addr_high; |
| 555 | __le32 len; |
| 556 | __le32 esgl; |
| 557 | } __attribute__((packed, aligned(4))); |
| 558 | |
| 559 | |
| 560 | /** |
| 561 | * brief the data structure of Firmware download |
| 562 | * use to describe MPI FW DOWNLOAD Command (64 bytes) |
| 563 | */ |
| 564 | struct fw_flash_Update_req { |
| 565 | __le32 tag; |
| 566 | __le32 cur_image_offset; |
| 567 | __le32 cur_image_len; |
| 568 | __le32 total_image_len; |
| 569 | u32 reserved0[7]; |
| 570 | __le32 sgl_addr_lo; |
| 571 | __le32 sgl_addr_hi; |
| 572 | __le32 len; |
| 573 | __le32 ext_reserved; |
| 574 | } __attribute__((packed, aligned(4))); |
| 575 | |
| 576 | |
| 577 | #define FWFLASH_IOMB_RESERVED_LEN 0x07 |
| 578 | /** |
| 579 | * brief the data structure of FW_FLASH_UPDATE Response |
| 580 | * use to describe MPI FW_FLASH_UPDATE Response (64 bytes) |
| 581 | * |
| 582 | */ |
| 583 | struct fw_flash_Update_resp { |
| 584 | dma_addr_t tag; |
| 585 | __le32 status; |
| 586 | u32 reserved[13]; |
| 587 | } __attribute__((packed, aligned(4))); |
| 588 | |
| 589 | |
| 590 | /** |
| 591 | * brief the data structure of Get NVM Data Command |
| 592 | * use to get data from NVM in HBA(64 bytes) |
| 593 | */ |
| 594 | struct get_nvm_data_req { |
| 595 | __le32 tag; |
| 596 | __le32 len_ir_vpdd; |
| 597 | __le32 vpd_offset; |
| 598 | u32 reserved[8]; |
| 599 | __le32 resp_addr_lo; |
| 600 | __le32 resp_addr_hi; |
| 601 | __le32 resp_len; |
| 602 | u32 reserved1; |
| 603 | } __attribute__((packed, aligned(4))); |
| 604 | |
| 605 | |
| 606 | struct set_nvm_data_req { |
| 607 | __le32 tag; |
| 608 | __le32 len_ir_vpdd; |
| 609 | __le32 vpd_offset; |
| 610 | u32 reserved[8]; |
| 611 | __le32 resp_addr_lo; |
| 612 | __le32 resp_addr_hi; |
| 613 | __le32 resp_len; |
| 614 | u32 reserved1; |
| 615 | } __attribute__((packed, aligned(4))); |
| 616 | |
| 617 | |
| 618 | #define TWI_DEVICE 0x0 |
| 619 | #define C_SEEPROM 0x1 |
| 620 | #define VPD_FLASH 0x4 |
| 621 | #define AAP1_RDUMP 0x5 |
| 622 | #define IOP_RDUMP 0x6 |
| 623 | #define EXPAN_ROM 0x7 |
| 624 | |
| 625 | #define IPMode 0x80000000 |
| 626 | #define NVMD_TYPE 0x0000000F |
| 627 | #define NVMD_STAT 0x0000FFFF |
| 628 | #define NVMD_LEN 0xFF000000 |
| 629 | /** |
| 630 | * brief the data structure of Get NVMD Data Response |
| 631 | * use to describe MPI Get NVMD Data Response (64 bytes) |
| 632 | */ |
| 633 | struct get_nvm_data_resp { |
| 634 | __le32 tag; |
| 635 | __le32 ir_tda_bn_dps_das_nvm; |
| 636 | __le32 dlen_status; |
| 637 | __le32 nvm_data[12]; |
| 638 | } __attribute__((packed, aligned(4))); |
| 639 | |
| 640 | |
| 641 | /** |
| 642 | * brief the data structure of SAS Diagnostic Start/End Response |
| 643 | * use to describe MPI SAS Diagnostic Start/End Response (64 bytes) |
| 644 | * |
| 645 | */ |
| 646 | struct sas_diag_start_end_resp { |
| 647 | __le32 tag; |
| 648 | __le32 status; |
| 649 | u32 reserved[13]; |
| 650 | } __attribute__((packed, aligned(4))); |
| 651 | |
| 652 | |
| 653 | /** |
| 654 | * brief the data structure of SAS Diagnostic Execute Response |
| 655 | * use to describe MPI SAS Diagnostic Execute Response (64 bytes) |
| 656 | * |
| 657 | */ |
| 658 | struct sas_diag_execute_resp { |
| 659 | __le32 tag; |
| 660 | __le32 cmdtype_cmddesc_phyid; |
| 661 | __le32 Status; |
| 662 | __le32 ReportData; |
| 663 | u32 reserved[11]; |
| 664 | } __attribute__((packed, aligned(4))); |
| 665 | |
| 666 | |
| 667 | /** |
| 668 | * brief the data structure of Set Device State Response |
| 669 | * use to describe MPI Set Device State Response (64 bytes) |
| 670 | * |
| 671 | */ |
| 672 | struct set_dev_state_resp { |
| 673 | __le32 tag; |
| 674 | __le32 status; |
| 675 | __le32 device_id; |
| 676 | __le32 pds_nds; |
| 677 | u32 reserved[11]; |
| 678 | } __attribute__((packed, aligned(4))); |
| 679 | |
| 680 | |
| 681 | #define NDS_BITS 0x0F |
| 682 | #define PDS_BITS 0xF0 |
| 683 | |
| 684 | /* |
| 685 | * HW Events type |
| 686 | */ |
| 687 | |
| 688 | #define HW_EVENT_RESET_START 0x01 |
| 689 | #define HW_EVENT_CHIP_RESET_COMPLETE 0x02 |
| 690 | #define HW_EVENT_PHY_STOP_STATUS 0x03 |
| 691 | #define HW_EVENT_SAS_PHY_UP 0x04 |
| 692 | #define HW_EVENT_SATA_PHY_UP 0x05 |
| 693 | #define HW_EVENT_SATA_SPINUP_HOLD 0x06 |
| 694 | #define HW_EVENT_PHY_DOWN 0x07 |
| 695 | #define HW_EVENT_PORT_INVALID 0x08 |
| 696 | #define HW_EVENT_BROADCAST_CHANGE 0x09 |
| 697 | #define HW_EVENT_PHY_ERROR 0x0A |
| 698 | #define HW_EVENT_BROADCAST_SES 0x0B |
| 699 | #define HW_EVENT_INBOUND_CRC_ERROR 0x0C |
| 700 | #define HW_EVENT_HARD_RESET_RECEIVED 0x0D |
| 701 | #define HW_EVENT_MALFUNCTION 0x0E |
| 702 | #define HW_EVENT_ID_FRAME_TIMEOUT 0x0F |
| 703 | #define HW_EVENT_BROADCAST_EXP 0x10 |
| 704 | #define HW_EVENT_PHY_START_STATUS 0x11 |
| 705 | #define HW_EVENT_LINK_ERR_INVALID_DWORD 0x12 |
| 706 | #define HW_EVENT_LINK_ERR_DISPARITY_ERROR 0x13 |
| 707 | #define HW_EVENT_LINK_ERR_CODE_VIOLATION 0x14 |
| 708 | #define HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH 0x15 |
| 709 | #define HW_EVENT_LINK_ERR_PHY_RESET_FAILED 0x16 |
| 710 | #define HW_EVENT_PORT_RECOVERY_TIMER_TMO 0x17 |
| 711 | #define HW_EVENT_PORT_RECOVER 0x18 |
| 712 | #define HW_EVENT_PORT_RESET_TIMER_TMO 0x19 |
| 713 | #define HW_EVENT_PORT_RESET_COMPLETE 0x20 |
| 714 | #define EVENT_BROADCAST_ASYNCH_EVENT 0x21 |
| 715 | |
| 716 | /* port state */ |
| 717 | #define PORT_NOT_ESTABLISHED 0x00 |
| 718 | #define PORT_VALID 0x01 |
| 719 | #define PORT_LOSTCOMM 0x02 |
| 720 | #define PORT_IN_RESET 0x04 |
| 721 | #define PORT_INVALID 0x08 |
| 722 | |
| 723 | /* |
| 724 | * SSP/SMP/SATA IO Completion Status values |
| 725 | */ |
| 726 | |
| 727 | #define IO_SUCCESS 0x00 |
| 728 | #define IO_ABORTED 0x01 |
| 729 | #define IO_OVERFLOW 0x02 |
| 730 | #define IO_UNDERFLOW 0x03 |
| 731 | #define IO_FAILED 0x04 |
| 732 | #define IO_ABORT_RESET 0x05 |
| 733 | #define IO_NOT_VALID 0x06 |
| 734 | #define IO_NO_DEVICE 0x07 |
| 735 | #define IO_ILLEGAL_PARAMETER 0x08 |
| 736 | #define IO_LINK_FAILURE 0x09 |
| 737 | #define IO_PROG_ERROR 0x0A |
| 738 | #define IO_EDC_IN_ERROR 0x0B |
| 739 | #define IO_EDC_OUT_ERROR 0x0C |
| 740 | #define IO_ERROR_HW_TIMEOUT 0x0D |
| 741 | #define IO_XFER_ERROR_BREAK 0x0E |
| 742 | #define IO_XFER_ERROR_PHY_NOT_READY 0x0F |
| 743 | #define IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED 0x10 |
| 744 | #define IO_OPEN_CNX_ERROR_ZONE_VIOLATION 0x11 |
| 745 | #define IO_OPEN_CNX_ERROR_BREAK 0x12 |
| 746 | #define IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS 0x13 |
| 747 | #define IO_OPEN_CNX_ERROR_BAD_DESTINATION 0x14 |
| 748 | #define IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED 0x15 |
| 749 | #define IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY 0x16 |
| 750 | #define IO_OPEN_CNX_ERROR_WRONG_DESTINATION 0x17 |
| 751 | #define IO_OPEN_CNX_ERROR_UNKNOWN_ERROR 0x18 |
| 752 | #define IO_XFER_ERROR_NAK_RECEIVED 0x19 |
| 753 | #define IO_XFER_ERROR_ACK_NAK_TIMEOUT 0x1A |
| 754 | #define IO_XFER_ERROR_PEER_ABORTED 0x1B |
| 755 | #define IO_XFER_ERROR_RX_FRAME 0x1C |
| 756 | #define IO_XFER_ERROR_DMA 0x1D |
| 757 | #define IO_XFER_ERROR_CREDIT_TIMEOUT 0x1E |
| 758 | #define IO_XFER_ERROR_SATA_LINK_TIMEOUT 0x1F |
| 759 | #define IO_XFER_ERROR_SATA 0x20 |
| 760 | #define IO_XFER_ERROR_ABORTED_DUE_TO_SRST 0x22 |
| 761 | #define IO_XFER_ERROR_REJECTED_NCQ_MODE 0x21 |
| 762 | #define IO_XFER_ERROR_ABORTED_NCQ_MODE 0x23 |
| 763 | #define IO_XFER_OPEN_RETRY_TIMEOUT 0x24 |
| 764 | #define IO_XFER_SMP_RESP_CONNECTION_ERROR 0x25 |
| 765 | #define IO_XFER_ERROR_UNEXPECTED_PHASE 0x26 |
| 766 | #define IO_XFER_ERROR_XFER_RDY_OVERRUN 0x27 |
| 767 | #define IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED 0x28 |
| 768 | |
| 769 | #define IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT 0x30 |
| 770 | #define IO_XFER_ERROR_CMD_ISSUE_BREAK_BEFORE_ACK_NAK 0x31 |
| 771 | #define IO_XFER_ERROR_CMD_ISSUE_PHY_DOWN_BEFORE_ACK_NAK 0x32 |
| 772 | |
| 773 | #define IO_XFER_ERROR_OFFSET_MISMATCH 0x34 |
| 774 | #define IO_XFER_ERROR_XFER_ZERO_DATA_LEN 0x35 |
| 775 | #define IO_XFER_CMD_FRAME_ISSUED 0x36 |
| 776 | #define IO_ERROR_INTERNAL_SMP_RESOURCE 0x37 |
| 777 | #define IO_PORT_IN_RESET 0x38 |
| 778 | #define IO_DS_NON_OPERATIONAL 0x39 |
| 779 | #define IO_DS_IN_RECOVERY 0x3A |
| 780 | #define IO_TM_TAG_NOT_FOUND 0x3B |
| 781 | #define IO_XFER_PIO_SETUP_ERROR 0x3C |
| 782 | #define IO_SSP_EXT_IU_ZERO_LEN_ERROR 0x3D |
| 783 | #define IO_DS_IN_ERROR 0x3E |
| 784 | #define IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY 0x3F |
| 785 | #define IO_ABORT_IN_PROGRESS 0x40 |
| 786 | #define IO_ABORT_DELAYED 0x41 |
| 787 | #define IO_INVALID_LENGTH 0x42 |
| 788 | |
| 789 | /* WARNING: This error code must always be the last number. |
| 790 | * If you add error code, modify this code also |
| 791 | * It is used as an index |
| 792 | */ |
| 793 | #define IO_ERROR_UNKNOWN_GENERIC 0x43 |
| 794 | |
| 795 | /* MSGU CONFIGURATION TABLE*/ |
| 796 | |
| 797 | #define SPC_MSGU_CFG_TABLE_UPDATE 0x01/* Inbound doorbell bit0 */ |
| 798 | #define SPC_MSGU_CFG_TABLE_RESET 0x02/* Inbound doorbell bit1 */ |
| 799 | #define SPC_MSGU_CFG_TABLE_FREEZE 0x04/* Inbound doorbell bit2 */ |
| 800 | #define SPC_MSGU_CFG_TABLE_UNFREEZE 0x08/* Inbound doorbell bit4 */ |
| 801 | #define MSGU_IBDB_SET 0x04 |
| 802 | #define MSGU_HOST_INT_STATUS 0x08 |
| 803 | #define MSGU_HOST_INT_MASK 0x0C |
| 804 | #define MSGU_IOPIB_INT_STATUS 0x18 |
| 805 | #define MSGU_IOPIB_INT_MASK 0x1C |
| 806 | #define MSGU_IBDB_CLEAR 0x20/* RevB - Host not use */ |
| 807 | #define MSGU_MSGU_CONTROL 0x24 |
| 808 | #define MSGU_ODR 0x3C/* RevB */ |
| 809 | #define MSGU_ODCR 0x40/* RevB */ |
| 810 | #define MSGU_SCRATCH_PAD_0 0x44 |
| 811 | #define MSGU_SCRATCH_PAD_1 0x48 |
| 812 | #define MSGU_SCRATCH_PAD_2 0x4C |
| 813 | #define MSGU_SCRATCH_PAD_3 0x50 |
| 814 | #define MSGU_HOST_SCRATCH_PAD_0 0x54 |
| 815 | #define MSGU_HOST_SCRATCH_PAD_1 0x58 |
| 816 | #define MSGU_HOST_SCRATCH_PAD_2 0x5C |
| 817 | #define MSGU_HOST_SCRATCH_PAD_3 0x60 |
| 818 | #define MSGU_HOST_SCRATCH_PAD_4 0x64 |
| 819 | #define MSGU_HOST_SCRATCH_PAD_5 0x68 |
| 820 | #define MSGU_HOST_SCRATCH_PAD_6 0x6C |
| 821 | #define MSGU_HOST_SCRATCH_PAD_7 0x70 |
| 822 | #define MSGU_ODMR 0x74/* RevB */ |
| 823 | |
| 824 | /* bit definition for ODMR register */ |
| 825 | #define ODMR_MASK_ALL 0xFFFFFFFF/* mask all |
| 826 | interrupt vector */ |
| 827 | #define ODMR_CLEAR_ALL 0/* clear all |
| 828 | interrupt vector */ |
| 829 | /* bit definition for ODCR register */ |
| 830 | #define ODCR_CLEAR_ALL 0xFFFFFFFF /* mask all |
| 831 | interrupt vector*/ |
| 832 | /* MSIX Interupts */ |
| 833 | #define MSIX_TABLE_OFFSET 0x2000 |
| 834 | #define MSIX_TABLE_ELEMENT_SIZE 0x10 |
| 835 | #define MSIX_INTERRUPT_CONTROL_OFFSET 0xC |
| 836 | #define MSIX_TABLE_BASE (MSIX_TABLE_OFFSET + MSIX_INTERRUPT_CONTROL_OFFSET) |
| 837 | #define MSIX_INTERRUPT_DISABLE 0x1 |
| 838 | #define MSIX_INTERRUPT_ENABLE 0x0 |
| 839 | |
| 840 | |
| 841 | /* state definition for Scratch Pad1 register */ |
| 842 | #define SCRATCH_PAD1_POR 0x00 /* power on reset state */ |
| 843 | #define SCRATCH_PAD1_SFR 0x01 /* soft reset state */ |
| 844 | #define SCRATCH_PAD1_ERR 0x02 /* error state */ |
| 845 | #define SCRATCH_PAD1_RDY 0x03 /* ready state */ |
| 846 | #define SCRATCH_PAD1_RST 0x04 /* soft reset toggle flag */ |
| 847 | #define SCRATCH_PAD1_AAP1RDY_RST 0x08 /* AAP1 ready for soft reset */ |
| 848 | #define SCRATCH_PAD1_STATE_MASK 0xFFFFFFF0 /* ScratchPad1 |
| 849 | Mask, bit1-0 State, bit2 Soft Reset, bit3 FW RDY for Soft Reset */ |
| 850 | #define SCRATCH_PAD1_RESERVED 0x000003F8 /* Scratch Pad1 |
| 851 | Reserved bit 3 to 9 */ |
| 852 | |
| 853 | /* state definition for Scratch Pad2 register */ |
| 854 | #define SCRATCH_PAD2_POR 0x00 /* power on state */ |
| 855 | #define SCRATCH_PAD2_SFR 0x01 /* soft reset state */ |
| 856 | #define SCRATCH_PAD2_ERR 0x02 /* error state */ |
| 857 | #define SCRATCH_PAD2_RDY 0x03 /* ready state */ |
| 858 | #define SCRATCH_PAD2_FWRDY_RST 0x04 /* FW ready for soft reset flag*/ |
| 859 | #define SCRATCH_PAD2_IOPRDY_RST 0x08 /* IOP ready for soft reset */ |
| 860 | #define SCRATCH_PAD2_STATE_MASK 0xFFFFFFF4 /* ScratchPad 2 |
| 861 | Mask, bit1-0 State */ |
| 862 | #define SCRATCH_PAD2_RESERVED 0x000003FC /* Scratch Pad1 |
| 863 | Reserved bit 2 to 9 */ |
| 864 | |
| 865 | #define SCRATCH_PAD_ERROR_MASK 0xFFFFFC00 /* Error mask bits */ |
| 866 | #define SCRATCH_PAD_STATE_MASK 0x00000003 /* State Mask bits */ |
| 867 | |
| 868 | /* main configuration offset - byte offset */ |
| 869 | #define MAIN_SIGNATURE_OFFSET 0x00/* DWORD 0x00 */ |
| 870 | #define MAIN_INTERFACE_REVISION 0x04/* DWORD 0x01 */ |
| 871 | #define MAIN_FW_REVISION 0x08/* DWORD 0x02 */ |
| 872 | #define MAIN_MAX_OUTSTANDING_IO_OFFSET 0x0C/* DWORD 0x03 */ |
| 873 | #define MAIN_MAX_SGL_OFFSET 0x10/* DWORD 0x04 */ |
| 874 | #define MAIN_CNTRL_CAP_OFFSET 0x14/* DWORD 0x05 */ |
| 875 | #define MAIN_GST_OFFSET 0x18/* DWORD 0x06 */ |
| 876 | #define MAIN_IBQ_OFFSET 0x1C/* DWORD 0x07 */ |
| 877 | #define MAIN_OBQ_OFFSET 0x20/* DWORD 0x08 */ |
| 878 | #define MAIN_IQNPPD_HPPD_OFFSET 0x24/* DWORD 0x09 */ |
| 879 | #define MAIN_OB_HW_EVENT_PID03_OFFSET 0x28/* DWORD 0x0A */ |
| 880 | #define MAIN_OB_HW_EVENT_PID47_OFFSET 0x2C/* DWORD 0x0B */ |
| 881 | #define MAIN_OB_NCQ_EVENT_PID03_OFFSET 0x30/* DWORD 0x0C */ |
| 882 | #define MAIN_OB_NCQ_EVENT_PID47_OFFSET 0x34/* DWORD 0x0D */ |
| 883 | #define MAIN_TITNX_EVENT_PID03_OFFSET 0x38/* DWORD 0x0E */ |
| 884 | #define MAIN_TITNX_EVENT_PID47_OFFSET 0x3C/* DWORD 0x0F */ |
| 885 | #define MAIN_OB_SSP_EVENT_PID03_OFFSET 0x40/* DWORD 0x10 */ |
| 886 | #define MAIN_OB_SSP_EVENT_PID47_OFFSET 0x44/* DWORD 0x11 */ |
| 887 | #define MAIN_OB_SMP_EVENT_PID03_OFFSET 0x48/* DWORD 0x12 */ |
| 888 | #define MAIN_OB_SMP_EVENT_PID47_OFFSET 0x4C/* DWORD 0x13 */ |
| 889 | #define MAIN_EVENT_LOG_ADDR_HI 0x50/* DWORD 0x14 */ |
| 890 | #define MAIN_EVENT_LOG_ADDR_LO 0x54/* DWORD 0x15 */ |
| 891 | #define MAIN_EVENT_LOG_BUFF_SIZE 0x58/* DWORD 0x16 */ |
| 892 | #define MAIN_EVENT_LOG_OPTION 0x5C/* DWORD 0x17 */ |
| 893 | #define MAIN_IOP_EVENT_LOG_ADDR_HI 0x60/* DWORD 0x18 */ |
| 894 | #define MAIN_IOP_EVENT_LOG_ADDR_LO 0x64/* DWORD 0x19 */ |
| 895 | #define MAIN_IOP_EVENT_LOG_BUFF_SIZE 0x68/* DWORD 0x1A */ |
| 896 | #define MAIN_IOP_EVENT_LOG_OPTION 0x6C/* DWORD 0x1B */ |
| 897 | #define MAIN_FATAL_ERROR_INTERRUPT 0x70/* DWORD 0x1C */ |
| 898 | #define MAIN_FATAL_ERROR_RDUMP0_OFFSET 0x74/* DWORD 0x1D */ |
| 899 | #define MAIN_FATAL_ERROR_RDUMP0_LENGTH 0x78/* DWORD 0x1E */ |
| 900 | #define MAIN_FATAL_ERROR_RDUMP1_OFFSET 0x7C/* DWORD 0x1F */ |
| 901 | #define MAIN_FATAL_ERROR_RDUMP1_LENGTH 0x80/* DWORD 0x20 */ |
| 902 | #define MAIN_HDA_FLAGS_OFFSET 0x84/* DWORD 0x21 */ |
| 903 | #define MAIN_ANALOG_SETUP_OFFSET 0x88/* DWORD 0x22 */ |
| 904 | |
| 905 | /* Gereral Status Table offset - byte offset */ |
| 906 | #define GST_GSTLEN_MPIS_OFFSET 0x00 |
| 907 | #define GST_IQ_FREEZE_STATE0_OFFSET 0x04 |
| 908 | #define GST_IQ_FREEZE_STATE1_OFFSET 0x08 |
| 909 | #define GST_MSGUTCNT_OFFSET 0x0C |
| 910 | #define GST_IOPTCNT_OFFSET 0x10 |
| 911 | #define GST_PHYSTATE_OFFSET 0x18 |
| 912 | #define GST_PHYSTATE0_OFFSET 0x18 |
| 913 | #define GST_PHYSTATE1_OFFSET 0x1C |
| 914 | #define GST_PHYSTATE2_OFFSET 0x20 |
| 915 | #define GST_PHYSTATE3_OFFSET 0x24 |
| 916 | #define GST_PHYSTATE4_OFFSET 0x28 |
| 917 | #define GST_PHYSTATE5_OFFSET 0x2C |
| 918 | #define GST_PHYSTATE6_OFFSET 0x30 |
| 919 | #define GST_PHYSTATE7_OFFSET 0x34 |
| 920 | #define GST_RERRINFO_OFFSET 0x44 |
| 921 | |
| 922 | /* General Status Table - MPI state */ |
| 923 | #define GST_MPI_STATE_UNINIT 0x00 |
| 924 | #define GST_MPI_STATE_INIT 0x01 |
| 925 | #define GST_MPI_STATE_TERMINATION 0x02 |
| 926 | #define GST_MPI_STATE_ERROR 0x03 |
| 927 | #define GST_MPI_STATE_MASK 0x07 |
| 928 | |
| 929 | #define MBIC_NMI_ENABLE_VPE0_IOP 0x000418 |
| 930 | #define MBIC_NMI_ENABLE_VPE0_AAP1 0x000418 |
| 931 | /* PCIE registers - BAR2(0x18), BAR1(win) 0x010000 */ |
| 932 | #define PCIE_EVENT_INTERRUPT_ENABLE 0x003040 |
| 933 | #define PCIE_EVENT_INTERRUPT 0x003044 |
| 934 | #define PCIE_ERROR_INTERRUPT_ENABLE 0x003048 |
| 935 | #define PCIE_ERROR_INTERRUPT 0x00304C |
| 936 | /* signature defintion for host scratch pad0 register */ |
| 937 | #define SPC_SOFT_RESET_SIGNATURE 0x252acbcd |
| 938 | /* Signature for Soft Reset */ |
| 939 | |
| 940 | /* SPC Reset register - BAR4(0x20), BAR2(win) (need dynamic mapping) */ |
| 941 | #define SPC_REG_RESET 0x000000/* reset register */ |
| 942 | |
| 943 | /* bit difination for SPC_RESET register */ |
| 944 | #define SPC_REG_RESET_OSSP 0x00000001 |
| 945 | #define SPC_REG_RESET_RAAE 0x00000002 |
| 946 | #define SPC_REG_RESET_PCS_SPBC 0x00000004 |
| 947 | #define SPC_REG_RESET_PCS_IOP_SS 0x00000008 |
| 948 | #define SPC_REG_RESET_PCS_AAP1_SS 0x00000010 |
| 949 | #define SPC_REG_RESET_PCS_AAP2_SS 0x00000020 |
| 950 | #define SPC_REG_RESET_PCS_LM 0x00000040 |
| 951 | #define SPC_REG_RESET_PCS 0x00000080 |
| 952 | #define SPC_REG_RESET_GSM 0x00000100 |
| 953 | #define SPC_REG_RESET_DDR2 0x00010000 |
| 954 | #define SPC_REG_RESET_BDMA_CORE 0x00020000 |
| 955 | #define SPC_REG_RESET_BDMA_SXCBI 0x00040000 |
| 956 | #define SPC_REG_RESET_PCIE_AL_SXCBI 0x00080000 |
| 957 | #define SPC_REG_RESET_PCIE_PWR 0x00100000 |
| 958 | #define SPC_REG_RESET_PCIE_SFT 0x00200000 |
| 959 | #define SPC_REG_RESET_PCS_SXCBI 0x00400000 |
| 960 | #define SPC_REG_RESET_LMS_SXCBI 0x00800000 |
| 961 | #define SPC_REG_RESET_PMIC_SXCBI 0x01000000 |
| 962 | #define SPC_REG_RESET_PMIC_CORE 0x02000000 |
| 963 | #define SPC_REG_RESET_PCIE_PC_SXCBI 0x04000000 |
| 964 | #define SPC_REG_RESET_DEVICE 0x80000000 |
| 965 | |
| 966 | /* registers for BAR Shifting - BAR2(0x18), BAR1(win) */ |
| 967 | #define SPC_IBW_AXI_TRANSLATION_LOW 0x003258 |
| 968 | |
| 969 | #define MBIC_AAP1_ADDR_BASE 0x060000 |
| 970 | #define MBIC_IOP_ADDR_BASE 0x070000 |
| 971 | #define GSM_ADDR_BASE 0x0700000 |
| 972 | /* Dynamic map through Bar4 - 0x00700000 */ |
| 973 | #define GSM_CONFIG_RESET 0x00000000 |
| 974 | #define RAM_ECC_DB_ERR 0x00000018 |
| 975 | #define GSM_READ_ADDR_PARITY_INDIC 0x00000058 |
| 976 | #define GSM_WRITE_ADDR_PARITY_INDIC 0x00000060 |
| 977 | #define GSM_WRITE_DATA_PARITY_INDIC 0x00000068 |
| 978 | #define GSM_READ_ADDR_PARITY_CHECK 0x00000038 |
| 979 | #define GSM_WRITE_ADDR_PARITY_CHECK 0x00000040 |
| 980 | #define GSM_WRITE_DATA_PARITY_CHECK 0x00000048 |
| 981 | |
| 982 | #define RB6_ACCESS_REG 0x6A0000 |
| 983 | #define HDAC_EXEC_CMD 0x0002 |
| 984 | #define HDA_C_PA 0xcb |
| 985 | #define HDA_SEQ_ID_BITS 0x00ff0000 |
| 986 | #define HDA_GSM_OFFSET_BITS 0x00FFFFFF |
| 987 | #define MBIC_AAP1_ADDR_BASE 0x060000 |
| 988 | #define MBIC_IOP_ADDR_BASE 0x070000 |
| 989 | #define GSM_ADDR_BASE 0x0700000 |
| 990 | #define SPC_TOP_LEVEL_ADDR_BASE 0x000000 |
| 991 | #define GSM_CONFIG_RESET_VALUE 0x00003b00 |
| 992 | #define GPIO_ADDR_BASE 0x00090000 |
| 993 | #define GPIO_GPIO_0_0UTPUT_CTL_OFFSET 0x0000010c |
| 994 | |
| 995 | /* RB6 offset */ |
| 996 | #define SPC_RB6_OFFSET 0x80C0 |
| 997 | /* Magic number of soft reset for RB6 */ |
| 998 | #define RB6_MAGIC_NUMBER_RST 0x1234 |
| 999 | |
| 1000 | /* Device Register status */ |
| 1001 | #define DEVREG_SUCCESS 0x00 |
| 1002 | #define DEVREG_FAILURE_OUT_OF_RESOURCE 0x01 |
| 1003 | #define DEVREG_FAILURE_DEVICE_ALREADY_REGISTERED 0x02 |
| 1004 | #define DEVREG_FAILURE_INVALID_PHY_ID 0x03 |
| 1005 | #define DEVREG_FAILURE_PHY_ID_ALREADY_REGISTERED 0x04 |
| 1006 | #define DEVREG_FAILURE_PORT_ID_OUT_OF_RANGE 0x05 |
| 1007 | #define DEVREG_FAILURE_PORT_NOT_VALID_STATE 0x06 |
| 1008 | #define DEVREG_FAILURE_DEVICE_TYPE_NOT_VALID 0x07 |
| 1009 | |
| 1010 | #endif |
| 1011 | |