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Joerg Roedelf6e2e6b2008-06-26 21:27:39 +02001/*
Joerg Roedel5d0d7152010-10-13 11:13:21 +02002 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
Joerg Roedelf6e2e6b2008-06-26 21:27:39 +02003 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#include <linux/pci.h>
21#include <linux/acpi.h>
Joerg Roedelf6e2e6b2008-06-26 21:27:39 +020022#include <linux/list.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090023#include <linux/slab.h>
Rafael J. Wysockif3c6ea12011-03-23 22:15:54 +010024#include <linux/syscore_ops.h>
Joerg Roedela80dc3e2008-09-11 16:51:41 +020025#include <linux/interrupt.h>
26#include <linux/msi.h>
Joerg Roedel403f81d2011-06-14 16:44:25 +020027#include <linux/amd-iommu.h>
Joerg Roedel400a28a2011-11-28 15:11:02 +010028#include <linux/export.h>
Joerg Roedelf6e2e6b2008-06-26 21:27:39 +020029#include <asm/pci-direct.h>
FUJITA Tomonori46a7fa22008-07-11 10:23:42 +090030#include <asm/iommu.h>
Joerg Roedel1d9b16d2008-11-27 18:39:15 +010031#include <asm/gart.h>
FUJITA Tomonoriea1b0d32009-11-10 19:46:15 +090032#include <asm/x86_init.h>
Konrad Rzeszutek Wilk22e6daf42010-08-26 13:58:03 -040033#include <asm/iommu_table.h>
Joerg Roedel403f81d2011-06-14 16:44:25 +020034
35#include "amd_iommu_proto.h"
36#include "amd_iommu_types.h"
37
Joerg Roedelf6e2e6b2008-06-26 21:27:39 +020038/*
39 * definitions for the ACPI scanning code
40 */
Joerg Roedelf6e2e6b2008-06-26 21:27:39 +020041#define IVRS_HEADER_LENGTH 48
Joerg Roedelf6e2e6b2008-06-26 21:27:39 +020042
43#define ACPI_IVHD_TYPE 0x10
44#define ACPI_IVMD_TYPE_ALL 0x20
45#define ACPI_IVMD_TYPE 0x21
46#define ACPI_IVMD_TYPE_RANGE 0x22
47
48#define IVHD_DEV_ALL 0x01
49#define IVHD_DEV_SELECT 0x02
50#define IVHD_DEV_SELECT_RANGE_START 0x03
51#define IVHD_DEV_RANGE_END 0x04
52#define IVHD_DEV_ALIAS 0x42
53#define IVHD_DEV_ALIAS_RANGE 0x43
54#define IVHD_DEV_EXT_SELECT 0x46
55#define IVHD_DEV_EXT_SELECT_RANGE 0x47
56
Joerg Roedel6da73422009-05-04 11:44:38 +020057#define IVHD_FLAG_HT_TUN_EN_MASK 0x01
58#define IVHD_FLAG_PASSPW_EN_MASK 0x02
59#define IVHD_FLAG_RESPASSPW_EN_MASK 0x04
60#define IVHD_FLAG_ISOC_EN_MASK 0x08
Joerg Roedelf6e2e6b2008-06-26 21:27:39 +020061
62#define IVMD_FLAG_EXCL_RANGE 0x08
63#define IVMD_FLAG_UNITY_MAP 0x01
64
65#define ACPI_DEVFLAG_INITPASS 0x01
66#define ACPI_DEVFLAG_EXTINT 0x02
67#define ACPI_DEVFLAG_NMI 0x04
68#define ACPI_DEVFLAG_SYSMGT1 0x10
69#define ACPI_DEVFLAG_SYSMGT2 0x20
70#define ACPI_DEVFLAG_LINT0 0x40
71#define ACPI_DEVFLAG_LINT1 0x80
72#define ACPI_DEVFLAG_ATSDIS 0x10000000
73
Joerg Roedelb65233a2008-07-11 17:14:21 +020074/*
75 * ACPI table definitions
76 *
77 * These data structures are laid over the table to parse the important values
78 * out of it.
79 */
80
81/*
82 * structure describing one IOMMU in the ACPI table. Typically followed by one
83 * or more ivhd_entrys.
84 */
Joerg Roedelf6e2e6b2008-06-26 21:27:39 +020085struct ivhd_header {
86 u8 type;
87 u8 flags;
88 u16 length;
89 u16 devid;
90 u16 cap_ptr;
91 u64 mmio_phys;
92 u16 pci_seg;
93 u16 info;
94 u32 reserved;
95} __attribute__((packed));
96
Joerg Roedelb65233a2008-07-11 17:14:21 +020097/*
98 * A device entry describing which devices a specific IOMMU translates and
99 * which requestor ids they use.
100 */
Joerg Roedelf6e2e6b2008-06-26 21:27:39 +0200101struct ivhd_entry {
102 u8 type;
103 u16 devid;
104 u8 flags;
105 u32 ext;
106} __attribute__((packed));
107
Joerg Roedelb65233a2008-07-11 17:14:21 +0200108/*
109 * An AMD IOMMU memory definition structure. It defines things like exclusion
110 * ranges for devices and regions that should be unity mapped.
111 */
Joerg Roedelf6e2e6b2008-06-26 21:27:39 +0200112struct ivmd_header {
113 u8 type;
114 u8 flags;
115 u16 length;
116 u16 devid;
117 u16 aux;
118 u64 resv;
119 u64 range_start;
120 u64 range_length;
121} __attribute__((packed));
122
Joerg Roedelfefda112009-05-20 12:21:42 +0200123bool amd_iommu_dump;
124
Joerg Roedelc1cbebe2008-07-03 19:35:10 +0200125static int __initdata amd_iommu_detected;
Joerg Roedela5235722010-05-11 17:12:33 +0200126static bool __initdata amd_iommu_disabled;
Joerg Roedelc1cbebe2008-07-03 19:35:10 +0200127
Joerg Roedelb65233a2008-07-11 17:14:21 +0200128u16 amd_iommu_last_bdf; /* largest PCI device id we have
129 to handle */
Joerg Roedel2e228472008-07-11 17:14:31 +0200130LIST_HEAD(amd_iommu_unity_map); /* a list of required unity mappings
Joerg Roedelb65233a2008-07-11 17:14:21 +0200131 we find in ACPI */
FUJITA Tomonoriafa9fdc2008-09-20 01:23:30 +0900132bool amd_iommu_unmap_flush; /* if true, flush on every unmap */
Joerg Roedel928abd22008-06-26 21:27:40 +0200133
Joerg Roedel2e228472008-07-11 17:14:31 +0200134LIST_HEAD(amd_iommu_list); /* list of all AMD IOMMUs in the
Joerg Roedelb65233a2008-07-11 17:14:21 +0200135 system */
136
Joerg Roedelbb527772009-11-20 14:31:51 +0100137/* Array to assign indices to IOMMUs*/
138struct amd_iommu *amd_iommus[MAX_IOMMUS];
139int amd_iommus_present;
140
Joerg Roedel318afd42009-11-23 18:32:38 +0100141/* IOMMUs have a non-present cache? */
142bool amd_iommu_np_cache __read_mostly;
Joerg Roedel60f723b2011-04-05 12:50:24 +0200143bool amd_iommu_iotlb_sup __read_mostly = true;
Joerg Roedel318afd42009-11-23 18:32:38 +0100144
Joerg Roedel62f71ab2011-11-10 14:41:57 +0100145u32 amd_iommu_max_pasids __read_mostly = ~0;
146
Joerg Roedel400a28a2011-11-28 15:11:02 +0100147bool amd_iommu_v2_present __read_mostly;
148
Joerg Roedel5abcdba2011-12-01 15:49:45 +0100149bool amd_iommu_force_isolation __read_mostly;
150
Joerg Roedelb65233a2008-07-11 17:14:21 +0200151/*
Joerg Roedel3551a702010-03-01 13:52:19 +0100152 * The ACPI table parsing functions set this variable on an error
Joerg Roedel0f764802009-12-21 15:51:23 +0100153 */
Joerg Roedel3551a702010-03-01 13:52:19 +0100154static int __initdata amd_iommu_init_err;
Joerg Roedel0f764802009-12-21 15:51:23 +0100155
156/*
Joerg Roedelaeb26f52009-11-20 16:44:01 +0100157 * List of protection domains - used during resume
158 */
159LIST_HEAD(amd_iommu_pd_list);
160spinlock_t amd_iommu_pd_lock;
161
162/*
Joerg Roedelb65233a2008-07-11 17:14:21 +0200163 * Pointer to the device table which is shared by all AMD IOMMUs
164 * it is indexed by the PCI device id or the HT unit id and contains
165 * information about the domain the device belongs to as well as the
166 * page table root pointer.
167 */
Joerg Roedel928abd22008-06-26 21:27:40 +0200168struct dev_table_entry *amd_iommu_dev_table;
Joerg Roedelb65233a2008-07-11 17:14:21 +0200169
170/*
171 * The alias table is a driver specific data structure which contains the
172 * mappings of the PCI device ids to the actual requestor ids on the IOMMU.
173 * More than one device can share the same requestor id.
174 */
Joerg Roedel928abd22008-06-26 21:27:40 +0200175u16 *amd_iommu_alias_table;
Joerg Roedelb65233a2008-07-11 17:14:21 +0200176
177/*
178 * The rlookup table is used to find the IOMMU which is responsible
179 * for a specific device. It is also indexed by the PCI device id.
180 */
Joerg Roedel928abd22008-06-26 21:27:40 +0200181struct amd_iommu **amd_iommu_rlookup_table;
Joerg Roedelb65233a2008-07-11 17:14:21 +0200182
183/*
Joerg Roedelb65233a2008-07-11 17:14:21 +0200184 * AMD IOMMU allows up to 2^16 differend protection domains. This is a bitmap
185 * to know which ones are already in use.
186 */
Joerg Roedel928abd22008-06-26 21:27:40 +0200187unsigned long *amd_iommu_pd_alloc_bitmap;
188
Joerg Roedelb65233a2008-07-11 17:14:21 +0200189static u32 dev_table_size; /* size of the device table */
190static u32 alias_table_size; /* size of the alias table */
191static u32 rlookup_table_size; /* size if the rlookup table */
Joerg Roedel3e8064b2008-06-26 21:27:41 +0200192
Joerg Roedel7d0c5cc2011-04-07 08:16:10 +0200193/*
194 * This function flushes all internal caches of
195 * the IOMMU used by this driver.
196 */
197extern void iommu_flush_all_caches(struct amd_iommu *iommu);
198
Gerard Snitselaarae295142012-03-16 11:38:22 -0700199static int amd_iommu_enable_interrupts(void);
Joerg Roedel3d9761e2012-03-15 16:39:21 +0100200
Joerg Roedel208ec8c2008-07-11 17:14:24 +0200201static inline void update_last_devid(u16 devid)
202{
203 if (devid > amd_iommu_last_bdf)
204 amd_iommu_last_bdf = devid;
205}
206
Joerg Roedelc5714842008-07-11 17:14:25 +0200207static inline unsigned long tbl_size(int entry_size)
208{
209 unsigned shift = PAGE_SHIFT +
Neil Turton421f9092009-05-14 14:00:35 +0100210 get_order(((int)amd_iommu_last_bdf + 1) * entry_size);
Joerg Roedelc5714842008-07-11 17:14:25 +0200211
212 return 1UL << shift;
213}
214
Matthew Garrett5bcd7572010-10-04 14:59:31 -0400215/* Access to l1 and l2 indexed register spaces */
216
217static u32 iommu_read_l1(struct amd_iommu *iommu, u16 l1, u8 address)
218{
219 u32 val;
220
221 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16));
222 pci_read_config_dword(iommu->dev, 0xfc, &val);
223 return val;
224}
225
226static void iommu_write_l1(struct amd_iommu *iommu, u16 l1, u8 address, u32 val)
227{
228 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16 | 1 << 31));
229 pci_write_config_dword(iommu->dev, 0xfc, val);
230 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16));
231}
232
233static u32 iommu_read_l2(struct amd_iommu *iommu, u8 address)
234{
235 u32 val;
236
237 pci_write_config_dword(iommu->dev, 0xf0, address);
238 pci_read_config_dword(iommu->dev, 0xf4, &val);
239 return val;
240}
241
242static void iommu_write_l2(struct amd_iommu *iommu, u8 address, u32 val)
243{
244 pci_write_config_dword(iommu->dev, 0xf0, (address | 1 << 8));
245 pci_write_config_dword(iommu->dev, 0xf4, val);
246}
247
Joerg Roedelb65233a2008-07-11 17:14:21 +0200248/****************************************************************************
249 *
250 * AMD IOMMU MMIO register space handling functions
251 *
252 * These functions are used to program the IOMMU device registers in
253 * MMIO space required for that driver.
254 *
255 ****************************************************************************/
256
257/*
258 * This function set the exclusion range in the IOMMU. DMA accesses to the
259 * exclusion range are passed through untranslated
260 */
Joerg Roedel05f92db2009-05-12 09:52:46 +0200261static void iommu_set_exclusion_range(struct amd_iommu *iommu)
Joerg Roedelb2026aa2008-06-26 21:27:44 +0200262{
263 u64 start = iommu->exclusion_start & PAGE_MASK;
264 u64 limit = (start + iommu->exclusion_length) & PAGE_MASK;
265 u64 entry;
266
267 if (!iommu->exclusion_start)
268 return;
269
270 entry = start | MMIO_EXCL_ENABLE_MASK;
271 memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET,
272 &entry, sizeof(entry));
273
274 entry = limit;
275 memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET,
276 &entry, sizeof(entry));
277}
278
Joerg Roedelb65233a2008-07-11 17:14:21 +0200279/* Programs the physical address of the device table into the IOMMU hardware */
Jan Beulich6b7f0002012-03-08 08:58:13 +0000280static void iommu_set_device_table(struct amd_iommu *iommu)
Joerg Roedelb2026aa2008-06-26 21:27:44 +0200281{
Andreas Herrmannf6098912008-10-16 16:27:36 +0200282 u64 entry;
Joerg Roedelb2026aa2008-06-26 21:27:44 +0200283
284 BUG_ON(iommu->mmio_base == NULL);
285
286 entry = virt_to_phys(amd_iommu_dev_table);
287 entry |= (dev_table_size >> 12) - 1;
288 memcpy_toio(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET,
289 &entry, sizeof(entry));
290}
291
Joerg Roedelb65233a2008-07-11 17:14:21 +0200292/* Generic functions to enable/disable certain features of the IOMMU. */
Joerg Roedel05f92db2009-05-12 09:52:46 +0200293static void iommu_feature_enable(struct amd_iommu *iommu, u8 bit)
Joerg Roedelb2026aa2008-06-26 21:27:44 +0200294{
295 u32 ctrl;
296
297 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
298 ctrl |= (1 << bit);
299 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
300}
301
Joerg Roedelca0207112009-10-28 18:02:26 +0100302static void iommu_feature_disable(struct amd_iommu *iommu, u8 bit)
Joerg Roedelb2026aa2008-06-26 21:27:44 +0200303{
304 u32 ctrl;
305
Joerg Roedel199d0d52008-09-17 16:45:59 +0200306 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
Joerg Roedelb2026aa2008-06-26 21:27:44 +0200307 ctrl &= ~(1 << bit);
308 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
309}
310
Joerg Roedel1456e9d2011-12-22 14:51:53 +0100311static void iommu_set_inv_tlb_timeout(struct amd_iommu *iommu, int timeout)
312{
313 u32 ctrl;
314
315 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
316 ctrl &= ~CTRL_INV_TO_MASK;
317 ctrl |= (timeout << CONTROL_INV_TIMEOUT) & CTRL_INV_TO_MASK;
318 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
319}
320
Joerg Roedelb65233a2008-07-11 17:14:21 +0200321/* Function to enable the hardware */
Joerg Roedel05f92db2009-05-12 09:52:46 +0200322static void iommu_enable(struct amd_iommu *iommu)
Joerg Roedelb2026aa2008-06-26 21:27:44 +0200323{
Joerg Roedeld99ddec2011-04-11 11:03:18 +0200324 static const char * const feat_str[] = {
325 "PreF", "PPR", "X2APIC", "NX", "GT", "[5]",
326 "IA", "GA", "HE", "PC", NULL
327 };
328 int i;
329
330 printk(KERN_INFO "AMD-Vi: Enabling IOMMU at %s cap 0x%hx",
Joerg Roedela4e267c2008-12-10 20:04:18 +0100331 dev_name(&iommu->dev->dev), iommu->cap_ptr);
Joerg Roedelb2026aa2008-06-26 21:27:44 +0200332
Joerg Roedeld99ddec2011-04-11 11:03:18 +0200333 if (iommu->cap & (1 << IOMMU_CAP_EFR)) {
334 printk(KERN_CONT " extended features: ");
335 for (i = 0; feat_str[i]; ++i)
336 if (iommu_feature(iommu, (1ULL << i)))
337 printk(KERN_CONT " %s", feat_str[i]);
338 }
339 printk(KERN_CONT "\n");
340
Joerg Roedelb2026aa2008-06-26 21:27:44 +0200341 iommu_feature_enable(iommu, CONTROL_IOMMU_EN);
Joerg Roedelb2026aa2008-06-26 21:27:44 +0200342}
343
Joerg Roedel92ac4322009-05-19 19:06:27 +0200344static void iommu_disable(struct amd_iommu *iommu)
Joerg Roedel126c52b2008-09-09 16:47:35 +0200345{
Chris Wrighta8c485b2009-06-15 15:53:45 +0200346 /* Disable command buffer */
347 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN);
348
349 /* Disable event logging and event interrupts */
350 iommu_feature_disable(iommu, CONTROL_EVT_INT_EN);
351 iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN);
352
353 /* Disable IOMMU hardware itself */
Joerg Roedel92ac4322009-05-19 19:06:27 +0200354 iommu_feature_disable(iommu, CONTROL_IOMMU_EN);
Joerg Roedel126c52b2008-09-09 16:47:35 +0200355}
356
Joerg Roedelb65233a2008-07-11 17:14:21 +0200357/*
358 * mapping and unmapping functions for the IOMMU MMIO space. Each AMD IOMMU in
359 * the system has one.
360 */
Joerg Roedel6c567472008-06-26 21:27:43 +0200361static u8 * __init iommu_map_mmio_space(u64 address)
362{
Joerg Roedele82752d2010-05-28 14:26:48 +0200363 if (!request_mem_region(address, MMIO_REGION_LENGTH, "amd_iommu")) {
364 pr_err("AMD-Vi: Can not reserve memory region %llx for mmio\n",
365 address);
366 pr_err("AMD-Vi: This is a BIOS bug. Please contact your hardware vendor\n");
Joerg Roedel6c567472008-06-26 21:27:43 +0200367 return NULL;
Joerg Roedele82752d2010-05-28 14:26:48 +0200368 }
Joerg Roedel6c567472008-06-26 21:27:43 +0200369
Joerg Roedel6e9300452012-03-09 13:37:48 +0100370 return ioremap_nocache(address, MMIO_REGION_LENGTH);
Joerg Roedel6c567472008-06-26 21:27:43 +0200371}
372
373static void __init iommu_unmap_mmio_space(struct amd_iommu *iommu)
374{
375 if (iommu->mmio_base)
376 iounmap(iommu->mmio_base);
377 release_mem_region(iommu->mmio_phys, MMIO_REGION_LENGTH);
378}
379
Joerg Roedelb65233a2008-07-11 17:14:21 +0200380/****************************************************************************
381 *
382 * The functions below belong to the first pass of AMD IOMMU ACPI table
383 * parsing. In this pass we try to find out the highest device id this
384 * code has to handle. Upon this information the size of the shared data
385 * structures is determined later.
386 *
387 ****************************************************************************/
388
389/*
Joerg Roedelb514e552008-09-17 17:14:27 +0200390 * This function calculates the length of a given IVHD entry
391 */
392static inline int ivhd_entry_length(u8 *ivhd)
393{
394 return 0x04 << (*ivhd >> 6);
395}
396
397/*
Joerg Roedelb65233a2008-07-11 17:14:21 +0200398 * This function reads the last device id the IOMMU has to handle from the PCI
399 * capability header for this IOMMU
400 */
Joerg Roedel3e8064b2008-06-26 21:27:41 +0200401static int __init find_last_devid_on_pci(int bus, int dev, int fn, int cap_ptr)
402{
403 u32 cap;
404
405 cap = read_pci_config(bus, dev, fn, cap_ptr+MMIO_RANGE_OFFSET);
Joerg Roedeld591b0a2008-07-11 17:14:35 +0200406 update_last_devid(calc_devid(MMIO_GET_BUS(cap), MMIO_GET_LD(cap)));
Joerg Roedel3e8064b2008-06-26 21:27:41 +0200407
408 return 0;
409}
410
Joerg Roedelb65233a2008-07-11 17:14:21 +0200411/*
412 * After reading the highest device id from the IOMMU PCI capability header
413 * this function looks if there is a higher device id defined in the ACPI table
414 */
Joerg Roedel3e8064b2008-06-26 21:27:41 +0200415static int __init find_last_devid_from_ivhd(struct ivhd_header *h)
416{
417 u8 *p = (void *)h, *end = (void *)h;
418 struct ivhd_entry *dev;
419
420 p += sizeof(*h);
421 end += h->length;
422
423 find_last_devid_on_pci(PCI_BUS(h->devid),
424 PCI_SLOT(h->devid),
425 PCI_FUNC(h->devid),
426 h->cap_ptr);
427
428 while (p < end) {
429 dev = (struct ivhd_entry *)p;
430 switch (dev->type) {
431 case IVHD_DEV_SELECT:
432 case IVHD_DEV_RANGE_END:
433 case IVHD_DEV_ALIAS:
434 case IVHD_DEV_EXT_SELECT:
Joerg Roedelb65233a2008-07-11 17:14:21 +0200435 /* all the above subfield types refer to device ids */
Joerg Roedel208ec8c2008-07-11 17:14:24 +0200436 update_last_devid(dev->devid);
Joerg Roedel3e8064b2008-06-26 21:27:41 +0200437 break;
438 default:
439 break;
440 }
Joerg Roedelb514e552008-09-17 17:14:27 +0200441 p += ivhd_entry_length(p);
Joerg Roedel3e8064b2008-06-26 21:27:41 +0200442 }
443
444 WARN_ON(p != end);
445
446 return 0;
447}
448
Joerg Roedelb65233a2008-07-11 17:14:21 +0200449/*
450 * Iterate over all IVHD entries in the ACPI table and find the highest device
451 * id which we need to handle. This is the first of three functions which parse
452 * the ACPI table. So we check the checksum here.
453 */
Joerg Roedel3e8064b2008-06-26 21:27:41 +0200454static int __init find_last_devid_acpi(struct acpi_table_header *table)
455{
456 int i;
457 u8 checksum = 0, *p = (u8 *)table, *end = (u8 *)table;
458 struct ivhd_header *h;
459
460 /*
461 * Validate checksum here so we don't need to do it when
462 * we actually parse the table
463 */
464 for (i = 0; i < table->length; ++i)
465 checksum += p[i];
Joerg Roedel3551a702010-03-01 13:52:19 +0100466 if (checksum != 0) {
Joerg Roedel3e8064b2008-06-26 21:27:41 +0200467 /* ACPI table corrupt */
Joerg Roedel3551a702010-03-01 13:52:19 +0100468 amd_iommu_init_err = -ENODEV;
469 return 0;
470 }
Joerg Roedel3e8064b2008-06-26 21:27:41 +0200471
472 p += IVRS_HEADER_LENGTH;
473
474 end += table->length;
475 while (p < end) {
476 h = (struct ivhd_header *)p;
477 switch (h->type) {
478 case ACPI_IVHD_TYPE:
479 find_last_devid_from_ivhd(h);
480 break;
481 default:
482 break;
483 }
484 p += h->length;
485 }
486 WARN_ON(p != end);
487
488 return 0;
489}
490
Joerg Roedelb65233a2008-07-11 17:14:21 +0200491/****************************************************************************
492 *
493 * The following functions belong the the code path which parses the ACPI table
494 * the second time. In this ACPI parsing iteration we allocate IOMMU specific
495 * data structures, initialize the device/alias/rlookup table and also
496 * basically initialize the hardware.
497 *
498 ****************************************************************************/
499
500/*
501 * Allocates the command buffer. This buffer is per AMD IOMMU. We can
502 * write commands to that buffer later and the IOMMU will execute them
503 * asynchronously
504 */
Joerg Roedelb36ca912008-06-26 21:27:45 +0200505static u8 * __init alloc_command_buffer(struct amd_iommu *iommu)
506{
Joerg Roedeld0312b22008-07-11 17:14:29 +0200507 u8 *cmd_buf = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
Joerg Roedelb36ca912008-06-26 21:27:45 +0200508 get_order(CMD_BUFFER_SIZE));
Joerg Roedelb36ca912008-06-26 21:27:45 +0200509
510 if (cmd_buf == NULL)
511 return NULL;
512
Chris Wright549c90d2010-04-02 18:27:53 -0700513 iommu->cmd_buf_size = CMD_BUFFER_SIZE | CMD_BUFFER_UNINITIALIZED;
Joerg Roedelb36ca912008-06-26 21:27:45 +0200514
Joerg Roedel58492e12009-05-04 18:41:16 +0200515 return cmd_buf;
516}
517
518/*
Joerg Roedel93f1cc672009-09-03 14:50:20 +0200519 * This function resets the command buffer if the IOMMU stopped fetching
520 * commands from it.
521 */
522void amd_iommu_reset_cmd_buffer(struct amd_iommu *iommu)
523{
524 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN);
525
526 writel(0x00, iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
527 writel(0x00, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
528
529 iommu_feature_enable(iommu, CONTROL_CMDBUF_EN);
530}
531
532/*
Joerg Roedel58492e12009-05-04 18:41:16 +0200533 * This function writes the command buffer address to the hardware and
534 * enables it.
535 */
536static void iommu_enable_command_buffer(struct amd_iommu *iommu)
537{
538 u64 entry;
539
540 BUG_ON(iommu->cmd_buf == NULL);
541
542 entry = (u64)virt_to_phys(iommu->cmd_buf);
Joerg Roedelb36ca912008-06-26 21:27:45 +0200543 entry |= MMIO_CMD_SIZE_512;
Joerg Roedel58492e12009-05-04 18:41:16 +0200544
Joerg Roedelb36ca912008-06-26 21:27:45 +0200545 memcpy_toio(iommu->mmio_base + MMIO_CMD_BUF_OFFSET,
Joerg Roedel58492e12009-05-04 18:41:16 +0200546 &entry, sizeof(entry));
Joerg Roedelb36ca912008-06-26 21:27:45 +0200547
Joerg Roedel93f1cc672009-09-03 14:50:20 +0200548 amd_iommu_reset_cmd_buffer(iommu);
Chris Wright549c90d2010-04-02 18:27:53 -0700549 iommu->cmd_buf_size &= ~(CMD_BUFFER_UNINITIALIZED);
Joerg Roedelb36ca912008-06-26 21:27:45 +0200550}
551
552static void __init free_command_buffer(struct amd_iommu *iommu)
553{
Joerg Roedel23c17132008-09-17 17:18:17 +0200554 free_pages((unsigned long)iommu->cmd_buf,
Chris Wright549c90d2010-04-02 18:27:53 -0700555 get_order(iommu->cmd_buf_size & ~(CMD_BUFFER_UNINITIALIZED)));
Joerg Roedelb36ca912008-06-26 21:27:45 +0200556}
557
Joerg Roedel335503e2008-09-05 14:29:07 +0200558/* allocates the memory where the IOMMU will log its events to */
559static u8 * __init alloc_event_buffer(struct amd_iommu *iommu)
560{
Joerg Roedel335503e2008-09-05 14:29:07 +0200561 iommu->evt_buf = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
562 get_order(EVT_BUFFER_SIZE));
563
564 if (iommu->evt_buf == NULL)
565 return NULL;
566
Joerg Roedel1bc6f832009-07-02 18:32:05 +0200567 iommu->evt_buf_size = EVT_BUFFER_SIZE;
568
Joerg Roedel58492e12009-05-04 18:41:16 +0200569 return iommu->evt_buf;
570}
571
572static void iommu_enable_event_buffer(struct amd_iommu *iommu)
573{
574 u64 entry;
575
576 BUG_ON(iommu->evt_buf == NULL);
577
Joerg Roedel335503e2008-09-05 14:29:07 +0200578 entry = (u64)virt_to_phys(iommu->evt_buf) | EVT_LEN_MASK;
Joerg Roedel58492e12009-05-04 18:41:16 +0200579
Joerg Roedel335503e2008-09-05 14:29:07 +0200580 memcpy_toio(iommu->mmio_base + MMIO_EVT_BUF_OFFSET,
581 &entry, sizeof(entry));
582
Joerg Roedel090672072009-06-15 16:06:48 +0200583 /* set head and tail to zero manually */
584 writel(0x00, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
585 writel(0x00, iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
586
Joerg Roedel58492e12009-05-04 18:41:16 +0200587 iommu_feature_enable(iommu, CONTROL_EVT_LOG_EN);
Joerg Roedel335503e2008-09-05 14:29:07 +0200588}
589
590static void __init free_event_buffer(struct amd_iommu *iommu)
591{
592 free_pages((unsigned long)iommu->evt_buf, get_order(EVT_BUFFER_SIZE));
593}
594
Joerg Roedel1a29ac02011-11-10 15:41:40 +0100595/* allocates the memory where the IOMMU will log its events to */
596static u8 * __init alloc_ppr_log(struct amd_iommu *iommu)
597{
598 iommu->ppr_log = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
599 get_order(PPR_LOG_SIZE));
600
601 if (iommu->ppr_log == NULL)
602 return NULL;
603
604 return iommu->ppr_log;
605}
606
607static void iommu_enable_ppr_log(struct amd_iommu *iommu)
608{
609 u64 entry;
610
611 if (iommu->ppr_log == NULL)
612 return;
613
614 entry = (u64)virt_to_phys(iommu->ppr_log) | PPR_LOG_SIZE_512;
615
616 memcpy_toio(iommu->mmio_base + MMIO_PPR_LOG_OFFSET,
617 &entry, sizeof(entry));
618
619 /* set head and tail to zero manually */
620 writel(0x00, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
621 writel(0x00, iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
622
623 iommu_feature_enable(iommu, CONTROL_PPFLOG_EN);
624 iommu_feature_enable(iommu, CONTROL_PPR_EN);
625}
626
627static void __init free_ppr_log(struct amd_iommu *iommu)
628{
629 if (iommu->ppr_log == NULL)
630 return;
631
632 free_pages((unsigned long)iommu->ppr_log, get_order(PPR_LOG_SIZE));
633}
634
Joerg Roedelcbc33a92011-11-25 11:41:31 +0100635static void iommu_enable_gt(struct amd_iommu *iommu)
636{
637 if (!iommu_feature(iommu, FEATURE_GT))
638 return;
639
640 iommu_feature_enable(iommu, CONTROL_GT_EN);
641}
642
Joerg Roedelb65233a2008-07-11 17:14:21 +0200643/* sets a specific bit in the device table entry. */
Joerg Roedel3566b772008-06-26 21:27:46 +0200644static void set_dev_entry_bit(u16 devid, u8 bit)
645{
Joerg Roedelee6c2862011-11-09 12:06:03 +0100646 int i = (bit >> 6) & 0x03;
647 int _bit = bit & 0x3f;
Joerg Roedel3566b772008-06-26 21:27:46 +0200648
Joerg Roedelee6c2862011-11-09 12:06:03 +0100649 amd_iommu_dev_table[devid].data[i] |= (1UL << _bit);
Joerg Roedel3566b772008-06-26 21:27:46 +0200650}
651
Joerg Roedelc5cca142009-10-09 18:31:20 +0200652static int get_dev_entry_bit(u16 devid, u8 bit)
653{
Joerg Roedelee6c2862011-11-09 12:06:03 +0100654 int i = (bit >> 6) & 0x03;
655 int _bit = bit & 0x3f;
Joerg Roedelc5cca142009-10-09 18:31:20 +0200656
Joerg Roedelee6c2862011-11-09 12:06:03 +0100657 return (amd_iommu_dev_table[devid].data[i] & (1UL << _bit)) >> _bit;
Joerg Roedelc5cca142009-10-09 18:31:20 +0200658}
659
660
661void amd_iommu_apply_erratum_63(u16 devid)
662{
663 int sysmgt;
664
665 sysmgt = get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1) |
666 (get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2) << 1);
667
668 if (sysmgt == 0x01)
669 set_dev_entry_bit(devid, DEV_ENTRY_IW);
670}
671
Joerg Roedel5ff47892008-07-14 20:11:18 +0200672/* Writes the specific IOMMU for a device into the rlookup table */
673static void __init set_iommu_for_device(struct amd_iommu *iommu, u16 devid)
674{
675 amd_iommu_rlookup_table[devid] = iommu;
676}
677
Joerg Roedelb65233a2008-07-11 17:14:21 +0200678/*
679 * This function takes the device specific flags read from the ACPI
680 * table and sets up the device table entry with that information
681 */
Joerg Roedel5ff47892008-07-14 20:11:18 +0200682static void __init set_dev_entry_from_acpi(struct amd_iommu *iommu,
683 u16 devid, u32 flags, u32 ext_flags)
Joerg Roedel3566b772008-06-26 21:27:46 +0200684{
685 if (flags & ACPI_DEVFLAG_INITPASS)
686 set_dev_entry_bit(devid, DEV_ENTRY_INIT_PASS);
687 if (flags & ACPI_DEVFLAG_EXTINT)
688 set_dev_entry_bit(devid, DEV_ENTRY_EINT_PASS);
689 if (flags & ACPI_DEVFLAG_NMI)
690 set_dev_entry_bit(devid, DEV_ENTRY_NMI_PASS);
691 if (flags & ACPI_DEVFLAG_SYSMGT1)
692 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1);
693 if (flags & ACPI_DEVFLAG_SYSMGT2)
694 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2);
695 if (flags & ACPI_DEVFLAG_LINT0)
696 set_dev_entry_bit(devid, DEV_ENTRY_LINT0_PASS);
697 if (flags & ACPI_DEVFLAG_LINT1)
698 set_dev_entry_bit(devid, DEV_ENTRY_LINT1_PASS);
Joerg Roedel3566b772008-06-26 21:27:46 +0200699
Joerg Roedelc5cca142009-10-09 18:31:20 +0200700 amd_iommu_apply_erratum_63(devid);
701
Joerg Roedel5ff47892008-07-14 20:11:18 +0200702 set_iommu_for_device(iommu, devid);
Joerg Roedel3566b772008-06-26 21:27:46 +0200703}
704
Joerg Roedelb65233a2008-07-11 17:14:21 +0200705/*
706 * Reads the device exclusion range from ACPI and initialize IOMMU with
707 * it
708 */
Joerg Roedel3566b772008-06-26 21:27:46 +0200709static void __init set_device_exclusion_range(u16 devid, struct ivmd_header *m)
710{
711 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
712
713 if (!(m->flags & IVMD_FLAG_EXCL_RANGE))
714 return;
715
716 if (iommu) {
Joerg Roedelb65233a2008-07-11 17:14:21 +0200717 /*
718 * We only can configure exclusion ranges per IOMMU, not
719 * per device. But we can enable the exclusion range per
720 * device. This is done here
721 */
Joerg Roedel3566b772008-06-26 21:27:46 +0200722 set_dev_entry_bit(m->devid, DEV_ENTRY_EX);
723 iommu->exclusion_start = m->range_start;
724 iommu->exclusion_length = m->range_length;
725 }
726}
727
Joerg Roedelb65233a2008-07-11 17:14:21 +0200728/*
729 * This function reads some important data from the IOMMU PCI space and
730 * initializes the driver data structure with it. It reads the hardware
731 * capabilities and the first/last device entries
732 */
Joerg Roedel5d0c8e42008-06-26 21:27:47 +0200733static void __init init_iommu_from_pci(struct amd_iommu *iommu)
734{
Joerg Roedel5d0c8e42008-06-26 21:27:47 +0200735 int cap_ptr = iommu->cap_ptr;
Joerg Roedeld99ddec2011-04-11 11:03:18 +0200736 u32 range, misc, low, high;
Matthew Garrett5bcd7572010-10-04 14:59:31 -0400737 int i, j;
Joerg Roedel5d0c8e42008-06-26 21:27:47 +0200738
Joerg Roedel3eaf28a2008-09-08 15:55:10 +0200739 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_CAP_HDR_OFFSET,
740 &iommu->cap);
741 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_RANGE_OFFSET,
742 &range);
Joerg Roedela80dc3e2008-09-11 16:51:41 +0200743 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_MISC_OFFSET,
744 &misc);
Joerg Roedel5d0c8e42008-06-26 21:27:47 +0200745
Joerg Roedeld591b0a2008-07-11 17:14:35 +0200746 iommu->first_device = calc_devid(MMIO_GET_BUS(range),
747 MMIO_GET_FD(range));
748 iommu->last_device = calc_devid(MMIO_GET_BUS(range),
749 MMIO_GET_LD(range));
Joerg Roedela80dc3e2008-09-11 16:51:41 +0200750 iommu->evt_msi_num = MMIO_MSI_NUM(misc);
Joerg Roedel4c894f42010-09-23 15:15:19 +0200751
Joerg Roedel60f723b2011-04-05 12:50:24 +0200752 if (!(iommu->cap & (1 << IOMMU_CAP_IOTLB)))
753 amd_iommu_iotlb_sup = false;
754
Joerg Roedeld99ddec2011-04-11 11:03:18 +0200755 /* read extended feature bits */
756 low = readl(iommu->mmio_base + MMIO_EXT_FEATURES);
757 high = readl(iommu->mmio_base + MMIO_EXT_FEATURES + 4);
758
759 iommu->features = ((u64)high << 32) | low;
760
Joerg Roedel62f71ab2011-11-10 14:41:57 +0100761 if (iommu_feature(iommu, FEATURE_GT)) {
Joerg Roedel52815b72011-11-17 17:24:28 +0100762 int glxval;
Joerg Roedel62f71ab2011-11-10 14:41:57 +0100763 u32 pasids;
764 u64 shift;
765
766 shift = iommu->features & FEATURE_PASID_MASK;
767 shift >>= FEATURE_PASID_SHIFT;
768 pasids = (1 << shift);
769
770 amd_iommu_max_pasids = min(amd_iommu_max_pasids, pasids);
Joerg Roedel52815b72011-11-17 17:24:28 +0100771
772 glxval = iommu->features & FEATURE_GLXVAL_MASK;
773 glxval >>= FEATURE_GLXVAL_SHIFT;
774
775 if (amd_iommu_max_glx_val == -1)
776 amd_iommu_max_glx_val = glxval;
777 else
778 amd_iommu_max_glx_val = min(amd_iommu_max_glx_val, glxval);
Joerg Roedel62f71ab2011-11-10 14:41:57 +0100779 }
780
Joerg Roedel400a28a2011-11-28 15:11:02 +0100781 if (iommu_feature(iommu, FEATURE_GT) &&
782 iommu_feature(iommu, FEATURE_PPR)) {
783 iommu->is_iommu_v2 = true;
784 amd_iommu_v2_present = true;
785 }
786
Matthew Garrett5bcd7572010-10-04 14:59:31 -0400787 if (!is_rd890_iommu(iommu->dev))
788 return;
789
790 /*
791 * Some rd890 systems may not be fully reconfigured by the BIOS, so
792 * it's necessary for us to store this information so it can be
793 * reprogrammed on resume
794 */
795
796 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 4,
797 &iommu->stored_addr_lo);
798 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 8,
799 &iommu->stored_addr_hi);
800
801 /* Low bit locks writes to configuration space */
802 iommu->stored_addr_lo &= ~1;
803
804 for (i = 0; i < 6; i++)
805 for (j = 0; j < 0x12; j++)
806 iommu->stored_l1[i][j] = iommu_read_l1(iommu, i, j);
807
808 for (i = 0; i < 0x83; i++)
809 iommu->stored_l2[i] = iommu_read_l2(iommu, i);
Joerg Roedel5d0c8e42008-06-26 21:27:47 +0200810}
811
Joerg Roedelb65233a2008-07-11 17:14:21 +0200812/*
813 * Takes a pointer to an AMD IOMMU entry in the ACPI table and
814 * initializes the hardware and our data structures with it.
815 */
Joerg Roedel5d0c8e42008-06-26 21:27:47 +0200816static void __init init_iommu_from_acpi(struct amd_iommu *iommu,
817 struct ivhd_header *h)
818{
819 u8 *p = (u8 *)h;
820 u8 *end = p, flags = 0;
Joerg Roedel0de66d52011-06-06 16:04:02 +0200821 u16 devid = 0, devid_start = 0, devid_to = 0;
822 u32 dev_i, ext_flags = 0;
Joerg Roedel58a3bee2008-07-11 17:14:30 +0200823 bool alias = false;
Joerg Roedel5d0c8e42008-06-26 21:27:47 +0200824 struct ivhd_entry *e;
825
826 /*
Joerg Roedele9bf5192010-09-20 14:33:07 +0200827 * First save the recommended feature enable bits from ACPI
Joerg Roedel5d0c8e42008-06-26 21:27:47 +0200828 */
Joerg Roedele9bf5192010-09-20 14:33:07 +0200829 iommu->acpi_flags = h->flags;
Joerg Roedel5d0c8e42008-06-26 21:27:47 +0200830
831 /*
832 * Done. Now parse the device entries
833 */
834 p += sizeof(struct ivhd_header);
835 end += h->length;
836
Joerg Roedel42a698f2009-05-20 15:41:28 +0200837
Joerg Roedel5d0c8e42008-06-26 21:27:47 +0200838 while (p < end) {
839 e = (struct ivhd_entry *)p;
840 switch (e->type) {
841 case IVHD_DEV_ALL:
Joerg Roedel42a698f2009-05-20 15:41:28 +0200842
843 DUMP_printk(" DEV_ALL\t\t\t first devid: %02x:%02x.%x"
844 " last device %02x:%02x.%x flags: %02x\n",
845 PCI_BUS(iommu->first_device),
846 PCI_SLOT(iommu->first_device),
847 PCI_FUNC(iommu->first_device),
848 PCI_BUS(iommu->last_device),
849 PCI_SLOT(iommu->last_device),
850 PCI_FUNC(iommu->last_device),
851 e->flags);
852
Joerg Roedel5d0c8e42008-06-26 21:27:47 +0200853 for (dev_i = iommu->first_device;
854 dev_i <= iommu->last_device; ++dev_i)
Joerg Roedel5ff47892008-07-14 20:11:18 +0200855 set_dev_entry_from_acpi(iommu, dev_i,
856 e->flags, 0);
Joerg Roedel5d0c8e42008-06-26 21:27:47 +0200857 break;
858 case IVHD_DEV_SELECT:
Joerg Roedel42a698f2009-05-20 15:41:28 +0200859
860 DUMP_printk(" DEV_SELECT\t\t\t devid: %02x:%02x.%x "
861 "flags: %02x\n",
862 PCI_BUS(e->devid),
863 PCI_SLOT(e->devid),
864 PCI_FUNC(e->devid),
865 e->flags);
866
Joerg Roedel5d0c8e42008-06-26 21:27:47 +0200867 devid = e->devid;
Joerg Roedel5ff47892008-07-14 20:11:18 +0200868 set_dev_entry_from_acpi(iommu, devid, e->flags, 0);
Joerg Roedel5d0c8e42008-06-26 21:27:47 +0200869 break;
870 case IVHD_DEV_SELECT_RANGE_START:
Joerg Roedel42a698f2009-05-20 15:41:28 +0200871
872 DUMP_printk(" DEV_SELECT_RANGE_START\t "
873 "devid: %02x:%02x.%x flags: %02x\n",
874 PCI_BUS(e->devid),
875 PCI_SLOT(e->devid),
876 PCI_FUNC(e->devid),
877 e->flags);
878
Joerg Roedel5d0c8e42008-06-26 21:27:47 +0200879 devid_start = e->devid;
880 flags = e->flags;
881 ext_flags = 0;
Joerg Roedel58a3bee2008-07-11 17:14:30 +0200882 alias = false;
Joerg Roedel5d0c8e42008-06-26 21:27:47 +0200883 break;
884 case IVHD_DEV_ALIAS:
Joerg Roedel42a698f2009-05-20 15:41:28 +0200885
886 DUMP_printk(" DEV_ALIAS\t\t\t devid: %02x:%02x.%x "
887 "flags: %02x devid_to: %02x:%02x.%x\n",
888 PCI_BUS(e->devid),
889 PCI_SLOT(e->devid),
890 PCI_FUNC(e->devid),
891 e->flags,
892 PCI_BUS(e->ext >> 8),
893 PCI_SLOT(e->ext >> 8),
894 PCI_FUNC(e->ext >> 8));
895
Joerg Roedel5d0c8e42008-06-26 21:27:47 +0200896 devid = e->devid;
897 devid_to = e->ext >> 8;
Joerg Roedel7a6a3a02009-07-02 12:23:23 +0200898 set_dev_entry_from_acpi(iommu, devid , e->flags, 0);
Neil Turton7455aab2009-05-14 14:08:11 +0100899 set_dev_entry_from_acpi(iommu, devid_to, e->flags, 0);
Joerg Roedel5d0c8e42008-06-26 21:27:47 +0200900 amd_iommu_alias_table[devid] = devid_to;
901 break;
902 case IVHD_DEV_ALIAS_RANGE:
Joerg Roedel42a698f2009-05-20 15:41:28 +0200903
904 DUMP_printk(" DEV_ALIAS_RANGE\t\t "
905 "devid: %02x:%02x.%x flags: %02x "
906 "devid_to: %02x:%02x.%x\n",
907 PCI_BUS(e->devid),
908 PCI_SLOT(e->devid),
909 PCI_FUNC(e->devid),
910 e->flags,
911 PCI_BUS(e->ext >> 8),
912 PCI_SLOT(e->ext >> 8),
913 PCI_FUNC(e->ext >> 8));
914
Joerg Roedel5d0c8e42008-06-26 21:27:47 +0200915 devid_start = e->devid;
916 flags = e->flags;
917 devid_to = e->ext >> 8;
918 ext_flags = 0;
Joerg Roedel58a3bee2008-07-11 17:14:30 +0200919 alias = true;
Joerg Roedel5d0c8e42008-06-26 21:27:47 +0200920 break;
921 case IVHD_DEV_EXT_SELECT:
Joerg Roedel42a698f2009-05-20 15:41:28 +0200922
923 DUMP_printk(" DEV_EXT_SELECT\t\t devid: %02x:%02x.%x "
924 "flags: %02x ext: %08x\n",
925 PCI_BUS(e->devid),
926 PCI_SLOT(e->devid),
927 PCI_FUNC(e->devid),
928 e->flags, e->ext);
929
Joerg Roedel5d0c8e42008-06-26 21:27:47 +0200930 devid = e->devid;
Joerg Roedel5ff47892008-07-14 20:11:18 +0200931 set_dev_entry_from_acpi(iommu, devid, e->flags,
932 e->ext);
Joerg Roedel5d0c8e42008-06-26 21:27:47 +0200933 break;
934 case IVHD_DEV_EXT_SELECT_RANGE:
Joerg Roedel42a698f2009-05-20 15:41:28 +0200935
936 DUMP_printk(" DEV_EXT_SELECT_RANGE\t devid: "
937 "%02x:%02x.%x flags: %02x ext: %08x\n",
938 PCI_BUS(e->devid),
939 PCI_SLOT(e->devid),
940 PCI_FUNC(e->devid),
941 e->flags, e->ext);
942
Joerg Roedel5d0c8e42008-06-26 21:27:47 +0200943 devid_start = e->devid;
944 flags = e->flags;
945 ext_flags = e->ext;
Joerg Roedel58a3bee2008-07-11 17:14:30 +0200946 alias = false;
Joerg Roedel5d0c8e42008-06-26 21:27:47 +0200947 break;
948 case IVHD_DEV_RANGE_END:
Joerg Roedel42a698f2009-05-20 15:41:28 +0200949
950 DUMP_printk(" DEV_RANGE_END\t\t devid: %02x:%02x.%x\n",
951 PCI_BUS(e->devid),
952 PCI_SLOT(e->devid),
953 PCI_FUNC(e->devid));
954
Joerg Roedel5d0c8e42008-06-26 21:27:47 +0200955 devid = e->devid;
956 for (dev_i = devid_start; dev_i <= devid; ++dev_i) {
Joerg Roedel7a6a3a02009-07-02 12:23:23 +0200957 if (alias) {
Joerg Roedel5d0c8e42008-06-26 21:27:47 +0200958 amd_iommu_alias_table[dev_i] = devid_to;
Joerg Roedel7a6a3a02009-07-02 12:23:23 +0200959 set_dev_entry_from_acpi(iommu,
960 devid_to, flags, ext_flags);
961 }
962 set_dev_entry_from_acpi(iommu, dev_i,
963 flags, ext_flags);
Joerg Roedel5d0c8e42008-06-26 21:27:47 +0200964 }
965 break;
966 default:
967 break;
968 }
969
Joerg Roedelb514e552008-09-17 17:14:27 +0200970 p += ivhd_entry_length(p);
Joerg Roedel5d0c8e42008-06-26 21:27:47 +0200971 }
972}
973
Joerg Roedelb65233a2008-07-11 17:14:21 +0200974/* Initializes the device->iommu mapping for the driver */
Joerg Roedel5d0c8e42008-06-26 21:27:47 +0200975static int __init init_iommu_devices(struct amd_iommu *iommu)
976{
Joerg Roedel0de66d52011-06-06 16:04:02 +0200977 u32 i;
Joerg Roedel5d0c8e42008-06-26 21:27:47 +0200978
979 for (i = iommu->first_device; i <= iommu->last_device; ++i)
980 set_iommu_for_device(iommu, i);
981
982 return 0;
983}
984
Joerg Roedele47d4022008-06-26 21:27:48 +0200985static void __init free_iommu_one(struct amd_iommu *iommu)
986{
987 free_command_buffer(iommu);
Joerg Roedel335503e2008-09-05 14:29:07 +0200988 free_event_buffer(iommu);
Joerg Roedel1a29ac02011-11-10 15:41:40 +0100989 free_ppr_log(iommu);
Joerg Roedele47d4022008-06-26 21:27:48 +0200990 iommu_unmap_mmio_space(iommu);
991}
992
993static void __init free_iommu_all(void)
994{
995 struct amd_iommu *iommu, *next;
996
Joerg Roedel3bd22172009-05-04 15:06:20 +0200997 for_each_iommu_safe(iommu, next) {
Joerg Roedele47d4022008-06-26 21:27:48 +0200998 list_del(&iommu->list);
999 free_iommu_one(iommu);
1000 kfree(iommu);
1001 }
1002}
1003
Joerg Roedelb65233a2008-07-11 17:14:21 +02001004/*
1005 * This function clues the initialization function for one IOMMU
1006 * together and also allocates the command buffer and programs the
1007 * hardware. It does NOT enable the IOMMU. This is done afterwards.
1008 */
Joerg Roedele47d4022008-06-26 21:27:48 +02001009static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h)
1010{
1011 spin_lock_init(&iommu->lock);
Joerg Roedelbb527772009-11-20 14:31:51 +01001012
1013 /* Add IOMMU to internal data structures */
Joerg Roedele47d4022008-06-26 21:27:48 +02001014 list_add_tail(&iommu->list, &amd_iommu_list);
Joerg Roedelbb527772009-11-20 14:31:51 +01001015 iommu->index = amd_iommus_present++;
1016
1017 if (unlikely(iommu->index >= MAX_IOMMUS)) {
1018 WARN(1, "AMD-Vi: System has more IOMMUs than supported by this driver\n");
1019 return -ENOSYS;
1020 }
1021
1022 /* Index is fine - add IOMMU to the array */
1023 amd_iommus[iommu->index] = iommu;
Joerg Roedele47d4022008-06-26 21:27:48 +02001024
1025 /*
1026 * Copy data from ACPI table entry to the iommu struct
1027 */
Joerg Roedel3eaf28a2008-09-08 15:55:10 +02001028 iommu->dev = pci_get_bus_and_slot(PCI_BUS(h->devid), h->devid & 0xff);
1029 if (!iommu->dev)
1030 return 1;
1031
Joerg Roedele47d4022008-06-26 21:27:48 +02001032 iommu->cap_ptr = h->cap_ptr;
Joerg Roedelee893c22008-09-08 14:48:04 +02001033 iommu->pci_seg = h->pci_seg;
Joerg Roedele47d4022008-06-26 21:27:48 +02001034 iommu->mmio_phys = h->mmio_phys;
1035 iommu->mmio_base = iommu_map_mmio_space(h->mmio_phys);
1036 if (!iommu->mmio_base)
1037 return -ENOMEM;
1038
Joerg Roedele47d4022008-06-26 21:27:48 +02001039 iommu->cmd_buf = alloc_command_buffer(iommu);
1040 if (!iommu->cmd_buf)
1041 return -ENOMEM;
1042
Joerg Roedel335503e2008-09-05 14:29:07 +02001043 iommu->evt_buf = alloc_event_buffer(iommu);
1044 if (!iommu->evt_buf)
1045 return -ENOMEM;
1046
Joerg Roedela80dc3e2008-09-11 16:51:41 +02001047 iommu->int_enabled = false;
1048
Joerg Roedele47d4022008-06-26 21:27:48 +02001049 init_iommu_from_pci(iommu);
1050 init_iommu_from_acpi(iommu, h);
1051 init_iommu_devices(iommu);
1052
Joerg Roedel1a29ac02011-11-10 15:41:40 +01001053 if (iommu_feature(iommu, FEATURE_PPR)) {
1054 iommu->ppr_log = alloc_ppr_log(iommu);
1055 if (!iommu->ppr_log)
1056 return -ENOMEM;
1057 }
1058
Joerg Roedel318afd42009-11-23 18:32:38 +01001059 if (iommu->cap & (1UL << IOMMU_CAP_NPCACHE))
1060 amd_iommu_np_cache = true;
1061
Ingo Molnar8a667122008-10-12 15:24:53 +02001062 return pci_enable_device(iommu->dev);
Joerg Roedele47d4022008-06-26 21:27:48 +02001063}
1064
Joerg Roedelb65233a2008-07-11 17:14:21 +02001065/*
1066 * Iterates over all IOMMU entries in the ACPI table, allocates the
1067 * IOMMU structure and initializes it with init_iommu_one()
1068 */
Joerg Roedele47d4022008-06-26 21:27:48 +02001069static int __init init_iommu_all(struct acpi_table_header *table)
1070{
1071 u8 *p = (u8 *)table, *end = (u8 *)table;
1072 struct ivhd_header *h;
1073 struct amd_iommu *iommu;
1074 int ret;
1075
Joerg Roedele47d4022008-06-26 21:27:48 +02001076 end += table->length;
1077 p += IVRS_HEADER_LENGTH;
1078
1079 while (p < end) {
1080 h = (struct ivhd_header *)p;
1081 switch (*p) {
1082 case ACPI_IVHD_TYPE:
Joerg Roedel9c720412009-05-20 13:53:57 +02001083
Joerg Roedelae908c22009-09-01 16:52:16 +02001084 DUMP_printk("device: %02x:%02x.%01x cap: %04x "
Joerg Roedel9c720412009-05-20 13:53:57 +02001085 "seg: %d flags: %01x info %04x\n",
1086 PCI_BUS(h->devid), PCI_SLOT(h->devid),
1087 PCI_FUNC(h->devid), h->cap_ptr,
1088 h->pci_seg, h->flags, h->info);
1089 DUMP_printk(" mmio-addr: %016llx\n",
1090 h->mmio_phys);
1091
Joerg Roedele47d4022008-06-26 21:27:48 +02001092 iommu = kzalloc(sizeof(struct amd_iommu), GFP_KERNEL);
Joerg Roedel3551a702010-03-01 13:52:19 +01001093 if (iommu == NULL) {
1094 amd_iommu_init_err = -ENOMEM;
1095 return 0;
1096 }
1097
Joerg Roedele47d4022008-06-26 21:27:48 +02001098 ret = init_iommu_one(iommu, h);
Joerg Roedel3551a702010-03-01 13:52:19 +01001099 if (ret) {
1100 amd_iommu_init_err = ret;
1101 return 0;
1102 }
Joerg Roedele47d4022008-06-26 21:27:48 +02001103 break;
1104 default:
1105 break;
1106 }
1107 p += h->length;
1108
1109 }
1110 WARN_ON(p != end);
1111
1112 return 0;
1113}
1114
Joerg Roedelb65233a2008-07-11 17:14:21 +02001115/****************************************************************************
1116 *
Joerg Roedela80dc3e2008-09-11 16:51:41 +02001117 * The following functions initialize the MSI interrupts for all IOMMUs
1118 * in the system. Its a bit challenging because there could be multiple
1119 * IOMMUs per PCI BDF but we can call pci_enable_msi(x) only once per
1120 * pci_dev.
1121 *
1122 ****************************************************************************/
1123
Joerg Roedel9f800de2009-11-23 12:45:25 +01001124static int iommu_setup_msi(struct amd_iommu *iommu)
Joerg Roedela80dc3e2008-09-11 16:51:41 +02001125{
1126 int r;
Joerg Roedela80dc3e2008-09-11 16:51:41 +02001127
Joerg Roedel9ddd5922012-03-15 16:29:47 +01001128 r = pci_enable_msi(iommu->dev);
1129 if (r)
1130 return r;
Joerg Roedela80dc3e2008-09-11 16:51:41 +02001131
Joerg Roedel72fe00f2011-05-10 10:50:42 +02001132 r = request_threaded_irq(iommu->dev->irq,
1133 amd_iommu_int_handler,
1134 amd_iommu_int_thread,
1135 0, "AMD-Vi",
1136 iommu->dev);
Joerg Roedela80dc3e2008-09-11 16:51:41 +02001137
1138 if (r) {
1139 pci_disable_msi(iommu->dev);
Joerg Roedel9ddd5922012-03-15 16:29:47 +01001140 return r;
Joerg Roedela80dc3e2008-09-11 16:51:41 +02001141 }
1142
Joerg Roedelfab6afa2009-05-04 18:46:34 +02001143 iommu->int_enabled = true;
Joerg Roedel1a29ac02011-11-10 15:41:40 +01001144
Joerg Roedela80dc3e2008-09-11 16:51:41 +02001145 return 0;
1146}
1147
Joerg Roedel05f92db2009-05-12 09:52:46 +02001148static int iommu_init_msi(struct amd_iommu *iommu)
Joerg Roedela80dc3e2008-09-11 16:51:41 +02001149{
Joerg Roedel9ddd5922012-03-15 16:29:47 +01001150 int ret;
1151
Joerg Roedela80dc3e2008-09-11 16:51:41 +02001152 if (iommu->int_enabled)
Joerg Roedel9ddd5922012-03-15 16:29:47 +01001153 goto enable_faults;
Joerg Roedela80dc3e2008-09-11 16:51:41 +02001154
Joerg Roedeld91cecd2009-05-04 18:51:00 +02001155 if (pci_find_capability(iommu->dev, PCI_CAP_ID_MSI))
Joerg Roedel9ddd5922012-03-15 16:29:47 +01001156 ret = iommu_setup_msi(iommu);
1157 else
1158 ret = -ENODEV;
Joerg Roedela80dc3e2008-09-11 16:51:41 +02001159
Joerg Roedel9ddd5922012-03-15 16:29:47 +01001160 if (ret)
1161 return ret;
1162
1163enable_faults:
1164 iommu_feature_enable(iommu, CONTROL_EVT_INT_EN);
1165
1166 if (iommu->ppr_log != NULL)
1167 iommu_feature_enable(iommu, CONTROL_PPFINT_EN);
1168
1169 return 0;
Joerg Roedela80dc3e2008-09-11 16:51:41 +02001170}
1171
1172/****************************************************************************
1173 *
Joerg Roedelb65233a2008-07-11 17:14:21 +02001174 * The next functions belong to the third pass of parsing the ACPI
1175 * table. In this last pass the memory mapping requirements are
1176 * gathered (like exclusion and unity mapping reanges).
1177 *
1178 ****************************************************************************/
1179
Joerg Roedelbe2a0222008-06-26 21:27:49 +02001180static void __init free_unity_maps(void)
1181{
1182 struct unity_map_entry *entry, *next;
1183
1184 list_for_each_entry_safe(entry, next, &amd_iommu_unity_map, list) {
1185 list_del(&entry->list);
1186 kfree(entry);
1187 }
1188}
1189
Joerg Roedelb65233a2008-07-11 17:14:21 +02001190/* called when we find an exclusion range definition in ACPI */
Joerg Roedelbe2a0222008-06-26 21:27:49 +02001191static int __init init_exclusion_range(struct ivmd_header *m)
1192{
1193 int i;
1194
1195 switch (m->type) {
1196 case ACPI_IVMD_TYPE:
1197 set_device_exclusion_range(m->devid, m);
1198 break;
1199 case ACPI_IVMD_TYPE_ALL:
Joerg Roedel3a61ec32008-07-25 13:07:50 +02001200 for (i = 0; i <= amd_iommu_last_bdf; ++i)
Joerg Roedelbe2a0222008-06-26 21:27:49 +02001201 set_device_exclusion_range(i, m);
1202 break;
1203 case ACPI_IVMD_TYPE_RANGE:
1204 for (i = m->devid; i <= m->aux; ++i)
1205 set_device_exclusion_range(i, m);
1206 break;
1207 default:
1208 break;
1209 }
1210
1211 return 0;
1212}
1213
Joerg Roedelb65233a2008-07-11 17:14:21 +02001214/* called for unity map ACPI definition */
Joerg Roedelbe2a0222008-06-26 21:27:49 +02001215static int __init init_unity_map_range(struct ivmd_header *m)
1216{
1217 struct unity_map_entry *e = 0;
Joerg Roedel02acc432009-05-20 16:24:21 +02001218 char *s;
Joerg Roedelbe2a0222008-06-26 21:27:49 +02001219
1220 e = kzalloc(sizeof(*e), GFP_KERNEL);
1221 if (e == NULL)
1222 return -ENOMEM;
1223
1224 switch (m->type) {
1225 default:
Joerg Roedel0bc252f2009-05-22 12:48:05 +02001226 kfree(e);
1227 return 0;
Joerg Roedelbe2a0222008-06-26 21:27:49 +02001228 case ACPI_IVMD_TYPE:
Joerg Roedel02acc432009-05-20 16:24:21 +02001229 s = "IVMD_TYPEi\t\t\t";
Joerg Roedelbe2a0222008-06-26 21:27:49 +02001230 e->devid_start = e->devid_end = m->devid;
1231 break;
1232 case ACPI_IVMD_TYPE_ALL:
Joerg Roedel02acc432009-05-20 16:24:21 +02001233 s = "IVMD_TYPE_ALL\t\t";
Joerg Roedelbe2a0222008-06-26 21:27:49 +02001234 e->devid_start = 0;
1235 e->devid_end = amd_iommu_last_bdf;
1236 break;
1237 case ACPI_IVMD_TYPE_RANGE:
Joerg Roedel02acc432009-05-20 16:24:21 +02001238 s = "IVMD_TYPE_RANGE\t\t";
Joerg Roedelbe2a0222008-06-26 21:27:49 +02001239 e->devid_start = m->devid;
1240 e->devid_end = m->aux;
1241 break;
1242 }
1243 e->address_start = PAGE_ALIGN(m->range_start);
1244 e->address_end = e->address_start + PAGE_ALIGN(m->range_length);
1245 e->prot = m->flags >> 1;
1246
Joerg Roedel02acc432009-05-20 16:24:21 +02001247 DUMP_printk("%s devid_start: %02x:%02x.%x devid_end: %02x:%02x.%x"
1248 " range_start: %016llx range_end: %016llx flags: %x\n", s,
1249 PCI_BUS(e->devid_start), PCI_SLOT(e->devid_start),
1250 PCI_FUNC(e->devid_start), PCI_BUS(e->devid_end),
1251 PCI_SLOT(e->devid_end), PCI_FUNC(e->devid_end),
1252 e->address_start, e->address_end, m->flags);
1253
Joerg Roedelbe2a0222008-06-26 21:27:49 +02001254 list_add_tail(&e->list, &amd_iommu_unity_map);
1255
1256 return 0;
1257}
1258
Joerg Roedelb65233a2008-07-11 17:14:21 +02001259/* iterates over all memory definitions we find in the ACPI table */
Joerg Roedelbe2a0222008-06-26 21:27:49 +02001260static int __init init_memory_definitions(struct acpi_table_header *table)
1261{
1262 u8 *p = (u8 *)table, *end = (u8 *)table;
1263 struct ivmd_header *m;
1264
Joerg Roedelbe2a0222008-06-26 21:27:49 +02001265 end += table->length;
1266 p += IVRS_HEADER_LENGTH;
1267
1268 while (p < end) {
1269 m = (struct ivmd_header *)p;
1270 if (m->flags & IVMD_FLAG_EXCL_RANGE)
1271 init_exclusion_range(m);
1272 else if (m->flags & IVMD_FLAG_UNITY_MAP)
1273 init_unity_map_range(m);
1274
1275 p += m->length;
1276 }
1277
1278 return 0;
1279}
1280
Joerg Roedelb65233a2008-07-11 17:14:21 +02001281/*
Joerg Roedel9f5f5fb2008-08-14 19:55:16 +02001282 * Init the device table to not allow DMA access for devices and
1283 * suppress all page faults
1284 */
1285static void init_device_table(void)
1286{
Joerg Roedel0de66d52011-06-06 16:04:02 +02001287 u32 devid;
Joerg Roedel9f5f5fb2008-08-14 19:55:16 +02001288
1289 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) {
1290 set_dev_entry_bit(devid, DEV_ENTRY_VALID);
1291 set_dev_entry_bit(devid, DEV_ENTRY_TRANSLATION);
Joerg Roedel9f5f5fb2008-08-14 19:55:16 +02001292 }
1293}
1294
Joerg Roedele9bf5192010-09-20 14:33:07 +02001295static void iommu_init_flags(struct amd_iommu *iommu)
1296{
1297 iommu->acpi_flags & IVHD_FLAG_HT_TUN_EN_MASK ?
1298 iommu_feature_enable(iommu, CONTROL_HT_TUN_EN) :
1299 iommu_feature_disable(iommu, CONTROL_HT_TUN_EN);
1300
1301 iommu->acpi_flags & IVHD_FLAG_PASSPW_EN_MASK ?
1302 iommu_feature_enable(iommu, CONTROL_PASSPW_EN) :
1303 iommu_feature_disable(iommu, CONTROL_PASSPW_EN);
1304
1305 iommu->acpi_flags & IVHD_FLAG_RESPASSPW_EN_MASK ?
1306 iommu_feature_enable(iommu, CONTROL_RESPASSPW_EN) :
1307 iommu_feature_disable(iommu, CONTROL_RESPASSPW_EN);
1308
1309 iommu->acpi_flags & IVHD_FLAG_ISOC_EN_MASK ?
1310 iommu_feature_enable(iommu, CONTROL_ISOC_EN) :
1311 iommu_feature_disable(iommu, CONTROL_ISOC_EN);
1312
1313 /*
1314 * make IOMMU memory accesses cache coherent
1315 */
1316 iommu_feature_enable(iommu, CONTROL_COHERENT_EN);
Joerg Roedel1456e9d2011-12-22 14:51:53 +01001317
1318 /* Set IOTLB invalidation timeout to 1s */
1319 iommu_set_inv_tlb_timeout(iommu, CTRL_INV_TO_1S);
Joerg Roedele9bf5192010-09-20 14:33:07 +02001320}
1321
Matthew Garrett5bcd7572010-10-04 14:59:31 -04001322static void iommu_apply_resume_quirks(struct amd_iommu *iommu)
Joerg Roedel4c894f42010-09-23 15:15:19 +02001323{
Matthew Garrett5bcd7572010-10-04 14:59:31 -04001324 int i, j;
1325 u32 ioc_feature_control;
1326 struct pci_dev *pdev = NULL;
1327
1328 /* RD890 BIOSes may not have completely reconfigured the iommu */
1329 if (!is_rd890_iommu(iommu->dev))
1330 return;
1331
1332 /*
1333 * First, we need to ensure that the iommu is enabled. This is
1334 * controlled by a register in the northbridge
1335 */
1336 pdev = pci_get_bus_and_slot(iommu->dev->bus->number, PCI_DEVFN(0, 0));
1337
1338 if (!pdev)
1339 return;
1340
1341 /* Select Northbridge indirect register 0x75 and enable writing */
1342 pci_write_config_dword(pdev, 0x60, 0x75 | (1 << 7));
1343 pci_read_config_dword(pdev, 0x64, &ioc_feature_control);
1344
1345 /* Enable the iommu */
1346 if (!(ioc_feature_control & 0x1))
1347 pci_write_config_dword(pdev, 0x64, ioc_feature_control | 1);
1348
1349 pci_dev_put(pdev);
1350
1351 /* Restore the iommu BAR */
1352 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4,
1353 iommu->stored_addr_lo);
1354 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 8,
1355 iommu->stored_addr_hi);
1356
1357 /* Restore the l1 indirect regs for each of the 6 l1s */
1358 for (i = 0; i < 6; i++)
1359 for (j = 0; j < 0x12; j++)
1360 iommu_write_l1(iommu, i, j, iommu->stored_l1[i][j]);
1361
1362 /* Restore the l2 indirect regs */
1363 for (i = 0; i < 0x83; i++)
1364 iommu_write_l2(iommu, i, iommu->stored_l2[i]);
1365
1366 /* Lock PCI setup registers */
1367 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4,
1368 iommu->stored_addr_lo | 1);
Joerg Roedel4c894f42010-09-23 15:15:19 +02001369}
1370
Joerg Roedel9f5f5fb2008-08-14 19:55:16 +02001371/*
Joerg Roedelb65233a2008-07-11 17:14:21 +02001372 * This function finally enables all IOMMUs found in the system after
1373 * they have been initialized
1374 */
Joerg Roedel05f92db2009-05-12 09:52:46 +02001375static void enable_iommus(void)
Joerg Roedel87361972008-06-26 21:28:07 +02001376{
1377 struct amd_iommu *iommu;
1378
Joerg Roedel3bd22172009-05-04 15:06:20 +02001379 for_each_iommu(iommu) {
Chris Wrighta8c485b2009-06-15 15:53:45 +02001380 iommu_disable(iommu);
Joerg Roedele9bf5192010-09-20 14:33:07 +02001381 iommu_init_flags(iommu);
Joerg Roedel58492e12009-05-04 18:41:16 +02001382 iommu_set_device_table(iommu);
1383 iommu_enable_command_buffer(iommu);
1384 iommu_enable_event_buffer(iommu);
Joerg Roedel1a29ac02011-11-10 15:41:40 +01001385 iommu_enable_ppr_log(iommu);
Joerg Roedelcbc33a92011-11-25 11:41:31 +01001386 iommu_enable_gt(iommu);
Joerg Roedel87361972008-06-26 21:28:07 +02001387 iommu_set_exclusion_range(iommu);
1388 iommu_enable(iommu);
Joerg Roedel7d0c5cc2011-04-07 08:16:10 +02001389 iommu_flush_all_caches(iommu);
Joerg Roedel87361972008-06-26 21:28:07 +02001390 }
1391}
1392
Joerg Roedel92ac4322009-05-19 19:06:27 +02001393static void disable_iommus(void)
1394{
1395 struct amd_iommu *iommu;
1396
1397 for_each_iommu(iommu)
1398 iommu_disable(iommu);
1399}
1400
Joerg Roedel7441e9c2008-06-30 20:18:02 +02001401/*
1402 * Suspend/Resume support
1403 * disable suspend until real resume implemented
1404 */
1405
Rafael J. Wysockif3c6ea12011-03-23 22:15:54 +01001406static void amd_iommu_resume(void)
Joerg Roedel7441e9c2008-06-30 20:18:02 +02001407{
Matthew Garrett5bcd7572010-10-04 14:59:31 -04001408 struct amd_iommu *iommu;
1409
1410 for_each_iommu(iommu)
1411 iommu_apply_resume_quirks(iommu);
1412
Joerg Roedel736501e2009-05-12 09:56:12 +02001413 /* re-load the hardware */
1414 enable_iommus();
Joerg Roedel3d9761e2012-03-15 16:39:21 +01001415
1416 amd_iommu_enable_interrupts();
Joerg Roedel7441e9c2008-06-30 20:18:02 +02001417}
1418
Rafael J. Wysockif3c6ea12011-03-23 22:15:54 +01001419static int amd_iommu_suspend(void)
Joerg Roedel7441e9c2008-06-30 20:18:02 +02001420{
Joerg Roedel736501e2009-05-12 09:56:12 +02001421 /* disable IOMMUs to go out of the way for BIOS */
1422 disable_iommus();
1423
1424 return 0;
Joerg Roedel7441e9c2008-06-30 20:18:02 +02001425}
1426
Rafael J. Wysockif3c6ea12011-03-23 22:15:54 +01001427static struct syscore_ops amd_iommu_syscore_ops = {
Joerg Roedel7441e9c2008-06-30 20:18:02 +02001428 .suspend = amd_iommu_suspend,
1429 .resume = amd_iommu_resume,
1430};
1431
Joerg Roedel8704a1b2012-03-01 15:57:53 +01001432static void __init free_on_init_error(void)
1433{
1434 amd_iommu_uninit_devices();
1435
1436 free_pages((unsigned long)amd_iommu_pd_alloc_bitmap,
1437 get_order(MAX_DOMAIN_ID/8));
1438
1439 free_pages((unsigned long)amd_iommu_rlookup_table,
1440 get_order(rlookup_table_size));
1441
1442 free_pages((unsigned long)amd_iommu_alias_table,
1443 get_order(alias_table_size));
1444
1445 free_pages((unsigned long)amd_iommu_dev_table,
1446 get_order(dev_table_size));
1447
1448 free_iommu_all();
1449
1450 free_unity_maps();
1451
1452#ifdef CONFIG_GART_IOMMU
1453 /*
1454 * We failed to initialize the AMD IOMMU - try fallback to GART
1455 * if possible.
1456 */
1457 gart_iommu_init();
1458
1459#endif
1460}
1461
Joerg Roedelb65233a2008-07-11 17:14:21 +02001462/*
Joerg Roedel8704a1b2012-03-01 15:57:53 +01001463 * This is the hardware init function for AMD IOMMU in the system.
1464 * This function is called either from amd_iommu_init or from the interrupt
1465 * remapping setup code.
Joerg Roedelb65233a2008-07-11 17:14:21 +02001466 *
1467 * This function basically parses the ACPI table for AMD IOMMU (IVRS)
1468 * three times:
1469 *
1470 * 1 pass) Find the highest PCI device id the driver has to handle.
1471 * Upon this information the size of the data structures is
1472 * determined that needs to be allocated.
1473 *
1474 * 2 pass) Initialize the data structures just allocated with the
1475 * information in the ACPI table about available AMD IOMMUs
1476 * in the system. It also maps the PCI devices in the
1477 * system to specific IOMMUs
1478 *
1479 * 3 pass) After the basic data structures are allocated and
1480 * initialized we update them with information about memory
1481 * remapping requirements parsed out of the ACPI table in
1482 * this last pass.
1483 *
Joerg Roedel8704a1b2012-03-01 15:57:53 +01001484 * After everything is set up the IOMMUs are enabled and the necessary
1485 * hotplug and suspend notifiers are registered.
Joerg Roedelb65233a2008-07-11 17:14:21 +02001486 */
Joerg Roedel8704a1b2012-03-01 15:57:53 +01001487int __init amd_iommu_init_hardware(void)
Joerg Roedelfe74c9c2008-06-26 21:27:50 +02001488{
1489 int i, ret = 0;
1490
Joerg Roedel8704a1b2012-03-01 15:57:53 +01001491 if (!amd_iommu_detected)
1492 return -ENODEV;
1493
1494 if (amd_iommu_dev_table != NULL) {
1495 /* Hardware already initialized */
1496 return 0;
1497 }
1498
Joerg Roedelfe74c9c2008-06-26 21:27:50 +02001499 /*
1500 * First parse ACPI tables to find the largest Bus/Dev/Func
1501 * we need to handle. Upon this information the shared data
1502 * structures for the IOMMUs in the system will be allocated
1503 */
1504 if (acpi_table_parse("IVRS", find_last_devid_acpi) != 0)
1505 return -ENODEV;
1506
Joerg Roedel3551a702010-03-01 13:52:19 +01001507 ret = amd_iommu_init_err;
1508 if (ret)
1509 goto out;
1510
Joerg Roedelc5714842008-07-11 17:14:25 +02001511 dev_table_size = tbl_size(DEV_TABLE_ENTRY_SIZE);
1512 alias_table_size = tbl_size(ALIAS_TABLE_ENTRY_SIZE);
1513 rlookup_table_size = tbl_size(RLOOKUP_TABLE_ENTRY_SIZE);
Joerg Roedelfe74c9c2008-06-26 21:27:50 +02001514
Joerg Roedelfe74c9c2008-06-26 21:27:50 +02001515 /* Device table - directly used by all IOMMUs */
Joerg Roedel8704a1b2012-03-01 15:57:53 +01001516 ret = -ENOMEM;
Joerg Roedel5dc8bff2008-07-11 17:14:32 +02001517 amd_iommu_dev_table = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
Joerg Roedelfe74c9c2008-06-26 21:27:50 +02001518 get_order(dev_table_size));
1519 if (amd_iommu_dev_table == NULL)
1520 goto out;
1521
1522 /*
1523 * Alias table - map PCI Bus/Dev/Func to Bus/Dev/Func the
1524 * IOMMU see for that device
1525 */
1526 amd_iommu_alias_table = (void *)__get_free_pages(GFP_KERNEL,
1527 get_order(alias_table_size));
1528 if (amd_iommu_alias_table == NULL)
1529 goto free;
1530
1531 /* IOMMU rlookup table - find the IOMMU for a specific device */
Joerg Roedel83fd5cc2008-12-16 19:17:11 +01001532 amd_iommu_rlookup_table = (void *)__get_free_pages(
1533 GFP_KERNEL | __GFP_ZERO,
Joerg Roedelfe74c9c2008-06-26 21:27:50 +02001534 get_order(rlookup_table_size));
1535 if (amd_iommu_rlookup_table == NULL)
1536 goto free;
1537
Joerg Roedel5dc8bff2008-07-11 17:14:32 +02001538 amd_iommu_pd_alloc_bitmap = (void *)__get_free_pages(
1539 GFP_KERNEL | __GFP_ZERO,
Joerg Roedelfe74c9c2008-06-26 21:27:50 +02001540 get_order(MAX_DOMAIN_ID/8));
1541 if (amd_iommu_pd_alloc_bitmap == NULL)
1542 goto free;
1543
Joerg Roedel9f5f5fb2008-08-14 19:55:16 +02001544 /* init the device table */
1545 init_device_table();
1546
Joerg Roedelfe74c9c2008-06-26 21:27:50 +02001547 /*
Joerg Roedel5dc8bff2008-07-11 17:14:32 +02001548 * let all alias entries point to itself
Joerg Roedelfe74c9c2008-06-26 21:27:50 +02001549 */
Joerg Roedel3a61ec32008-07-25 13:07:50 +02001550 for (i = 0; i <= amd_iommu_last_bdf; ++i)
Joerg Roedelfe74c9c2008-06-26 21:27:50 +02001551 amd_iommu_alias_table[i] = i;
1552
Joerg Roedelfe74c9c2008-06-26 21:27:50 +02001553 /*
1554 * never allocate domain 0 because its used as the non-allocated and
1555 * error value placeholder
1556 */
1557 amd_iommu_pd_alloc_bitmap[0] = 1;
1558
Joerg Roedelaeb26f52009-11-20 16:44:01 +01001559 spin_lock_init(&amd_iommu_pd_lock);
1560
Joerg Roedelfe74c9c2008-06-26 21:27:50 +02001561 /*
1562 * now the data structures are allocated and basically initialized
1563 * start the real acpi table scan
1564 */
1565 ret = -ENODEV;
1566 if (acpi_table_parse("IVRS", init_iommu_all) != 0)
1567 goto free;
1568
Joerg Roedel3551a702010-03-01 13:52:19 +01001569 if (amd_iommu_init_err) {
1570 ret = amd_iommu_init_err;
Joerg Roedel0f764802009-12-21 15:51:23 +01001571 goto free;
Joerg Roedel3551a702010-03-01 13:52:19 +01001572 }
Joerg Roedel0f764802009-12-21 15:51:23 +01001573
Joerg Roedelfe74c9c2008-06-26 21:27:50 +02001574 if (acpi_table_parse("IVRS", init_memory_definitions) != 0)
1575 goto free;
1576
Joerg Roedel3551a702010-03-01 13:52:19 +01001577 if (amd_iommu_init_err) {
1578 ret = amd_iommu_init_err;
1579 goto free;
1580 }
1581
Joerg Roedelb7cc9552009-12-10 11:03:39 +01001582 ret = amd_iommu_init_devices();
1583 if (ret)
1584 goto free;
1585
Chris Wright75f66532010-04-02 18:27:52 -07001586 enable_iommus();
1587
Joerg Roedel8704a1b2012-03-01 15:57:53 +01001588 amd_iommu_init_notifier();
1589
1590 register_syscore_ops(&amd_iommu_syscore_ops);
1591
1592out:
1593 return ret;
1594
1595free:
1596 free_on_init_error();
1597
1598 return ret;
1599}
1600
Gerard Snitselaarae295142012-03-16 11:38:22 -07001601static int amd_iommu_enable_interrupts(void)
Joerg Roedel3d9761e2012-03-15 16:39:21 +01001602{
1603 struct amd_iommu *iommu;
1604 int ret = 0;
1605
1606 for_each_iommu(iommu) {
1607 ret = iommu_init_msi(iommu);
1608 if (ret)
1609 goto out;
1610 }
1611
1612out:
1613 return ret;
1614}
1615
Joerg Roedel8704a1b2012-03-01 15:57:53 +01001616/*
1617 * This is the core init function for AMD IOMMU hardware in the system.
1618 * This function is called from the generic x86 DMA layer initialization
1619 * code.
1620 *
1621 * The function calls amd_iommu_init_hardware() to setup and enable the
1622 * IOMMU hardware if this has not happened yet. After that the driver
1623 * registers for the DMA-API and for the IOMMU-API as necessary.
1624 */
1625static int __init amd_iommu_init(void)
1626{
1627 int ret = 0;
1628
1629 ret = amd_iommu_init_hardware();
1630 if (ret)
1631 goto out;
1632
Joerg Roedel3d9761e2012-03-15 16:39:21 +01001633 ret = amd_iommu_enable_interrupts();
1634 if (ret)
1635 goto free;
1636
Joerg Roedel4751a952009-09-01 15:53:54 +02001637 if (iommu_pass_through)
1638 ret = amd_iommu_init_passthrough();
1639 else
1640 ret = amd_iommu_init_dma_ops();
Joerg Roedelf5325092010-01-22 17:44:35 +01001641
Joerg Roedel129d6ab2008-08-14 19:55:18 +02001642 if (ret)
Joerg Roedel8704a1b2012-03-01 15:57:53 +01001643 goto free;
Joerg Roedel129d6ab2008-08-14 19:55:18 +02001644
Joerg Roedelf5325092010-01-22 17:44:35 +01001645 amd_iommu_init_api();
1646
Joerg Roedel4751a952009-09-01 15:53:54 +02001647 if (iommu_pass_through)
1648 goto out;
1649
FUJITA Tomonoriafa9fdc2008-09-20 01:23:30 +09001650 if (amd_iommu_unmap_flush)
Joerg Roedel4c6f40d2009-09-01 16:43:58 +02001651 printk(KERN_INFO "AMD-Vi: IO/TLB flush on unmap enabled\n");
Joerg Roedel1c655772008-09-04 18:40:05 +02001652 else
Joerg Roedel4c6f40d2009-09-01 16:43:58 +02001653 printk(KERN_INFO "AMD-Vi: Lazy IO/TLB flushing enabled\n");
Joerg Roedel1c655772008-09-04 18:40:05 +02001654
FUJITA Tomonori338bac52009-10-27 16:34:44 +09001655 x86_platform.iommu_shutdown = disable_iommus;
Joerg Roedel8704a1b2012-03-01 15:57:53 +01001656
Joerg Roedelfe74c9c2008-06-26 21:27:50 +02001657out:
1658 return ret;
1659
Joerg Roedel8704a1b2012-03-01 15:57:53 +01001660free:
Chris Wright75f66532010-04-02 18:27:52 -07001661 disable_iommus();
Joerg Roedelb7cc9552009-12-10 11:03:39 +01001662
Joerg Roedel8704a1b2012-03-01 15:57:53 +01001663 free_on_init_error();
Joerg Roedeld7f07762010-05-31 15:05:20 +02001664
Joerg Roedelfe74c9c2008-06-26 21:27:50 +02001665 goto out;
1666}
1667
Joerg Roedelb65233a2008-07-11 17:14:21 +02001668/****************************************************************************
1669 *
1670 * Early detect code. This code runs at IOMMU detection time in the DMA
1671 * layer. It just looks if there is an IVRS ACPI table to detect AMD
1672 * IOMMUs
1673 *
1674 ****************************************************************************/
Joerg Roedelae7877d2008-06-26 21:27:51 +02001675static int __init early_amd_iommu_detect(struct acpi_table_header *table)
1676{
1677 return 0;
1678}
1679
Konrad Rzeszutek Wilk480125b2010-08-26 13:57:57 -04001680int __init amd_iommu_detect(void)
Joerg Roedelae7877d2008-06-26 21:27:51 +02001681{
FUJITA Tomonori75f1cdf2009-11-10 19:46:20 +09001682 if (no_iommu || (iommu_detected && !gart_iommu_aperture))
Konrad Rzeszutek Wilk480125b2010-08-26 13:57:57 -04001683 return -ENODEV;
Joerg Roedelae7877d2008-06-26 21:27:51 +02001684
Joerg Roedela5235722010-05-11 17:12:33 +02001685 if (amd_iommu_disabled)
Konrad Rzeszutek Wilk480125b2010-08-26 13:57:57 -04001686 return -ENODEV;
Joerg Roedela5235722010-05-11 17:12:33 +02001687
Joerg Roedelae7877d2008-06-26 21:27:51 +02001688 if (acpi_table_parse("IVRS", early_amd_iommu_detect) == 0) {
1689 iommu_detected = 1;
Joerg Roedelc1cbebe2008-07-03 19:35:10 +02001690 amd_iommu_detected = 1;
FUJITA Tomonoriea1b0d32009-11-10 19:46:15 +09001691 x86_init.iommu.iommu_init = amd_iommu_init;
Linus Torvalds11bd04f2009-12-11 12:18:16 -08001692
Chris Wright5d990b62009-12-04 12:15:21 -08001693 /* Make sure ACS will be enabled */
1694 pci_request_acs();
Konrad Rzeszutek Wilk480125b2010-08-26 13:57:57 -04001695 return 1;
Joerg Roedelae7877d2008-06-26 21:27:51 +02001696 }
Konrad Rzeszutek Wilk480125b2010-08-26 13:57:57 -04001697 return -ENODEV;
Joerg Roedelae7877d2008-06-26 21:27:51 +02001698}
1699
Joerg Roedelb65233a2008-07-11 17:14:21 +02001700/****************************************************************************
1701 *
1702 * Parsing functions for the AMD IOMMU specific kernel command line
1703 * options.
1704 *
1705 ****************************************************************************/
1706
Joerg Roedelfefda112009-05-20 12:21:42 +02001707static int __init parse_amd_iommu_dump(char *str)
1708{
1709 amd_iommu_dump = true;
1710
1711 return 1;
1712}
1713
Joerg Roedel918ad6c2008-06-26 21:27:52 +02001714static int __init parse_amd_iommu_options(char *str)
1715{
1716 for (; *str; ++str) {
Joerg Roedel695b5672008-11-17 15:16:43 +01001717 if (strncmp(str, "fullflush", 9) == 0)
FUJITA Tomonoriafa9fdc2008-09-20 01:23:30 +09001718 amd_iommu_unmap_flush = true;
Joerg Roedela5235722010-05-11 17:12:33 +02001719 if (strncmp(str, "off", 3) == 0)
1720 amd_iommu_disabled = true;
Joerg Roedel5abcdba2011-12-01 15:49:45 +01001721 if (strncmp(str, "force_isolation", 15) == 0)
1722 amd_iommu_force_isolation = true;
Joerg Roedel918ad6c2008-06-26 21:27:52 +02001723 }
1724
1725 return 1;
1726}
1727
Joerg Roedelfefda112009-05-20 12:21:42 +02001728__setup("amd_iommu_dump", parse_amd_iommu_dump);
Joerg Roedel918ad6c2008-06-26 21:27:52 +02001729__setup("amd_iommu=", parse_amd_iommu_options);
Konrad Rzeszutek Wilk22e6daf42010-08-26 13:58:03 -04001730
1731IOMMU_INIT_FINISH(amd_iommu_detect,
1732 gart_iommu_hole_init,
1733 0,
1734 0);
Joerg Roedel400a28a2011-11-28 15:11:02 +01001735
1736bool amd_iommu_v2_supported(void)
1737{
1738 return amd_iommu_v2_present;
1739}
1740EXPORT_SYMBOL(amd_iommu_v2_supported);