blob: bc9f918a7f286e2e07690cc5e64ec3376fd58aa3 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * sata_sil.c - Silicon Image SATA
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
Jeff Garzikaf36d7f2005-08-28 20:18:39 -04008 * Copyright 2003-2005 Red Hat, Inc.
Linus Torvalds1da177e2005-04-16 15:20:36 -07009 * Copyright 2003 Benjamin Herrenschmidt
10 *
Linus Torvalds1da177e2005-04-16 15:20:36 -070011 *
Jeff Garzikaf36d7f2005-08-28 20:18:39 -040012 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2, or (at your option)
15 * any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; see the file COPYING. If not, write to
24 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 *
27 * libata documentation is available via 'make {ps|pdf}docs',
28 * as Documentation/DocBook/libata.*
Linus Torvalds1da177e2005-04-16 15:20:36 -070029 *
Jeff Garzik953d1132005-08-26 19:46:24 -040030 * Documentation for SiI 3112:
31 * http://gkernel.sourceforge.net/specs/sii/3112A_SiI-DS-0095-B2.pdf.bz2
32 *
33 * Other errata and documentation available under NDA.
34 *
Linus Torvalds1da177e2005-04-16 15:20:36 -070035 */
36
37#include <linux/kernel.h>
38#include <linux/module.h>
39#include <linux/pci.h>
40#include <linux/init.h>
41#include <linux/blkdev.h>
42#include <linux/delay.h>
43#include <linux/interrupt.h>
Jeff Garzika9524a72005-10-30 14:39:11 -050044#include <linux/device.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070045#include <scsi/scsi_host.h>
46#include <linux/libata.h>
47
48#define DRV_NAME "sata_sil"
Jeff Garzikaf643712006-04-02 20:41:36 -040049#define DRV_VERSION "1.0"
Linus Torvalds1da177e2005-04-16 15:20:36 -070050
51enum {
Tejun Heoe653a1e2006-03-05 16:03:52 +090052 /*
53 * host flags
54 */
Tejun Heoe4e10e32006-02-25 13:52:30 +090055 SIL_FLAG_RERR_ON_DMA_ACT = (1 << 29),
Tejun Heoe4deec62005-08-23 07:27:25 +090056 SIL_FLAG_MOD15WRITE = (1 << 30),
Tejun Heo20888d82006-05-31 18:27:53 +090057
Tejun Heoe653a1e2006-03-05 16:03:52 +090058 SIL_DFL_HOST_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
Tejun Heoe5738902006-05-31 18:28:16 +090059 ATA_FLAG_MMIO | ATA_FLAG_HRST_TO_RESUME,
Tejun Heoe4deec62005-08-23 07:27:25 +090060
Tejun Heoe653a1e2006-03-05 16:03:52 +090061 /*
62 * Controller IDs
63 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070064 sil_3112 = 0,
Tejun Heo81c2af32006-03-05 16:03:52 +090065 sil_3512 = 1,
66 sil_3114 = 2,
Linus Torvalds1da177e2005-04-16 15:20:36 -070067
Tejun Heoe653a1e2006-03-05 16:03:52 +090068 /*
69 * Register offsets
70 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070071 SIL_SYSCFG = 0x48,
Tejun Heoe653a1e2006-03-05 16:03:52 +090072
73 /*
74 * Register bits
75 */
76 /* SYSCFG */
Linus Torvalds1da177e2005-04-16 15:20:36 -070077 SIL_MASK_IDE0_INT = (1 << 22),
78 SIL_MASK_IDE1_INT = (1 << 23),
79 SIL_MASK_IDE2_INT = (1 << 24),
80 SIL_MASK_IDE3_INT = (1 << 25),
81 SIL_MASK_2PORT = SIL_MASK_IDE0_INT | SIL_MASK_IDE1_INT,
82 SIL_MASK_4PORT = SIL_MASK_2PORT |
83 SIL_MASK_IDE2_INT | SIL_MASK_IDE3_INT,
84
Tejun Heoe653a1e2006-03-05 16:03:52 +090085 /* BMDMA/BMDMA2 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070086 SIL_INTR_STEERING = (1 << 1),
Tejun Heoe653a1e2006-03-05 16:03:52 +090087
Tejun Heo20888d82006-05-31 18:27:53 +090088 SIL_DMA_ENABLE = (1 << 0), /* DMA run switch */
89 SIL_DMA_RDWR = (1 << 3), /* DMA Rd-Wr */
90 SIL_DMA_SATA_IRQ = (1 << 4), /* OR of all SATA IRQs */
91 SIL_DMA_ACTIVE = (1 << 16), /* DMA running */
92 SIL_DMA_ERROR = (1 << 17), /* PCI bus error */
93 SIL_DMA_COMPLETE = (1 << 18), /* cmd complete / IRQ pending */
94 SIL_DMA_N_SATA_IRQ = (1 << 6), /* SATA_IRQ for the next channel */
95 SIL_DMA_N_ACTIVE = (1 << 24), /* ACTIVE for the next channel */
96 SIL_DMA_N_ERROR = (1 << 25), /* ERROR for the next channel */
97 SIL_DMA_N_COMPLETE = (1 << 26), /* COMPLETE for the next channel */
98
99 /* SIEN */
100 SIL_SIEN_N = (1 << 16), /* triggered by SError.N */
101
Tejun Heoe653a1e2006-03-05 16:03:52 +0900102 /*
103 * Others
104 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700105 SIL_QUIRK_MOD15WRITE = (1 << 0),
106 SIL_QUIRK_UDMA5MAX = (1 << 1),
107};
108
109static int sil_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
110static void sil_dev_config(struct ata_port *ap, struct ata_device *dev);
111static u32 sil_scr_read (struct ata_port *ap, unsigned int sc_reg);
112static void sil_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
113static void sil_post_set_mode (struct ata_port *ap);
Tejun Heocbe88fb2006-05-31 18:27:55 +0900114static irqreturn_t sil_interrupt(int irq, void *dev_instance,
115 struct pt_regs *regs);
Tejun Heof6aae272006-05-15 20:58:27 +0900116static void sil_freeze(struct ata_port *ap);
117static void sil_thaw(struct ata_port *ap);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700118
Jeff Garzik374b1872005-08-30 05:42:52 -0400119
Jeff Garzik3b7d6972005-11-10 11:04:11 -0500120static const struct pci_device_id sil_pci_tbl[] = {
Tejun Heo81c2af32006-03-05 16:03:52 +0900121 { 0x1095, 0x3112, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112 },
122 { 0x1095, 0x0240, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112 },
Tejun Heo0ee304d2006-02-25 13:52:30 +0900123 { 0x1095, 0x3512, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3512 },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700124 { 0x1095, 0x3114, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3114 },
Tejun Heo81c2af32006-03-05 16:03:52 +0900125 { 0x1002, 0x436e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112 },
126 { 0x1002, 0x4379, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112 },
127 { 0x1002, 0x437a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112 },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700128 { } /* terminate list */
129};
130
131
132/* TODO firmware versions should be added - eric */
133static const struct sil_drivelist {
134 const char * product;
135 unsigned int quirk;
136} sil_blacklist [] = {
137 { "ST320012AS", SIL_QUIRK_MOD15WRITE },
138 { "ST330013AS", SIL_QUIRK_MOD15WRITE },
139 { "ST340017AS", SIL_QUIRK_MOD15WRITE },
140 { "ST360015AS", SIL_QUIRK_MOD15WRITE },
141 { "ST380013AS", SIL_QUIRK_MOD15WRITE },
142 { "ST380023AS", SIL_QUIRK_MOD15WRITE },
143 { "ST3120023AS", SIL_QUIRK_MOD15WRITE },
144 { "ST3160023AS", SIL_QUIRK_MOD15WRITE },
145 { "ST3120026AS", SIL_QUIRK_MOD15WRITE },
146 { "ST3200822AS", SIL_QUIRK_MOD15WRITE },
147 { "ST340014ASL", SIL_QUIRK_MOD15WRITE },
148 { "ST360014ASL", SIL_QUIRK_MOD15WRITE },
149 { "ST380011ASL", SIL_QUIRK_MOD15WRITE },
150 { "ST3120022ASL", SIL_QUIRK_MOD15WRITE },
151 { "ST3160021ASL", SIL_QUIRK_MOD15WRITE },
152 { "Maxtor 4D060H3", SIL_QUIRK_UDMA5MAX },
153 { }
154};
155
156static struct pci_driver sil_pci_driver = {
157 .name = DRV_NAME,
158 .id_table = sil_pci_tbl,
159 .probe = sil_init_one,
160 .remove = ata_pci_remove_one,
161};
162
Jeff Garzik193515d2005-11-07 00:59:37 -0500163static struct scsi_host_template sil_sht = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700164 .module = THIS_MODULE,
165 .name = DRV_NAME,
166 .ioctl = ata_scsi_ioctl,
167 .queuecommand = ata_scsi_queuecmd,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700168 .can_queue = ATA_DEF_QUEUE,
169 .this_id = ATA_SHT_THIS_ID,
170 .sg_tablesize = LIBATA_MAX_PRD,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700171 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
172 .emulated = ATA_SHT_EMULATED,
173 .use_clustering = ATA_SHT_USE_CLUSTERING,
174 .proc_name = DRV_NAME,
175 .dma_boundary = ATA_DMA_BOUNDARY,
176 .slave_configure = ata_scsi_slave_config,
Tejun Heoccf68c32006-05-31 18:28:09 +0900177 .slave_destroy = ata_scsi_slave_destroy,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700178 .bios_param = ata_std_bios_param,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700179};
180
Jeff Garzik057ace52005-10-22 14:27:05 -0400181static const struct ata_port_operations sil_ops = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700182 .port_disable = ata_port_disable,
183 .dev_config = sil_dev_config,
184 .tf_load = ata_tf_load,
185 .tf_read = ata_tf_read,
186 .check_status = ata_check_status,
187 .exec_command = ata_exec_command,
188 .dev_select = ata_std_dev_select,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700189 .post_set_mode = sil_post_set_mode,
190 .bmdma_setup = ata_bmdma_setup,
191 .bmdma_start = ata_bmdma_start,
192 .bmdma_stop = ata_bmdma_stop,
193 .bmdma_status = ata_bmdma_status,
194 .qc_prep = ata_qc_prep,
195 .qc_issue = ata_qc_issue_prot,
Alan Coxa6b2c5d2006-05-22 16:59:59 +0100196 .data_xfer = ata_mmio_data_xfer,
Tejun Heof6aae272006-05-15 20:58:27 +0900197 .freeze = sil_freeze,
198 .thaw = sil_thaw,
199 .error_handler = ata_bmdma_error_handler,
200 .post_internal_cmd = ata_bmdma_post_internal_cmd,
Tejun Heocbe88fb2006-05-31 18:27:55 +0900201 .irq_handler = sil_interrupt,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700202 .irq_clear = ata_bmdma_irq_clear,
203 .scr_read = sil_scr_read,
204 .scr_write = sil_scr_write,
205 .port_start = ata_port_start,
206 .port_stop = ata_port_stop,
Jeff Garzik374b1872005-08-30 05:42:52 -0400207 .host_stop = ata_pci_host_stop,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700208};
209
Arjan van de Ven98ac62d2005-11-28 10:06:23 +0100210static const struct ata_port_info sil_port_info[] = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700211 /* sil_3112 */
212 {
213 .sht = &sil_sht,
Tejun Heoe653a1e2006-03-05 16:03:52 +0900214 .host_flags = SIL_DFL_HOST_FLAGS | SIL_FLAG_MOD15WRITE,
Tejun Heoe4deec62005-08-23 07:27:25 +0900215 .pio_mask = 0x1f, /* pio0-4 */
216 .mwdma_mask = 0x07, /* mwdma0-2 */
217 .udma_mask = 0x3f, /* udma0-5 */
218 .port_ops = &sil_ops,
Tejun Heo0ee304d2006-02-25 13:52:30 +0900219 },
220 /* sil_3512 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700221 {
222 .sht = &sil_sht,
Tejun Heoe653a1e2006-03-05 16:03:52 +0900223 .host_flags = SIL_DFL_HOST_FLAGS | SIL_FLAG_RERR_ON_DMA_ACT,
Tejun Heo0ee304d2006-02-25 13:52:30 +0900224 .pio_mask = 0x1f, /* pio0-4 */
225 .mwdma_mask = 0x07, /* mwdma0-2 */
226 .udma_mask = 0x3f, /* udma0-5 */
227 .port_ops = &sil_ops,
228 },
229 /* sil_3114 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700230 {
231 .sht = &sil_sht,
Tejun Heoe653a1e2006-03-05 16:03:52 +0900232 .host_flags = SIL_DFL_HOST_FLAGS | SIL_FLAG_RERR_ON_DMA_ACT,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700233 .pio_mask = 0x1f, /* pio0-4 */
234 .mwdma_mask = 0x07, /* mwdma0-2 */
235 .udma_mask = 0x3f, /* udma0-5 */
236 .port_ops = &sil_ops,
237 },
238};
239
240/* per-port register offsets */
241/* TODO: we can probably calculate rather than use a table */
242static const struct {
243 unsigned long tf; /* ATA taskfile register block */
244 unsigned long ctl; /* ATA control/altstatus register block */
245 unsigned long bmdma; /* DMA register block */
Tejun Heo20888d82006-05-31 18:27:53 +0900246 unsigned long bmdma2; /* DMA register block #2 */
Tejun Heo48d4ef22006-03-05 16:03:52 +0900247 unsigned long fifo_cfg; /* FIFO Valid Byte Count and Control */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700248 unsigned long scr; /* SATA control register block */
249 unsigned long sien; /* SATA Interrupt Enable register */
250 unsigned long xfer_mode;/* data transfer mode register */
Tejun Heoe4e10e32006-02-25 13:52:30 +0900251 unsigned long sfis_cfg; /* SATA FIS reception config register */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700252} sil_port[] = {
253 /* port 0 ... */
Tejun Heo20888d82006-05-31 18:27:53 +0900254 { 0x80, 0x8A, 0x00, 0x10, 0x40, 0x100, 0x148, 0xb4, 0x14c },
255 { 0xC0, 0xCA, 0x08, 0x18, 0x44, 0x180, 0x1c8, 0xf4, 0x1cc },
256 { 0x280, 0x28A, 0x200, 0x210, 0x240, 0x300, 0x348, 0x2b4, 0x34c },
257 { 0x2C0, 0x2CA, 0x208, 0x218, 0x244, 0x380, 0x3c8, 0x2f4, 0x3cc },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700258 /* ... port 3 */
259};
260
261MODULE_AUTHOR("Jeff Garzik");
262MODULE_DESCRIPTION("low-level driver for Silicon Image SATA controller");
263MODULE_LICENSE("GPL");
264MODULE_DEVICE_TABLE(pci, sil_pci_tbl);
265MODULE_VERSION(DRV_VERSION);
266
Jeff Garzik51e9f2f2006-01-27 16:50:27 -0500267static int slow_down = 0;
268module_param(slow_down, int, 0444);
269MODULE_PARM_DESC(slow_down, "Sledgehammer used to work around random problems, by limiting commands to 15 sectors (0=off, 1=on)");
270
Jeff Garzik374b1872005-08-30 05:42:52 -0400271
Linus Torvalds1da177e2005-04-16 15:20:36 -0700272static unsigned char sil_get_device_cache_line(struct pci_dev *pdev)
273{
274 u8 cache_line = 0;
275 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache_line);
276 return cache_line;
277}
278
279static void sil_post_set_mode (struct ata_port *ap)
280{
281 struct ata_host_set *host_set = ap->host_set;
282 struct ata_device *dev;
Jeff Garzikea6ba102005-08-30 05:18:18 -0400283 void __iomem *addr =
284 host_set->mmio_base + sil_port[ap->port_no].xfer_mode;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700285 u32 tmp, dev_mode[2];
286 unsigned int i;
287
288 for (i = 0; i < 2; i++) {
289 dev = &ap->device[i];
Tejun Heoe1211e32006-04-01 01:38:18 +0900290 if (!ata_dev_enabled(dev))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700291 dev_mode[i] = 0; /* PIO0/1/2 */
292 else if (dev->flags & ATA_DFLAG_PIO)
293 dev_mode[i] = 1; /* PIO3/4 */
294 else
295 dev_mode[i] = 3; /* UDMA */
296 /* value 2 indicates MDMA */
297 }
298
299 tmp = readl(addr);
300 tmp &= ~((1<<5) | (1<<4) | (1<<1) | (1<<0));
301 tmp |= dev_mode[0];
302 tmp |= (dev_mode[1] << 4);
303 writel(tmp, addr);
304 readl(addr); /* flush */
305}
306
307static inline unsigned long sil_scr_addr(struct ata_port *ap, unsigned int sc_reg)
308{
309 unsigned long offset = ap->ioaddr.scr_addr;
310
311 switch (sc_reg) {
312 case SCR_STATUS:
313 return offset + 4;
314 case SCR_ERROR:
315 return offset + 8;
316 case SCR_CONTROL:
317 return offset;
318 default:
319 /* do nothing */
320 break;
321 }
322
323 return 0;
324}
325
326static u32 sil_scr_read (struct ata_port *ap, unsigned int sc_reg)
327{
Al Viro9aa36e82005-10-21 06:46:02 +0100328 void __iomem *mmio = (void __iomem *) sil_scr_addr(ap, sc_reg);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700329 if (mmio)
330 return readl(mmio);
331 return 0xffffffffU;
332}
333
334static void sil_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
335{
Al Viro9aa36e82005-10-21 06:46:02 +0100336 void *mmio = (void __iomem *) sil_scr_addr(ap, sc_reg);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700337 if (mmio)
338 writel(val, mmio);
339}
340
Tejun Heocbe88fb2006-05-31 18:27:55 +0900341static void sil_host_intr(struct ata_port *ap, u32 bmdma2)
342{
343 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->active_tag);
344 u8 status;
345
Tejun Heoe5738902006-05-31 18:28:16 +0900346 if (unlikely(bmdma2 & SIL_DMA_SATA_IRQ)) {
Tejun Heod4c85322006-06-12 18:45:55 +0900347 u32 serror;
348
349 /* SIEN doesn't mask SATA IRQs on some 3112s. Those
350 * controllers continue to assert IRQ as long as
351 * SError bits are pending. Clear SError immediately.
352 */
353 serror = sil_scr_read(ap, SCR_ERROR);
354 sil_scr_write(ap, SCR_ERROR, serror);
355
356 /* Trigger hotplug and accumulate SError only if the
357 * port isn't already frozen. Otherwise, PHY events
358 * during hardreset makes controllers with broken SIEN
359 * repeat probing needlessly.
360 */
361 if (!(ap->flags & ATA_FLAG_FROZEN)) {
362 ata_ehi_hotplugged(&ap->eh_info);
363 ap->eh_info.serror |= serror;
364 }
365
Tejun Heoe5738902006-05-31 18:28:16 +0900366 goto freeze;
367 }
368
Tejun Heocbe88fb2006-05-31 18:27:55 +0900369 if (unlikely(!qc || qc->tf.ctl & ATA_NIEN))
370 goto freeze;
371
372 /* Check whether we are expecting interrupt in this state */
373 switch (ap->hsm_task_state) {
374 case HSM_ST_FIRST:
375 /* Some pre-ATAPI-4 devices assert INTRQ
376 * at this state when ready to receive CDB.
377 */
378
379 /* Check the ATA_DFLAG_CDB_INTR flag is enough here.
380 * The flag was turned on only for atapi devices.
381 * No need to check is_atapi_taskfile(&qc->tf) again.
382 */
383 if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR))
384 goto err_hsm;
385 break;
386 case HSM_ST_LAST:
387 if (qc->tf.protocol == ATA_PROT_DMA ||
388 qc->tf.protocol == ATA_PROT_ATAPI_DMA) {
389 /* clear DMA-Start bit */
390 ap->ops->bmdma_stop(qc);
391
392 if (bmdma2 & SIL_DMA_ERROR) {
393 qc->err_mask |= AC_ERR_HOST_BUS;
394 ap->hsm_task_state = HSM_ST_ERR;
395 }
396 }
397 break;
398 case HSM_ST:
399 break;
400 default:
401 goto err_hsm;
402 }
403
404 /* check main status, clearing INTRQ */
405 status = ata_chk_status(ap);
406 if (unlikely(status & ATA_BUSY))
407 goto err_hsm;
408
409 /* ack bmdma irq events */
410 ata_bmdma_irq_clear(ap);
411
412 /* kick HSM in the ass */
413 ata_hsm_move(ap, qc, status, 0);
414
415 return;
416
417 err_hsm:
418 qc->err_mask |= AC_ERR_HSM;
419 freeze:
420 ata_port_freeze(ap);
421}
422
423static irqreturn_t sil_interrupt(int irq, void *dev_instance,
424 struct pt_regs *regs)
425{
426 struct ata_host_set *host_set = dev_instance;
427 void __iomem *mmio_base = host_set->mmio_base;
428 int handled = 0;
429 int i;
430
431 spin_lock(&host_set->lock);
432
433 for (i = 0; i < host_set->n_ports; i++) {
434 struct ata_port *ap = host_set->ports[i];
435 u32 bmdma2 = readl(mmio_base + sil_port[ap->port_no].bmdma2);
436
437 if (unlikely(!ap || ap->flags & ATA_FLAG_DISABLED))
438 continue;
439
Tejun Heo23fa9612006-06-12 14:18:51 +0900440 if (bmdma2 == 0xffffffff ||
441 !(bmdma2 & (SIL_DMA_COMPLETE | SIL_DMA_SATA_IRQ)))
Tejun Heocbe88fb2006-05-31 18:27:55 +0900442 continue;
443
444 sil_host_intr(ap, bmdma2);
445 handled = 1;
446 }
447
448 spin_unlock(&host_set->lock);
449
450 return IRQ_RETVAL(handled);
451}
452
Tejun Heof6aae272006-05-15 20:58:27 +0900453static void sil_freeze(struct ata_port *ap)
454{
455 void __iomem *mmio_base = ap->host_set->mmio_base;
456 u32 tmp;
457
Tejun Heoe5738902006-05-31 18:28:16 +0900458 /* global IRQ mask doesn't block SATA IRQ, turn off explicitly */
459 writel(0, mmio_base + sil_port[ap->port_no].sien);
460
Tejun Heof6aae272006-05-15 20:58:27 +0900461 /* plug IRQ */
462 tmp = readl(mmio_base + SIL_SYSCFG);
463 tmp |= SIL_MASK_IDE0_INT << ap->port_no;
464 writel(tmp, mmio_base + SIL_SYSCFG);
465 readl(mmio_base + SIL_SYSCFG); /* flush */
466}
467
468static void sil_thaw(struct ata_port *ap)
469{
470 void __iomem *mmio_base = ap->host_set->mmio_base;
471 u32 tmp;
472
473 /* clear IRQ */
474 ata_chk_status(ap);
475 ata_bmdma_irq_clear(ap);
476
Tejun Heoe5738902006-05-31 18:28:16 +0900477 /* turn on SATA IRQ */
478 writel(SIL_SIEN_N, mmio_base + sil_port[ap->port_no].sien);
479
Tejun Heof6aae272006-05-15 20:58:27 +0900480 /* turn on IRQ */
481 tmp = readl(mmio_base + SIL_SYSCFG);
482 tmp &= ~(SIL_MASK_IDE0_INT << ap->port_no);
483 writel(tmp, mmio_base + SIL_SYSCFG);
484}
485
Linus Torvalds1da177e2005-04-16 15:20:36 -0700486/**
487 * sil_dev_config - Apply device/host-specific errata fixups
488 * @ap: Port containing device to be examined
489 * @dev: Device to be examined
490 *
491 * After the IDENTIFY [PACKET] DEVICE step is complete, and a
492 * device is known to be present, this function is called.
493 * We apply two errata fixups which are specific to Silicon Image,
494 * a Seagate and a Maxtor fixup.
495 *
496 * For certain Seagate devices, we must limit the maximum sectors
497 * to under 8K.
498 *
499 * For certain Maxtor devices, we must not program the drive
500 * beyond udma5.
501 *
502 * Both fixups are unfairly pessimistic. As soon as I get more
503 * information on these errata, I will create a more exhaustive
504 * list, and apply the fixups to only the specific
505 * devices/hosts/firmwares that need it.
506 *
507 * 20040111 - Seagate drives affected by the Mod15Write bug are blacklisted
508 * The Maxtor quirk is in the blacklist, but I'm keeping the original
509 * pessimistic fix for the following reasons...
510 * - There seems to be less info on it, only one device gleaned off the
511 * Windows driver, maybe only one is affected. More info would be greatly
512 * appreciated.
513 * - But then again UDMA5 is hardly anything to complain about
514 */
515static void sil_dev_config(struct ata_port *ap, struct ata_device *dev)
516{
517 unsigned int n, quirks = 0;
Tejun Heo2e026712006-02-12 22:47:04 +0900518 unsigned char model_num[41];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700519
Tejun Heo6a62a042006-02-13 10:02:46 +0900520 ata_id_c_string(dev->id, model_num, ATA_ID_PROD_OFS, sizeof(model_num));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700521
Jeff Garzik8a60a072005-07-31 13:13:24 -0400522 for (n = 0; sil_blacklist[n].product; n++)
Tejun Heo2e026712006-02-12 22:47:04 +0900523 if (!strcmp(sil_blacklist[n].product, model_num)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700524 quirks = sil_blacklist[n].quirk;
525 break;
526 }
Jeff Garzik8a60a072005-07-31 13:13:24 -0400527
Linus Torvalds1da177e2005-04-16 15:20:36 -0700528 /* limit requests to 15 sectors */
Jeff Garzik51e9f2f2006-01-27 16:50:27 -0500529 if (slow_down ||
530 ((ap->flags & SIL_FLAG_MOD15WRITE) &&
531 (quirks & SIL_QUIRK_MOD15WRITE))) {
Tejun Heof15a1da2006-05-15 20:57:56 +0900532 ata_dev_printk(dev, KERN_INFO, "applying Seagate errata fix "
533 "(mod15write workaround)\n");
Tejun Heob00eec12006-02-12 23:32:59 +0900534 dev->max_sectors = 15;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700535 return;
536 }
537
538 /* limit to udma5 */
539 if (quirks & SIL_QUIRK_UDMA5MAX) {
Tejun Heof15a1da2006-05-15 20:57:56 +0900540 ata_dev_printk(dev, KERN_INFO,
541 "applying Maxtor errata fix %s\n", model_num);
Tejun Heo5a529132006-03-24 14:07:50 +0900542 dev->udma_mask &= ATA_UDMA5;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700543 return;
544 }
545}
546
547static int sil_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
548{
549 static int printed_version;
550 struct ata_probe_ent *probe_ent = NULL;
551 unsigned long base;
Jeff Garzikea6ba102005-08-30 05:18:18 -0400552 void __iomem *mmio_base;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700553 int rc;
554 unsigned int i;
555 int pci_dev_busy = 0;
Tejun Heof6aae272006-05-15 20:58:27 +0900556 u32 tmp;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700557 u8 cls;
558
559 if (!printed_version++)
Jeff Garzika9524a72005-10-30 14:39:11 -0500560 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700561
Linus Torvalds1da177e2005-04-16 15:20:36 -0700562 rc = pci_enable_device(pdev);
563 if (rc)
564 return rc;
565
566 rc = pci_request_regions(pdev, DRV_NAME);
567 if (rc) {
568 pci_dev_busy = 1;
569 goto err_out;
570 }
571
572 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
573 if (rc)
574 goto err_out_regions;
575 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
576 if (rc)
577 goto err_out_regions;
578
Tejun Heo9a531442006-03-05 16:03:52 +0900579 probe_ent = kzalloc(sizeof(*probe_ent), GFP_KERNEL);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700580 if (probe_ent == NULL) {
581 rc = -ENOMEM;
582 goto err_out_regions;
583 }
584
Linus Torvalds1da177e2005-04-16 15:20:36 -0700585 INIT_LIST_HEAD(&probe_ent->node);
586 probe_ent->dev = pci_dev_to_dev(pdev);
587 probe_ent->port_ops = sil_port_info[ent->driver_data].port_ops;
588 probe_ent->sht = sil_port_info[ent->driver_data].sht;
589 probe_ent->n_ports = (ent->driver_data == sil_3114) ? 4 : 2;
590 probe_ent->pio_mask = sil_port_info[ent->driver_data].pio_mask;
591 probe_ent->mwdma_mask = sil_port_info[ent->driver_data].mwdma_mask;
592 probe_ent->udma_mask = sil_port_info[ent->driver_data].udma_mask;
593 probe_ent->irq = pdev->irq;
594 probe_ent->irq_flags = SA_SHIRQ;
595 probe_ent->host_flags = sil_port_info[ent->driver_data].host_flags;
596
Jeff Garzik374b1872005-08-30 05:42:52 -0400597 mmio_base = pci_iomap(pdev, 5, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700598 if (mmio_base == NULL) {
599 rc = -ENOMEM;
600 goto err_out_free_ent;
601 }
602
603 probe_ent->mmio_base = mmio_base;
604
605 base = (unsigned long) mmio_base;
606
607 for (i = 0; i < probe_ent->n_ports; i++) {
608 probe_ent->port[i].cmd_addr = base + sil_port[i].tf;
609 probe_ent->port[i].altstatus_addr =
610 probe_ent->port[i].ctl_addr = base + sil_port[i].ctl;
611 probe_ent->port[i].bmdma_addr = base + sil_port[i].bmdma;
612 probe_ent->port[i].scr_addr = base + sil_port[i].scr;
613 ata_std_ports(&probe_ent->port[i]);
614 }
615
616 /* Initialize FIFO PCI bus arbitration */
617 cls = sil_get_device_cache_line(pdev);
618 if (cls) {
619 cls >>= 3;
620 cls++; /* cls = (line_size/8)+1 */
Tejun Heo48d4ef22006-03-05 16:03:52 +0900621 for (i = 0; i < probe_ent->n_ports; i++)
622 writew(cls << 8 | cls,
623 mmio_base + sil_port[i].fifo_cfg);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700624 } else
Jeff Garzika9524a72005-10-30 14:39:11 -0500625 dev_printk(KERN_WARNING, &pdev->dev,
Tejun Heo48d4ef22006-03-05 16:03:52 +0900626 "cache line size not set. Driver may not function\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700627
Tejun Heoe4e10e32006-02-25 13:52:30 +0900628 /* Apply R_ERR on DMA activate FIS errata workaround */
629 if (probe_ent->host_flags & SIL_FLAG_RERR_ON_DMA_ACT) {
630 int cnt;
631
632 for (i = 0, cnt = 0; i < probe_ent->n_ports; i++) {
633 tmp = readl(mmio_base + sil_port[i].sfis_cfg);
634 if ((tmp & 0x3) != 0x01)
635 continue;
636 if (!cnt)
637 dev_printk(KERN_INFO, &pdev->dev,
638 "Applying R_ERR on DMA activate "
639 "FIS errata fix\n");
640 writel(tmp & ~0x3, mmio_base + sil_port[i].sfis_cfg);
641 cnt++;
642 }
643 }
644
Linus Torvalds1da177e2005-04-16 15:20:36 -0700645 if (ent->driver_data == sil_3114) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700646 /* flip the magic "make 4 ports work" bit */
Tejun Heo48d4ef22006-03-05 16:03:52 +0900647 tmp = readl(mmio_base + sil_port[2].bmdma);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700648 if ((tmp & SIL_INTR_STEERING) == 0)
649 writel(tmp | SIL_INTR_STEERING,
Tejun Heo48d4ef22006-03-05 16:03:52 +0900650 mmio_base + sil_port[2].bmdma);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700651 }
652
Linus Torvalds1da177e2005-04-16 15:20:36 -0700653 pci_set_master(pdev);
654
655 /* FIXME: check ata_device_add return value */
656 ata_device_add(probe_ent);
657 kfree(probe_ent);
658
659 return 0;
660
661err_out_free_ent:
662 kfree(probe_ent);
663err_out_regions:
664 pci_release_regions(pdev);
665err_out:
666 if (!pci_dev_busy)
667 pci_disable_device(pdev);
668 return rc;
669}
670
671static int __init sil_init(void)
672{
673 return pci_module_init(&sil_pci_driver);
674}
675
676static void __exit sil_exit(void)
677{
678 pci_unregister_driver(&sil_pci_driver);
679}
680
681
682module_init(sil_init);
683module_exit(sil_exit);