Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1 | /* |
| 2 | * arch/powerpc/kernel/mpic.c |
| 3 | * |
| 4 | * Driver for interrupt controllers following the OpenPIC standard, the |
| 5 | * common implementation beeing IBM's MPIC. This driver also can deal |
| 6 | * with various broken implementations of this HW. |
| 7 | * |
| 8 | * Copyright (C) 2004 Benjamin Herrenschmidt, IBM Corp. |
| 9 | * |
| 10 | * This file is subject to the terms and conditions of the GNU General Public |
| 11 | * License. See the file COPYING in the main directory of this archive |
| 12 | * for more details. |
| 13 | */ |
| 14 | |
| 15 | #undef DEBUG |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 16 | #undef DEBUG_IPI |
| 17 | #undef DEBUG_IRQ |
| 18 | #undef DEBUG_LOW |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 19 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 20 | #include <linux/types.h> |
| 21 | #include <linux/kernel.h> |
| 22 | #include <linux/init.h> |
| 23 | #include <linux/irq.h> |
| 24 | #include <linux/smp.h> |
| 25 | #include <linux/interrupt.h> |
| 26 | #include <linux/bootmem.h> |
| 27 | #include <linux/spinlock.h> |
| 28 | #include <linux/pci.h> |
| 29 | |
| 30 | #include <asm/ptrace.h> |
| 31 | #include <asm/signal.h> |
| 32 | #include <asm/io.h> |
| 33 | #include <asm/pgtable.h> |
| 34 | #include <asm/irq.h> |
| 35 | #include <asm/machdep.h> |
| 36 | #include <asm/mpic.h> |
| 37 | #include <asm/smp.h> |
| 38 | |
Michael Ellerman | a7de7c7 | 2007-05-08 12:58:36 +1000 | [diff] [blame] | 39 | #include "mpic.h" |
| 40 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 41 | #ifdef DEBUG |
| 42 | #define DBG(fmt...) printk(fmt) |
| 43 | #else |
| 44 | #define DBG(fmt...) |
| 45 | #endif |
| 46 | |
| 47 | static struct mpic *mpics; |
| 48 | static struct mpic *mpic_primary; |
| 49 | static DEFINE_SPINLOCK(mpic_lock); |
| 50 | |
Paul Mackerras | c0c0d99 | 2005-10-01 13:49:08 +1000 | [diff] [blame] | 51 | #ifdef CONFIG_PPC32 /* XXX for now */ |
Andy Whitcroft | e40c7f0 | 2005-11-29 19:25:54 +0000 | [diff] [blame] | 52 | #ifdef CONFIG_IRQ_ALL_CPUS |
| 53 | #define distribute_irqs (1) |
| 54 | #else |
| 55 | #define distribute_irqs (0) |
| 56 | #endif |
Paul Mackerras | c0c0d99 | 2005-10-01 13:49:08 +1000 | [diff] [blame] | 57 | #endif |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 58 | |
Zang Roy-r61911 | 7233593 | 2006-08-25 14:16:30 +1000 | [diff] [blame] | 59 | #ifdef CONFIG_MPIC_WEIRD |
| 60 | static u32 mpic_infos[][MPIC_IDX_END] = { |
| 61 | [0] = { /* Original OpenPIC compatible MPIC */ |
| 62 | MPIC_GREG_BASE, |
| 63 | MPIC_GREG_FEATURE_0, |
| 64 | MPIC_GREG_GLOBAL_CONF_0, |
| 65 | MPIC_GREG_VENDOR_ID, |
| 66 | MPIC_GREG_IPI_VECTOR_PRI_0, |
| 67 | MPIC_GREG_IPI_STRIDE, |
| 68 | MPIC_GREG_SPURIOUS, |
| 69 | MPIC_GREG_TIMER_FREQ, |
| 70 | |
| 71 | MPIC_TIMER_BASE, |
| 72 | MPIC_TIMER_STRIDE, |
| 73 | MPIC_TIMER_CURRENT_CNT, |
| 74 | MPIC_TIMER_BASE_CNT, |
| 75 | MPIC_TIMER_VECTOR_PRI, |
| 76 | MPIC_TIMER_DESTINATION, |
| 77 | |
| 78 | MPIC_CPU_BASE, |
| 79 | MPIC_CPU_STRIDE, |
| 80 | MPIC_CPU_IPI_DISPATCH_0, |
| 81 | MPIC_CPU_IPI_DISPATCH_STRIDE, |
| 82 | MPIC_CPU_CURRENT_TASK_PRI, |
| 83 | MPIC_CPU_WHOAMI, |
| 84 | MPIC_CPU_INTACK, |
| 85 | MPIC_CPU_EOI, |
Olof Johansson | f365355 | 2007-12-20 13:11:18 -0600 | [diff] [blame] | 86 | MPIC_CPU_MCACK, |
Zang Roy-r61911 | 7233593 | 2006-08-25 14:16:30 +1000 | [diff] [blame] | 87 | |
| 88 | MPIC_IRQ_BASE, |
| 89 | MPIC_IRQ_STRIDE, |
| 90 | MPIC_IRQ_VECTOR_PRI, |
| 91 | MPIC_VECPRI_VECTOR_MASK, |
| 92 | MPIC_VECPRI_POLARITY_POSITIVE, |
| 93 | MPIC_VECPRI_POLARITY_NEGATIVE, |
| 94 | MPIC_VECPRI_SENSE_LEVEL, |
| 95 | MPIC_VECPRI_SENSE_EDGE, |
| 96 | MPIC_VECPRI_POLARITY_MASK, |
| 97 | MPIC_VECPRI_SENSE_MASK, |
| 98 | MPIC_IRQ_DESTINATION |
| 99 | }, |
| 100 | [1] = { /* Tsi108/109 PIC */ |
| 101 | TSI108_GREG_BASE, |
| 102 | TSI108_GREG_FEATURE_0, |
| 103 | TSI108_GREG_GLOBAL_CONF_0, |
| 104 | TSI108_GREG_VENDOR_ID, |
| 105 | TSI108_GREG_IPI_VECTOR_PRI_0, |
| 106 | TSI108_GREG_IPI_STRIDE, |
| 107 | TSI108_GREG_SPURIOUS, |
| 108 | TSI108_GREG_TIMER_FREQ, |
| 109 | |
| 110 | TSI108_TIMER_BASE, |
| 111 | TSI108_TIMER_STRIDE, |
| 112 | TSI108_TIMER_CURRENT_CNT, |
| 113 | TSI108_TIMER_BASE_CNT, |
| 114 | TSI108_TIMER_VECTOR_PRI, |
| 115 | TSI108_TIMER_DESTINATION, |
| 116 | |
| 117 | TSI108_CPU_BASE, |
| 118 | TSI108_CPU_STRIDE, |
| 119 | TSI108_CPU_IPI_DISPATCH_0, |
| 120 | TSI108_CPU_IPI_DISPATCH_STRIDE, |
| 121 | TSI108_CPU_CURRENT_TASK_PRI, |
| 122 | TSI108_CPU_WHOAMI, |
| 123 | TSI108_CPU_INTACK, |
| 124 | TSI108_CPU_EOI, |
Olof Johansson | f365355 | 2007-12-20 13:11:18 -0600 | [diff] [blame] | 125 | TSI108_CPU_MCACK, |
Zang Roy-r61911 | 7233593 | 2006-08-25 14:16:30 +1000 | [diff] [blame] | 126 | |
| 127 | TSI108_IRQ_BASE, |
| 128 | TSI108_IRQ_STRIDE, |
| 129 | TSI108_IRQ_VECTOR_PRI, |
| 130 | TSI108_VECPRI_VECTOR_MASK, |
| 131 | TSI108_VECPRI_POLARITY_POSITIVE, |
| 132 | TSI108_VECPRI_POLARITY_NEGATIVE, |
| 133 | TSI108_VECPRI_SENSE_LEVEL, |
| 134 | TSI108_VECPRI_SENSE_EDGE, |
| 135 | TSI108_VECPRI_POLARITY_MASK, |
| 136 | TSI108_VECPRI_SENSE_MASK, |
| 137 | TSI108_IRQ_DESTINATION |
| 138 | }, |
| 139 | }; |
| 140 | |
| 141 | #define MPIC_INFO(name) mpic->hw_set[MPIC_IDX_##name] |
| 142 | |
| 143 | #else /* CONFIG_MPIC_WEIRD */ |
| 144 | |
| 145 | #define MPIC_INFO(name) MPIC_##name |
| 146 | |
| 147 | #endif /* CONFIG_MPIC_WEIRD */ |
| 148 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 149 | /* |
| 150 | * Register accessor functions |
| 151 | */ |
| 152 | |
| 153 | |
Benjamin Herrenschmidt | fbf0274 | 2006-11-11 17:24:55 +1100 | [diff] [blame] | 154 | static inline u32 _mpic_read(enum mpic_reg_type type, |
| 155 | struct mpic_reg_bank *rb, |
| 156 | unsigned int reg) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 157 | { |
Benjamin Herrenschmidt | fbf0274 | 2006-11-11 17:24:55 +1100 | [diff] [blame] | 158 | switch(type) { |
| 159 | #ifdef CONFIG_PPC_DCR |
| 160 | case mpic_access_dcr: |
Michael Ellerman | 83f34df | 2007-10-15 19:34:36 +1000 | [diff] [blame] | 161 | return dcr_read(rb->dhost, reg); |
Benjamin Herrenschmidt | fbf0274 | 2006-11-11 17:24:55 +1100 | [diff] [blame] | 162 | #endif |
| 163 | case mpic_access_mmio_be: |
| 164 | return in_be32(rb->base + (reg >> 2)); |
| 165 | case mpic_access_mmio_le: |
| 166 | default: |
| 167 | return in_le32(rb->base + (reg >> 2)); |
| 168 | } |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 169 | } |
| 170 | |
Benjamin Herrenschmidt | fbf0274 | 2006-11-11 17:24:55 +1100 | [diff] [blame] | 171 | static inline void _mpic_write(enum mpic_reg_type type, |
| 172 | struct mpic_reg_bank *rb, |
| 173 | unsigned int reg, u32 value) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 174 | { |
Benjamin Herrenschmidt | fbf0274 | 2006-11-11 17:24:55 +1100 | [diff] [blame] | 175 | switch(type) { |
| 176 | #ifdef CONFIG_PPC_DCR |
| 177 | case mpic_access_dcr: |
Johannes Berg | d9d1063 | 2008-02-21 20:39:01 +1100 | [diff] [blame] | 178 | dcr_write(rb->dhost, reg, value); |
| 179 | break; |
Benjamin Herrenschmidt | fbf0274 | 2006-11-11 17:24:55 +1100 | [diff] [blame] | 180 | #endif |
| 181 | case mpic_access_mmio_be: |
Johannes Berg | d9d1063 | 2008-02-21 20:39:01 +1100 | [diff] [blame] | 182 | out_be32(rb->base + (reg >> 2), value); |
| 183 | break; |
Benjamin Herrenschmidt | fbf0274 | 2006-11-11 17:24:55 +1100 | [diff] [blame] | 184 | case mpic_access_mmio_le: |
| 185 | default: |
Johannes Berg | d9d1063 | 2008-02-21 20:39:01 +1100 | [diff] [blame] | 186 | out_le32(rb->base + (reg >> 2), value); |
| 187 | break; |
Benjamin Herrenschmidt | fbf0274 | 2006-11-11 17:24:55 +1100 | [diff] [blame] | 188 | } |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 189 | } |
| 190 | |
| 191 | static inline u32 _mpic_ipi_read(struct mpic *mpic, unsigned int ipi) |
| 192 | { |
Benjamin Herrenschmidt | fbf0274 | 2006-11-11 17:24:55 +1100 | [diff] [blame] | 193 | enum mpic_reg_type type = mpic->reg_type; |
Zang Roy-r61911 | 7233593 | 2006-08-25 14:16:30 +1000 | [diff] [blame] | 194 | unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) + |
| 195 | (ipi * MPIC_INFO(GREG_IPI_STRIDE)); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 196 | |
Benjamin Herrenschmidt | fbf0274 | 2006-11-11 17:24:55 +1100 | [diff] [blame] | 197 | if ((mpic->flags & MPIC_BROKEN_IPI) && type == mpic_access_mmio_le) |
| 198 | type = mpic_access_mmio_be; |
| 199 | return _mpic_read(type, &mpic->gregs, offset); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 200 | } |
| 201 | |
| 202 | static inline void _mpic_ipi_write(struct mpic *mpic, unsigned int ipi, u32 value) |
| 203 | { |
Zang Roy-r61911 | 7233593 | 2006-08-25 14:16:30 +1000 | [diff] [blame] | 204 | unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) + |
| 205 | (ipi * MPIC_INFO(GREG_IPI_STRIDE)); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 206 | |
Benjamin Herrenschmidt | fbf0274 | 2006-11-11 17:24:55 +1100 | [diff] [blame] | 207 | _mpic_write(mpic->reg_type, &mpic->gregs, offset, value); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 208 | } |
| 209 | |
| 210 | static inline u32 _mpic_cpu_read(struct mpic *mpic, unsigned int reg) |
| 211 | { |
| 212 | unsigned int cpu = 0; |
| 213 | |
| 214 | if (mpic->flags & MPIC_PRIMARY) |
| 215 | cpu = hard_smp_processor_id(); |
Benjamin Herrenschmidt | fbf0274 | 2006-11-11 17:24:55 +1100 | [diff] [blame] | 216 | return _mpic_read(mpic->reg_type, &mpic->cpuregs[cpu], reg); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 217 | } |
| 218 | |
| 219 | static inline void _mpic_cpu_write(struct mpic *mpic, unsigned int reg, u32 value) |
| 220 | { |
| 221 | unsigned int cpu = 0; |
| 222 | |
| 223 | if (mpic->flags & MPIC_PRIMARY) |
| 224 | cpu = hard_smp_processor_id(); |
| 225 | |
Benjamin Herrenschmidt | fbf0274 | 2006-11-11 17:24:55 +1100 | [diff] [blame] | 226 | _mpic_write(mpic->reg_type, &mpic->cpuregs[cpu], reg, value); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 227 | } |
| 228 | |
| 229 | static inline u32 _mpic_irq_read(struct mpic *mpic, unsigned int src_no, unsigned int reg) |
| 230 | { |
| 231 | unsigned int isu = src_no >> mpic->isu_shift; |
| 232 | unsigned int idx = src_no & mpic->isu_mask; |
| 233 | |
Olof Johansson | 0d72ba9 | 2007-09-08 05:13:19 +1000 | [diff] [blame] | 234 | #ifdef CONFIG_MPIC_BROKEN_REGREAD |
| 235 | if (reg == 0) |
| 236 | return mpic->isu_reg0_shadow[idx]; |
| 237 | else |
| 238 | #endif |
| 239 | return _mpic_read(mpic->reg_type, &mpic->isus[isu], |
| 240 | reg + (idx * MPIC_INFO(IRQ_STRIDE))); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 241 | } |
| 242 | |
| 243 | static inline void _mpic_irq_write(struct mpic *mpic, unsigned int src_no, |
| 244 | unsigned int reg, u32 value) |
| 245 | { |
| 246 | unsigned int isu = src_no >> mpic->isu_shift; |
| 247 | unsigned int idx = src_no & mpic->isu_mask; |
| 248 | |
Benjamin Herrenschmidt | fbf0274 | 2006-11-11 17:24:55 +1100 | [diff] [blame] | 249 | _mpic_write(mpic->reg_type, &mpic->isus[isu], |
Zang Roy-r61911 | 7233593 | 2006-08-25 14:16:30 +1000 | [diff] [blame] | 250 | reg + (idx * MPIC_INFO(IRQ_STRIDE)), value); |
Olof Johansson | 0d72ba9 | 2007-09-08 05:13:19 +1000 | [diff] [blame] | 251 | |
| 252 | #ifdef CONFIG_MPIC_BROKEN_REGREAD |
| 253 | if (reg == 0) |
| 254 | mpic->isu_reg0_shadow[idx] = value; |
| 255 | #endif |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 256 | } |
| 257 | |
Benjamin Herrenschmidt | fbf0274 | 2006-11-11 17:24:55 +1100 | [diff] [blame] | 258 | #define mpic_read(b,r) _mpic_read(mpic->reg_type,&(b),(r)) |
| 259 | #define mpic_write(b,r,v) _mpic_write(mpic->reg_type,&(b),(r),(v)) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 260 | #define mpic_ipi_read(i) _mpic_ipi_read(mpic,(i)) |
| 261 | #define mpic_ipi_write(i,v) _mpic_ipi_write(mpic,(i),(v)) |
| 262 | #define mpic_cpu_read(i) _mpic_cpu_read(mpic,(i)) |
| 263 | #define mpic_cpu_write(i,v) _mpic_cpu_write(mpic,(i),(v)) |
| 264 | #define mpic_irq_read(s,r) _mpic_irq_read(mpic,(s),(r)) |
| 265 | #define mpic_irq_write(s,r,v) _mpic_irq_write(mpic,(s),(r),(v)) |
| 266 | |
| 267 | |
| 268 | /* |
| 269 | * Low level utility functions |
| 270 | */ |
| 271 | |
| 272 | |
Becky Bruce | c51a3fd | 2008-01-14 20:56:18 -0600 | [diff] [blame] | 273 | static void _mpic_map_mmio(struct mpic *mpic, phys_addr_t phys_addr, |
Benjamin Herrenschmidt | fbf0274 | 2006-11-11 17:24:55 +1100 | [diff] [blame] | 274 | struct mpic_reg_bank *rb, unsigned int offset, |
| 275 | unsigned int size) |
| 276 | { |
| 277 | rb->base = ioremap(phys_addr + offset, size); |
| 278 | BUG_ON(rb->base == NULL); |
| 279 | } |
| 280 | |
| 281 | #ifdef CONFIG_PPC_DCR |
| 282 | static void _mpic_map_dcr(struct mpic *mpic, struct mpic_reg_bank *rb, |
| 283 | unsigned int offset, unsigned int size) |
| 284 | { |
Michael Ellerman | 0411a5e | 2007-09-17 16:05:01 +1000 | [diff] [blame] | 285 | const u32 *dbasep; |
| 286 | |
| 287 | dbasep = of_get_property(mpic->irqhost->of_node, "dcr-reg", NULL); |
| 288 | |
| 289 | rb->dhost = dcr_map(mpic->irqhost->of_node, *dbasep + offset, size); |
Benjamin Herrenschmidt | fbf0274 | 2006-11-11 17:24:55 +1100 | [diff] [blame] | 290 | BUG_ON(!DCR_MAP_OK(rb->dhost)); |
| 291 | } |
| 292 | |
Becky Bruce | c51a3fd | 2008-01-14 20:56:18 -0600 | [diff] [blame] | 293 | static inline void mpic_map(struct mpic *mpic, phys_addr_t phys_addr, |
Benjamin Herrenschmidt | fbf0274 | 2006-11-11 17:24:55 +1100 | [diff] [blame] | 294 | struct mpic_reg_bank *rb, unsigned int offset, |
| 295 | unsigned int size) |
| 296 | { |
| 297 | if (mpic->flags & MPIC_USES_DCR) |
| 298 | _mpic_map_dcr(mpic, rb, offset, size); |
| 299 | else |
| 300 | _mpic_map_mmio(mpic, phys_addr, rb, offset, size); |
| 301 | } |
| 302 | #else /* CONFIG_PPC_DCR */ |
| 303 | #define mpic_map(m,p,b,o,s) _mpic_map_mmio(m,p,b,o,s) |
| 304 | #endif /* !CONFIG_PPC_DCR */ |
| 305 | |
| 306 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 307 | |
| 308 | /* Check if we have one of those nice broken MPICs with a flipped endian on |
| 309 | * reads from IPI registers |
| 310 | */ |
| 311 | static void __init mpic_test_broken_ipi(struct mpic *mpic) |
| 312 | { |
| 313 | u32 r; |
| 314 | |
Zang Roy-r61911 | 7233593 | 2006-08-25 14:16:30 +1000 | [diff] [blame] | 315 | mpic_write(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0), MPIC_VECPRI_MASK); |
| 316 | r = mpic_read(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0)); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 317 | |
| 318 | if (r == le32_to_cpu(MPIC_VECPRI_MASK)) { |
| 319 | printk(KERN_INFO "mpic: Detected reversed IPI registers\n"); |
| 320 | mpic->flags |= MPIC_BROKEN_IPI; |
| 321 | } |
| 322 | } |
| 323 | |
Michael Ellerman | 6cfef5b | 2007-04-23 18:47:08 +1000 | [diff] [blame] | 324 | #ifdef CONFIG_MPIC_U3_HT_IRQS |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 325 | |
| 326 | /* Test if an interrupt is sourced from HyperTransport (used on broken U3s) |
| 327 | * to force the edge setting on the MPIC and do the ack workaround. |
| 328 | */ |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 329 | static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 330 | { |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 331 | if (source >= 128 || !mpic->fixups) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 332 | return 0; |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 333 | return mpic->fixups[source].base != NULL; |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 334 | } |
| 335 | |
Segher Boessenkool | c4b22f2 | 2005-12-13 18:04:29 +1100 | [diff] [blame] | 336 | |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 337 | static inline void mpic_ht_end_irq(struct mpic *mpic, unsigned int source) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 338 | { |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 339 | struct mpic_irq_fixup *fixup = &mpic->fixups[source]; |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 340 | |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 341 | if (fixup->applebase) { |
| 342 | unsigned int soff = (fixup->index >> 3) & ~3; |
| 343 | unsigned int mask = 1U << (fixup->index & 0x1f); |
| 344 | writel(mask, fixup->applebase + soff); |
| 345 | } else { |
| 346 | spin_lock(&mpic->fixup_lock); |
| 347 | writeb(0x11 + 2 * fixup->index, fixup->base + 2); |
| 348 | writel(fixup->data, fixup->base + 4); |
| 349 | spin_unlock(&mpic->fixup_lock); |
| 350 | } |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 351 | } |
| 352 | |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 353 | static void mpic_startup_ht_interrupt(struct mpic *mpic, unsigned int source, |
| 354 | unsigned int irqflags) |
| 355 | { |
| 356 | struct mpic_irq_fixup *fixup = &mpic->fixups[source]; |
| 357 | unsigned long flags; |
| 358 | u32 tmp; |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 359 | |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 360 | if (fixup->base == NULL) |
| 361 | return; |
| 362 | |
Benjamin Herrenschmidt | 06fe98e | 2006-07-10 04:44:43 -0700 | [diff] [blame] | 363 | DBG("startup_ht_interrupt(0x%x, 0x%x) index: %d\n", |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 364 | source, irqflags, fixup->index); |
| 365 | spin_lock_irqsave(&mpic->fixup_lock, flags); |
| 366 | /* Enable and configure */ |
| 367 | writeb(0x10 + 2 * fixup->index, fixup->base + 2); |
| 368 | tmp = readl(fixup->base + 4); |
| 369 | tmp &= ~(0x23U); |
| 370 | if (irqflags & IRQ_LEVEL) |
| 371 | tmp |= 0x22; |
| 372 | writel(tmp, fixup->base + 4); |
| 373 | spin_unlock_irqrestore(&mpic->fixup_lock, flags); |
Johannes Berg | 3669e93 | 2007-05-02 16:33:41 +1000 | [diff] [blame] | 374 | |
| 375 | #ifdef CONFIG_PM |
| 376 | /* use the lowest bit inverted to the actual HW, |
| 377 | * set if this fixup was enabled, clear otherwise */ |
| 378 | mpic->save_data[source].fixup_data = tmp | 1; |
| 379 | #endif |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 380 | } |
| 381 | |
| 382 | static void mpic_shutdown_ht_interrupt(struct mpic *mpic, unsigned int source, |
| 383 | unsigned int irqflags) |
| 384 | { |
| 385 | struct mpic_irq_fixup *fixup = &mpic->fixups[source]; |
| 386 | unsigned long flags; |
| 387 | u32 tmp; |
| 388 | |
| 389 | if (fixup->base == NULL) |
| 390 | return; |
| 391 | |
Benjamin Herrenschmidt | 06fe98e | 2006-07-10 04:44:43 -0700 | [diff] [blame] | 392 | DBG("shutdown_ht_interrupt(0x%x, 0x%x)\n", source, irqflags); |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 393 | |
| 394 | /* Disable */ |
| 395 | spin_lock_irqsave(&mpic->fixup_lock, flags); |
| 396 | writeb(0x10 + 2 * fixup->index, fixup->base + 2); |
| 397 | tmp = readl(fixup->base + 4); |
Segher Boessenkool | 72b1381 | 2006-02-17 11:25:42 +0100 | [diff] [blame] | 398 | tmp |= 1; |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 399 | writel(tmp, fixup->base + 4); |
| 400 | spin_unlock_irqrestore(&mpic->fixup_lock, flags); |
Johannes Berg | 3669e93 | 2007-05-02 16:33:41 +1000 | [diff] [blame] | 401 | |
| 402 | #ifdef CONFIG_PM |
| 403 | /* use the lowest bit inverted to the actual HW, |
| 404 | * set if this fixup was enabled, clear otherwise */ |
| 405 | mpic->save_data[source].fixup_data = tmp & ~1; |
| 406 | #endif |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 407 | } |
| 408 | |
Michael Ellerman | 812fd1f | 2007-05-08 12:58:36 +1000 | [diff] [blame] | 409 | #ifdef CONFIG_PCI_MSI |
| 410 | static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase, |
| 411 | unsigned int devfn) |
| 412 | { |
| 413 | u8 __iomem *base; |
| 414 | u8 pos, flags; |
| 415 | u64 addr = 0; |
| 416 | |
| 417 | for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0; |
| 418 | pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) { |
| 419 | u8 id = readb(devbase + pos + PCI_CAP_LIST_ID); |
| 420 | if (id == PCI_CAP_ID_HT) { |
| 421 | id = readb(devbase + pos + 3); |
| 422 | if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_MSI_MAPPING) |
| 423 | break; |
| 424 | } |
| 425 | } |
| 426 | |
| 427 | if (pos == 0) |
| 428 | return; |
| 429 | |
| 430 | base = devbase + pos; |
| 431 | |
| 432 | flags = readb(base + HT_MSI_FLAGS); |
| 433 | if (!(flags & HT_MSI_FLAGS_FIXED)) { |
| 434 | addr = readl(base + HT_MSI_ADDR_LO) & HT_MSI_ADDR_LO_MASK; |
| 435 | addr = addr | ((u64)readl(base + HT_MSI_ADDR_HI) << 32); |
| 436 | } |
| 437 | |
Ingo Molnar | fe33332 | 2009-01-06 14:26:03 +0000 | [diff] [blame] | 438 | printk(KERN_DEBUG "mpic: - HT:%02x.%x %s MSI mapping found @ 0x%llx\n", |
Michael Ellerman | 812fd1f | 2007-05-08 12:58:36 +1000 | [diff] [blame] | 439 | PCI_SLOT(devfn), PCI_FUNC(devfn), |
| 440 | flags & HT_MSI_FLAGS_ENABLE ? "enabled" : "disabled", addr); |
| 441 | |
| 442 | if (!(flags & HT_MSI_FLAGS_ENABLE)) |
| 443 | writeb(flags | HT_MSI_FLAGS_ENABLE, base + HT_MSI_FLAGS); |
| 444 | } |
| 445 | #else |
| 446 | static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase, |
| 447 | unsigned int devfn) |
| 448 | { |
| 449 | return; |
| 450 | } |
| 451 | #endif |
| 452 | |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 453 | static void __init mpic_scan_ht_pic(struct mpic *mpic, u8 __iomem *devbase, |
| 454 | unsigned int devfn, u32 vdid) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 455 | { |
Segher Boessenkool | c4b22f2 | 2005-12-13 18:04:29 +1100 | [diff] [blame] | 456 | int i, irq, n; |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 457 | u8 __iomem *base; |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 458 | u32 tmp; |
Segher Boessenkool | c4b22f2 | 2005-12-13 18:04:29 +1100 | [diff] [blame] | 459 | u8 pos; |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 460 | |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 461 | for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0; |
| 462 | pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) { |
| 463 | u8 id = readb(devbase + pos + PCI_CAP_LIST_ID); |
Brice Goglin | 46ff346 | 2006-08-31 01:55:24 -0400 | [diff] [blame] | 464 | if (id == PCI_CAP_ID_HT) { |
Segher Boessenkool | c4b22f2 | 2005-12-13 18:04:29 +1100 | [diff] [blame] | 465 | id = readb(devbase + pos + 3); |
Michael Ellerman | beb7cc8 | 2006-11-22 18:26:22 +1100 | [diff] [blame] | 466 | if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_IRQ) |
Segher Boessenkool | c4b22f2 | 2005-12-13 18:04:29 +1100 | [diff] [blame] | 467 | break; |
| 468 | } |
| 469 | } |
| 470 | if (pos == 0) |
| 471 | return; |
| 472 | |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 473 | base = devbase + pos; |
| 474 | writeb(0x01, base + 2); |
| 475 | n = (readl(base + 4) >> 16) & 0xff; |
Segher Boessenkool | c4b22f2 | 2005-12-13 18:04:29 +1100 | [diff] [blame] | 476 | |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 477 | printk(KERN_INFO "mpic: - HT:%02x.%x [0x%02x] vendor %04x device %04x" |
| 478 | " has %d irqs\n", |
| 479 | devfn >> 3, devfn & 0x7, pos, vdid & 0xffff, vdid >> 16, n + 1); |
Segher Boessenkool | c4b22f2 | 2005-12-13 18:04:29 +1100 | [diff] [blame] | 480 | |
| 481 | for (i = 0; i <= n; i++) { |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 482 | writeb(0x10 + 2 * i, base + 2); |
| 483 | tmp = readl(base + 4); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 484 | irq = (tmp >> 16) & 0xff; |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 485 | DBG("HT PIC index 0x%x, irq 0x%x, tmp: %08x\n", i, irq, tmp); |
| 486 | /* mask it , will be unmasked later */ |
| 487 | tmp |= 0x1; |
| 488 | writel(tmp, base + 4); |
| 489 | mpic->fixups[irq].index = i; |
| 490 | mpic->fixups[irq].base = base; |
| 491 | /* Apple HT PIC has a non-standard way of doing EOIs */ |
| 492 | if ((vdid & 0xffff) == 0x106b) |
| 493 | mpic->fixups[irq].applebase = devbase + 0x60; |
| 494 | else |
| 495 | mpic->fixups[irq].applebase = NULL; |
| 496 | writeb(0x11 + 2 * i, base + 2); |
| 497 | mpic->fixups[irq].data = readl(base + 4) | 0x80000000; |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 498 | } |
| 499 | } |
| 500 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 501 | |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 502 | static void __init mpic_scan_ht_pics(struct mpic *mpic) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 503 | { |
| 504 | unsigned int devfn; |
| 505 | u8 __iomem *cfgspace; |
| 506 | |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 507 | printk(KERN_INFO "mpic: Setting up HT PICs workarounds for U3/U4\n"); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 508 | |
| 509 | /* Allocate fixups array */ |
| 510 | mpic->fixups = alloc_bootmem(128 * sizeof(struct mpic_irq_fixup)); |
| 511 | BUG_ON(mpic->fixups == NULL); |
| 512 | memset(mpic->fixups, 0, 128 * sizeof(struct mpic_irq_fixup)); |
| 513 | |
| 514 | /* Init spinlock */ |
| 515 | spin_lock_init(&mpic->fixup_lock); |
| 516 | |
Segher Boessenkool | c4b22f2 | 2005-12-13 18:04:29 +1100 | [diff] [blame] | 517 | /* Map U3 config space. We assume all IO-APICs are on the primary bus |
| 518 | * so we only need to map 64kB. |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 519 | */ |
Segher Boessenkool | c4b22f2 | 2005-12-13 18:04:29 +1100 | [diff] [blame] | 520 | cfgspace = ioremap(0xf2000000, 0x10000); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 521 | BUG_ON(cfgspace == NULL); |
| 522 | |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 523 | /* Now we scan all slots. We do a very quick scan, we read the header |
| 524 | * type, vendor ID and device ID only, that's plenty enough |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 525 | */ |
Segher Boessenkool | c4b22f2 | 2005-12-13 18:04:29 +1100 | [diff] [blame] | 526 | for (devfn = 0; devfn < 0x100; devfn++) { |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 527 | u8 __iomem *devbase = cfgspace + (devfn << 8); |
| 528 | u8 hdr_type = readb(devbase + PCI_HEADER_TYPE); |
| 529 | u32 l = readl(devbase + PCI_VENDOR_ID); |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 530 | u16 s; |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 531 | |
| 532 | DBG("devfn %x, l: %x\n", devfn, l); |
| 533 | |
| 534 | /* If no device, skip */ |
| 535 | if (l == 0xffffffff || l == 0x00000000 || |
| 536 | l == 0x0000ffff || l == 0xffff0000) |
| 537 | goto next; |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 538 | /* Check if is supports capability lists */ |
| 539 | s = readw(devbase + PCI_STATUS); |
| 540 | if (!(s & PCI_STATUS_CAP_LIST)) |
| 541 | goto next; |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 542 | |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 543 | mpic_scan_ht_pic(mpic, devbase, devfn, l); |
Michael Ellerman | 812fd1f | 2007-05-08 12:58:36 +1000 | [diff] [blame] | 544 | mpic_scan_ht_msi(mpic, devbase, devfn); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 545 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 546 | next: |
| 547 | /* next device, if function 0 */ |
Segher Boessenkool | c4b22f2 | 2005-12-13 18:04:29 +1100 | [diff] [blame] | 548 | if (PCI_FUNC(devfn) == 0 && (hdr_type & 0x80) == 0) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 549 | devfn += 7; |
| 550 | } |
| 551 | } |
| 552 | |
Michael Ellerman | 6cfef5b | 2007-04-23 18:47:08 +1000 | [diff] [blame] | 553 | #else /* CONFIG_MPIC_U3_HT_IRQS */ |
Benjamin Herrenschmidt | 6e99e45 | 2006-07-10 04:44:42 -0700 | [diff] [blame] | 554 | |
| 555 | static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source) |
| 556 | { |
| 557 | return 0; |
| 558 | } |
| 559 | |
| 560 | static void __init mpic_scan_ht_pics(struct mpic *mpic) |
| 561 | { |
| 562 | } |
| 563 | |
Michael Ellerman | 6cfef5b | 2007-04-23 18:47:08 +1000 | [diff] [blame] | 564 | #endif /* CONFIG_MPIC_U3_HT_IRQS */ |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 565 | |
Kumar Gala | 3c10c9c | 2008-10-28 18:01:39 +0000 | [diff] [blame] | 566 | #ifdef CONFIG_SMP |
| 567 | static int irq_choose_cpu(unsigned int virt_irq) |
| 568 | { |
Mike Travis | e65e49d | 2009-01-12 15:27:13 -0800 | [diff] [blame] | 569 | cpumask_t mask; |
Kumar Gala | 3c10c9c | 2008-10-28 18:01:39 +0000 | [diff] [blame] | 570 | int cpuid; |
| 571 | |
Mike Travis | e65e49d | 2009-01-12 15:27:13 -0800 | [diff] [blame] | 572 | cpumask_copy(&mask, irq_desc[virt_irq].affinity); |
Kumar Gala | 3c10c9c | 2008-10-28 18:01:39 +0000 | [diff] [blame] | 573 | if (cpus_equal(mask, CPU_MASK_ALL)) { |
| 574 | static int irq_rover; |
| 575 | static DEFINE_SPINLOCK(irq_rover_lock); |
| 576 | unsigned long flags; |
| 577 | |
| 578 | /* Round-robin distribution... */ |
| 579 | do_round_robin: |
| 580 | spin_lock_irqsave(&irq_rover_lock, flags); |
| 581 | |
| 582 | while (!cpu_online(irq_rover)) { |
| 583 | if (++irq_rover >= NR_CPUS) |
| 584 | irq_rover = 0; |
| 585 | } |
| 586 | cpuid = irq_rover; |
| 587 | do { |
| 588 | if (++irq_rover >= NR_CPUS) |
| 589 | irq_rover = 0; |
| 590 | } while (!cpu_online(irq_rover)); |
| 591 | |
| 592 | spin_unlock_irqrestore(&irq_rover_lock, flags); |
| 593 | } else { |
| 594 | cpumask_t tmp; |
| 595 | |
| 596 | cpus_and(tmp, cpu_online_map, mask); |
| 597 | |
| 598 | if (cpus_empty(tmp)) |
| 599 | goto do_round_robin; |
| 600 | |
| 601 | cpuid = first_cpu(tmp); |
| 602 | } |
| 603 | |
Kumar Gala | 7a0d794 | 2008-12-02 13:37:01 -0600 | [diff] [blame] | 604 | return get_hard_smp_processor_id(cpuid); |
Kumar Gala | 3c10c9c | 2008-10-28 18:01:39 +0000 | [diff] [blame] | 605 | } |
| 606 | #else |
| 607 | static int irq_choose_cpu(unsigned int virt_irq) |
| 608 | { |
| 609 | return hard_smp_processor_id(); |
| 610 | } |
| 611 | #endif |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 612 | |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 613 | #define mpic_irq_to_hw(virq) ((unsigned int)irq_map[virq].hwirq) |
| 614 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 615 | /* Find an mpic associated with a given linux interrupt */ |
| 616 | static struct mpic *mpic_find(unsigned int irq, unsigned int *is_ipi) |
| 617 | { |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 618 | unsigned int src = mpic_irq_to_hw(irq); |
Olof Johansson | 7df2457 | 2007-01-28 23:33:18 -0600 | [diff] [blame] | 619 | struct mpic *mpic; |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 620 | |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 621 | if (irq < NUM_ISA_INTERRUPTS) |
| 622 | return NULL; |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 623 | |
Olof Johansson | 7df2457 | 2007-01-28 23:33:18 -0600 | [diff] [blame] | 624 | mpic = irq_desc[irq].chip_data; |
| 625 | |
| 626 | if (is_ipi) |
| 627 | *is_ipi = (src >= mpic->ipi_vecs[0] && |
| 628 | src <= mpic->ipi_vecs[3]); |
| 629 | |
| 630 | return mpic; |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 631 | } |
| 632 | |
| 633 | /* Convert a cpu mask from logical to physical cpu numbers. */ |
| 634 | static inline u32 mpic_physmask(u32 cpumask) |
| 635 | { |
| 636 | int i; |
| 637 | u32 mask = 0; |
| 638 | |
| 639 | for (i = 0; i < NR_CPUS; ++i, cpumask >>= 1) |
| 640 | mask |= (cpumask & 1) << get_hard_smp_processor_id(i); |
| 641 | return mask; |
| 642 | } |
| 643 | |
| 644 | #ifdef CONFIG_SMP |
| 645 | /* Get the mpic structure from the IPI number */ |
| 646 | static inline struct mpic * mpic_from_ipi(unsigned int ipi) |
| 647 | { |
Benjamin Herrenschmidt | b9e5b4e | 2006-07-03 19:32:51 +1000 | [diff] [blame] | 648 | return irq_desc[ipi].chip_data; |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 649 | } |
| 650 | #endif |
| 651 | |
| 652 | /* Get the mpic structure from the irq number */ |
| 653 | static inline struct mpic * mpic_from_irq(unsigned int irq) |
| 654 | { |
Benjamin Herrenschmidt | b9e5b4e | 2006-07-03 19:32:51 +1000 | [diff] [blame] | 655 | return irq_desc[irq].chip_data; |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 656 | } |
| 657 | |
| 658 | /* Send an EOI */ |
| 659 | static inline void mpic_eoi(struct mpic *mpic) |
| 660 | { |
Zang Roy-r61911 | 7233593 | 2006-08-25 14:16:30 +1000 | [diff] [blame] | 661 | mpic_cpu_write(MPIC_INFO(CPU_EOI), 0); |
| 662 | (void)mpic_cpu_read(MPIC_INFO(CPU_WHOAMI)); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 663 | } |
| 664 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 665 | /* |
| 666 | * Linux descriptor level callbacks |
| 667 | */ |
| 668 | |
| 669 | |
Michael Ellerman | 05af7bd | 2007-05-08 12:58:37 +1000 | [diff] [blame] | 670 | void mpic_unmask_irq(unsigned int irq) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 671 | { |
| 672 | unsigned int loops = 100000; |
| 673 | struct mpic *mpic = mpic_from_irq(irq); |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 674 | unsigned int src = mpic_irq_to_hw(irq); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 675 | |
Paul Mackerras | bd561c7 | 2005-10-26 21:55:33 +1000 | [diff] [blame] | 676 | DBG("%p: %s: enable_irq: %d (src %d)\n", mpic, mpic->name, irq, src); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 677 | |
Zang Roy-r61911 | 7233593 | 2006-08-25 14:16:30 +1000 | [diff] [blame] | 678 | mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), |
| 679 | mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & |
Benjamin Herrenschmidt | e535664 | 2005-11-18 17:18:15 +1100 | [diff] [blame] | 680 | ~MPIC_VECPRI_MASK); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 681 | /* make sure mask gets to controller before we return to user */ |
| 682 | do { |
| 683 | if (!loops--) { |
| 684 | printk(KERN_ERR "mpic_enable_irq timeout\n"); |
| 685 | break; |
| 686 | } |
Zang Roy-r61911 | 7233593 | 2006-08-25 14:16:30 +1000 | [diff] [blame] | 687 | } while(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK); |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 688 | } |
| 689 | |
Michael Ellerman | 05af7bd | 2007-05-08 12:58:37 +1000 | [diff] [blame] | 690 | void mpic_mask_irq(unsigned int irq) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 691 | { |
| 692 | unsigned int loops = 100000; |
| 693 | struct mpic *mpic = mpic_from_irq(irq); |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 694 | unsigned int src = mpic_irq_to_hw(irq); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 695 | |
| 696 | DBG("%s: disable_irq: %d (src %d)\n", mpic->name, irq, src); |
| 697 | |
Zang Roy-r61911 | 7233593 | 2006-08-25 14:16:30 +1000 | [diff] [blame] | 698 | mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), |
| 699 | mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) | |
Benjamin Herrenschmidt | e535664 | 2005-11-18 17:18:15 +1100 | [diff] [blame] | 700 | MPIC_VECPRI_MASK); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 701 | |
| 702 | /* make sure mask gets to controller before we return to user */ |
| 703 | do { |
| 704 | if (!loops--) { |
| 705 | printk(KERN_ERR "mpic_enable_irq timeout\n"); |
| 706 | break; |
| 707 | } |
Zang Roy-r61911 | 7233593 | 2006-08-25 14:16:30 +1000 | [diff] [blame] | 708 | } while(!(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK)); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 709 | } |
| 710 | |
Michael Ellerman | 05af7bd | 2007-05-08 12:58:37 +1000 | [diff] [blame] | 711 | void mpic_end_irq(unsigned int irq) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 712 | { |
| 713 | struct mpic *mpic = mpic_from_irq(irq); |
| 714 | |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 715 | #ifdef DEBUG_IRQ |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 716 | DBG("%s: end_irq: %d\n", mpic->name, irq); |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 717 | #endif |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 718 | /* We always EOI on end_irq() even for edge interrupts since that |
| 719 | * should only lower the priority, the MPIC should have properly |
| 720 | * latched another edge interrupt coming in anyway |
| 721 | */ |
| 722 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 723 | mpic_eoi(mpic); |
| 724 | } |
| 725 | |
Michael Ellerman | 6cfef5b | 2007-04-23 18:47:08 +1000 | [diff] [blame] | 726 | #ifdef CONFIG_MPIC_U3_HT_IRQS |
Benjamin Herrenschmidt | b9e5b4e | 2006-07-03 19:32:51 +1000 | [diff] [blame] | 727 | |
| 728 | static void mpic_unmask_ht_irq(unsigned int irq) |
| 729 | { |
| 730 | struct mpic *mpic = mpic_from_irq(irq); |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 731 | unsigned int src = mpic_irq_to_hw(irq); |
Benjamin Herrenschmidt | b9e5b4e | 2006-07-03 19:32:51 +1000 | [diff] [blame] | 732 | |
| 733 | mpic_unmask_irq(irq); |
| 734 | |
| 735 | if (irq_desc[irq].status & IRQ_LEVEL) |
| 736 | mpic_ht_end_irq(mpic, src); |
| 737 | } |
| 738 | |
| 739 | static unsigned int mpic_startup_ht_irq(unsigned int irq) |
| 740 | { |
| 741 | struct mpic *mpic = mpic_from_irq(irq); |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 742 | unsigned int src = mpic_irq_to_hw(irq); |
Benjamin Herrenschmidt | b9e5b4e | 2006-07-03 19:32:51 +1000 | [diff] [blame] | 743 | |
| 744 | mpic_unmask_irq(irq); |
| 745 | mpic_startup_ht_interrupt(mpic, src, irq_desc[irq].status); |
| 746 | |
| 747 | return 0; |
| 748 | } |
| 749 | |
| 750 | static void mpic_shutdown_ht_irq(unsigned int irq) |
| 751 | { |
| 752 | struct mpic *mpic = mpic_from_irq(irq); |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 753 | unsigned int src = mpic_irq_to_hw(irq); |
Benjamin Herrenschmidt | b9e5b4e | 2006-07-03 19:32:51 +1000 | [diff] [blame] | 754 | |
| 755 | mpic_shutdown_ht_interrupt(mpic, src, irq_desc[irq].status); |
| 756 | mpic_mask_irq(irq); |
| 757 | } |
| 758 | |
| 759 | static void mpic_end_ht_irq(unsigned int irq) |
| 760 | { |
| 761 | struct mpic *mpic = mpic_from_irq(irq); |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 762 | unsigned int src = mpic_irq_to_hw(irq); |
Benjamin Herrenschmidt | b9e5b4e | 2006-07-03 19:32:51 +1000 | [diff] [blame] | 763 | |
| 764 | #ifdef DEBUG_IRQ |
| 765 | DBG("%s: end_irq: %d\n", mpic->name, irq); |
| 766 | #endif |
| 767 | /* We always EOI on end_irq() even for edge interrupts since that |
| 768 | * should only lower the priority, the MPIC should have properly |
| 769 | * latched another edge interrupt coming in anyway |
| 770 | */ |
| 771 | |
| 772 | if (irq_desc[irq].status & IRQ_LEVEL) |
| 773 | mpic_ht_end_irq(mpic, src); |
| 774 | mpic_eoi(mpic); |
| 775 | } |
Michael Ellerman | 6cfef5b | 2007-04-23 18:47:08 +1000 | [diff] [blame] | 776 | #endif /* !CONFIG_MPIC_U3_HT_IRQS */ |
Benjamin Herrenschmidt | b9e5b4e | 2006-07-03 19:32:51 +1000 | [diff] [blame] | 777 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 778 | #ifdef CONFIG_SMP |
| 779 | |
Benjamin Herrenschmidt | b9e5b4e | 2006-07-03 19:32:51 +1000 | [diff] [blame] | 780 | static void mpic_unmask_ipi(unsigned int irq) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 781 | { |
| 782 | struct mpic *mpic = mpic_from_ipi(irq); |
Olof Johansson | 7df2457 | 2007-01-28 23:33:18 -0600 | [diff] [blame] | 783 | unsigned int src = mpic_irq_to_hw(irq) - mpic->ipi_vecs[0]; |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 784 | |
| 785 | DBG("%s: enable_ipi: %d (ipi %d)\n", mpic->name, irq, src); |
| 786 | mpic_ipi_write(src, mpic_ipi_read(src) & ~MPIC_VECPRI_MASK); |
| 787 | } |
| 788 | |
Benjamin Herrenschmidt | b9e5b4e | 2006-07-03 19:32:51 +1000 | [diff] [blame] | 789 | static void mpic_mask_ipi(unsigned int irq) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 790 | { |
| 791 | /* NEVER disable an IPI... that's just plain wrong! */ |
| 792 | } |
| 793 | |
| 794 | static void mpic_end_ipi(unsigned int irq) |
| 795 | { |
| 796 | struct mpic *mpic = mpic_from_ipi(irq); |
| 797 | |
| 798 | /* |
| 799 | * IPIs are marked IRQ_PER_CPU. This has the side effect of |
| 800 | * preventing the IRQ_PENDING/IRQ_INPROGRESS logic from |
| 801 | * applying to them. We EOI them late to avoid re-entering. |
Thomas Gleixner | 6714465 | 2006-07-01 19:29:22 -0700 | [diff] [blame] | 802 | * We mark IPI's with IRQF_DISABLED as they must run with |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 803 | * irqs disabled. |
| 804 | */ |
| 805 | mpic_eoi(mpic); |
| 806 | } |
| 807 | |
| 808 | #endif /* CONFIG_SMP */ |
| 809 | |
Yinghai Lu | d5dedd4 | 2009-04-27 17:59:21 -0700 | [diff] [blame^] | 810 | int mpic_set_affinity(unsigned int irq, const struct cpumask *cpumask) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 811 | { |
| 812 | struct mpic *mpic = mpic_from_irq(irq); |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 813 | unsigned int src = mpic_irq_to_hw(irq); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 814 | |
Kumar Gala | 3c10c9c | 2008-10-28 18:01:39 +0000 | [diff] [blame] | 815 | if (mpic->flags & MPIC_SINGLE_DEST_CPU) { |
| 816 | int cpuid = irq_choose_cpu(irq); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 817 | |
Kumar Gala | 3c10c9c | 2008-10-28 18:01:39 +0000 | [diff] [blame] | 818 | mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 1 << cpuid); |
| 819 | } else { |
| 820 | cpumask_t tmp; |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 821 | |
Rusty Russell | 0de2652 | 2008-12-13 21:20:26 +1030 | [diff] [blame] | 822 | cpumask_and(&tmp, cpumask, cpu_online_mask); |
Kumar Gala | 3c10c9c | 2008-10-28 18:01:39 +0000 | [diff] [blame] | 823 | |
| 824 | mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), |
| 825 | mpic_physmask(cpus_addr(tmp)[0])); |
| 826 | } |
Yinghai Lu | d5dedd4 | 2009-04-27 17:59:21 -0700 | [diff] [blame^] | 827 | |
| 828 | return 0; |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 829 | } |
| 830 | |
Zang Roy-r61911 | 7233593 | 2006-08-25 14:16:30 +1000 | [diff] [blame] | 831 | static unsigned int mpic_type_to_vecpri(struct mpic *mpic, unsigned int type) |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 832 | { |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 833 | /* Now convert sense value */ |
Benjamin Herrenschmidt | 6e99e45 | 2006-07-10 04:44:42 -0700 | [diff] [blame] | 834 | switch(type & IRQ_TYPE_SENSE_MASK) { |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 835 | case IRQ_TYPE_EDGE_RISING: |
Zang Roy-r61911 | 7233593 | 2006-08-25 14:16:30 +1000 | [diff] [blame] | 836 | return MPIC_INFO(VECPRI_SENSE_EDGE) | |
| 837 | MPIC_INFO(VECPRI_POLARITY_POSITIVE); |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 838 | case IRQ_TYPE_EDGE_FALLING: |
Benjamin Herrenschmidt | 6e99e45 | 2006-07-10 04:44:42 -0700 | [diff] [blame] | 839 | case IRQ_TYPE_EDGE_BOTH: |
Zang Roy-r61911 | 7233593 | 2006-08-25 14:16:30 +1000 | [diff] [blame] | 840 | return MPIC_INFO(VECPRI_SENSE_EDGE) | |
| 841 | MPIC_INFO(VECPRI_POLARITY_NEGATIVE); |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 842 | case IRQ_TYPE_LEVEL_HIGH: |
Zang Roy-r61911 | 7233593 | 2006-08-25 14:16:30 +1000 | [diff] [blame] | 843 | return MPIC_INFO(VECPRI_SENSE_LEVEL) | |
| 844 | MPIC_INFO(VECPRI_POLARITY_POSITIVE); |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 845 | case IRQ_TYPE_LEVEL_LOW: |
| 846 | default: |
Zang Roy-r61911 | 7233593 | 2006-08-25 14:16:30 +1000 | [diff] [blame] | 847 | return MPIC_INFO(VECPRI_SENSE_LEVEL) | |
| 848 | MPIC_INFO(VECPRI_POLARITY_NEGATIVE); |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 849 | } |
Benjamin Herrenschmidt | 6e99e45 | 2006-07-10 04:44:42 -0700 | [diff] [blame] | 850 | } |
| 851 | |
Michael Ellerman | 05af7bd | 2007-05-08 12:58:37 +1000 | [diff] [blame] | 852 | int mpic_set_irq_type(unsigned int virq, unsigned int flow_type) |
Benjamin Herrenschmidt | 6e99e45 | 2006-07-10 04:44:42 -0700 | [diff] [blame] | 853 | { |
| 854 | struct mpic *mpic = mpic_from_irq(virq); |
| 855 | unsigned int src = mpic_irq_to_hw(virq); |
| 856 | struct irq_desc *desc = get_irq_desc(virq); |
| 857 | unsigned int vecpri, vold, vnew; |
| 858 | |
Benjamin Herrenschmidt | 06fe98e | 2006-07-10 04:44:43 -0700 | [diff] [blame] | 859 | DBG("mpic: set_irq_type(mpic:@%p,virq:%d,src:0x%x,type:0x%x)\n", |
| 860 | mpic, virq, src, flow_type); |
Benjamin Herrenschmidt | 6e99e45 | 2006-07-10 04:44:42 -0700 | [diff] [blame] | 861 | |
| 862 | if (src >= mpic->irq_count) |
| 863 | return -EINVAL; |
| 864 | |
| 865 | if (flow_type == IRQ_TYPE_NONE) |
| 866 | if (mpic->senses && src < mpic->senses_count) |
| 867 | flow_type = mpic->senses[src]; |
| 868 | if (flow_type == IRQ_TYPE_NONE) |
| 869 | flow_type = IRQ_TYPE_LEVEL_LOW; |
| 870 | |
| 871 | desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL); |
| 872 | desc->status |= flow_type & IRQ_TYPE_SENSE_MASK; |
| 873 | if (flow_type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) |
| 874 | desc->status |= IRQ_LEVEL; |
| 875 | |
| 876 | if (mpic_is_ht_interrupt(mpic, src)) |
| 877 | vecpri = MPIC_VECPRI_POLARITY_POSITIVE | |
| 878 | MPIC_VECPRI_SENSE_EDGE; |
| 879 | else |
Zang Roy-r61911 | 7233593 | 2006-08-25 14:16:30 +1000 | [diff] [blame] | 880 | vecpri = mpic_type_to_vecpri(mpic, flow_type); |
Benjamin Herrenschmidt | 6e99e45 | 2006-07-10 04:44:42 -0700 | [diff] [blame] | 881 | |
Zang Roy-r61911 | 7233593 | 2006-08-25 14:16:30 +1000 | [diff] [blame] | 882 | vold = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)); |
| 883 | vnew = vold & ~(MPIC_INFO(VECPRI_POLARITY_MASK) | |
| 884 | MPIC_INFO(VECPRI_SENSE_MASK)); |
Benjamin Herrenschmidt | 6e99e45 | 2006-07-10 04:44:42 -0700 | [diff] [blame] | 885 | vnew |= vecpri; |
| 886 | if (vold != vnew) |
Zang Roy-r61911 | 7233593 | 2006-08-25 14:16:30 +1000 | [diff] [blame] | 887 | mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vnew); |
Benjamin Herrenschmidt | 6e99e45 | 2006-07-10 04:44:42 -0700 | [diff] [blame] | 888 | |
| 889 | return 0; |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 890 | } |
| 891 | |
Olof Johansson | 38958dd | 2007-12-12 17:44:46 +1100 | [diff] [blame] | 892 | void mpic_set_vector(unsigned int virq, unsigned int vector) |
| 893 | { |
| 894 | struct mpic *mpic = mpic_from_irq(virq); |
| 895 | unsigned int src = mpic_irq_to_hw(virq); |
| 896 | unsigned int vecpri; |
| 897 | |
| 898 | DBG("mpic: set_vector(mpic:@%p,virq:%d,src:%d,vector:0x%x)\n", |
| 899 | mpic, virq, src, vector); |
| 900 | |
| 901 | if (src >= mpic->irq_count) |
| 902 | return; |
| 903 | |
| 904 | vecpri = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)); |
| 905 | vecpri = vecpri & ~MPIC_INFO(VECPRI_VECTOR_MASK); |
| 906 | vecpri |= vector; |
| 907 | mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vecpri); |
| 908 | } |
| 909 | |
Benjamin Herrenschmidt | b9e5b4e | 2006-07-03 19:32:51 +1000 | [diff] [blame] | 910 | static struct irq_chip mpic_irq_chip = { |
Benjamin Herrenschmidt | 6e99e45 | 2006-07-10 04:44:42 -0700 | [diff] [blame] | 911 | .mask = mpic_mask_irq, |
| 912 | .unmask = mpic_unmask_irq, |
| 913 | .eoi = mpic_end_irq, |
| 914 | .set_type = mpic_set_irq_type, |
Benjamin Herrenschmidt | b9e5b4e | 2006-07-03 19:32:51 +1000 | [diff] [blame] | 915 | }; |
| 916 | |
| 917 | #ifdef CONFIG_SMP |
| 918 | static struct irq_chip mpic_ipi_chip = { |
Benjamin Herrenschmidt | 6e99e45 | 2006-07-10 04:44:42 -0700 | [diff] [blame] | 919 | .mask = mpic_mask_ipi, |
| 920 | .unmask = mpic_unmask_ipi, |
| 921 | .eoi = mpic_end_ipi, |
Benjamin Herrenschmidt | b9e5b4e | 2006-07-03 19:32:51 +1000 | [diff] [blame] | 922 | }; |
| 923 | #endif /* CONFIG_SMP */ |
| 924 | |
Michael Ellerman | 6cfef5b | 2007-04-23 18:47:08 +1000 | [diff] [blame] | 925 | #ifdef CONFIG_MPIC_U3_HT_IRQS |
Benjamin Herrenschmidt | b9e5b4e | 2006-07-03 19:32:51 +1000 | [diff] [blame] | 926 | static struct irq_chip mpic_irq_ht_chip = { |
| 927 | .startup = mpic_startup_ht_irq, |
| 928 | .shutdown = mpic_shutdown_ht_irq, |
| 929 | .mask = mpic_mask_irq, |
| 930 | .unmask = mpic_unmask_ht_irq, |
| 931 | .eoi = mpic_end_ht_irq, |
Benjamin Herrenschmidt | 6e99e45 | 2006-07-10 04:44:42 -0700 | [diff] [blame] | 932 | .set_type = mpic_set_irq_type, |
Benjamin Herrenschmidt | b9e5b4e | 2006-07-03 19:32:51 +1000 | [diff] [blame] | 933 | }; |
Michael Ellerman | 6cfef5b | 2007-04-23 18:47:08 +1000 | [diff] [blame] | 934 | #endif /* CONFIG_MPIC_U3_HT_IRQS */ |
Benjamin Herrenschmidt | b9e5b4e | 2006-07-03 19:32:51 +1000 | [diff] [blame] | 935 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 936 | |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 937 | static int mpic_host_match(struct irq_host *h, struct device_node *node) |
| 938 | { |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 939 | /* Exact match, unless mpic node is NULL */ |
Michael Ellerman | 52964f8 | 2007-08-28 18:47:54 +1000 | [diff] [blame] | 940 | return h->of_node == NULL || h->of_node == node; |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 941 | } |
| 942 | |
| 943 | static int mpic_host_map(struct irq_host *h, unsigned int virq, |
Benjamin Herrenschmidt | 6e99e45 | 2006-07-10 04:44:42 -0700 | [diff] [blame] | 944 | irq_hw_number_t hw) |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 945 | { |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 946 | struct mpic *mpic = h->host_data; |
Benjamin Herrenschmidt | 6e99e45 | 2006-07-10 04:44:42 -0700 | [diff] [blame] | 947 | struct irq_chip *chip; |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 948 | |
Benjamin Herrenschmidt | 06fe98e | 2006-07-10 04:44:43 -0700 | [diff] [blame] | 949 | DBG("mpic: map virq %d, hwirq 0x%lx\n", virq, hw); |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 950 | |
Olof Johansson | 7df2457 | 2007-01-28 23:33:18 -0600 | [diff] [blame] | 951 | if (hw == mpic->spurious_vec) |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 952 | return -EINVAL; |
Benjamin Herrenschmidt | 7fd7218 | 2007-07-21 09:55:21 +1000 | [diff] [blame] | 953 | if (mpic->protected && test_bit(hw, mpic->protected)) |
| 954 | return -EINVAL; |
Benjamin Herrenschmidt | 06fe98e | 2006-07-10 04:44:43 -0700 | [diff] [blame] | 955 | |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 956 | #ifdef CONFIG_SMP |
Olof Johansson | 7df2457 | 2007-01-28 23:33:18 -0600 | [diff] [blame] | 957 | else if (hw >= mpic->ipi_vecs[0]) { |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 958 | WARN_ON(!(mpic->flags & MPIC_PRIMARY)); |
| 959 | |
Benjamin Herrenschmidt | 06fe98e | 2006-07-10 04:44:43 -0700 | [diff] [blame] | 960 | DBG("mpic: mapping as IPI\n"); |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 961 | set_irq_chip_data(virq, mpic); |
| 962 | set_irq_chip_and_handler(virq, &mpic->hc_ipi, |
| 963 | handle_percpu_irq); |
| 964 | return 0; |
| 965 | } |
| 966 | #endif /* CONFIG_SMP */ |
| 967 | |
| 968 | if (hw >= mpic->irq_count) |
| 969 | return -EINVAL; |
| 970 | |
Michael Ellerman | a7de7c7 | 2007-05-08 12:58:36 +1000 | [diff] [blame] | 971 | mpic_msi_reserve_hwirq(mpic, hw); |
| 972 | |
Benjamin Herrenschmidt | 6e99e45 | 2006-07-10 04:44:42 -0700 | [diff] [blame] | 973 | /* Default chip */ |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 974 | chip = &mpic->hc_irq; |
| 975 | |
Michael Ellerman | 6cfef5b | 2007-04-23 18:47:08 +1000 | [diff] [blame] | 976 | #ifdef CONFIG_MPIC_U3_HT_IRQS |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 977 | /* Check for HT interrupts, override vecpri */ |
Benjamin Herrenschmidt | 6e99e45 | 2006-07-10 04:44:42 -0700 | [diff] [blame] | 978 | if (mpic_is_ht_interrupt(mpic, hw)) |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 979 | chip = &mpic->hc_ht_irq; |
Michael Ellerman | 6cfef5b | 2007-04-23 18:47:08 +1000 | [diff] [blame] | 980 | #endif /* CONFIG_MPIC_U3_HT_IRQS */ |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 981 | |
Benjamin Herrenschmidt | 06fe98e | 2006-07-10 04:44:43 -0700 | [diff] [blame] | 982 | DBG("mpic: mapping to irq chip @%p\n", chip); |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 983 | |
| 984 | set_irq_chip_data(virq, mpic); |
| 985 | set_irq_chip_and_handler(virq, chip, handle_fasteoi_irq); |
Benjamin Herrenschmidt | 6e99e45 | 2006-07-10 04:44:42 -0700 | [diff] [blame] | 986 | |
| 987 | /* Set default irq type */ |
| 988 | set_irq_type(virq, IRQ_TYPE_NONE); |
| 989 | |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 990 | return 0; |
| 991 | } |
| 992 | |
| 993 | static int mpic_host_xlate(struct irq_host *h, struct device_node *ct, |
| 994 | u32 *intspec, unsigned int intsize, |
| 995 | irq_hw_number_t *out_hwirq, unsigned int *out_flags) |
| 996 | |
| 997 | { |
| 998 | static unsigned char map_mpic_senses[4] = { |
| 999 | IRQ_TYPE_EDGE_RISING, |
| 1000 | IRQ_TYPE_LEVEL_LOW, |
| 1001 | IRQ_TYPE_LEVEL_HIGH, |
| 1002 | IRQ_TYPE_EDGE_FALLING, |
| 1003 | }; |
| 1004 | |
| 1005 | *out_hwirq = intspec[0]; |
Benjamin Herrenschmidt | 06fe98e | 2006-07-10 04:44:43 -0700 | [diff] [blame] | 1006 | if (intsize > 1) { |
| 1007 | u32 mask = 0x3; |
| 1008 | |
| 1009 | /* Apple invented a new race of encoding on machines with |
| 1010 | * an HT APIC. They encode, among others, the index within |
| 1011 | * the HT APIC. We don't care about it here since thankfully, |
| 1012 | * it appears that they have the APIC already properly |
| 1013 | * configured, and thus our current fixup code that reads the |
| 1014 | * APIC config works fine. However, we still need to mask out |
| 1015 | * bits in the specifier to make sure we only get bit 0 which |
| 1016 | * is the level/edge bit (the only sense bit exposed by Apple), |
| 1017 | * as their bit 1 means something else. |
| 1018 | */ |
| 1019 | if (machine_is(powermac)) |
| 1020 | mask = 0x1; |
| 1021 | *out_flags = map_mpic_senses[intspec[1] & mask]; |
| 1022 | } else |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 1023 | *out_flags = IRQ_TYPE_NONE; |
| 1024 | |
Benjamin Herrenschmidt | 06fe98e | 2006-07-10 04:44:43 -0700 | [diff] [blame] | 1025 | DBG("mpic: xlate (%d cells: 0x%08x 0x%08x) to line 0x%lx sense 0x%x\n", |
| 1026 | intsize, intspec[0], intspec[1], *out_hwirq, *out_flags); |
| 1027 | |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 1028 | return 0; |
| 1029 | } |
| 1030 | |
| 1031 | static struct irq_host_ops mpic_host_ops = { |
| 1032 | .match = mpic_host_match, |
| 1033 | .map = mpic_host_map, |
| 1034 | .xlate = mpic_host_xlate, |
| 1035 | }; |
| 1036 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1037 | /* |
| 1038 | * Exported functions |
| 1039 | */ |
| 1040 | |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 1041 | struct mpic * __init mpic_alloc(struct device_node *node, |
Benjamin Herrenschmidt | a959ff5 | 2006-11-11 17:24:56 +1100 | [diff] [blame] | 1042 | phys_addr_t phys_addr, |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1043 | unsigned int flags, |
| 1044 | unsigned int isu_size, |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1045 | unsigned int irq_count, |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1046 | const char *name) |
| 1047 | { |
| 1048 | struct mpic *mpic; |
Johannes Berg | d9d1063 | 2008-02-21 20:39:01 +1100 | [diff] [blame] | 1049 | u32 greg_feature; |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1050 | const char *vers; |
| 1051 | int i; |
Olof Johansson | 7df2457 | 2007-01-28 23:33:18 -0600 | [diff] [blame] | 1052 | int intvec_top; |
Benjamin Herrenschmidt | a959ff5 | 2006-11-11 17:24:56 +1100 | [diff] [blame] | 1053 | u64 paddr = phys_addr; |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1054 | |
| 1055 | mpic = alloc_bootmem(sizeof(struct mpic)); |
| 1056 | if (mpic == NULL) |
| 1057 | return NULL; |
| 1058 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1059 | memset(mpic, 0, sizeof(struct mpic)); |
| 1060 | mpic->name = name; |
| 1061 | |
Michael Ellerman | 19fc65b | 2008-05-26 12:12:32 +1000 | [diff] [blame] | 1062 | mpic->irqhost = irq_alloc_host(node, IRQ_HOST_MAP_LINEAR, |
Michael Ellerman | 52964f8 | 2007-08-28 18:47:54 +1000 | [diff] [blame] | 1063 | isu_size, &mpic_host_ops, |
Olof Johansson | 7df2457 | 2007-01-28 23:33:18 -0600 | [diff] [blame] | 1064 | flags & MPIC_LARGE_VECTORS ? 2048 : 256); |
Michael Ellerman | 19fc65b | 2008-05-26 12:12:32 +1000 | [diff] [blame] | 1065 | if (mpic->irqhost == NULL) |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 1066 | return NULL; |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 1067 | |
| 1068 | mpic->irqhost->host_data = mpic; |
Benjamin Herrenschmidt | b9e5b4e | 2006-07-03 19:32:51 +1000 | [diff] [blame] | 1069 | mpic->hc_irq = mpic_irq_chip; |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1070 | mpic->hc_irq.typename = name; |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1071 | if (flags & MPIC_PRIMARY) |
| 1072 | mpic->hc_irq.set_affinity = mpic_set_affinity; |
Michael Ellerman | 6cfef5b | 2007-04-23 18:47:08 +1000 | [diff] [blame] | 1073 | #ifdef CONFIG_MPIC_U3_HT_IRQS |
Benjamin Herrenschmidt | b9e5b4e | 2006-07-03 19:32:51 +1000 | [diff] [blame] | 1074 | mpic->hc_ht_irq = mpic_irq_ht_chip; |
| 1075 | mpic->hc_ht_irq.typename = name; |
| 1076 | if (flags & MPIC_PRIMARY) |
| 1077 | mpic->hc_ht_irq.set_affinity = mpic_set_affinity; |
Michael Ellerman | 6cfef5b | 2007-04-23 18:47:08 +1000 | [diff] [blame] | 1078 | #endif /* CONFIG_MPIC_U3_HT_IRQS */ |
Benjamin Herrenschmidt | fbf0274 | 2006-11-11 17:24:55 +1100 | [diff] [blame] | 1079 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1080 | #ifdef CONFIG_SMP |
Benjamin Herrenschmidt | b9e5b4e | 2006-07-03 19:32:51 +1000 | [diff] [blame] | 1081 | mpic->hc_ipi = mpic_ipi_chip; |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 1082 | mpic->hc_ipi.typename = name; |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1083 | #endif /* CONFIG_SMP */ |
| 1084 | |
| 1085 | mpic->flags = flags; |
| 1086 | mpic->isu_size = isu_size; |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1087 | mpic->irq_count = irq_count; |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1088 | mpic->num_sources = 0; /* so far */ |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1089 | |
Olof Johansson | 7df2457 | 2007-01-28 23:33:18 -0600 | [diff] [blame] | 1090 | if (flags & MPIC_LARGE_VECTORS) |
| 1091 | intvec_top = 2047; |
| 1092 | else |
| 1093 | intvec_top = 255; |
| 1094 | |
| 1095 | mpic->timer_vecs[0] = intvec_top - 8; |
| 1096 | mpic->timer_vecs[1] = intvec_top - 7; |
| 1097 | mpic->timer_vecs[2] = intvec_top - 6; |
| 1098 | mpic->timer_vecs[3] = intvec_top - 5; |
| 1099 | mpic->ipi_vecs[0] = intvec_top - 4; |
| 1100 | mpic->ipi_vecs[1] = intvec_top - 3; |
| 1101 | mpic->ipi_vecs[2] = intvec_top - 2; |
| 1102 | mpic->ipi_vecs[3] = intvec_top - 1; |
| 1103 | mpic->spurious_vec = intvec_top; |
| 1104 | |
Benjamin Herrenschmidt | a959ff5 | 2006-11-11 17:24:56 +1100 | [diff] [blame] | 1105 | /* Check for "big-endian" in device-tree */ |
Stephen Rothwell | e2eb639 | 2007-04-03 22:26:41 +1000 | [diff] [blame] | 1106 | if (node && of_get_property(node, "big-endian", NULL) != NULL) |
Benjamin Herrenschmidt | a959ff5 | 2006-11-11 17:24:56 +1100 | [diff] [blame] | 1107 | mpic->flags |= MPIC_BIG_ENDIAN; |
| 1108 | |
Benjamin Herrenschmidt | 7fd7218 | 2007-07-21 09:55:21 +1000 | [diff] [blame] | 1109 | /* Look for protected sources */ |
| 1110 | if (node) { |
Johannes Berg | d9d1063 | 2008-02-21 20:39:01 +1100 | [diff] [blame] | 1111 | int psize; |
| 1112 | unsigned int bits, mapsize; |
Benjamin Herrenschmidt | 7fd7218 | 2007-07-21 09:55:21 +1000 | [diff] [blame] | 1113 | const u32 *psrc = |
| 1114 | of_get_property(node, "protected-sources", &psize); |
| 1115 | if (psrc) { |
| 1116 | psize /= 4; |
| 1117 | bits = intvec_top + 1; |
| 1118 | mapsize = BITS_TO_LONGS(bits) * sizeof(unsigned long); |
| 1119 | mpic->protected = alloc_bootmem(mapsize); |
| 1120 | BUG_ON(mpic->protected == NULL); |
| 1121 | memset(mpic->protected, 0, mapsize); |
| 1122 | for (i = 0; i < psize; i++) { |
| 1123 | if (psrc[i] > intvec_top) |
| 1124 | continue; |
| 1125 | __set_bit(psrc[i], mpic->protected); |
| 1126 | } |
| 1127 | } |
| 1128 | } |
Benjamin Herrenschmidt | a959ff5 | 2006-11-11 17:24:56 +1100 | [diff] [blame] | 1129 | |
Zang Roy-r61911 | 7233593 | 2006-08-25 14:16:30 +1000 | [diff] [blame] | 1130 | #ifdef CONFIG_MPIC_WEIRD |
| 1131 | mpic->hw_set = mpic_infos[MPIC_GET_REGSET(flags)]; |
| 1132 | #endif |
| 1133 | |
Benjamin Herrenschmidt | fbf0274 | 2006-11-11 17:24:55 +1100 | [diff] [blame] | 1134 | /* default register type */ |
| 1135 | mpic->reg_type = (flags & MPIC_BIG_ENDIAN) ? |
| 1136 | mpic_access_mmio_be : mpic_access_mmio_le; |
| 1137 | |
Benjamin Herrenschmidt | a959ff5 | 2006-11-11 17:24:56 +1100 | [diff] [blame] | 1138 | /* If no physical address is passed in, a device-node is mandatory */ |
| 1139 | BUG_ON(paddr == 0 && node == NULL); |
| 1140 | |
| 1141 | /* If no physical address passed in, check if it's dcr based */ |
Michael Ellerman | 0411a5e | 2007-09-17 16:05:01 +1000 | [diff] [blame] | 1142 | if (paddr == 0 && of_get_property(node, "dcr-reg", NULL) != NULL) { |
Benjamin Herrenschmidt | fbf0274 | 2006-11-11 17:24:55 +1100 | [diff] [blame] | 1143 | #ifdef CONFIG_PPC_DCR |
Michael Ellerman | 0411a5e | 2007-09-17 16:05:01 +1000 | [diff] [blame] | 1144 | mpic->flags |= MPIC_USES_DCR; |
Benjamin Herrenschmidt | fbf0274 | 2006-11-11 17:24:55 +1100 | [diff] [blame] | 1145 | mpic->reg_type = mpic_access_dcr; |
Benjamin Herrenschmidt | fbf0274 | 2006-11-11 17:24:55 +1100 | [diff] [blame] | 1146 | #else |
Michael Ellerman | 0411a5e | 2007-09-17 16:05:01 +1000 | [diff] [blame] | 1147 | BUG(); |
Benjamin Herrenschmidt | fbf0274 | 2006-11-11 17:24:55 +1100 | [diff] [blame] | 1148 | #endif /* CONFIG_PPC_DCR */ |
Michael Ellerman | 0411a5e | 2007-09-17 16:05:01 +1000 | [diff] [blame] | 1149 | } |
Benjamin Herrenschmidt | fbf0274 | 2006-11-11 17:24:55 +1100 | [diff] [blame] | 1150 | |
Benjamin Herrenschmidt | a959ff5 | 2006-11-11 17:24:56 +1100 | [diff] [blame] | 1151 | /* If the MPIC is not DCR based, and no physical address was passed |
| 1152 | * in, try to obtain one |
| 1153 | */ |
| 1154 | if (paddr == 0 && !(mpic->flags & MPIC_USES_DCR)) { |
Johannes Berg | d9d1063 | 2008-02-21 20:39:01 +1100 | [diff] [blame] | 1155 | const u32 *reg = of_get_property(node, "reg", NULL); |
Benjamin Herrenschmidt | a959ff5 | 2006-11-11 17:24:56 +1100 | [diff] [blame] | 1156 | BUG_ON(reg == NULL); |
| 1157 | paddr = of_translate_address(node, reg); |
| 1158 | BUG_ON(paddr == OF_BAD_ADDR); |
| 1159 | } |
| 1160 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1161 | /* Map the global registers */ |
Benjamin Herrenschmidt | a959ff5 | 2006-11-11 17:24:56 +1100 | [diff] [blame] | 1162 | mpic_map(mpic, paddr, &mpic->gregs, MPIC_INFO(GREG_BASE), 0x1000); |
| 1163 | mpic_map(mpic, paddr, &mpic->tmregs, MPIC_INFO(TIMER_BASE), 0x1000); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1164 | |
| 1165 | /* Reset */ |
| 1166 | if (flags & MPIC_WANTS_RESET) { |
Zang Roy-r61911 | 7233593 | 2006-08-25 14:16:30 +1000 | [diff] [blame] | 1167 | mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), |
| 1168 | mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1169 | | MPIC_GREG_GCONF_RESET); |
Zang Roy-r61911 | 7233593 | 2006-08-25 14:16:30 +1000 | [diff] [blame] | 1170 | while( mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1171 | & MPIC_GREG_GCONF_RESET) |
| 1172 | mb(); |
| 1173 | } |
| 1174 | |
Kumar Gala | d91e4ea | 2009-01-07 15:53:29 -0600 | [diff] [blame] | 1175 | /* CoreInt */ |
| 1176 | if (flags & MPIC_ENABLE_COREINT) |
| 1177 | mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), |
| 1178 | mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) |
| 1179 | | MPIC_GREG_GCONF_COREINT); |
| 1180 | |
Olof Johansson | f365355 | 2007-12-20 13:11:18 -0600 | [diff] [blame] | 1181 | if (flags & MPIC_ENABLE_MCK) |
| 1182 | mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), |
| 1183 | mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) |
| 1184 | | MPIC_GREG_GCONF_MCK); |
| 1185 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1186 | /* Read feature register, calculate num CPUs and, for non-ISU |
| 1187 | * MPICs, num sources as well. On ISU MPICs, sources are counted |
| 1188 | * as ISUs are added |
| 1189 | */ |
Johannes Berg | d9d1063 | 2008-02-21 20:39:01 +1100 | [diff] [blame] | 1190 | greg_feature = mpic_read(mpic->gregs, MPIC_INFO(GREG_FEATURE_0)); |
| 1191 | mpic->num_cpus = ((greg_feature & MPIC_GREG_FEATURE_LAST_CPU_MASK) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1192 | >> MPIC_GREG_FEATURE_LAST_CPU_SHIFT) + 1; |
Anton Vorontsov | 5073e7e | 2008-05-24 04:40:00 +1000 | [diff] [blame] | 1193 | if (isu_size == 0) { |
Kumar Gala | 475ca39 | 2008-05-22 06:59:23 +1000 | [diff] [blame] | 1194 | if (flags & MPIC_BROKEN_FRR_NIRQS) |
| 1195 | mpic->num_sources = mpic->irq_count; |
| 1196 | else |
| 1197 | mpic->num_sources = |
| 1198 | ((greg_feature & MPIC_GREG_FEATURE_LAST_SRC_MASK) |
| 1199 | >> MPIC_GREG_FEATURE_LAST_SRC_SHIFT) + 1; |
Anton Vorontsov | 5073e7e | 2008-05-24 04:40:00 +1000 | [diff] [blame] | 1200 | } |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1201 | |
| 1202 | /* Map the per-CPU registers */ |
| 1203 | for (i = 0; i < mpic->num_cpus; i++) { |
Benjamin Herrenschmidt | a959ff5 | 2006-11-11 17:24:56 +1100 | [diff] [blame] | 1204 | mpic_map(mpic, paddr, &mpic->cpuregs[i], |
Benjamin Herrenschmidt | fbf0274 | 2006-11-11 17:24:55 +1100 | [diff] [blame] | 1205 | MPIC_INFO(CPU_BASE) + i * MPIC_INFO(CPU_STRIDE), |
| 1206 | 0x1000); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1207 | } |
| 1208 | |
| 1209 | /* Initialize main ISU if none provided */ |
| 1210 | if (mpic->isu_size == 0) { |
| 1211 | mpic->isu_size = mpic->num_sources; |
Benjamin Herrenschmidt | a959ff5 | 2006-11-11 17:24:56 +1100 | [diff] [blame] | 1212 | mpic_map(mpic, paddr, &mpic->isus[0], |
Benjamin Herrenschmidt | fbf0274 | 2006-11-11 17:24:55 +1100 | [diff] [blame] | 1213 | MPIC_INFO(IRQ_BASE), MPIC_INFO(IRQ_STRIDE) * mpic->isu_size); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1214 | } |
| 1215 | mpic->isu_shift = 1 + __ilog2(mpic->isu_size - 1); |
| 1216 | mpic->isu_mask = (1 << mpic->isu_shift) - 1; |
| 1217 | |
| 1218 | /* Display version */ |
Johannes Berg | d9d1063 | 2008-02-21 20:39:01 +1100 | [diff] [blame] | 1219 | switch (greg_feature & MPIC_GREG_FEATURE_VERSION_MASK) { |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1220 | case 1: |
| 1221 | vers = "1.0"; |
| 1222 | break; |
| 1223 | case 2: |
| 1224 | vers = "1.2"; |
| 1225 | break; |
| 1226 | case 3: |
| 1227 | vers = "1.3"; |
| 1228 | break; |
| 1229 | default: |
| 1230 | vers = "<unknown>"; |
| 1231 | break; |
| 1232 | } |
Benjamin Herrenschmidt | a959ff5 | 2006-11-11 17:24:56 +1100 | [diff] [blame] | 1233 | printk(KERN_INFO "mpic: Setting up MPIC \"%s\" version %s at %llx," |
| 1234 | " max %d CPUs\n", |
| 1235 | name, vers, (unsigned long long)paddr, mpic->num_cpus); |
| 1236 | printk(KERN_INFO "mpic: ISU size: %d, shift: %d, mask: %x\n", |
| 1237 | mpic->isu_size, mpic->isu_shift, mpic->isu_mask); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1238 | |
| 1239 | mpic->next = mpics; |
| 1240 | mpics = mpic; |
| 1241 | |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 1242 | if (flags & MPIC_PRIMARY) { |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1243 | mpic_primary = mpic; |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 1244 | irq_set_default_host(mpic->irqhost); |
| 1245 | } |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1246 | |
| 1247 | return mpic; |
| 1248 | } |
| 1249 | |
| 1250 | void __init mpic_assign_isu(struct mpic *mpic, unsigned int isu_num, |
Benjamin Herrenschmidt | a959ff5 | 2006-11-11 17:24:56 +1100 | [diff] [blame] | 1251 | phys_addr_t paddr) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1252 | { |
| 1253 | unsigned int isu_first = isu_num * mpic->isu_size; |
| 1254 | |
| 1255 | BUG_ON(isu_num >= MPIC_MAX_ISU); |
| 1256 | |
Benjamin Herrenschmidt | a959ff5 | 2006-11-11 17:24:56 +1100 | [diff] [blame] | 1257 | mpic_map(mpic, paddr, &mpic->isus[isu_num], 0, |
Benjamin Herrenschmidt | fbf0274 | 2006-11-11 17:24:55 +1100 | [diff] [blame] | 1258 | MPIC_INFO(IRQ_STRIDE) * mpic->isu_size); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1259 | if ((isu_first + mpic->isu_size) > mpic->num_sources) |
| 1260 | mpic->num_sources = isu_first + mpic->isu_size; |
| 1261 | } |
| 1262 | |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 1263 | void __init mpic_set_default_senses(struct mpic *mpic, u8 *senses, int count) |
| 1264 | { |
| 1265 | mpic->senses = senses; |
| 1266 | mpic->senses_count = count; |
| 1267 | } |
| 1268 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1269 | void __init mpic_init(struct mpic *mpic) |
| 1270 | { |
| 1271 | int i; |
Arnd Bergmann | cc353c3 | 2008-11-28 09:51:23 +0000 | [diff] [blame] | 1272 | int cpu; |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1273 | |
| 1274 | BUG_ON(mpic->num_sources == 0); |
| 1275 | |
| 1276 | printk(KERN_INFO "mpic: Initializing for %d sources\n", mpic->num_sources); |
| 1277 | |
| 1278 | /* Set current processor priority to max */ |
Zang Roy-r61911 | 7233593 | 2006-08-25 14:16:30 +1000 | [diff] [blame] | 1279 | mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1280 | |
| 1281 | /* Initialize timers: just disable them all */ |
| 1282 | for (i = 0; i < 4; i++) { |
| 1283 | mpic_write(mpic->tmregs, |
Zang Roy-r61911 | 7233593 | 2006-08-25 14:16:30 +1000 | [diff] [blame] | 1284 | i * MPIC_INFO(TIMER_STRIDE) + |
| 1285 | MPIC_INFO(TIMER_DESTINATION), 0); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1286 | mpic_write(mpic->tmregs, |
Zang Roy-r61911 | 7233593 | 2006-08-25 14:16:30 +1000 | [diff] [blame] | 1287 | i * MPIC_INFO(TIMER_STRIDE) + |
| 1288 | MPIC_INFO(TIMER_VECTOR_PRI), |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1289 | MPIC_VECPRI_MASK | |
Olof Johansson | 7df2457 | 2007-01-28 23:33:18 -0600 | [diff] [blame] | 1290 | (mpic->timer_vecs[0] + i)); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1291 | } |
| 1292 | |
| 1293 | /* Initialize IPIs to our reserved vectors and mark them disabled for now */ |
| 1294 | mpic_test_broken_ipi(mpic); |
| 1295 | for (i = 0; i < 4; i++) { |
| 1296 | mpic_ipi_write(i, |
| 1297 | MPIC_VECPRI_MASK | |
| 1298 | (10 << MPIC_VECPRI_PRIORITY_SHIFT) | |
Olof Johansson | 7df2457 | 2007-01-28 23:33:18 -0600 | [diff] [blame] | 1299 | (mpic->ipi_vecs[0] + i)); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1300 | } |
| 1301 | |
| 1302 | /* Initialize interrupt sources */ |
| 1303 | if (mpic->irq_count == 0) |
| 1304 | mpic->irq_count = mpic->num_sources; |
| 1305 | |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 1306 | /* Do the HT PIC fixups on U3 broken mpic */ |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1307 | DBG("MPIC flags: %x\n", mpic->flags); |
Michael Ellerman | 05af7bd | 2007-05-08 12:58:37 +1000 | [diff] [blame] | 1308 | if ((mpic->flags & MPIC_U3_HT_IRQS) && (mpic->flags & MPIC_PRIMARY)) { |
Johannes Berg | 3669e93 | 2007-05-02 16:33:41 +1000 | [diff] [blame] | 1309 | mpic_scan_ht_pics(mpic); |
Michael Ellerman | 05af7bd | 2007-05-08 12:58:37 +1000 | [diff] [blame] | 1310 | mpic_u3msi_init(mpic); |
| 1311 | } |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1312 | |
Olof Johansson | 38958dd | 2007-12-12 17:44:46 +1100 | [diff] [blame] | 1313 | mpic_pasemi_msi_init(mpic); |
| 1314 | |
Arnd Bergmann | cc353c3 | 2008-11-28 09:51:23 +0000 | [diff] [blame] | 1315 | if (mpic->flags & MPIC_PRIMARY) |
| 1316 | cpu = hard_smp_processor_id(); |
| 1317 | else |
| 1318 | cpu = 0; |
| 1319 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1320 | for (i = 0; i < mpic->num_sources; i++) { |
| 1321 | /* start with vector = source number, and masked */ |
Benjamin Herrenschmidt | 6e99e45 | 2006-07-10 04:44:42 -0700 | [diff] [blame] | 1322 | u32 vecpri = MPIC_VECPRI_MASK | i | |
| 1323 | (8 << MPIC_VECPRI_PRIORITY_SHIFT); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1324 | |
Benjamin Herrenschmidt | 7fd7218 | 2007-07-21 09:55:21 +1000 | [diff] [blame] | 1325 | /* check if protected */ |
| 1326 | if (mpic->protected && test_bit(i, mpic->protected)) |
| 1327 | continue; |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1328 | /* init hw */ |
Zang Roy-r61911 | 7233593 | 2006-08-25 14:16:30 +1000 | [diff] [blame] | 1329 | mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI), vecpri); |
Arnd Bergmann | cc353c3 | 2008-11-28 09:51:23 +0000 | [diff] [blame] | 1330 | mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), 1 << cpu); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1331 | } |
| 1332 | |
Olof Johansson | 7df2457 | 2007-01-28 23:33:18 -0600 | [diff] [blame] | 1333 | /* Init spurious vector */ |
| 1334 | mpic_write(mpic->gregs, MPIC_INFO(GREG_SPURIOUS), mpic->spurious_vec); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1335 | |
Zang Roy-r61911 | 7233593 | 2006-08-25 14:16:30 +1000 | [diff] [blame] | 1336 | /* Disable 8259 passthrough, if supported */ |
| 1337 | if (!(mpic->flags & MPIC_NO_PTHROU_DIS)) |
| 1338 | mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), |
| 1339 | mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) |
| 1340 | | MPIC_GREG_GCONF_8259_PTHROU_DIS); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1341 | |
Olof Johansson | d87bf3b | 2007-12-27 22:16:29 -0600 | [diff] [blame] | 1342 | if (mpic->flags & MPIC_NO_BIAS) |
| 1343 | mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), |
| 1344 | mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) |
| 1345 | | MPIC_GREG_GCONF_NO_BIAS); |
| 1346 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1347 | /* Set current processor priority to 0 */ |
Zang Roy-r61911 | 7233593 | 2006-08-25 14:16:30 +1000 | [diff] [blame] | 1348 | mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0); |
Johannes Berg | 3669e93 | 2007-05-02 16:33:41 +1000 | [diff] [blame] | 1349 | |
| 1350 | #ifdef CONFIG_PM |
| 1351 | /* allocate memory to save mpic state */ |
| 1352 | mpic->save_data = alloc_bootmem(mpic->num_sources * sizeof(struct mpic_irq_save)); |
| 1353 | BUG_ON(mpic->save_data == NULL); |
| 1354 | #endif |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1355 | } |
| 1356 | |
Mark A. Greer | 868ea0c | 2006-06-20 14:15:36 -0700 | [diff] [blame] | 1357 | void __init mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio) |
| 1358 | { |
| 1359 | u32 v; |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1360 | |
Mark A. Greer | 868ea0c | 2006-06-20 14:15:36 -0700 | [diff] [blame] | 1361 | v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1); |
| 1362 | v &= ~MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK; |
| 1363 | v |= MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO(clock_ratio); |
| 1364 | mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v); |
| 1365 | } |
| 1366 | |
| 1367 | void __init mpic_set_serial_int(struct mpic *mpic, int enable) |
| 1368 | { |
Benjamin Herrenschmidt | ba1826e | 2006-07-05 15:36:15 +1000 | [diff] [blame] | 1369 | unsigned long flags; |
Mark A. Greer | 868ea0c | 2006-06-20 14:15:36 -0700 | [diff] [blame] | 1370 | u32 v; |
| 1371 | |
Benjamin Herrenschmidt | ba1826e | 2006-07-05 15:36:15 +1000 | [diff] [blame] | 1372 | spin_lock_irqsave(&mpic_lock, flags); |
Mark A. Greer | 868ea0c | 2006-06-20 14:15:36 -0700 | [diff] [blame] | 1373 | v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1); |
| 1374 | if (enable) |
| 1375 | v |= MPIC_GREG_GLOBAL_CONF_1_SIE; |
| 1376 | else |
| 1377 | v &= ~MPIC_GREG_GLOBAL_CONF_1_SIE; |
| 1378 | mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v); |
Benjamin Herrenschmidt | ba1826e | 2006-07-05 15:36:15 +1000 | [diff] [blame] | 1379 | spin_unlock_irqrestore(&mpic_lock, flags); |
Mark A. Greer | 868ea0c | 2006-06-20 14:15:36 -0700 | [diff] [blame] | 1380 | } |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1381 | |
| 1382 | void mpic_irq_set_priority(unsigned int irq, unsigned int pri) |
| 1383 | { |
Johannes Berg | d9d1063 | 2008-02-21 20:39:01 +1100 | [diff] [blame] | 1384 | unsigned int is_ipi; |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1385 | struct mpic *mpic = mpic_find(irq, &is_ipi); |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 1386 | unsigned int src = mpic_irq_to_hw(irq); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1387 | unsigned long flags; |
| 1388 | u32 reg; |
| 1389 | |
Stephen Rothwell | 06a901c | 2008-05-21 16:24:31 +1000 | [diff] [blame] | 1390 | if (!mpic) |
| 1391 | return; |
| 1392 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1393 | spin_lock_irqsave(&mpic_lock, flags); |
| 1394 | if (is_ipi) { |
Olof Johansson | 7df2457 | 2007-01-28 23:33:18 -0600 | [diff] [blame] | 1395 | reg = mpic_ipi_read(src - mpic->ipi_vecs[0]) & |
Benjamin Herrenschmidt | e535664 | 2005-11-18 17:18:15 +1100 | [diff] [blame] | 1396 | ~MPIC_VECPRI_PRIORITY_MASK; |
Olof Johansson | 7df2457 | 2007-01-28 23:33:18 -0600 | [diff] [blame] | 1397 | mpic_ipi_write(src - mpic->ipi_vecs[0], |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1398 | reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT)); |
| 1399 | } else { |
Zang Roy-r61911 | 7233593 | 2006-08-25 14:16:30 +1000 | [diff] [blame] | 1400 | reg = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) |
Benjamin Herrenschmidt | e535664 | 2005-11-18 17:18:15 +1100 | [diff] [blame] | 1401 | & ~MPIC_VECPRI_PRIORITY_MASK; |
Zang Roy-r61911 | 7233593 | 2006-08-25 14:16:30 +1000 | [diff] [blame] | 1402 | mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1403 | reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT)); |
| 1404 | } |
| 1405 | spin_unlock_irqrestore(&mpic_lock, flags); |
| 1406 | } |
| 1407 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1408 | void mpic_setup_this_cpu(void) |
| 1409 | { |
| 1410 | #ifdef CONFIG_SMP |
| 1411 | struct mpic *mpic = mpic_primary; |
| 1412 | unsigned long flags; |
| 1413 | u32 msk = 1 << hard_smp_processor_id(); |
| 1414 | unsigned int i; |
| 1415 | |
| 1416 | BUG_ON(mpic == NULL); |
| 1417 | |
| 1418 | DBG("%s: setup_this_cpu(%d)\n", mpic->name, hard_smp_processor_id()); |
| 1419 | |
| 1420 | spin_lock_irqsave(&mpic_lock, flags); |
| 1421 | |
| 1422 | /* let the mpic know we want intrs. default affinity is 0xffffffff |
| 1423 | * until changed via /proc. That's how it's done on x86. If we want |
| 1424 | * it differently, then we should make sure we also change the default |
Ingo Molnar | a53da52 | 2006-06-29 02:24:38 -0700 | [diff] [blame] | 1425 | * values of irq_desc[].affinity in irq.c. |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1426 | */ |
| 1427 | if (distribute_irqs) { |
| 1428 | for (i = 0; i < mpic->num_sources ; i++) |
Zang Roy-r61911 | 7233593 | 2006-08-25 14:16:30 +1000 | [diff] [blame] | 1429 | mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), |
| 1430 | mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) | msk); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1431 | } |
| 1432 | |
| 1433 | /* Set current processor priority to 0 */ |
Zang Roy-r61911 | 7233593 | 2006-08-25 14:16:30 +1000 | [diff] [blame] | 1434 | mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1435 | |
| 1436 | spin_unlock_irqrestore(&mpic_lock, flags); |
| 1437 | #endif /* CONFIG_SMP */ |
| 1438 | } |
| 1439 | |
| 1440 | int mpic_cpu_get_priority(void) |
| 1441 | { |
| 1442 | struct mpic *mpic = mpic_primary; |
| 1443 | |
Zang Roy-r61911 | 7233593 | 2006-08-25 14:16:30 +1000 | [diff] [blame] | 1444 | return mpic_cpu_read(MPIC_INFO(CPU_CURRENT_TASK_PRI)); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1445 | } |
| 1446 | |
| 1447 | void mpic_cpu_set_priority(int prio) |
| 1448 | { |
| 1449 | struct mpic *mpic = mpic_primary; |
| 1450 | |
| 1451 | prio &= MPIC_CPU_TASKPRI_MASK; |
Zang Roy-r61911 | 7233593 | 2006-08-25 14:16:30 +1000 | [diff] [blame] | 1452 | mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), prio); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1453 | } |
| 1454 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1455 | void mpic_teardown_this_cpu(int secondary) |
| 1456 | { |
| 1457 | struct mpic *mpic = mpic_primary; |
| 1458 | unsigned long flags; |
| 1459 | u32 msk = 1 << hard_smp_processor_id(); |
| 1460 | unsigned int i; |
| 1461 | |
| 1462 | BUG_ON(mpic == NULL); |
| 1463 | |
| 1464 | DBG("%s: teardown_this_cpu(%d)\n", mpic->name, hard_smp_processor_id()); |
| 1465 | spin_lock_irqsave(&mpic_lock, flags); |
| 1466 | |
| 1467 | /* let the mpic know we don't want intrs. */ |
| 1468 | for (i = 0; i < mpic->num_sources ; i++) |
Zang Roy-r61911 | 7233593 | 2006-08-25 14:16:30 +1000 | [diff] [blame] | 1469 | mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), |
| 1470 | mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) & ~msk); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1471 | |
| 1472 | /* Set current processor priority to max */ |
Zang Roy-r61911 | 7233593 | 2006-08-25 14:16:30 +1000 | [diff] [blame] | 1473 | mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf); |
Valentine Barshak | 7132799 | 2008-04-03 23:09:43 +0400 | [diff] [blame] | 1474 | /* We need to EOI the IPI since not all platforms reset the MPIC |
| 1475 | * on boot and new interrupts wouldn't get delivered otherwise. |
| 1476 | */ |
| 1477 | mpic_eoi(mpic); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1478 | |
| 1479 | spin_unlock_irqrestore(&mpic_lock, flags); |
| 1480 | } |
| 1481 | |
| 1482 | |
| 1483 | void mpic_send_ipi(unsigned int ipi_no, unsigned int cpu_mask) |
| 1484 | { |
| 1485 | struct mpic *mpic = mpic_primary; |
| 1486 | |
| 1487 | BUG_ON(mpic == NULL); |
| 1488 | |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 1489 | #ifdef DEBUG_IPI |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1490 | DBG("%s: send_ipi(ipi_no: %d)\n", mpic->name, ipi_no); |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 1491 | #endif |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1492 | |
Zang Roy-r61911 | 7233593 | 2006-08-25 14:16:30 +1000 | [diff] [blame] | 1493 | mpic_cpu_write(MPIC_INFO(CPU_IPI_DISPATCH_0) + |
| 1494 | ipi_no * MPIC_INFO(CPU_IPI_DISPATCH_STRIDE), |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1495 | mpic_physmask(cpu_mask & cpus_addr(cpu_online_map)[0])); |
| 1496 | } |
| 1497 | |
Olof Johansson | f365355 | 2007-12-20 13:11:18 -0600 | [diff] [blame] | 1498 | static unsigned int _mpic_get_one_irq(struct mpic *mpic, int reg) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1499 | { |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 1500 | u32 src; |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1501 | |
Olof Johansson | f365355 | 2007-12-20 13:11:18 -0600 | [diff] [blame] | 1502 | src = mpic_cpu_read(reg) & MPIC_INFO(VECPRI_VECTOR_MASK); |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 1503 | #ifdef DEBUG_LOW |
Olof Johansson | f365355 | 2007-12-20 13:11:18 -0600 | [diff] [blame] | 1504 | DBG("%s: get_one_irq(reg 0x%x): %d\n", mpic->name, reg, src); |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 1505 | #endif |
Josh Boyer | 5cddd2e | 2007-05-01 06:38:11 +1000 | [diff] [blame] | 1506 | if (unlikely(src == mpic->spurious_vec)) { |
| 1507 | if (mpic->flags & MPIC_SPV_EOI) |
| 1508 | mpic_eoi(mpic); |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 1509 | return NO_IRQ; |
Josh Boyer | 5cddd2e | 2007-05-01 06:38:11 +1000 | [diff] [blame] | 1510 | } |
Benjamin Herrenschmidt | 7fd7218 | 2007-07-21 09:55:21 +1000 | [diff] [blame] | 1511 | if (unlikely(mpic->protected && test_bit(src, mpic->protected))) { |
| 1512 | if (printk_ratelimit()) |
| 1513 | printk(KERN_WARNING "%s: Got protected source %d !\n", |
| 1514 | mpic->name, (int)src); |
| 1515 | mpic_eoi(mpic); |
| 1516 | return NO_IRQ; |
| 1517 | } |
| 1518 | |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 1519 | return irq_linear_revmap(mpic->irqhost, src); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1520 | } |
| 1521 | |
Olof Johansson | f365355 | 2007-12-20 13:11:18 -0600 | [diff] [blame] | 1522 | unsigned int mpic_get_one_irq(struct mpic *mpic) |
| 1523 | { |
| 1524 | return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_INTACK)); |
| 1525 | } |
| 1526 | |
Olaf Hering | 35a84c2 | 2006-10-07 22:08:26 +1000 | [diff] [blame] | 1527 | unsigned int mpic_get_irq(void) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1528 | { |
| 1529 | struct mpic *mpic = mpic_primary; |
| 1530 | |
| 1531 | BUG_ON(mpic == NULL); |
| 1532 | |
Olaf Hering | 35a84c2 | 2006-10-07 22:08:26 +1000 | [diff] [blame] | 1533 | return mpic_get_one_irq(mpic); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1534 | } |
| 1535 | |
Kumar Gala | d91e4ea | 2009-01-07 15:53:29 -0600 | [diff] [blame] | 1536 | unsigned int mpic_get_coreint_irq(void) |
| 1537 | { |
| 1538 | #ifdef CONFIG_BOOKE |
| 1539 | struct mpic *mpic = mpic_primary; |
| 1540 | u32 src; |
| 1541 | |
| 1542 | BUG_ON(mpic == NULL); |
| 1543 | |
| 1544 | src = mfspr(SPRN_EPR); |
| 1545 | |
| 1546 | if (unlikely(src == mpic->spurious_vec)) { |
| 1547 | if (mpic->flags & MPIC_SPV_EOI) |
| 1548 | mpic_eoi(mpic); |
| 1549 | return NO_IRQ; |
| 1550 | } |
| 1551 | if (unlikely(mpic->protected && test_bit(src, mpic->protected))) { |
| 1552 | if (printk_ratelimit()) |
| 1553 | printk(KERN_WARNING "%s: Got protected source %d !\n", |
| 1554 | mpic->name, (int)src); |
| 1555 | return NO_IRQ; |
| 1556 | } |
| 1557 | |
| 1558 | return irq_linear_revmap(mpic->irqhost, src); |
| 1559 | #else |
| 1560 | return NO_IRQ; |
| 1561 | #endif |
| 1562 | } |
| 1563 | |
Olof Johansson | f365355 | 2007-12-20 13:11:18 -0600 | [diff] [blame] | 1564 | unsigned int mpic_get_mcirq(void) |
| 1565 | { |
| 1566 | struct mpic *mpic = mpic_primary; |
| 1567 | |
| 1568 | BUG_ON(mpic == NULL); |
| 1569 | |
| 1570 | return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_MCACK)); |
| 1571 | } |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1572 | |
| 1573 | #ifdef CONFIG_SMP |
| 1574 | void mpic_request_ipis(void) |
| 1575 | { |
| 1576 | struct mpic *mpic = mpic_primary; |
Milton Miller | 78608dd | 2008-10-10 01:56:50 +0000 | [diff] [blame] | 1577 | int i; |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1578 | BUG_ON(mpic == NULL); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1579 | |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 1580 | printk(KERN_INFO "mpic: requesting IPIs ... \n"); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1581 | |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 1582 | for (i = 0; i < 4; i++) { |
| 1583 | unsigned int vipi = irq_create_mapping(mpic->irqhost, |
Olof Johansson | 7df2457 | 2007-01-28 23:33:18 -0600 | [diff] [blame] | 1584 | mpic->ipi_vecs[0] + i); |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 1585 | if (vipi == NO_IRQ) { |
Milton Miller | 78608dd | 2008-10-10 01:56:50 +0000 | [diff] [blame] | 1586 | printk(KERN_ERR "Failed to map %s\n", smp_ipi_name[i]); |
| 1587 | continue; |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 1588 | } |
Milton Miller | 78608dd | 2008-10-10 01:56:50 +0000 | [diff] [blame] | 1589 | smp_request_message_ipi(vipi, i); |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 1590 | } |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1591 | } |
Paul Mackerras | a9c5926 | 2005-10-20 17:09:51 +1000 | [diff] [blame] | 1592 | |
| 1593 | void smp_mpic_message_pass(int target, int msg) |
| 1594 | { |
| 1595 | /* make sure we're sending something that translates to an IPI */ |
| 1596 | if ((unsigned int)msg > 3) { |
| 1597 | printk("SMP %d: smp_message_pass: unknown msg %d\n", |
| 1598 | smp_processor_id(), msg); |
| 1599 | return; |
| 1600 | } |
| 1601 | switch (target) { |
| 1602 | case MSG_ALL: |
| 1603 | mpic_send_ipi(msg, 0xffffffff); |
| 1604 | break; |
| 1605 | case MSG_ALL_BUT_SELF: |
| 1606 | mpic_send_ipi(msg, 0xffffffff & ~(1 << smp_processor_id())); |
| 1607 | break; |
| 1608 | default: |
| 1609 | mpic_send_ipi(msg, 1 << target); |
| 1610 | break; |
| 1611 | } |
| 1612 | } |
Michael Ellerman | 775aeff | 2007-02-08 18:34:04 +1100 | [diff] [blame] | 1613 | |
| 1614 | int __init smp_mpic_probe(void) |
| 1615 | { |
| 1616 | int nr_cpus; |
| 1617 | |
| 1618 | DBG("smp_mpic_probe()...\n"); |
| 1619 | |
| 1620 | nr_cpus = cpus_weight(cpu_possible_map); |
| 1621 | |
| 1622 | DBG("nr_cpus: %d\n", nr_cpus); |
| 1623 | |
| 1624 | if (nr_cpus > 1) |
| 1625 | mpic_request_ipis(); |
| 1626 | |
| 1627 | return nr_cpus; |
| 1628 | } |
| 1629 | |
| 1630 | void __devinit smp_mpic_setup_cpu(int cpu) |
| 1631 | { |
| 1632 | mpic_setup_this_cpu(); |
| 1633 | } |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1634 | #endif /* CONFIG_SMP */ |
Johannes Berg | 3669e93 | 2007-05-02 16:33:41 +1000 | [diff] [blame] | 1635 | |
| 1636 | #ifdef CONFIG_PM |
| 1637 | static int mpic_suspend(struct sys_device *dev, pm_message_t state) |
| 1638 | { |
| 1639 | struct mpic *mpic = container_of(dev, struct mpic, sysdev); |
| 1640 | int i; |
| 1641 | |
| 1642 | for (i = 0; i < mpic->num_sources; i++) { |
| 1643 | mpic->save_data[i].vecprio = |
| 1644 | mpic_irq_read(i, MPIC_INFO(IRQ_VECTOR_PRI)); |
| 1645 | mpic->save_data[i].dest = |
| 1646 | mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)); |
| 1647 | } |
| 1648 | |
| 1649 | return 0; |
| 1650 | } |
| 1651 | |
| 1652 | static int mpic_resume(struct sys_device *dev) |
| 1653 | { |
| 1654 | struct mpic *mpic = container_of(dev, struct mpic, sysdev); |
| 1655 | int i; |
| 1656 | |
| 1657 | for (i = 0; i < mpic->num_sources; i++) { |
| 1658 | mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI), |
| 1659 | mpic->save_data[i].vecprio); |
| 1660 | mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), |
| 1661 | mpic->save_data[i].dest); |
| 1662 | |
| 1663 | #ifdef CONFIG_MPIC_U3_HT_IRQS |
| 1664 | { |
| 1665 | struct mpic_irq_fixup *fixup = &mpic->fixups[i]; |
| 1666 | |
| 1667 | if (fixup->base) { |
| 1668 | /* we use the lowest bit in an inverted meaning */ |
| 1669 | if ((mpic->save_data[i].fixup_data & 1) == 0) |
| 1670 | continue; |
| 1671 | |
| 1672 | /* Enable and configure */ |
| 1673 | writeb(0x10 + 2 * fixup->index, fixup->base + 2); |
| 1674 | |
| 1675 | writel(mpic->save_data[i].fixup_data & ~1, |
| 1676 | fixup->base + 4); |
| 1677 | } |
| 1678 | } |
| 1679 | #endif |
| 1680 | } /* end for loop */ |
| 1681 | |
| 1682 | return 0; |
| 1683 | } |
| 1684 | #endif |
| 1685 | |
| 1686 | static struct sysdev_class mpic_sysclass = { |
| 1687 | #ifdef CONFIG_PM |
| 1688 | .resume = mpic_resume, |
| 1689 | .suspend = mpic_suspend, |
| 1690 | #endif |
Kay Sievers | af5ca3f | 2007-12-20 02:09:39 +0100 | [diff] [blame] | 1691 | .name = "mpic", |
Johannes Berg | 3669e93 | 2007-05-02 16:33:41 +1000 | [diff] [blame] | 1692 | }; |
| 1693 | |
| 1694 | static int mpic_init_sys(void) |
| 1695 | { |
| 1696 | struct mpic *mpic = mpics; |
| 1697 | int error, id = 0; |
| 1698 | |
| 1699 | error = sysdev_class_register(&mpic_sysclass); |
| 1700 | |
| 1701 | while (mpic && !error) { |
| 1702 | mpic->sysdev.cls = &mpic_sysclass; |
| 1703 | mpic->sysdev.id = id++; |
| 1704 | error = sysdev_register(&mpic->sysdev); |
| 1705 | mpic = mpic->next; |
| 1706 | } |
| 1707 | return error; |
| 1708 | } |
| 1709 | |
| 1710 | device_initcall(mpic_init_sys); |