Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2003 PMC-Sierra |
| 3 | * Author: Manish Lachwani (lachwani@pmc-sierra.com) |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify it |
| 6 | * under the terms of the GNU General Public License as published by the |
| 7 | * Free Software Foundation; either version 2 of the License, or (at your |
| 8 | * option) any later version. |
| 9 | * |
| 10 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED |
| 11 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 12 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN |
| 13 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| 14 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| 15 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF |
| 16 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
| 17 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 18 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| 19 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 20 | * |
| 21 | * You should have received a copy of the GNU General Public License along |
| 22 | * with this program; if not, write to the Free Software Foundation, Inc., |
| 23 | * 675 Mass Ave, Cambridge, MA 02139, USA. |
| 24 | */ |
| 25 | |
| 26 | #include <linux/types.h> |
| 27 | #include <linux/pci.h> |
| 28 | #include <linux/kernel.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 29 | #include <linux/delay.h> |
| 30 | #include <asm/io.h> |
| 31 | |
| 32 | #include <asm/titan_dep.h> |
| 33 | |
| 34 | static int titan_ht_config_read_dword(struct pci_bus *bus, unsigned int devfn, |
Andrea Gelmini | 11ed4ad | 2010-05-23 21:52:11 +0200 | [diff] [blame] | 35 | int offset, u32 *val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 36 | { |
| 37 | volatile uint32_t address; |
| 38 | int busno; |
| 39 | |
| 40 | busno = bus->number; |
| 41 | |
| 42 | address = (busno << 16) | (devfn << 8) | (offset & 0xfc) | 0x80000000; |
| 43 | if (busno != 0) |
| 44 | address |= 1; |
| 45 | |
| 46 | /* |
| 47 | * RM9000 HT Errata: Issue back to back HT config |
| 48 | * transcations. Issue a BIU sync before and |
| 49 | * after the HT cycle |
| 50 | */ |
| 51 | |
| 52 | *(volatile int32_t *) 0xfb0000f0 |= 0x2; |
| 53 | |
| 54 | udelay(30); |
| 55 | |
| 56 | *(volatile int32_t *) 0xfb0006f8 = address; |
| 57 | *(val) = *(volatile int32_t *) 0xfb0006fc; |
| 58 | |
| 59 | udelay(30); |
| 60 | |
| 61 | * (volatile int32_t *) 0xfb0000f0 |= 0x2; |
| 62 | |
| 63 | return PCIBIOS_SUCCESSFUL; |
| 64 | } |
| 65 | |
| 66 | static int titan_ht_config_read(struct pci_bus *bus, unsigned int devfn, |
Andrea Gelmini | 11ed4ad | 2010-05-23 21:52:11 +0200 | [diff] [blame] | 67 | int offset, int size, u32 *val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 68 | { |
| 69 | uint32_t dword; |
| 70 | |
| 71 | titan_ht_config_read_dword(bus, devfn, offset, &dword); |
| 72 | |
| 73 | dword >>= ((offset & 3) << 3); |
| 74 | dword &= (0xffffffffU >> ((4 - size) << 8)); |
| 75 | |
| 76 | return PCIBIOS_SUCCESSFUL; |
| 77 | } |
| 78 | |
| 79 | static inline int titan_ht_config_write_dword(struct pci_bus *bus, |
| 80 | unsigned int devfn, int offset, u32 val) |
| 81 | { |
| 82 | volatile uint32_t address; |
| 83 | int busno; |
| 84 | |
| 85 | busno = bus->number; |
| 86 | |
| 87 | address = (busno << 16) | (devfn << 8) | (offset & 0xfc) | 0x80000000; |
| 88 | if (busno != 0) |
| 89 | address |= 1; |
| 90 | |
| 91 | *(volatile int32_t *) 0xfb0000f0 |= 0x2; |
| 92 | |
| 93 | udelay(30); |
| 94 | |
| 95 | *(volatile int32_t *) 0xfb0006f8 = address; |
| 96 | *(volatile int32_t *) 0xfb0006fc = val; |
| 97 | |
| 98 | udelay(30); |
| 99 | |
| 100 | *(volatile int32_t *) 0xfb0000f0 |= 0x2; |
| 101 | |
| 102 | return PCIBIOS_SUCCESSFUL; |
| 103 | } |
| 104 | |
| 105 | static int titan_ht_config_write(struct pci_bus *bus, unsigned int devfn, |
| 106 | int offset, int size, u32 val) |
| 107 | { |
| 108 | uint32_t val1, val2, mask; |
| 109 | |
| 110 | titan_ht_config_read_dword(bus, devfn, offset, &val2); |
| 111 | |
| 112 | val1 = val << ((offset & 3) << 3); |
| 113 | mask = ~(0xffffffffU >> ((4 - size) << 8)); |
| 114 | val2 &= ~(mask << ((offset & 3) << 8)); |
| 115 | |
| 116 | titan_ht_config_write_dword(bus, devfn, offset, val1 | val2); |
| 117 | |
| 118 | return PCIBIOS_SUCCESSFUL; |
| 119 | } |
| 120 | |
| 121 | struct pci_ops titan_ht_pci_ops = { |
| 122 | .read = titan_ht_config_read, |
| 123 | .write = titan_ht_config_write, |
| 124 | }; |