SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 1 | /* |
Andrew Victor | 9d04126 | 2007-02-05 11:42:07 +0100 | [diff] [blame] | 2 | * linux/arch/arm/mach-at91/gpio.c |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 3 | * |
| 4 | * Copyright (C) 2005 HP Labs |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; either version 2 of the License, or |
| 9 | * (at your option) any later version. |
| 10 | */ |
| 11 | |
Andrew Victor | f217383 | 2006-09-27 13:23:00 +0100 | [diff] [blame] | 12 | #include <linux/clk.h> |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 13 | #include <linux/errno.h> |
Thomas Gleixner | 07d265d | 2006-07-01 23:01:50 +0100 | [diff] [blame] | 14 | #include <linux/interrupt.h> |
| 15 | #include <linux/irq.h> |
Andrew Victor | b66545e | 2007-11-23 16:09:10 +0100 | [diff] [blame] | 16 | #include <linux/debugfs.h> |
| 17 | #include <linux/seq_file.h> |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 18 | #include <linux/kernel.h> |
| 19 | #include <linux/list.h> |
| 20 | #include <linux/module.h> |
| 21 | |
| 22 | #include <asm/io.h> |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 23 | #include <mach/hardware.h> |
| 24 | #include <mach/at91_pio.h> |
| 25 | #include <mach/gpio.h> |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 26 | |
Andrew Victor | f217383 | 2006-09-27 13:23:00 +0100 | [diff] [blame] | 27 | #include "generic.h" |
| 28 | |
| 29 | |
| 30 | static struct at91_gpio_bank *gpio; |
| 31 | static int gpio_banks; |
| 32 | |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 33 | |
| 34 | static inline void __iomem *pin_to_controller(unsigned pin) |
| 35 | { |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 36 | pin -= PIN_BASE; |
| 37 | pin /= 32; |
Andrew Victor | f217383 | 2006-09-27 13:23:00 +0100 | [diff] [blame] | 38 | if (likely(pin < gpio_banks)) |
David Brownell | e83aff5 | 2008-01-04 18:30:24 +0100 | [diff] [blame] | 39 | return gpio[pin].regbase; |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 40 | |
| 41 | return NULL; |
| 42 | } |
| 43 | |
| 44 | static inline unsigned pin_to_mask(unsigned pin) |
| 45 | { |
| 46 | pin -= PIN_BASE; |
| 47 | return 1 << (pin % 32); |
| 48 | } |
| 49 | |
| 50 | |
| 51 | /*--------------------------------------------------------------------------*/ |
| 52 | |
| 53 | /* Not all hardware capabilities are exposed through these calls; they |
| 54 | * only encapsulate the most common features and modes. (So if you |
| 55 | * want to change signals in groups, do it directly.) |
| 56 | * |
| 57 | * Bootloaders will usually handle some of the pin multiplexing setup. |
| 58 | * The intent is certainly that by the time Linux is fully booted, all |
| 59 | * pins should have been fully initialized. These setup calls should |
| 60 | * only be used by board setup routines, or possibly in driver probe(). |
| 61 | * |
| 62 | * For bootloaders doing all that setup, these calls could be inlined |
| 63 | * as NOPs so Linux won't duplicate any setup code |
| 64 | */ |
| 65 | |
| 66 | |
| 67 | /* |
David Brownell | a31c4ee | 2007-02-12 00:53:13 -0800 | [diff] [blame] | 68 | * mux the pin to the "GPIO" peripheral role. |
| 69 | */ |
| 70 | int __init_or_module at91_set_GPIO_periph(unsigned pin, int use_pullup) |
| 71 | { |
| 72 | void __iomem *pio = pin_to_controller(pin); |
| 73 | unsigned mask = pin_to_mask(pin); |
| 74 | |
| 75 | if (!pio) |
| 76 | return -EINVAL; |
| 77 | __raw_writel(mask, pio + PIO_IDR); |
| 78 | __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR)); |
| 79 | __raw_writel(mask, pio + PIO_PER); |
| 80 | return 0; |
| 81 | } |
| 82 | EXPORT_SYMBOL(at91_set_GPIO_periph); |
| 83 | |
| 84 | |
| 85 | /* |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 86 | * mux the pin to the "A" internal peripheral role. |
| 87 | */ |
| 88 | int __init_or_module at91_set_A_periph(unsigned pin, int use_pullup) |
| 89 | { |
| 90 | void __iomem *pio = pin_to_controller(pin); |
| 91 | unsigned mask = pin_to_mask(pin); |
| 92 | |
| 93 | if (!pio) |
| 94 | return -EINVAL; |
| 95 | |
| 96 | __raw_writel(mask, pio + PIO_IDR); |
| 97 | __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR)); |
| 98 | __raw_writel(mask, pio + PIO_ASR); |
| 99 | __raw_writel(mask, pio + PIO_PDR); |
| 100 | return 0; |
| 101 | } |
| 102 | EXPORT_SYMBOL(at91_set_A_periph); |
| 103 | |
| 104 | |
| 105 | /* |
| 106 | * mux the pin to the "B" internal peripheral role. |
| 107 | */ |
| 108 | int __init_or_module at91_set_B_periph(unsigned pin, int use_pullup) |
| 109 | { |
| 110 | void __iomem *pio = pin_to_controller(pin); |
| 111 | unsigned mask = pin_to_mask(pin); |
| 112 | |
| 113 | if (!pio) |
| 114 | return -EINVAL; |
| 115 | |
| 116 | __raw_writel(mask, pio + PIO_IDR); |
| 117 | __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR)); |
| 118 | __raw_writel(mask, pio + PIO_BSR); |
| 119 | __raw_writel(mask, pio + PIO_PDR); |
| 120 | return 0; |
| 121 | } |
| 122 | EXPORT_SYMBOL(at91_set_B_periph); |
| 123 | |
| 124 | |
| 125 | /* |
| 126 | * mux the pin to the gpio controller (instead of "A" or "B" peripheral), and |
| 127 | * configure it for an input. |
| 128 | */ |
| 129 | int __init_or_module at91_set_gpio_input(unsigned pin, int use_pullup) |
| 130 | { |
| 131 | void __iomem *pio = pin_to_controller(pin); |
| 132 | unsigned mask = pin_to_mask(pin); |
| 133 | |
| 134 | if (!pio) |
| 135 | return -EINVAL; |
| 136 | |
| 137 | __raw_writel(mask, pio + PIO_IDR); |
| 138 | __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR)); |
| 139 | __raw_writel(mask, pio + PIO_ODR); |
| 140 | __raw_writel(mask, pio + PIO_PER); |
| 141 | return 0; |
| 142 | } |
| 143 | EXPORT_SYMBOL(at91_set_gpio_input); |
| 144 | |
| 145 | |
| 146 | /* |
| 147 | * mux the pin to the gpio controller (instead of "A" or "B" peripheral), |
| 148 | * and configure it for an output. |
| 149 | */ |
| 150 | int __init_or_module at91_set_gpio_output(unsigned pin, int value) |
| 151 | { |
| 152 | void __iomem *pio = pin_to_controller(pin); |
| 153 | unsigned mask = pin_to_mask(pin); |
| 154 | |
| 155 | if (!pio) |
| 156 | return -EINVAL; |
| 157 | |
| 158 | __raw_writel(mask, pio + PIO_IDR); |
| 159 | __raw_writel(mask, pio + PIO_PUDR); |
| 160 | __raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR)); |
| 161 | __raw_writel(mask, pio + PIO_OER); |
| 162 | __raw_writel(mask, pio + PIO_PER); |
| 163 | return 0; |
| 164 | } |
| 165 | EXPORT_SYMBOL(at91_set_gpio_output); |
| 166 | |
| 167 | |
| 168 | /* |
| 169 | * enable/disable the glitch filter; mostly used with IRQ handling. |
| 170 | */ |
| 171 | int __init_or_module at91_set_deglitch(unsigned pin, int is_on) |
| 172 | { |
| 173 | void __iomem *pio = pin_to_controller(pin); |
| 174 | unsigned mask = pin_to_mask(pin); |
| 175 | |
| 176 | if (!pio) |
| 177 | return -EINVAL; |
| 178 | __raw_writel(mask, pio + (is_on ? PIO_IFER : PIO_IFDR)); |
| 179 | return 0; |
| 180 | } |
| 181 | EXPORT_SYMBOL(at91_set_deglitch); |
| 182 | |
Andrew Victor | df666b9 | 2006-02-22 21:23:35 +0000 | [diff] [blame] | 183 | /* |
| 184 | * enable/disable the multi-driver; This is only valid for output and |
| 185 | * allows the output pin to run as an open collector output. |
| 186 | */ |
| 187 | int __init_or_module at91_set_multi_drive(unsigned pin, int is_on) |
| 188 | { |
| 189 | void __iomem *pio = pin_to_controller(pin); |
| 190 | unsigned mask = pin_to_mask(pin); |
| 191 | |
| 192 | if (!pio) |
| 193 | return -EINVAL; |
| 194 | |
| 195 | __raw_writel(mask, pio + (is_on ? PIO_MDER : PIO_MDDR)); |
| 196 | return 0; |
| 197 | } |
| 198 | EXPORT_SYMBOL(at91_set_multi_drive); |
| 199 | |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 200 | /*--------------------------------------------------------------------------*/ |
| 201 | |
David Brownell | a31c4ee | 2007-02-12 00:53:13 -0800 | [diff] [blame] | 202 | /* new-style GPIO calls; these expect at91_set_GPIO_periph to have been |
| 203 | * called, and maybe at91_set_multi_drive() for putout pins. |
| 204 | */ |
| 205 | |
| 206 | int gpio_direction_input(unsigned pin) |
| 207 | { |
| 208 | void __iomem *pio = pin_to_controller(pin); |
| 209 | unsigned mask = pin_to_mask(pin); |
| 210 | |
| 211 | if (!pio || !(__raw_readl(pio + PIO_PSR) & mask)) |
| 212 | return -EINVAL; |
Andrew Victor | 0ebffe3 | 2007-02-22 09:38:52 +0100 | [diff] [blame] | 213 | __raw_writel(mask, pio + PIO_ODR); |
David Brownell | a31c4ee | 2007-02-12 00:53:13 -0800 | [diff] [blame] | 214 | return 0; |
| 215 | } |
| 216 | EXPORT_SYMBOL(gpio_direction_input); |
| 217 | |
David Brownell | 28735a7 | 2007-03-16 13:38:14 -0800 | [diff] [blame] | 218 | int gpio_direction_output(unsigned pin, int value) |
David Brownell | a31c4ee | 2007-02-12 00:53:13 -0800 | [diff] [blame] | 219 | { |
| 220 | void __iomem *pio = pin_to_controller(pin); |
| 221 | unsigned mask = pin_to_mask(pin); |
| 222 | |
| 223 | if (!pio || !(__raw_readl(pio + PIO_PSR) & mask)) |
| 224 | return -EINVAL; |
David Brownell | 28735a7 | 2007-03-16 13:38:14 -0800 | [diff] [blame] | 225 | __raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR)); |
David Brownell | a31c4ee | 2007-02-12 00:53:13 -0800 | [diff] [blame] | 226 | __raw_writel(mask, pio + PIO_OER); |
| 227 | return 0; |
| 228 | } |
| 229 | EXPORT_SYMBOL(gpio_direction_output); |
| 230 | |
| 231 | /*--------------------------------------------------------------------------*/ |
| 232 | |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 233 | /* |
| 234 | * assuming the pin is muxed as a gpio output, set its value. |
| 235 | */ |
| 236 | int at91_set_gpio_value(unsigned pin, int value) |
| 237 | { |
| 238 | void __iomem *pio = pin_to_controller(pin); |
| 239 | unsigned mask = pin_to_mask(pin); |
| 240 | |
| 241 | if (!pio) |
| 242 | return -EINVAL; |
| 243 | __raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR)); |
| 244 | return 0; |
| 245 | } |
| 246 | EXPORT_SYMBOL(at91_set_gpio_value); |
| 247 | |
| 248 | |
| 249 | /* |
| 250 | * read the pin's value (works even if it's not muxed as a gpio). |
| 251 | */ |
| 252 | int at91_get_gpio_value(unsigned pin) |
| 253 | { |
| 254 | void __iomem *pio = pin_to_controller(pin); |
| 255 | unsigned mask = pin_to_mask(pin); |
| 256 | u32 pdsr; |
| 257 | |
| 258 | if (!pio) |
| 259 | return -EINVAL; |
| 260 | pdsr = __raw_readl(pio + PIO_PDSR); |
| 261 | return (pdsr & mask) != 0; |
| 262 | } |
| 263 | EXPORT_SYMBOL(at91_get_gpio_value); |
| 264 | |
| 265 | /*--------------------------------------------------------------------------*/ |
| 266 | |
Andrew Victor | 814138f | 2006-06-19 15:26:54 +0100 | [diff] [blame] | 267 | #ifdef CONFIG_PM |
| 268 | |
Andrew Victor | f217383 | 2006-09-27 13:23:00 +0100 | [diff] [blame] | 269 | static u32 wakeups[MAX_GPIO_BANKS]; |
| 270 | static u32 backups[MAX_GPIO_BANKS]; |
Andrew Victor | 814138f | 2006-06-19 15:26:54 +0100 | [diff] [blame] | 271 | |
| 272 | static int gpio_irq_set_wake(unsigned pin, unsigned state) |
| 273 | { |
| 274 | unsigned mask = pin_to_mask(pin); |
Andrew Victor | 3ea163e | 2007-01-09 13:47:29 +0100 | [diff] [blame] | 275 | unsigned bank = (pin - PIN_BASE) / 32; |
Andrew Victor | 814138f | 2006-06-19 15:26:54 +0100 | [diff] [blame] | 276 | |
Andrew Victor | 3ea163e | 2007-01-09 13:47:29 +0100 | [diff] [blame] | 277 | if (unlikely(bank >= MAX_GPIO_BANKS)) |
Andrew Victor | 814138f | 2006-06-19 15:26:54 +0100 | [diff] [blame] | 278 | return -EINVAL; |
| 279 | |
| 280 | if (state) |
Andrew Victor | 3ea163e | 2007-01-09 13:47:29 +0100 | [diff] [blame] | 281 | wakeups[bank] |= mask; |
Andrew Victor | 814138f | 2006-06-19 15:26:54 +0100 | [diff] [blame] | 282 | else |
Andrew Victor | 3ea163e | 2007-01-09 13:47:29 +0100 | [diff] [blame] | 283 | wakeups[bank] &= ~mask; |
| 284 | |
| 285 | set_irq_wake(gpio[bank].id, state); |
Andrew Victor | 814138f | 2006-06-19 15:26:54 +0100 | [diff] [blame] | 286 | |
| 287 | return 0; |
| 288 | } |
| 289 | |
| 290 | void at91_gpio_suspend(void) |
| 291 | { |
| 292 | int i; |
| 293 | |
Andrew Victor | f217383 | 2006-09-27 13:23:00 +0100 | [diff] [blame] | 294 | for (i = 0; i < gpio_banks; i++) { |
David Brownell | e83aff5 | 2008-01-04 18:30:24 +0100 | [diff] [blame] | 295 | void __iomem *pio = gpio[i].regbase; |
Andrew Victor | 814138f | 2006-06-19 15:26:54 +0100 | [diff] [blame] | 296 | |
David Brownell | e83aff5 | 2008-01-04 18:30:24 +0100 | [diff] [blame] | 297 | backups[i] = __raw_readl(pio + PIO_IMR); |
| 298 | __raw_writel(backups[i], pio + PIO_IDR); |
| 299 | __raw_writel(wakeups[i], pio + PIO_IER); |
Andrew Victor | 814138f | 2006-06-19 15:26:54 +0100 | [diff] [blame] | 300 | |
Andrew Victor | 3ea163e | 2007-01-09 13:47:29 +0100 | [diff] [blame] | 301 | if (!wakeups[i]) |
| 302 | clk_disable(gpio[i].clock); |
| 303 | else { |
Andrew Victor | 814138f | 2006-06-19 15:26:54 +0100 | [diff] [blame] | 304 | #ifdef CONFIG_PM_DEBUG |
Andrew Victor | 3ea163e | 2007-01-09 13:47:29 +0100 | [diff] [blame] | 305 | printk(KERN_DEBUG "GPIO-%c may wake for %08x\n", 'A'+i, wakeups[i]); |
Andrew Victor | 814138f | 2006-06-19 15:26:54 +0100 | [diff] [blame] | 306 | #endif |
| 307 | } |
| 308 | } |
| 309 | } |
| 310 | |
| 311 | void at91_gpio_resume(void) |
| 312 | { |
| 313 | int i; |
| 314 | |
Andrew Victor | f217383 | 2006-09-27 13:23:00 +0100 | [diff] [blame] | 315 | for (i = 0; i < gpio_banks; i++) { |
David Brownell | e83aff5 | 2008-01-04 18:30:24 +0100 | [diff] [blame] | 316 | void __iomem *pio = gpio[i].regbase; |
Andrew Victor | 814138f | 2006-06-19 15:26:54 +0100 | [diff] [blame] | 317 | |
Andrew Victor | 3ea163e | 2007-01-09 13:47:29 +0100 | [diff] [blame] | 318 | if (!wakeups[i]) |
| 319 | clk_enable(gpio[i].clock); |
| 320 | |
David Brownell | e83aff5 | 2008-01-04 18:30:24 +0100 | [diff] [blame] | 321 | __raw_writel(wakeups[i], pio + PIO_IDR); |
| 322 | __raw_writel(backups[i], pio + PIO_IER); |
Andrew Victor | f217383 | 2006-09-27 13:23:00 +0100 | [diff] [blame] | 323 | } |
Andrew Victor | 814138f | 2006-06-19 15:26:54 +0100 | [diff] [blame] | 324 | } |
| 325 | |
| 326 | #else |
| 327 | #define gpio_irq_set_wake NULL |
| 328 | #endif |
| 329 | |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 330 | |
| 331 | /* Several AIC controller irqs are dispatched through this GPIO handler. |
| 332 | * To use any AT91_PIN_* as an externally triggered IRQ, first call |
| 333 | * at91_set_gpio_input() then maybe enable its glitch filter. |
| 334 | * Then just request_irq() with the pin ID; it works like any ARM IRQ |
| 335 | * handler, though it always triggers on rising and falling edges. |
| 336 | * |
| 337 | * Alternatively, certain pins may be used directly as IRQ0..IRQ6 after |
| 338 | * configuring them with at91_set_a_periph() or at91_set_b_periph(). |
| 339 | * IRQ0..IRQ6 should be configurable, e.g. level vs edge triggering. |
| 340 | */ |
| 341 | |
| 342 | static void gpio_irq_mask(unsigned pin) |
| 343 | { |
| 344 | void __iomem *pio = pin_to_controller(pin); |
| 345 | unsigned mask = pin_to_mask(pin); |
| 346 | |
| 347 | if (pio) |
| 348 | __raw_writel(mask, pio + PIO_IDR); |
| 349 | } |
| 350 | |
| 351 | static void gpio_irq_unmask(unsigned pin) |
| 352 | { |
| 353 | void __iomem *pio = pin_to_controller(pin); |
| 354 | unsigned mask = pin_to_mask(pin); |
| 355 | |
| 356 | if (pio) |
| 357 | __raw_writel(mask, pio + PIO_IER); |
| 358 | } |
| 359 | |
| 360 | static int gpio_irq_type(unsigned pin, unsigned type) |
| 361 | { |
David Brownell | e83aff5 | 2008-01-04 18:30:24 +0100 | [diff] [blame] | 362 | switch (type) { |
| 363 | case IRQ_TYPE_NONE: |
| 364 | case IRQ_TYPE_EDGE_BOTH: |
| 365 | return 0; |
| 366 | default: |
| 367 | return -EINVAL; |
| 368 | } |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 369 | } |
| 370 | |
David Brownell | 38c677c | 2006-08-01 22:26:25 +0100 | [diff] [blame] | 371 | static struct irq_chip gpio_irqchip = { |
| 372 | .name = "GPIO", |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 373 | .mask = gpio_irq_mask, |
| 374 | .unmask = gpio_irq_unmask, |
| 375 | .set_type = gpio_irq_type, |
Andrew Victor | 814138f | 2006-06-19 15:26:54 +0100 | [diff] [blame] | 376 | .set_wake = gpio_irq_set_wake, |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 377 | }; |
| 378 | |
Russell King | 10dd5ce | 2006-11-23 11:41:32 +0000 | [diff] [blame] | 379 | static void gpio_irq_handler(unsigned irq, struct irq_desc *desc) |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 380 | { |
| 381 | unsigned pin; |
Russell King | 10dd5ce | 2006-11-23 11:41:32 +0000 | [diff] [blame] | 382 | struct irq_desc *gpio; |
David Brownell | e83aff5 | 2008-01-04 18:30:24 +0100 | [diff] [blame] | 383 | struct at91_gpio_bank *bank; |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 384 | void __iomem *pio; |
| 385 | u32 isr; |
| 386 | |
David Brownell | e83aff5 | 2008-01-04 18:30:24 +0100 | [diff] [blame] | 387 | bank = get_irq_chip_data(irq); |
| 388 | pio = bank->regbase; |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 389 | |
| 390 | /* temporarily mask (level sensitive) parent IRQ */ |
| 391 | desc->chip->ack(irq); |
| 392 | for (;;) { |
David Brownell | e83aff5 | 2008-01-04 18:30:24 +0100 | [diff] [blame] | 393 | /* Reading ISR acks pending (edge triggered) GPIO interrupts. |
| 394 | * When there none are pending, we're finished unless we need |
| 395 | * to process multiple banks (like ID_PIOCDE on sam9263). |
| 396 | */ |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 397 | isr = __raw_readl(pio + PIO_ISR) & __raw_readl(pio + PIO_IMR); |
David Brownell | e83aff5 | 2008-01-04 18:30:24 +0100 | [diff] [blame] | 398 | if (!isr) { |
| 399 | if (!bank->next) |
| 400 | break; |
| 401 | bank = bank->next; |
| 402 | pio = bank->regbase; |
| 403 | continue; |
| 404 | } |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 405 | |
David Brownell | e83aff5 | 2008-01-04 18:30:24 +0100 | [diff] [blame] | 406 | pin = bank->chipbase; |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 407 | |
| 408 | while (isr) { |
Andrew Victor | abbea71 | 2006-02-24 22:27:50 +0000 | [diff] [blame] | 409 | if (isr & 1) { |
Thomas Gleixner | 07d265d | 2006-07-01 23:01:50 +0100 | [diff] [blame] | 410 | if (unlikely(gpio->depth)) { |
Andrew Victor | abbea71 | 2006-02-24 22:27:50 +0000 | [diff] [blame] | 411 | /* |
| 412 | * The core ARM interrupt handler lazily disables IRQs so |
| 413 | * another IRQ must be generated before it actually gets |
| 414 | * here to be disabled on the GPIO controller. |
| 415 | */ |
| 416 | gpio_irq_mask(pin); |
| 417 | } |
| 418 | else |
Dmitry Baryshkov | d8aa025 | 2008-10-09 13:36:24 +0100 | [diff] [blame^] | 419 | generic_handle_irq(pin); |
Andrew Victor | abbea71 | 2006-02-24 22:27:50 +0000 | [diff] [blame] | 420 | } |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 421 | pin++; |
| 422 | gpio++; |
| 423 | isr >>= 1; |
| 424 | } |
| 425 | } |
| 426 | desc->chip->unmask(irq); |
| 427 | /* now it may re-trigger */ |
| 428 | } |
| 429 | |
Andrew Victor | f217383 | 2006-09-27 13:23:00 +0100 | [diff] [blame] | 430 | /*--------------------------------------------------------------------------*/ |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 431 | |
Andrew Victor | b66545e | 2007-11-23 16:09:10 +0100 | [diff] [blame] | 432 | #ifdef CONFIG_DEBUG_FS |
| 433 | |
| 434 | static int at91_gpio_show(struct seq_file *s, void *unused) |
| 435 | { |
| 436 | int bank, j; |
| 437 | |
| 438 | /* print heading */ |
| 439 | seq_printf(s, "Pin\t"); |
| 440 | for (bank = 0; bank < gpio_banks; bank++) { |
| 441 | seq_printf(s, "PIO%c\t", 'A' + bank); |
| 442 | }; |
| 443 | seq_printf(s, "\n\n"); |
| 444 | |
| 445 | /* print pin status */ |
| 446 | for (j = 0; j < 32; j++) { |
| 447 | seq_printf(s, "%i:\t", j); |
| 448 | |
| 449 | for (bank = 0; bank < gpio_banks; bank++) { |
| 450 | unsigned pin = PIN_BASE + (32 * bank) + j; |
| 451 | void __iomem *pio = pin_to_controller(pin); |
| 452 | unsigned mask = pin_to_mask(pin); |
| 453 | |
| 454 | if (__raw_readl(pio + PIO_PSR) & mask) |
| 455 | seq_printf(s, "GPIO:%s", __raw_readl(pio + PIO_PDSR) & mask ? "1" : "0"); |
| 456 | else |
| 457 | seq_printf(s, "%s", __raw_readl(pio + PIO_ABSR) & mask ? "B" : "A"); |
| 458 | |
| 459 | seq_printf(s, "\t"); |
| 460 | } |
| 461 | |
| 462 | seq_printf(s, "\n"); |
| 463 | } |
| 464 | |
| 465 | return 0; |
| 466 | } |
| 467 | |
| 468 | static int at91_gpio_open(struct inode *inode, struct file *file) |
| 469 | { |
| 470 | return single_open(file, at91_gpio_show, NULL); |
| 471 | } |
| 472 | |
| 473 | static const struct file_operations at91_gpio_operations = { |
| 474 | .open = at91_gpio_open, |
| 475 | .read = seq_read, |
| 476 | .llseek = seq_lseek, |
| 477 | .release = single_release, |
| 478 | }; |
| 479 | |
| 480 | static int __init at91_gpio_debugfs_init(void) |
| 481 | { |
| 482 | /* /sys/kernel/debug/at91_gpio */ |
| 483 | (void) debugfs_create_file("at91_gpio", S_IFREG | S_IRUGO, NULL, NULL, &at91_gpio_operations); |
| 484 | return 0; |
| 485 | } |
| 486 | postcore_initcall(at91_gpio_debugfs_init); |
| 487 | |
| 488 | #endif |
| 489 | |
| 490 | /*--------------------------------------------------------------------------*/ |
| 491 | |
David Brownell | 37aca70 | 2008-03-05 00:08:29 +0100 | [diff] [blame] | 492 | /* This lock class tells lockdep that GPIO irqs are in a different |
| 493 | * category than their parents, so it won't report false recursion. |
| 494 | */ |
| 495 | static struct lock_class_key gpio_lock_class; |
| 496 | |
Andrew Victor | f217383 | 2006-09-27 13:23:00 +0100 | [diff] [blame] | 497 | /* |
| 498 | * Called from the processor-specific init to enable GPIO interrupt support. |
| 499 | */ |
| 500 | void __init at91_gpio_irq_setup(void) |
| 501 | { |
David Brownell | e83aff5 | 2008-01-04 18:30:24 +0100 | [diff] [blame] | 502 | unsigned pioc, pin; |
| 503 | struct at91_gpio_bank *this, *prev; |
Andrew Victor | f217383 | 2006-09-27 13:23:00 +0100 | [diff] [blame] | 504 | |
David Brownell | e83aff5 | 2008-01-04 18:30:24 +0100 | [diff] [blame] | 505 | for (pioc = 0, pin = PIN_BASE, this = gpio, prev = NULL; |
| 506 | pioc++ < gpio_banks; |
| 507 | prev = this, this++) { |
| 508 | unsigned id = this->id; |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 509 | unsigned i; |
| 510 | |
David Brownell | e83aff5 | 2008-01-04 18:30:24 +0100 | [diff] [blame] | 511 | /* enable PIO controller's clock */ |
| 512 | clk_enable(this->clock); |
Andrew Victor | f217383 | 2006-09-27 13:23:00 +0100 | [diff] [blame] | 513 | |
David Brownell | e83aff5 | 2008-01-04 18:30:24 +0100 | [diff] [blame] | 514 | __raw_writel(~0, this->regbase + PIO_IDR); |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 515 | |
David Brownell | e83aff5 | 2008-01-04 18:30:24 +0100 | [diff] [blame] | 516 | for (i = 0, pin = this->chipbase; i < 32; i++, pin++) { |
David Brownell | 37aca70 | 2008-03-05 00:08:29 +0100 | [diff] [blame] | 517 | lockdep_set_class(&irq_desc[pin].lock, &gpio_lock_class); |
| 518 | |
Andrew Victor | 814138f | 2006-06-19 15:26:54 +0100 | [diff] [blame] | 519 | /* |
| 520 | * Can use the "simple" and not "edge" handler since it's |
Robert P. J. Day | 3a4fa0a | 2007-10-19 23:10:43 +0200 | [diff] [blame] | 521 | * shorter, and the AIC handles interrupts sanely. |
Andrew Victor | 814138f | 2006-06-19 15:26:54 +0100 | [diff] [blame] | 522 | */ |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 523 | set_irq_chip(pin, &gpio_irqchip); |
Russell King | 10dd5ce | 2006-11-23 11:41:32 +0000 | [diff] [blame] | 524 | set_irq_handler(pin, handle_simple_irq); |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 525 | set_irq_flags(pin, IRQF_VALID); |
| 526 | } |
| 527 | |
David Brownell | e83aff5 | 2008-01-04 18:30:24 +0100 | [diff] [blame] | 528 | /* The toplevel handler handles one bank of GPIOs, except |
| 529 | * AT91SAM9263_ID_PIOCDE handles three... PIOC is first in |
| 530 | * the list, so we only set up that handler. |
| 531 | */ |
| 532 | if (prev && prev->next == this) |
| 533 | continue; |
| 534 | |
| 535 | set_irq_chip_data(id, this); |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 536 | set_irq_chained_handler(id, gpio_irq_handler); |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 537 | } |
Andrew Victor | f217383 | 2006-09-27 13:23:00 +0100 | [diff] [blame] | 538 | pr_info("AT91: %d gpio irqs in %d banks\n", pin - PIN_BASE, gpio_banks); |
| 539 | } |
| 540 | |
| 541 | /* |
| 542 | * Called from the processor-specific init to enable GPIO pin support. |
| 543 | */ |
| 544 | void __init at91_gpio_init(struct at91_gpio_bank *data, int nr_banks) |
| 545 | { |
David Brownell | e83aff5 | 2008-01-04 18:30:24 +0100 | [diff] [blame] | 546 | unsigned i; |
| 547 | struct at91_gpio_bank *last; |
| 548 | |
Andrew Victor | f217383 | 2006-09-27 13:23:00 +0100 | [diff] [blame] | 549 | BUG_ON(nr_banks > MAX_GPIO_BANKS); |
| 550 | |
| 551 | gpio = data; |
| 552 | gpio_banks = nr_banks; |
David Brownell | e83aff5 | 2008-01-04 18:30:24 +0100 | [diff] [blame] | 553 | |
| 554 | for (i = 0, last = NULL; i < nr_banks; i++, last = data, data++) { |
| 555 | data->chipbase = PIN_BASE + i * 32; |
| 556 | data->regbase = data->offset + (void __iomem *)AT91_VA_BASE_SYS; |
| 557 | |
| 558 | /* AT91SAM9263_ID_PIOCDE groups PIOC, PIOD, PIOE */ |
| 559 | if (last && last->id == data->id) |
| 560 | last->next = data; |
| 561 | } |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 562 | } |