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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * sata_nv.c - NVIDIA nForce SATA
3 *
4 * Copyright 2004 NVIDIA Corp. All rights reserved.
5 * Copyright 2004 Andrew Chew
6 *
Linus Torvalds1da177e2005-04-16 15:20:36 -07007 *
Jeff Garzikaa7e16d2005-08-29 15:12:56 -04008 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2, or (at your option)
11 * any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; see the file COPYING. If not, write to
20 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
Linus Torvalds1da177e2005-04-16 15:20:36 -070021 *
Jeff Garzikaf36d7f2005-08-28 20:18:39 -040022 *
23 * libata documentation is available via 'make {ps|pdf}docs',
24 * as Documentation/DocBook/libata.*
25 *
26 * No hardware documentation available outside of NVIDIA.
27 * This driver programs the NVIDIA SATA controller in a similar
28 * fashion as with other PCI IDE BMDMA controllers, with a few
29 * NV-specific details such as register offsets, SATA phy location,
30 * hotplug info, etc.
31 *
Robert Hancockfbbb2622006-10-27 19:08:41 -070032 * CK804/MCP04 controllers support an alternate programming interface
33 * similar to the ADMA specification (with some modifications).
34 * This allows the use of NCQ. Non-DMA-mapped ATA commands are still
35 * sent through the legacy interface.
36 *
Linus Torvalds1da177e2005-04-16 15:20:36 -070037 */
38
Linus Torvalds1da177e2005-04-16 15:20:36 -070039#include <linux/kernel.h>
40#include <linux/module.h>
41#include <linux/pci.h>
42#include <linux/init.h>
43#include <linux/blkdev.h>
44#include <linux/delay.h>
45#include <linux/interrupt.h>
Jeff Garzika9524a72005-10-30 14:39:11 -050046#include <linux/device.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070047#include <scsi/scsi_host.h>
Robert Hancockfbbb2622006-10-27 19:08:41 -070048#include <scsi/scsi_device.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070049#include <linux/libata.h>
50
51#define DRV_NAME "sata_nv"
Jeff Garzik8bc3fc42007-05-21 20:26:38 -040052#define DRV_VERSION "3.4"
Robert Hancockfbbb2622006-10-27 19:08:41 -070053
54#define NV_ADMA_DMA_BOUNDARY 0xffffffffUL
Linus Torvalds1da177e2005-04-16 15:20:36 -070055
Jeff Garzik10ad05d2006-03-22 23:50:50 -050056enum {
Tejun Heo0d5ff562007-02-01 15:06:36 +090057 NV_MMIO_BAR = 5,
58
Jeff Garzik10ad05d2006-03-22 23:50:50 -050059 NV_PORTS = 2,
60 NV_PIO_MASK = 0x1f,
61 NV_MWDMA_MASK = 0x07,
62 NV_UDMA_MASK = 0x7f,
63 NV_PORT0_SCR_REG_OFFSET = 0x00,
64 NV_PORT1_SCR_REG_OFFSET = 0x40,
Linus Torvalds1da177e2005-04-16 15:20:36 -070065
Tejun Heo27e4b272006-06-17 15:49:55 +090066 /* INT_STATUS/ENABLE */
Jeff Garzik10ad05d2006-03-22 23:50:50 -050067 NV_INT_STATUS = 0x10,
Jeff Garzik10ad05d2006-03-22 23:50:50 -050068 NV_INT_ENABLE = 0x11,
Tejun Heo27e4b272006-06-17 15:49:55 +090069 NV_INT_STATUS_CK804 = 0x440,
Jeff Garzik10ad05d2006-03-22 23:50:50 -050070 NV_INT_ENABLE_CK804 = 0x441,
Linus Torvalds1da177e2005-04-16 15:20:36 -070071
Tejun Heo27e4b272006-06-17 15:49:55 +090072 /* INT_STATUS/ENABLE bits */
73 NV_INT_DEV = 0x01,
74 NV_INT_PM = 0x02,
75 NV_INT_ADDED = 0x04,
76 NV_INT_REMOVED = 0x08,
77
78 NV_INT_PORT_SHIFT = 4, /* each port occupies 4 bits */
79
Tejun Heo39f87582006-06-17 15:49:56 +090080 NV_INT_ALL = 0x0f,
Tejun Heo5a44eff2006-06-17 15:49:56 +090081 NV_INT_MASK = NV_INT_DEV |
82 NV_INT_ADDED | NV_INT_REMOVED,
Tejun Heo39f87582006-06-17 15:49:56 +090083
Tejun Heo27e4b272006-06-17 15:49:55 +090084 /* INT_CONFIG */
Jeff Garzik10ad05d2006-03-22 23:50:50 -050085 NV_INT_CONFIG = 0x12,
86 NV_INT_CONFIG_METHD = 0x01, // 0 = INT, 1 = SMI
Linus Torvalds1da177e2005-04-16 15:20:36 -070087
Jeff Garzik10ad05d2006-03-22 23:50:50 -050088 // For PCI config register 20
89 NV_MCP_SATA_CFG_20 = 0x50,
90 NV_MCP_SATA_CFG_20_SATA_SPACE_EN = 0x04,
Robert Hancockfbbb2622006-10-27 19:08:41 -070091 NV_MCP_SATA_CFG_20_PORT0_EN = (1 << 17),
92 NV_MCP_SATA_CFG_20_PORT1_EN = (1 << 16),
93 NV_MCP_SATA_CFG_20_PORT0_PWB_EN = (1 << 14),
94 NV_MCP_SATA_CFG_20_PORT1_PWB_EN = (1 << 12),
95
96 NV_ADMA_MAX_CPBS = 32,
97 NV_ADMA_CPB_SZ = 128,
98 NV_ADMA_APRD_SZ = 16,
99 NV_ADMA_SGTBL_LEN = (1024 - NV_ADMA_CPB_SZ) /
100 NV_ADMA_APRD_SZ,
101 NV_ADMA_SGTBL_TOTAL_LEN = NV_ADMA_SGTBL_LEN + 5,
102 NV_ADMA_SGTBL_SZ = NV_ADMA_SGTBL_LEN * NV_ADMA_APRD_SZ,
103 NV_ADMA_PORT_PRIV_DMA_SZ = NV_ADMA_MAX_CPBS *
104 (NV_ADMA_CPB_SZ + NV_ADMA_SGTBL_SZ),
105
106 /* BAR5 offset to ADMA general registers */
107 NV_ADMA_GEN = 0x400,
108 NV_ADMA_GEN_CTL = 0x00,
109 NV_ADMA_NOTIFIER_CLEAR = 0x30,
110
111 /* BAR5 offset to ADMA ports */
112 NV_ADMA_PORT = 0x480,
113
114 /* size of ADMA port register space */
115 NV_ADMA_PORT_SIZE = 0x100,
116
117 /* ADMA port registers */
118 NV_ADMA_CTL = 0x40,
119 NV_ADMA_CPB_COUNT = 0x42,
120 NV_ADMA_NEXT_CPB_IDX = 0x43,
121 NV_ADMA_STAT = 0x44,
122 NV_ADMA_CPB_BASE_LOW = 0x48,
123 NV_ADMA_CPB_BASE_HIGH = 0x4C,
124 NV_ADMA_APPEND = 0x50,
125 NV_ADMA_NOTIFIER = 0x68,
126 NV_ADMA_NOTIFIER_ERROR = 0x6C,
127
128 /* NV_ADMA_CTL register bits */
129 NV_ADMA_CTL_HOTPLUG_IEN = (1 << 0),
130 NV_ADMA_CTL_CHANNEL_RESET = (1 << 5),
131 NV_ADMA_CTL_GO = (1 << 7),
132 NV_ADMA_CTL_AIEN = (1 << 8),
133 NV_ADMA_CTL_READ_NON_COHERENT = (1 << 11),
134 NV_ADMA_CTL_WRITE_NON_COHERENT = (1 << 12),
135
136 /* CPB response flag bits */
137 NV_CPB_RESP_DONE = (1 << 0),
138 NV_CPB_RESP_ATA_ERR = (1 << 3),
139 NV_CPB_RESP_CMD_ERR = (1 << 4),
140 NV_CPB_RESP_CPB_ERR = (1 << 7),
141
142 /* CPB control flag bits */
143 NV_CPB_CTL_CPB_VALID = (1 << 0),
144 NV_CPB_CTL_QUEUE = (1 << 1),
145 NV_CPB_CTL_APRD_VALID = (1 << 2),
146 NV_CPB_CTL_IEN = (1 << 3),
147 NV_CPB_CTL_FPDMA = (1 << 4),
148
149 /* APRD flags */
150 NV_APRD_WRITE = (1 << 1),
151 NV_APRD_END = (1 << 2),
152 NV_APRD_CONT = (1 << 3),
153
154 /* NV_ADMA_STAT flags */
155 NV_ADMA_STAT_TIMEOUT = (1 << 0),
156 NV_ADMA_STAT_HOTUNPLUG = (1 << 1),
157 NV_ADMA_STAT_HOTPLUG = (1 << 2),
158 NV_ADMA_STAT_CPBERR = (1 << 4),
159 NV_ADMA_STAT_SERROR = (1 << 5),
160 NV_ADMA_STAT_CMD_COMPLETE = (1 << 6),
161 NV_ADMA_STAT_IDLE = (1 << 8),
162 NV_ADMA_STAT_LEGACY = (1 << 9),
163 NV_ADMA_STAT_STOPPED = (1 << 10),
164 NV_ADMA_STAT_DONE = (1 << 12),
165 NV_ADMA_STAT_ERR = NV_ADMA_STAT_CPBERR |
166 NV_ADMA_STAT_TIMEOUT,
167
168 /* port flags */
169 NV_ADMA_PORT_REGISTER_MODE = (1 << 0),
Robert Hancock2dec7552006-11-26 14:20:19 -0600170 NV_ADMA_ATAPI_SETUP_COMPLETE = (1 << 1),
Robert Hancockfbbb2622006-10-27 19:08:41 -0700171
Jeff Garzik10ad05d2006-03-22 23:50:50 -0500172};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700173
Robert Hancockfbbb2622006-10-27 19:08:41 -0700174/* ADMA Physical Region Descriptor - one SG segment */
175struct nv_adma_prd {
176 __le64 addr;
177 __le32 len;
178 u8 flags;
179 u8 packet_len;
180 __le16 reserved;
181};
182
183enum nv_adma_regbits {
184 CMDEND = (1 << 15), /* end of command list */
185 WNB = (1 << 14), /* wait-not-BSY */
186 IGN = (1 << 13), /* ignore this entry */
187 CS1n = (1 << (4 + 8)), /* std. PATA signals follow... */
188 DA2 = (1 << (2 + 8)),
189 DA1 = (1 << (1 + 8)),
190 DA0 = (1 << (0 + 8)),
191};
192
193/* ADMA Command Parameter Block
194 The first 5 SG segments are stored inside the Command Parameter Block itself.
195 If there are more than 5 segments the remainder are stored in a separate
196 memory area indicated by next_aprd. */
197struct nv_adma_cpb {
198 u8 resp_flags; /* 0 */
199 u8 reserved1; /* 1 */
200 u8 ctl_flags; /* 2 */
201 /* len is length of taskfile in 64 bit words */
202 u8 len; /* 3 */
203 u8 tag; /* 4 */
204 u8 next_cpb_idx; /* 5 */
205 __le16 reserved2; /* 6-7 */
206 __le16 tf[12]; /* 8-31 */
207 struct nv_adma_prd aprd[5]; /* 32-111 */
208 __le64 next_aprd; /* 112-119 */
209 __le64 reserved3; /* 120-127 */
210};
211
212
213struct nv_adma_port_priv {
214 struct nv_adma_cpb *cpb;
215 dma_addr_t cpb_dma;
216 struct nv_adma_prd *aprd;
217 dma_addr_t aprd_dma;
Robert Hancockcdf56bc2007-01-03 18:13:57 -0600218 void __iomem * ctl_block;
219 void __iomem * gen_block;
220 void __iomem * notifier_clear_block;
Robert Hancockfbbb2622006-10-27 19:08:41 -0700221 u8 flags;
Robert Hancock5e5c74a2007-02-19 18:42:30 -0600222 int last_issue_ncq;
Robert Hancockfbbb2622006-10-27 19:08:41 -0700223};
224
Robert Hancockcdf56bc2007-01-03 18:13:57 -0600225struct nv_host_priv {
226 unsigned long type;
227};
228
Robert Hancockfbbb2622006-10-27 19:08:41 -0700229#define NV_ADMA_CHECK_INTR(GCTL, PORT) ((GCTL) & ( 1 << (19 + (12 * (PORT)))))
230
Linus Torvalds1da177e2005-04-16 15:20:36 -0700231static int nv_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
Tejun Heo438ac6d2007-03-02 17:31:26 +0900232#ifdef CONFIG_PM
Robert Hancockcdf56bc2007-01-03 18:13:57 -0600233static int nv_pci_device_resume(struct pci_dev *pdev);
Tejun Heo438ac6d2007-03-02 17:31:26 +0900234#endif
Jeff Garzikcca39742006-08-24 03:19:22 -0400235static void nv_ck804_host_stop(struct ata_host *host);
David Howells7d12e782006-10-05 14:55:46 +0100236static irqreturn_t nv_generic_interrupt(int irq, void *dev_instance);
237static irqreturn_t nv_nf2_interrupt(int irq, void *dev_instance);
238static irqreturn_t nv_ck804_interrupt(int irq, void *dev_instance);
Tejun Heoda3dbb12007-07-16 14:29:40 +0900239static int nv_scr_read (struct ata_port *ap, unsigned int sc_reg, u32 *val);
240static int nv_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700241
Tejun Heo39f87582006-06-17 15:49:56 +0900242static void nv_nf2_freeze(struct ata_port *ap);
243static void nv_nf2_thaw(struct ata_port *ap);
244static void nv_ck804_freeze(struct ata_port *ap);
245static void nv_ck804_thaw(struct ata_port *ap);
246static void nv_error_handler(struct ata_port *ap);
Robert Hancockfbbb2622006-10-27 19:08:41 -0700247static int nv_adma_slave_config(struct scsi_device *sdev);
Robert Hancock2dec7552006-11-26 14:20:19 -0600248static int nv_adma_check_atapi_dma(struct ata_queued_cmd *qc);
Robert Hancockfbbb2622006-10-27 19:08:41 -0700249static void nv_adma_qc_prep(struct ata_queued_cmd *qc);
250static unsigned int nv_adma_qc_issue(struct ata_queued_cmd *qc);
251static irqreturn_t nv_adma_interrupt(int irq, void *dev_instance);
252static void nv_adma_irq_clear(struct ata_port *ap);
253static int nv_adma_port_start(struct ata_port *ap);
254static void nv_adma_port_stop(struct ata_port *ap);
Tejun Heo438ac6d2007-03-02 17:31:26 +0900255#ifdef CONFIG_PM
Robert Hancockcdf56bc2007-01-03 18:13:57 -0600256static int nv_adma_port_suspend(struct ata_port *ap, pm_message_t mesg);
257static int nv_adma_port_resume(struct ata_port *ap);
Tejun Heo438ac6d2007-03-02 17:31:26 +0900258#endif
Robert Hancock53014e22007-05-05 15:36:36 -0600259static void nv_adma_freeze(struct ata_port *ap);
260static void nv_adma_thaw(struct ata_port *ap);
Robert Hancockfbbb2622006-10-27 19:08:41 -0700261static void nv_adma_error_handler(struct ata_port *ap);
262static void nv_adma_host_stop(struct ata_host *host);
Robert Hancockf5ecac22007-02-20 21:49:10 -0600263static void nv_adma_post_internal_cmd(struct ata_queued_cmd *qc);
Robert Hancockf2fb3442007-03-26 21:43:36 -0800264static void nv_adma_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
Tejun Heo39f87582006-06-17 15:49:56 +0900265
Linus Torvalds1da177e2005-04-16 15:20:36 -0700266enum nv_host_type
267{
268 GENERIC,
269 NFORCE2,
Tejun Heo27e4b272006-06-17 15:49:55 +0900270 NFORCE3 = NFORCE2, /* NF2 == NF3 as far as sata_nv is concerned */
Robert Hancockfbbb2622006-10-27 19:08:41 -0700271 CK804,
272 ADMA
Linus Torvalds1da177e2005-04-16 15:20:36 -0700273};
274
Jeff Garzik3b7d6972005-11-10 11:04:11 -0500275static const struct pci_device_id nv_pci_tbl[] = {
Jeff Garzik54bb3a92006-09-27 22:20:11 -0400276 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_SATA), NFORCE2 },
277 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA), NFORCE3 },
278 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA2), NFORCE3 },
279 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA), CK804 },
280 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA2), CK804 },
281 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA), CK804 },
282 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA2), CK804 },
283 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA), GENERIC },
284 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA2), GENERIC },
285 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA), GENERIC },
286 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA2), GENERIC },
287 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA), GENERIC },
288 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA2), GENERIC },
289 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA3), GENERIC },
Jeff Garzik2d2744f2006-09-28 20:21:59 -0400290
291 { } /* terminate list */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700292};
293
Linus Torvalds1da177e2005-04-16 15:20:36 -0700294static struct pci_driver nv_pci_driver = {
295 .name = DRV_NAME,
296 .id_table = nv_pci_tbl,
297 .probe = nv_init_one,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900298#ifdef CONFIG_PM
Robert Hancockcdf56bc2007-01-03 18:13:57 -0600299 .suspend = ata_pci_device_suspend,
300 .resume = nv_pci_device_resume,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900301#endif
Tejun Heo1daf9ce2007-05-17 13:13:57 +0200302 .remove = ata_pci_remove_one,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700303};
304
Jeff Garzik193515d2005-11-07 00:59:37 -0500305static struct scsi_host_template nv_sht = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700306 .module = THIS_MODULE,
307 .name = DRV_NAME,
308 .ioctl = ata_scsi_ioctl,
309 .queuecommand = ata_scsi_queuecmd,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700310 .can_queue = ATA_DEF_QUEUE,
311 .this_id = ATA_SHT_THIS_ID,
312 .sg_tablesize = LIBATA_MAX_PRD,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700313 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
314 .emulated = ATA_SHT_EMULATED,
315 .use_clustering = ATA_SHT_USE_CLUSTERING,
316 .proc_name = DRV_NAME,
317 .dma_boundary = ATA_DMA_BOUNDARY,
318 .slave_configure = ata_scsi_slave_config,
Tejun Heoccf68c32006-05-31 18:28:09 +0900319 .slave_destroy = ata_scsi_slave_destroy,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700320 .bios_param = ata_std_bios_param,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700321};
322
Robert Hancockfbbb2622006-10-27 19:08:41 -0700323static struct scsi_host_template nv_adma_sht = {
324 .module = THIS_MODULE,
325 .name = DRV_NAME,
326 .ioctl = ata_scsi_ioctl,
327 .queuecommand = ata_scsi_queuecmd,
Robert Hancock1e0b5ab2007-06-28 18:52:24 -0600328 .change_queue_depth = ata_scsi_change_queue_depth,
Robert Hancockfbbb2622006-10-27 19:08:41 -0700329 .can_queue = NV_ADMA_MAX_CPBS,
330 .this_id = ATA_SHT_THIS_ID,
331 .sg_tablesize = NV_ADMA_SGTBL_TOTAL_LEN,
Robert Hancockfbbb2622006-10-27 19:08:41 -0700332 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
333 .emulated = ATA_SHT_EMULATED,
334 .use_clustering = ATA_SHT_USE_CLUSTERING,
335 .proc_name = DRV_NAME,
336 .dma_boundary = NV_ADMA_DMA_BOUNDARY,
337 .slave_configure = nv_adma_slave_config,
338 .slave_destroy = ata_scsi_slave_destroy,
339 .bios_param = ata_std_bios_param,
340};
341
Tejun Heoada364e2006-06-17 15:49:56 +0900342static const struct ata_port_operations nv_generic_ops = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700343 .port_disable = ata_port_disable,
344 .tf_load = ata_tf_load,
345 .tf_read = ata_tf_read,
346 .exec_command = ata_exec_command,
347 .check_status = ata_check_status,
348 .dev_select = ata_std_dev_select,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700349 .bmdma_setup = ata_bmdma_setup,
350 .bmdma_start = ata_bmdma_start,
351 .bmdma_stop = ata_bmdma_stop,
352 .bmdma_status = ata_bmdma_status,
353 .qc_prep = ata_qc_prep,
354 .qc_issue = ata_qc_issue_prot,
Tejun Heo39f87582006-06-17 15:49:56 +0900355 .freeze = ata_bmdma_freeze,
356 .thaw = ata_bmdma_thaw,
357 .error_handler = nv_error_handler,
358 .post_internal_cmd = ata_bmdma_post_internal_cmd,
Tejun Heo0d5ff562007-02-01 15:06:36 +0900359 .data_xfer = ata_data_xfer,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700360 .irq_clear = ata_bmdma_irq_clear,
Akira Iguchi246ce3b2007-01-26 16:27:58 +0900361 .irq_on = ata_irq_on,
362 .irq_ack = ata_irq_ack,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700363 .scr_read = nv_scr_read,
364 .scr_write = nv_scr_write,
365 .port_start = ata_port_start,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700366};
367
Tejun Heoada364e2006-06-17 15:49:56 +0900368static const struct ata_port_operations nv_nf2_ops = {
369 .port_disable = ata_port_disable,
370 .tf_load = ata_tf_load,
371 .tf_read = ata_tf_read,
372 .exec_command = ata_exec_command,
373 .check_status = ata_check_status,
374 .dev_select = ata_std_dev_select,
Tejun Heoada364e2006-06-17 15:49:56 +0900375 .bmdma_setup = ata_bmdma_setup,
376 .bmdma_start = ata_bmdma_start,
377 .bmdma_stop = ata_bmdma_stop,
378 .bmdma_status = ata_bmdma_status,
379 .qc_prep = ata_qc_prep,
380 .qc_issue = ata_qc_issue_prot,
Tejun Heo39f87582006-06-17 15:49:56 +0900381 .freeze = nv_nf2_freeze,
382 .thaw = nv_nf2_thaw,
383 .error_handler = nv_error_handler,
384 .post_internal_cmd = ata_bmdma_post_internal_cmd,
Tejun Heo0d5ff562007-02-01 15:06:36 +0900385 .data_xfer = ata_data_xfer,
Tejun Heoada364e2006-06-17 15:49:56 +0900386 .irq_clear = ata_bmdma_irq_clear,
Akira Iguchi246ce3b2007-01-26 16:27:58 +0900387 .irq_on = ata_irq_on,
388 .irq_ack = ata_irq_ack,
Tejun Heoada364e2006-06-17 15:49:56 +0900389 .scr_read = nv_scr_read,
390 .scr_write = nv_scr_write,
391 .port_start = ata_port_start,
Tejun Heoada364e2006-06-17 15:49:56 +0900392};
393
394static const struct ata_port_operations nv_ck804_ops = {
395 .port_disable = ata_port_disable,
396 .tf_load = ata_tf_load,
397 .tf_read = ata_tf_read,
398 .exec_command = ata_exec_command,
399 .check_status = ata_check_status,
400 .dev_select = ata_std_dev_select,
Tejun Heoada364e2006-06-17 15:49:56 +0900401 .bmdma_setup = ata_bmdma_setup,
402 .bmdma_start = ata_bmdma_start,
403 .bmdma_stop = ata_bmdma_stop,
404 .bmdma_status = ata_bmdma_status,
405 .qc_prep = ata_qc_prep,
406 .qc_issue = ata_qc_issue_prot,
Tejun Heo39f87582006-06-17 15:49:56 +0900407 .freeze = nv_ck804_freeze,
408 .thaw = nv_ck804_thaw,
409 .error_handler = nv_error_handler,
410 .post_internal_cmd = ata_bmdma_post_internal_cmd,
Tejun Heo0d5ff562007-02-01 15:06:36 +0900411 .data_xfer = ata_data_xfer,
Tejun Heoada364e2006-06-17 15:49:56 +0900412 .irq_clear = ata_bmdma_irq_clear,
Akira Iguchi246ce3b2007-01-26 16:27:58 +0900413 .irq_on = ata_irq_on,
414 .irq_ack = ata_irq_ack,
Tejun Heoada364e2006-06-17 15:49:56 +0900415 .scr_read = nv_scr_read,
416 .scr_write = nv_scr_write,
417 .port_start = ata_port_start,
Tejun Heoada364e2006-06-17 15:49:56 +0900418 .host_stop = nv_ck804_host_stop,
419};
420
Robert Hancockfbbb2622006-10-27 19:08:41 -0700421static const struct ata_port_operations nv_adma_ops = {
422 .port_disable = ata_port_disable,
423 .tf_load = ata_tf_load,
Robert Hancockf2fb3442007-03-26 21:43:36 -0800424 .tf_read = nv_adma_tf_read,
Robert Hancock2dec7552006-11-26 14:20:19 -0600425 .check_atapi_dma = nv_adma_check_atapi_dma,
Robert Hancockfbbb2622006-10-27 19:08:41 -0700426 .exec_command = ata_exec_command,
427 .check_status = ata_check_status,
428 .dev_select = ata_std_dev_select,
Robert Hancockf5ecac22007-02-20 21:49:10 -0600429 .bmdma_setup = ata_bmdma_setup,
430 .bmdma_start = ata_bmdma_start,
431 .bmdma_stop = ata_bmdma_stop,
432 .bmdma_status = ata_bmdma_status,
Robert Hancockfbbb2622006-10-27 19:08:41 -0700433 .qc_prep = nv_adma_qc_prep,
434 .qc_issue = nv_adma_qc_issue,
Robert Hancock53014e22007-05-05 15:36:36 -0600435 .freeze = nv_adma_freeze,
436 .thaw = nv_adma_thaw,
Robert Hancockfbbb2622006-10-27 19:08:41 -0700437 .error_handler = nv_adma_error_handler,
Robert Hancockf5ecac22007-02-20 21:49:10 -0600438 .post_internal_cmd = nv_adma_post_internal_cmd,
Tejun Heo0d5ff562007-02-01 15:06:36 +0900439 .data_xfer = ata_data_xfer,
Robert Hancockfbbb2622006-10-27 19:08:41 -0700440 .irq_clear = nv_adma_irq_clear,
Akira Iguchi246ce3b2007-01-26 16:27:58 +0900441 .irq_on = ata_irq_on,
442 .irq_ack = ata_irq_ack,
Robert Hancockfbbb2622006-10-27 19:08:41 -0700443 .scr_read = nv_scr_read,
444 .scr_write = nv_scr_write,
445 .port_start = nv_adma_port_start,
446 .port_stop = nv_adma_port_stop,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900447#ifdef CONFIG_PM
Robert Hancockcdf56bc2007-01-03 18:13:57 -0600448 .port_suspend = nv_adma_port_suspend,
449 .port_resume = nv_adma_port_resume,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900450#endif
Robert Hancockfbbb2622006-10-27 19:08:41 -0700451 .host_stop = nv_adma_host_stop,
452};
453
Tejun Heo1626aeb2007-05-04 12:43:58 +0200454static const struct ata_port_info nv_port_info[] = {
Tejun Heoada364e2006-06-17 15:49:56 +0900455 /* generic */
456 {
457 .sht = &nv_sht,
Tejun Heo722420f2006-09-28 17:49:22 +0900458 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
459 ATA_FLAG_HRST_TO_RESUME,
Tejun Heoada364e2006-06-17 15:49:56 +0900460 .pio_mask = NV_PIO_MASK,
461 .mwdma_mask = NV_MWDMA_MASK,
462 .udma_mask = NV_UDMA_MASK,
463 .port_ops = &nv_generic_ops,
Tejun Heo9a829cc2007-04-17 23:44:08 +0900464 .irq_handler = nv_generic_interrupt,
Tejun Heoada364e2006-06-17 15:49:56 +0900465 },
466 /* nforce2/3 */
467 {
468 .sht = &nv_sht,
Tejun Heo722420f2006-09-28 17:49:22 +0900469 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
470 ATA_FLAG_HRST_TO_RESUME,
Tejun Heoada364e2006-06-17 15:49:56 +0900471 .pio_mask = NV_PIO_MASK,
472 .mwdma_mask = NV_MWDMA_MASK,
473 .udma_mask = NV_UDMA_MASK,
474 .port_ops = &nv_nf2_ops,
Tejun Heo9a829cc2007-04-17 23:44:08 +0900475 .irq_handler = nv_nf2_interrupt,
Tejun Heoada364e2006-06-17 15:49:56 +0900476 },
477 /* ck804 */
478 {
479 .sht = &nv_sht,
Tejun Heo722420f2006-09-28 17:49:22 +0900480 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
481 ATA_FLAG_HRST_TO_RESUME,
Tejun Heoada364e2006-06-17 15:49:56 +0900482 .pio_mask = NV_PIO_MASK,
483 .mwdma_mask = NV_MWDMA_MASK,
484 .udma_mask = NV_UDMA_MASK,
485 .port_ops = &nv_ck804_ops,
Tejun Heo9a829cc2007-04-17 23:44:08 +0900486 .irq_handler = nv_ck804_interrupt,
Tejun Heoada364e2006-06-17 15:49:56 +0900487 },
Robert Hancockfbbb2622006-10-27 19:08:41 -0700488 /* ADMA */
489 {
490 .sht = &nv_adma_sht,
491 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
Robert Hancockcdf56bc2007-01-03 18:13:57 -0600492 ATA_FLAG_HRST_TO_RESUME |
Robert Hancockfbbb2622006-10-27 19:08:41 -0700493 ATA_FLAG_MMIO | ATA_FLAG_NCQ,
494 .pio_mask = NV_PIO_MASK,
495 .mwdma_mask = NV_MWDMA_MASK,
496 .udma_mask = NV_UDMA_MASK,
497 .port_ops = &nv_adma_ops,
Tejun Heo9a829cc2007-04-17 23:44:08 +0900498 .irq_handler = nv_adma_interrupt,
Robert Hancockfbbb2622006-10-27 19:08:41 -0700499 },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700500};
501
502MODULE_AUTHOR("NVIDIA");
503MODULE_DESCRIPTION("low-level driver for NVIDIA nForce SATA controller");
504MODULE_LICENSE("GPL");
505MODULE_DEVICE_TABLE(pci, nv_pci_tbl);
506MODULE_VERSION(DRV_VERSION);
507
Robert Hancockfbbb2622006-10-27 19:08:41 -0700508static int adma_enabled = 1;
509
Robert Hancock2dec7552006-11-26 14:20:19 -0600510static void nv_adma_register_mode(struct ata_port *ap)
511{
Robert Hancock2dec7552006-11-26 14:20:19 -0600512 struct nv_adma_port_priv *pp = ap->private_data;
Robert Hancockcdf56bc2007-01-03 18:13:57 -0600513 void __iomem *mmio = pp->ctl_block;
Robert Hancocka2cfe812007-02-05 16:26:03 -0800514 u16 tmp, status;
515 int count = 0;
Robert Hancock2dec7552006-11-26 14:20:19 -0600516
517 if (pp->flags & NV_ADMA_PORT_REGISTER_MODE)
518 return;
519
Robert Hancocka2cfe812007-02-05 16:26:03 -0800520 status = readw(mmio + NV_ADMA_STAT);
521 while(!(status & NV_ADMA_STAT_IDLE) && count < 20) {
522 ndelay(50);
523 status = readw(mmio + NV_ADMA_STAT);
524 count++;
525 }
526 if(count == 20)
527 ata_port_printk(ap, KERN_WARNING,
528 "timeout waiting for ADMA IDLE, stat=0x%hx\n",
529 status);
530
Robert Hancock2dec7552006-11-26 14:20:19 -0600531 tmp = readw(mmio + NV_ADMA_CTL);
532 writew(tmp & ~NV_ADMA_CTL_GO, mmio + NV_ADMA_CTL);
533
Robert Hancocka2cfe812007-02-05 16:26:03 -0800534 count = 0;
535 status = readw(mmio + NV_ADMA_STAT);
536 while(!(status & NV_ADMA_STAT_LEGACY) && count < 20) {
537 ndelay(50);
538 status = readw(mmio + NV_ADMA_STAT);
539 count++;
540 }
541 if(count == 20)
542 ata_port_printk(ap, KERN_WARNING,
543 "timeout waiting for ADMA LEGACY, stat=0x%hx\n",
544 status);
545
Robert Hancock2dec7552006-11-26 14:20:19 -0600546 pp->flags |= NV_ADMA_PORT_REGISTER_MODE;
547}
548
549static void nv_adma_mode(struct ata_port *ap)
550{
Robert Hancock2dec7552006-11-26 14:20:19 -0600551 struct nv_adma_port_priv *pp = ap->private_data;
Robert Hancockcdf56bc2007-01-03 18:13:57 -0600552 void __iomem *mmio = pp->ctl_block;
Robert Hancocka2cfe812007-02-05 16:26:03 -0800553 u16 tmp, status;
554 int count = 0;
Robert Hancock2dec7552006-11-26 14:20:19 -0600555
556 if (!(pp->flags & NV_ADMA_PORT_REGISTER_MODE))
557 return;
Jeff Garzikf20b16f2006-12-11 11:14:06 -0500558
Robert Hancock2dec7552006-11-26 14:20:19 -0600559 WARN_ON(pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE);
560
561 tmp = readw(mmio + NV_ADMA_CTL);
562 writew(tmp | NV_ADMA_CTL_GO, mmio + NV_ADMA_CTL);
563
Robert Hancocka2cfe812007-02-05 16:26:03 -0800564 status = readw(mmio + NV_ADMA_STAT);
565 while(((status & NV_ADMA_STAT_LEGACY) ||
566 !(status & NV_ADMA_STAT_IDLE)) && count < 20) {
567 ndelay(50);
568 status = readw(mmio + NV_ADMA_STAT);
569 count++;
570 }
571 if(count == 20)
572 ata_port_printk(ap, KERN_WARNING,
573 "timeout waiting for ADMA LEGACY clear and IDLE, stat=0x%hx\n",
574 status);
575
Robert Hancock2dec7552006-11-26 14:20:19 -0600576 pp->flags &= ~NV_ADMA_PORT_REGISTER_MODE;
577}
578
Robert Hancockfbbb2622006-10-27 19:08:41 -0700579static int nv_adma_slave_config(struct scsi_device *sdev)
580{
581 struct ata_port *ap = ata_shost_to_port(sdev->host);
Robert Hancock2dec7552006-11-26 14:20:19 -0600582 struct nv_adma_port_priv *pp = ap->private_data;
583 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
Robert Hancockfbbb2622006-10-27 19:08:41 -0700584 u64 bounce_limit;
585 unsigned long segment_boundary;
586 unsigned short sg_tablesize;
587 int rc;
Robert Hancock2dec7552006-11-26 14:20:19 -0600588 int adma_enable;
589 u32 current_reg, new_reg, config_mask;
Robert Hancockfbbb2622006-10-27 19:08:41 -0700590
591 rc = ata_scsi_slave_config(sdev);
592
593 if (sdev->id >= ATA_MAX_DEVICES || sdev->channel || sdev->lun)
594 /* Not a proper libata device, ignore */
595 return rc;
596
597 if (ap->device[sdev->id].class == ATA_DEV_ATAPI) {
598 /*
599 * NVIDIA reports that ADMA mode does not support ATAPI commands.
600 * Therefore ATAPI commands are sent through the legacy interface.
601 * However, the legacy interface only supports 32-bit DMA.
602 * Restrict DMA parameters as required by the legacy interface
603 * when an ATAPI device is connected.
604 */
605 bounce_limit = ATA_DMA_MASK;
606 segment_boundary = ATA_DMA_BOUNDARY;
607 /* Subtract 1 since an extra entry may be needed for padding, see
608 libata-scsi.c */
609 sg_tablesize = LIBATA_MAX_PRD - 1;
Jeff Garzikf20b16f2006-12-11 11:14:06 -0500610
Robert Hancock2dec7552006-11-26 14:20:19 -0600611 /* Since the legacy DMA engine is in use, we need to disable ADMA
612 on the port. */
613 adma_enable = 0;
614 nv_adma_register_mode(ap);
Robert Hancockfbbb2622006-10-27 19:08:41 -0700615 }
616 else {
617 bounce_limit = *ap->dev->dma_mask;
618 segment_boundary = NV_ADMA_DMA_BOUNDARY;
619 sg_tablesize = NV_ADMA_SGTBL_TOTAL_LEN;
Robert Hancock2dec7552006-11-26 14:20:19 -0600620 adma_enable = 1;
Robert Hancockfbbb2622006-10-27 19:08:41 -0700621 }
Jeff Garzikf20b16f2006-12-11 11:14:06 -0500622
Robert Hancock2dec7552006-11-26 14:20:19 -0600623 pci_read_config_dword(pdev, NV_MCP_SATA_CFG_20, &current_reg);
Robert Hancockfbbb2622006-10-27 19:08:41 -0700624
Robert Hancock2dec7552006-11-26 14:20:19 -0600625 if(ap->port_no == 1)
626 config_mask = NV_MCP_SATA_CFG_20_PORT1_EN |
627 NV_MCP_SATA_CFG_20_PORT1_PWB_EN;
628 else
629 config_mask = NV_MCP_SATA_CFG_20_PORT0_EN |
630 NV_MCP_SATA_CFG_20_PORT0_PWB_EN;
Jeff Garzikf20b16f2006-12-11 11:14:06 -0500631
Robert Hancock2dec7552006-11-26 14:20:19 -0600632 if(adma_enable) {
633 new_reg = current_reg | config_mask;
634 pp->flags &= ~NV_ADMA_ATAPI_SETUP_COMPLETE;
635 }
636 else {
637 new_reg = current_reg & ~config_mask;
638 pp->flags |= NV_ADMA_ATAPI_SETUP_COMPLETE;
639 }
Jeff Garzikf20b16f2006-12-11 11:14:06 -0500640
Robert Hancock2dec7552006-11-26 14:20:19 -0600641 if(current_reg != new_reg)
642 pci_write_config_dword(pdev, NV_MCP_SATA_CFG_20, new_reg);
Jeff Garzikf20b16f2006-12-11 11:14:06 -0500643
Robert Hancockfbbb2622006-10-27 19:08:41 -0700644 blk_queue_bounce_limit(sdev->request_queue, bounce_limit);
645 blk_queue_segment_boundary(sdev->request_queue, segment_boundary);
646 blk_queue_max_hw_segments(sdev->request_queue, sg_tablesize);
647 ata_port_printk(ap, KERN_INFO,
648 "bounce limit 0x%llX, segment boundary 0x%lX, hw segs %hu\n",
649 (unsigned long long)bounce_limit, segment_boundary, sg_tablesize);
650 return rc;
651}
652
Robert Hancock2dec7552006-11-26 14:20:19 -0600653static int nv_adma_check_atapi_dma(struct ata_queued_cmd *qc)
654{
655 struct nv_adma_port_priv *pp = qc->ap->private_data;
656 return !(pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE);
657}
658
Robert Hancockf2fb3442007-03-26 21:43:36 -0800659static void nv_adma_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
660{
661 /* Since commands where a result TF is requested are not
662 executed in ADMA mode, the only time this function will be called
663 in ADMA mode will be if a command fails. In this case we
664 don't care about going into register mode with ADMA commands
665 pending, as the commands will all shortly be aborted anyway. */
666 nv_adma_register_mode(ap);
667
668 ata_tf_read(ap, tf);
669}
670
Robert Hancock2dec7552006-11-26 14:20:19 -0600671static unsigned int nv_adma_tf_to_cpb(struct ata_taskfile *tf, __le16 *cpb)
Robert Hancockfbbb2622006-10-27 19:08:41 -0700672{
673 unsigned int idx = 0;
674
Robert Hancockac3d6b82007-02-19 19:02:46 -0600675 if(tf->flags & ATA_TFLAG_ISADDR) {
676 if (tf->flags & ATA_TFLAG_LBA48) {
677 cpb[idx++] = cpu_to_le16((ATA_REG_ERR << 8) | tf->hob_feature | WNB);
678 cpb[idx++] = cpu_to_le16((ATA_REG_NSECT << 8) | tf->hob_nsect);
679 cpb[idx++] = cpu_to_le16((ATA_REG_LBAL << 8) | tf->hob_lbal);
680 cpb[idx++] = cpu_to_le16((ATA_REG_LBAM << 8) | tf->hob_lbam);
681 cpb[idx++] = cpu_to_le16((ATA_REG_LBAH << 8) | tf->hob_lbah);
682 cpb[idx++] = cpu_to_le16((ATA_REG_ERR << 8) | tf->feature);
683 } else
684 cpb[idx++] = cpu_to_le16((ATA_REG_ERR << 8) | tf->feature | WNB);
Jeff Garzika84471f2007-02-26 05:51:33 -0500685
Robert Hancockac3d6b82007-02-19 19:02:46 -0600686 cpb[idx++] = cpu_to_le16((ATA_REG_NSECT << 8) | tf->nsect);
687 cpb[idx++] = cpu_to_le16((ATA_REG_LBAL << 8) | tf->lbal);
688 cpb[idx++] = cpu_to_le16((ATA_REG_LBAM << 8) | tf->lbam);
689 cpb[idx++] = cpu_to_le16((ATA_REG_LBAH << 8) | tf->lbah);
Robert Hancockfbbb2622006-10-27 19:08:41 -0700690 }
Jeff Garzika84471f2007-02-26 05:51:33 -0500691
Robert Hancockac3d6b82007-02-19 19:02:46 -0600692 if(tf->flags & ATA_TFLAG_DEVICE)
693 cpb[idx++] = cpu_to_le16((ATA_REG_DEVICE << 8) | tf->device);
Robert Hancockfbbb2622006-10-27 19:08:41 -0700694
695 cpb[idx++] = cpu_to_le16((ATA_REG_CMD << 8) | tf->command | CMDEND);
Jeff Garzika84471f2007-02-26 05:51:33 -0500696
Robert Hancockac3d6b82007-02-19 19:02:46 -0600697 while(idx < 12)
698 cpb[idx++] = cpu_to_le16(IGN);
Robert Hancockfbbb2622006-10-27 19:08:41 -0700699
700 return idx;
701}
702
Robert Hancock5bd28a42007-02-05 16:26:01 -0800703static int nv_adma_check_cpb(struct ata_port *ap, int cpb_num, int force_err)
Robert Hancockfbbb2622006-10-27 19:08:41 -0700704{
705 struct nv_adma_port_priv *pp = ap->private_data;
Robert Hancock2dec7552006-11-26 14:20:19 -0600706 u8 flags = pp->cpb[cpb_num].resp_flags;
Robert Hancockfbbb2622006-10-27 19:08:41 -0700707
708 VPRINTK("CPB %d, flags=0x%x\n", cpb_num, flags);
709
Robert Hancock5bd28a42007-02-05 16:26:01 -0800710 if (unlikely((force_err ||
711 flags & (NV_CPB_RESP_ATA_ERR |
712 NV_CPB_RESP_CMD_ERR |
713 NV_CPB_RESP_CPB_ERR)))) {
714 struct ata_eh_info *ehi = &ap->eh_info;
715 int freeze = 0;
716
717 ata_ehi_clear_desc(ehi);
Tejun Heob64bbc32007-07-16 14:29:39 +0900718 __ata_ehi_push_desc(ehi, "CPB resp_flags 0x%x: ", flags );
Robert Hancock5bd28a42007-02-05 16:26:01 -0800719 if (flags & NV_CPB_RESP_ATA_ERR) {
Tejun Heob64bbc32007-07-16 14:29:39 +0900720 ata_ehi_push_desc(ehi, "ATA error");
Robert Hancock5bd28a42007-02-05 16:26:01 -0800721 ehi->err_mask |= AC_ERR_DEV;
722 } else if (flags & NV_CPB_RESP_CMD_ERR) {
Tejun Heob64bbc32007-07-16 14:29:39 +0900723 ata_ehi_push_desc(ehi, "CMD error");
Robert Hancock5bd28a42007-02-05 16:26:01 -0800724 ehi->err_mask |= AC_ERR_DEV;
725 } else if (flags & NV_CPB_RESP_CPB_ERR) {
Tejun Heob64bbc32007-07-16 14:29:39 +0900726 ata_ehi_push_desc(ehi, "CPB error");
Robert Hancock5bd28a42007-02-05 16:26:01 -0800727 ehi->err_mask |= AC_ERR_SYSTEM;
728 freeze = 1;
729 } else {
730 /* notifier error, but no error in CPB flags? */
Tejun Heob64bbc32007-07-16 14:29:39 +0900731 ata_ehi_push_desc(ehi, "unknown");
Robert Hancock5bd28a42007-02-05 16:26:01 -0800732 ehi->err_mask |= AC_ERR_OTHER;
733 freeze = 1;
734 }
735 /* Kill all commands. EH will determine what actually failed. */
736 if (freeze)
737 ata_port_freeze(ap);
738 else
739 ata_port_abort(ap);
740 return 1;
741 }
742
Robert Hancockf2fb3442007-03-26 21:43:36 -0800743 if (likely(flags & NV_CPB_RESP_DONE)) {
Robert Hancockfbbb2622006-10-27 19:08:41 -0700744 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, cpb_num);
Robert Hancock5bd28a42007-02-05 16:26:01 -0800745 VPRINTK("CPB flags done, flags=0x%x\n", flags);
746 if (likely(qc)) {
Robert Hancockf2fb3442007-03-26 21:43:36 -0800747 DPRINTK("Completing qc from tag %d\n",cpb_num);
Robert Hancockfbbb2622006-10-27 19:08:41 -0700748 ata_qc_complete(qc);
Robert Hancock2a54cf72007-02-21 23:53:03 -0600749 } else {
750 struct ata_eh_info *ehi = &ap->eh_info;
751 /* Notifier bits set without a command may indicate the drive
752 is misbehaving. Raise host state machine violation on this
753 condition. */
754 ata_port_printk(ap, KERN_ERR, "notifier for tag %d with no command?\n",
755 cpb_num);
756 ehi->err_mask |= AC_ERR_HSM;
757 ehi->action |= ATA_EH_SOFTRESET;
758 ata_port_freeze(ap);
759 return 1;
Robert Hancockfbbb2622006-10-27 19:08:41 -0700760 }
761 }
Robert Hancock5bd28a42007-02-05 16:26:01 -0800762 return 0;
Robert Hancockfbbb2622006-10-27 19:08:41 -0700763}
764
Robert Hancock2dec7552006-11-26 14:20:19 -0600765static int nv_host_intr(struct ata_port *ap, u8 irq_stat)
766{
767 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->active_tag);
Robert Hancock2dec7552006-11-26 14:20:19 -0600768
769 /* freeze if hotplugged */
770 if (unlikely(irq_stat & (NV_INT_ADDED | NV_INT_REMOVED))) {
771 ata_port_freeze(ap);
772 return 1;
773 }
774
775 /* bail out if not our interrupt */
776 if (!(irq_stat & NV_INT_DEV))
777 return 0;
778
779 /* DEV interrupt w/ no active qc? */
780 if (unlikely(!qc || (qc->tf.flags & ATA_TFLAG_POLLING))) {
781 ata_check_status(ap);
782 return 1;
783 }
784
785 /* handle interrupt */
Robert Hancockf740d162007-01-23 20:09:02 -0600786 return ata_host_intr(ap, qc);
Robert Hancock2dec7552006-11-26 14:20:19 -0600787}
788
Robert Hancockfbbb2622006-10-27 19:08:41 -0700789static irqreturn_t nv_adma_interrupt(int irq, void *dev_instance)
790{
791 struct ata_host *host = dev_instance;
792 int i, handled = 0;
Robert Hancock2dec7552006-11-26 14:20:19 -0600793 u32 notifier_clears[2];
Robert Hancockfbbb2622006-10-27 19:08:41 -0700794
795 spin_lock(&host->lock);
796
797 for (i = 0; i < host->n_ports; i++) {
798 struct ata_port *ap = host->ports[i];
Robert Hancock2dec7552006-11-26 14:20:19 -0600799 notifier_clears[i] = 0;
Robert Hancockfbbb2622006-10-27 19:08:41 -0700800
801 if (ap && !(ap->flags & ATA_FLAG_DISABLED)) {
802 struct nv_adma_port_priv *pp = ap->private_data;
Robert Hancockcdf56bc2007-01-03 18:13:57 -0600803 void __iomem *mmio = pp->ctl_block;
Robert Hancockfbbb2622006-10-27 19:08:41 -0700804 u16 status;
805 u32 gen_ctl;
Robert Hancockfbbb2622006-10-27 19:08:41 -0700806 u32 notifier, notifier_error;
Jeff Garzika617c092007-05-21 20:14:23 -0400807
Robert Hancock53014e22007-05-05 15:36:36 -0600808 /* if ADMA is disabled, use standard ata interrupt handler */
809 if (pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE) {
810 u8 irq_stat = readb(host->iomap[NV_MMIO_BAR] + NV_INT_STATUS_CK804)
811 >> (NV_INT_PORT_SHIFT * i);
812 handled += nv_host_intr(ap, irq_stat);
813 continue;
814 }
Robert Hancockfbbb2622006-10-27 19:08:41 -0700815
Robert Hancock53014e22007-05-05 15:36:36 -0600816 /* if in ATA register mode, check for standard interrupts */
Robert Hancockfbbb2622006-10-27 19:08:41 -0700817 if (pp->flags & NV_ADMA_PORT_REGISTER_MODE) {
Tejun Heo0d5ff562007-02-01 15:06:36 +0900818 u8 irq_stat = readb(host->iomap[NV_MMIO_BAR] + NV_INT_STATUS_CK804)
Robert Hancock2dec7552006-11-26 14:20:19 -0600819 >> (NV_INT_PORT_SHIFT * i);
Robert Hancockf740d162007-01-23 20:09:02 -0600820 if(ata_tag_valid(ap->active_tag))
821 /** NV_INT_DEV indication seems unreliable at times
822 at least in ADMA mode. Force it on always when a
823 command is active, to prevent losing interrupts. */
824 irq_stat |= NV_INT_DEV;
Robert Hancock2dec7552006-11-26 14:20:19 -0600825 handled += nv_host_intr(ap, irq_stat);
Robert Hancockfbbb2622006-10-27 19:08:41 -0700826 }
827
828 notifier = readl(mmio + NV_ADMA_NOTIFIER);
829 notifier_error = readl(mmio + NV_ADMA_NOTIFIER_ERROR);
Robert Hancock2dec7552006-11-26 14:20:19 -0600830 notifier_clears[i] = notifier | notifier_error;
Robert Hancockfbbb2622006-10-27 19:08:41 -0700831
Robert Hancockcdf56bc2007-01-03 18:13:57 -0600832 gen_ctl = readl(pp->gen_block + NV_ADMA_GEN_CTL);
Robert Hancockfbbb2622006-10-27 19:08:41 -0700833
Robert Hancockfbbb2622006-10-27 19:08:41 -0700834 if( !NV_ADMA_CHECK_INTR(gen_ctl, ap->port_no) && !notifier &&
835 !notifier_error)
836 /* Nothing to do */
837 continue;
838
839 status = readw(mmio + NV_ADMA_STAT);
840
841 /* Clear status. Ensure the controller sees the clearing before we start
842 looking at any of the CPB statuses, so that any CPB completions after
843 this point in the handler will raise another interrupt. */
844 writew(status, mmio + NV_ADMA_STAT);
845 readw(mmio + NV_ADMA_STAT); /* flush posted write */
846 rmb();
847
Robert Hancock5bd28a42007-02-05 16:26:01 -0800848 handled++; /* irq handled if we got here */
849
850 /* freeze if hotplugged or controller error */
851 if (unlikely(status & (NV_ADMA_STAT_HOTPLUG |
852 NV_ADMA_STAT_HOTUNPLUG |
Robert Hancock5278b502007-02-11 18:36:56 -0600853 NV_ADMA_STAT_TIMEOUT |
854 NV_ADMA_STAT_SERROR))) {
Robert Hancock5bd28a42007-02-05 16:26:01 -0800855 struct ata_eh_info *ehi = &ap->eh_info;
856
857 ata_ehi_clear_desc(ehi);
Tejun Heob64bbc32007-07-16 14:29:39 +0900858 __ata_ehi_push_desc(ehi, "ADMA status 0x%08x: ", status );
Robert Hancock5bd28a42007-02-05 16:26:01 -0800859 if (status & NV_ADMA_STAT_TIMEOUT) {
860 ehi->err_mask |= AC_ERR_SYSTEM;
Tejun Heob64bbc32007-07-16 14:29:39 +0900861 ata_ehi_push_desc(ehi, "timeout");
Robert Hancock5bd28a42007-02-05 16:26:01 -0800862 } else if (status & NV_ADMA_STAT_HOTPLUG) {
863 ata_ehi_hotplugged(ehi);
Tejun Heob64bbc32007-07-16 14:29:39 +0900864 ata_ehi_push_desc(ehi, "hotplug");
Robert Hancock5bd28a42007-02-05 16:26:01 -0800865 } else if (status & NV_ADMA_STAT_HOTUNPLUG) {
866 ata_ehi_hotplugged(ehi);
Tejun Heob64bbc32007-07-16 14:29:39 +0900867 ata_ehi_push_desc(ehi, "hot unplug");
Robert Hancock5278b502007-02-11 18:36:56 -0600868 } else if (status & NV_ADMA_STAT_SERROR) {
869 /* let libata analyze SError and figure out the cause */
Tejun Heob64bbc32007-07-16 14:29:39 +0900870 ata_ehi_push_desc(ehi, "SError");
871 } else
872 ata_ehi_push_desc(ehi, "unknown");
Robert Hancockfbbb2622006-10-27 19:08:41 -0700873 ata_port_freeze(ap);
Robert Hancockfbbb2622006-10-27 19:08:41 -0700874 continue;
875 }
876
Robert Hancock5bd28a42007-02-05 16:26:01 -0800877 if (status & (NV_ADMA_STAT_DONE |
878 NV_ADMA_STAT_CPBERR)) {
Robert Hancock8ba5e4c2007-03-08 18:02:18 -0600879 u32 check_commands;
Robert Hancock721449b2007-02-19 19:03:08 -0600880 int pos, error = 0;
Robert Hancock8ba5e4c2007-03-08 18:02:18 -0600881
882 if(ata_tag_valid(ap->active_tag))
883 check_commands = 1 << ap->active_tag;
884 else
885 check_commands = ap->sactive;
886
Robert Hancockfbbb2622006-10-27 19:08:41 -0700887 /** Check CPBs for completed commands */
Robert Hancock721449b2007-02-19 19:03:08 -0600888 while ((pos = ffs(check_commands)) && !error) {
889 pos--;
890 error = nv_adma_check_cpb(ap, pos,
891 notifier_error & (1 << pos) );
892 check_commands &= ~(1 << pos );
Robert Hancockfbbb2622006-10-27 19:08:41 -0700893 }
894 }
Robert Hancockfbbb2622006-10-27 19:08:41 -0700895 }
896 }
Jeff Garzikf20b16f2006-12-11 11:14:06 -0500897
Robert Hancock2dec7552006-11-26 14:20:19 -0600898 if(notifier_clears[0] || notifier_clears[1]) {
899 /* Note: Both notifier clear registers must be written
900 if either is set, even if one is zero, according to NVIDIA. */
Robert Hancockcdf56bc2007-01-03 18:13:57 -0600901 struct nv_adma_port_priv *pp = host->ports[0]->private_data;
902 writel(notifier_clears[0], pp->notifier_clear_block);
903 pp = host->ports[1]->private_data;
904 writel(notifier_clears[1], pp->notifier_clear_block);
Robert Hancock2dec7552006-11-26 14:20:19 -0600905 }
Robert Hancockfbbb2622006-10-27 19:08:41 -0700906
907 spin_unlock(&host->lock);
908
909 return IRQ_RETVAL(handled);
910}
911
Robert Hancock53014e22007-05-05 15:36:36 -0600912static void nv_adma_freeze(struct ata_port *ap)
913{
914 struct nv_adma_port_priv *pp = ap->private_data;
915 void __iomem *mmio = pp->ctl_block;
916 u16 tmp;
917
918 nv_ck804_freeze(ap);
919
920 if (pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE)
921 return;
922
923 /* clear any outstanding CK804 notifications */
924 writeb( NV_INT_ALL << (ap->port_no * NV_INT_PORT_SHIFT),
925 ap->host->iomap[NV_MMIO_BAR] + NV_INT_STATUS_CK804);
926
927 /* Disable interrupt */
928 tmp = readw(mmio + NV_ADMA_CTL);
929 writew( tmp & ~(NV_ADMA_CTL_AIEN | NV_ADMA_CTL_HOTPLUG_IEN),
930 mmio + NV_ADMA_CTL);
931 readw( mmio + NV_ADMA_CTL ); /* flush posted write */
932}
933
934static void nv_adma_thaw(struct ata_port *ap)
935{
936 struct nv_adma_port_priv *pp = ap->private_data;
937 void __iomem *mmio = pp->ctl_block;
938 u16 tmp;
939
940 nv_ck804_thaw(ap);
941
942 if (pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE)
943 return;
944
945 /* Enable interrupt */
946 tmp = readw(mmio + NV_ADMA_CTL);
947 writew( tmp | (NV_ADMA_CTL_AIEN | NV_ADMA_CTL_HOTPLUG_IEN),
948 mmio + NV_ADMA_CTL);
949 readw( mmio + NV_ADMA_CTL ); /* flush posted write */
950}
951
Robert Hancockfbbb2622006-10-27 19:08:41 -0700952static void nv_adma_irq_clear(struct ata_port *ap)
953{
Robert Hancockcdf56bc2007-01-03 18:13:57 -0600954 struct nv_adma_port_priv *pp = ap->private_data;
955 void __iomem *mmio = pp->ctl_block;
Robert Hancock53014e22007-05-05 15:36:36 -0600956 u32 notifier_clears[2];
957
958 if (pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE) {
959 ata_bmdma_irq_clear(ap);
960 return;
961 }
962
963 /* clear any outstanding CK804 notifications */
964 writeb( NV_INT_ALL << (ap->port_no * NV_INT_PORT_SHIFT),
965 ap->host->iomap[NV_MMIO_BAR] + NV_INT_STATUS_CK804);
Robert Hancockfbbb2622006-10-27 19:08:41 -0700966
967 /* clear ADMA status */
Robert Hancock53014e22007-05-05 15:36:36 -0600968 writew(0xffff, mmio + NV_ADMA_STAT);
Jeff Garzika617c092007-05-21 20:14:23 -0400969
Robert Hancock53014e22007-05-05 15:36:36 -0600970 /* clear notifiers - note both ports need to be written with
971 something even though we are only clearing on one */
972 if (ap->port_no == 0) {
973 notifier_clears[0] = 0xFFFFFFFF;
974 notifier_clears[1] = 0;
975 } else {
976 notifier_clears[0] = 0;
977 notifier_clears[1] = 0xFFFFFFFF;
978 }
979 pp = ap->host->ports[0]->private_data;
980 writel(notifier_clears[0], pp->notifier_clear_block);
981 pp = ap->host->ports[1]->private_data;
982 writel(notifier_clears[1], pp->notifier_clear_block);
Robert Hancockfbbb2622006-10-27 19:08:41 -0700983}
984
Robert Hancockf5ecac22007-02-20 21:49:10 -0600985static void nv_adma_post_internal_cmd(struct ata_queued_cmd *qc)
Robert Hancockfbbb2622006-10-27 19:08:41 -0700986{
Robert Hancockf5ecac22007-02-20 21:49:10 -0600987 struct nv_adma_port_priv *pp = qc->ap->private_data;
Robert Hancockfbbb2622006-10-27 19:08:41 -0700988
Robert Hancockf5ecac22007-02-20 21:49:10 -0600989 if(pp->flags & NV_ADMA_PORT_REGISTER_MODE)
990 ata_bmdma_post_internal_cmd(qc);
Robert Hancockfbbb2622006-10-27 19:08:41 -0700991}
992
993static int nv_adma_port_start(struct ata_port *ap)
994{
995 struct device *dev = ap->host->dev;
996 struct nv_adma_port_priv *pp;
997 int rc;
998 void *mem;
999 dma_addr_t mem_dma;
Robert Hancockcdf56bc2007-01-03 18:13:57 -06001000 void __iomem *mmio;
Robert Hancockfbbb2622006-10-27 19:08:41 -07001001 u16 tmp;
1002
1003 VPRINTK("ENTER\n");
1004
1005 rc = ata_port_start(ap);
1006 if (rc)
1007 return rc;
1008
Tejun Heo24dc5f32007-01-20 16:00:28 +09001009 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
1010 if (!pp)
1011 return -ENOMEM;
Robert Hancockfbbb2622006-10-27 19:08:41 -07001012
Tejun Heo0d5ff562007-02-01 15:06:36 +09001013 mmio = ap->host->iomap[NV_MMIO_BAR] + NV_ADMA_PORT +
Robert Hancockcdf56bc2007-01-03 18:13:57 -06001014 ap->port_no * NV_ADMA_PORT_SIZE;
1015 pp->ctl_block = mmio;
Tejun Heo0d5ff562007-02-01 15:06:36 +09001016 pp->gen_block = ap->host->iomap[NV_MMIO_BAR] + NV_ADMA_GEN;
Robert Hancockcdf56bc2007-01-03 18:13:57 -06001017 pp->notifier_clear_block = pp->gen_block +
1018 NV_ADMA_NOTIFIER_CLEAR + (4 * ap->port_no);
1019
Tejun Heo24dc5f32007-01-20 16:00:28 +09001020 mem = dmam_alloc_coherent(dev, NV_ADMA_PORT_PRIV_DMA_SZ,
1021 &mem_dma, GFP_KERNEL);
1022 if (!mem)
1023 return -ENOMEM;
Robert Hancockfbbb2622006-10-27 19:08:41 -07001024 memset(mem, 0, NV_ADMA_PORT_PRIV_DMA_SZ);
1025
1026 /*
1027 * First item in chunk of DMA memory:
1028 * 128-byte command parameter block (CPB)
1029 * one for each command tag
1030 */
1031 pp->cpb = mem;
1032 pp->cpb_dma = mem_dma;
1033
1034 writel(mem_dma & 0xFFFFFFFF, mmio + NV_ADMA_CPB_BASE_LOW);
1035 writel((mem_dma >> 16 ) >> 16, mmio + NV_ADMA_CPB_BASE_HIGH);
1036
1037 mem += NV_ADMA_MAX_CPBS * NV_ADMA_CPB_SZ;
1038 mem_dma += NV_ADMA_MAX_CPBS * NV_ADMA_CPB_SZ;
1039
1040 /*
1041 * Second item: block of ADMA_SGTBL_LEN s/g entries
1042 */
1043 pp->aprd = mem;
1044 pp->aprd_dma = mem_dma;
1045
1046 ap->private_data = pp;
1047
1048 /* clear any outstanding interrupt conditions */
1049 writew(0xffff, mmio + NV_ADMA_STAT);
1050
1051 /* initialize port variables */
1052 pp->flags = NV_ADMA_PORT_REGISTER_MODE;
1053
1054 /* clear CPB fetch count */
1055 writew(0, mmio + NV_ADMA_CPB_COUNT);
1056
Robert Hancockcdf56bc2007-01-03 18:13:57 -06001057 /* clear GO for register mode, enable interrupt */
Robert Hancockfbbb2622006-10-27 19:08:41 -07001058 tmp = readw(mmio + NV_ADMA_CTL);
Robert Hancock5ce0cf62007-02-19 19:03:27 -06001059 writew( (tmp & ~NV_ADMA_CTL_GO) | NV_ADMA_CTL_AIEN |
1060 NV_ADMA_CTL_HOTPLUG_IEN, mmio + NV_ADMA_CTL);
Robert Hancockfbbb2622006-10-27 19:08:41 -07001061
1062 tmp = readw(mmio + NV_ADMA_CTL);
1063 writew(tmp | NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);
Robert Hancock5ce0cf62007-02-19 19:03:27 -06001064 readw( mmio + NV_ADMA_CTL ); /* flush posted write */
Robert Hancockfbbb2622006-10-27 19:08:41 -07001065 udelay(1);
1066 writew(tmp & ~NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);
Robert Hancock5ce0cf62007-02-19 19:03:27 -06001067 readw( mmio + NV_ADMA_CTL ); /* flush posted write */
Robert Hancockfbbb2622006-10-27 19:08:41 -07001068
1069 return 0;
Robert Hancockfbbb2622006-10-27 19:08:41 -07001070}
1071
1072static void nv_adma_port_stop(struct ata_port *ap)
1073{
Robert Hancockfbbb2622006-10-27 19:08:41 -07001074 struct nv_adma_port_priv *pp = ap->private_data;
Robert Hancockcdf56bc2007-01-03 18:13:57 -06001075 void __iomem *mmio = pp->ctl_block;
Robert Hancockfbbb2622006-10-27 19:08:41 -07001076
1077 VPRINTK("ENTER\n");
Robert Hancockfbbb2622006-10-27 19:08:41 -07001078 writew(0, mmio + NV_ADMA_CTL);
Robert Hancockfbbb2622006-10-27 19:08:41 -07001079}
1080
Tejun Heo438ac6d2007-03-02 17:31:26 +09001081#ifdef CONFIG_PM
Robert Hancockcdf56bc2007-01-03 18:13:57 -06001082static int nv_adma_port_suspend(struct ata_port *ap, pm_message_t mesg)
1083{
1084 struct nv_adma_port_priv *pp = ap->private_data;
1085 void __iomem *mmio = pp->ctl_block;
1086
1087 /* Go to register mode - clears GO */
1088 nv_adma_register_mode(ap);
1089
1090 /* clear CPB fetch count */
1091 writew(0, mmio + NV_ADMA_CPB_COUNT);
1092
1093 /* disable interrupt, shut down port */
1094 writew(0, mmio + NV_ADMA_CTL);
1095
1096 return 0;
1097}
1098
1099static int nv_adma_port_resume(struct ata_port *ap)
1100{
1101 struct nv_adma_port_priv *pp = ap->private_data;
1102 void __iomem *mmio = pp->ctl_block;
1103 u16 tmp;
1104
1105 /* set CPB block location */
1106 writel(pp->cpb_dma & 0xFFFFFFFF, mmio + NV_ADMA_CPB_BASE_LOW);
1107 writel((pp->cpb_dma >> 16 ) >> 16, mmio + NV_ADMA_CPB_BASE_HIGH);
1108
1109 /* clear any outstanding interrupt conditions */
1110 writew(0xffff, mmio + NV_ADMA_STAT);
1111
1112 /* initialize port variables */
1113 pp->flags |= NV_ADMA_PORT_REGISTER_MODE;
1114
1115 /* clear CPB fetch count */
1116 writew(0, mmio + NV_ADMA_CPB_COUNT);
1117
1118 /* clear GO for register mode, enable interrupt */
1119 tmp = readw(mmio + NV_ADMA_CTL);
Robert Hancock5ce0cf62007-02-19 19:03:27 -06001120 writew( (tmp & ~NV_ADMA_CTL_GO) | NV_ADMA_CTL_AIEN |
1121 NV_ADMA_CTL_HOTPLUG_IEN, mmio + NV_ADMA_CTL);
Robert Hancockcdf56bc2007-01-03 18:13:57 -06001122
1123 tmp = readw(mmio + NV_ADMA_CTL);
1124 writew(tmp | NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);
Robert Hancock5ce0cf62007-02-19 19:03:27 -06001125 readw( mmio + NV_ADMA_CTL ); /* flush posted write */
Robert Hancockcdf56bc2007-01-03 18:13:57 -06001126 udelay(1);
1127 writew(tmp & ~NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);
Robert Hancock5ce0cf62007-02-19 19:03:27 -06001128 readw( mmio + NV_ADMA_CTL ); /* flush posted write */
Robert Hancockcdf56bc2007-01-03 18:13:57 -06001129
1130 return 0;
1131}
Tejun Heo438ac6d2007-03-02 17:31:26 +09001132#endif
Robert Hancockfbbb2622006-10-27 19:08:41 -07001133
Tejun Heo9a829cc2007-04-17 23:44:08 +09001134static void nv_adma_setup_port(struct ata_port *ap)
Robert Hancockfbbb2622006-10-27 19:08:41 -07001135{
Tejun Heo9a829cc2007-04-17 23:44:08 +09001136 void __iomem *mmio = ap->host->iomap[NV_MMIO_BAR];
1137 struct ata_ioports *ioport = &ap->ioaddr;
Robert Hancockfbbb2622006-10-27 19:08:41 -07001138
1139 VPRINTK("ENTER\n");
1140
Tejun Heo9a829cc2007-04-17 23:44:08 +09001141 mmio += NV_ADMA_PORT + ap->port_no * NV_ADMA_PORT_SIZE;
Robert Hancockfbbb2622006-10-27 19:08:41 -07001142
Tejun Heo0d5ff562007-02-01 15:06:36 +09001143 ioport->cmd_addr = mmio;
1144 ioport->data_addr = mmio + (ATA_REG_DATA * 4);
Robert Hancockfbbb2622006-10-27 19:08:41 -07001145 ioport->error_addr =
Tejun Heo0d5ff562007-02-01 15:06:36 +09001146 ioport->feature_addr = mmio + (ATA_REG_ERR * 4);
1147 ioport->nsect_addr = mmio + (ATA_REG_NSECT * 4);
1148 ioport->lbal_addr = mmio + (ATA_REG_LBAL * 4);
1149 ioport->lbam_addr = mmio + (ATA_REG_LBAM * 4);
1150 ioport->lbah_addr = mmio + (ATA_REG_LBAH * 4);
1151 ioport->device_addr = mmio + (ATA_REG_DEVICE * 4);
Robert Hancockfbbb2622006-10-27 19:08:41 -07001152 ioport->status_addr =
Tejun Heo0d5ff562007-02-01 15:06:36 +09001153 ioport->command_addr = mmio + (ATA_REG_STATUS * 4);
Robert Hancockfbbb2622006-10-27 19:08:41 -07001154 ioport->altstatus_addr =
Tejun Heo0d5ff562007-02-01 15:06:36 +09001155 ioport->ctl_addr = mmio + 0x20;
Robert Hancockfbbb2622006-10-27 19:08:41 -07001156}
1157
Tejun Heo9a829cc2007-04-17 23:44:08 +09001158static int nv_adma_host_init(struct ata_host *host)
Robert Hancockfbbb2622006-10-27 19:08:41 -07001159{
Tejun Heo9a829cc2007-04-17 23:44:08 +09001160 struct pci_dev *pdev = to_pci_dev(host->dev);
Robert Hancockfbbb2622006-10-27 19:08:41 -07001161 unsigned int i;
1162 u32 tmp32;
1163
1164 VPRINTK("ENTER\n");
1165
1166 /* enable ADMA on the ports */
1167 pci_read_config_dword(pdev, NV_MCP_SATA_CFG_20, &tmp32);
1168 tmp32 |= NV_MCP_SATA_CFG_20_PORT0_EN |
1169 NV_MCP_SATA_CFG_20_PORT0_PWB_EN |
1170 NV_MCP_SATA_CFG_20_PORT1_EN |
1171 NV_MCP_SATA_CFG_20_PORT1_PWB_EN;
1172
1173 pci_write_config_dword(pdev, NV_MCP_SATA_CFG_20, tmp32);
1174
Tejun Heo9a829cc2007-04-17 23:44:08 +09001175 for (i = 0; i < host->n_ports; i++)
1176 nv_adma_setup_port(host->ports[i]);
Robert Hancockfbbb2622006-10-27 19:08:41 -07001177
Robert Hancockfbbb2622006-10-27 19:08:41 -07001178 return 0;
1179}
1180
1181static void nv_adma_fill_aprd(struct ata_queued_cmd *qc,
1182 struct scatterlist *sg,
1183 int idx,
1184 struct nv_adma_prd *aprd)
1185{
Robert Hancock41949ed2007-02-19 19:02:27 -06001186 u8 flags = 0;
Robert Hancockfbbb2622006-10-27 19:08:41 -07001187 if (qc->tf.flags & ATA_TFLAG_WRITE)
1188 flags |= NV_APRD_WRITE;
1189 if (idx == qc->n_elem - 1)
1190 flags |= NV_APRD_END;
1191 else if (idx != 4)
1192 flags |= NV_APRD_CONT;
1193
1194 aprd->addr = cpu_to_le64(((u64)sg_dma_address(sg)));
1195 aprd->len = cpu_to_le32(((u32)sg_dma_len(sg))); /* len in bytes */
Robert Hancock2dec7552006-11-26 14:20:19 -06001196 aprd->flags = flags;
Robert Hancock41949ed2007-02-19 19:02:27 -06001197 aprd->packet_len = 0;
Robert Hancockfbbb2622006-10-27 19:08:41 -07001198}
1199
1200static void nv_adma_fill_sg(struct ata_queued_cmd *qc, struct nv_adma_cpb *cpb)
1201{
1202 struct nv_adma_port_priv *pp = qc->ap->private_data;
1203 unsigned int idx;
1204 struct nv_adma_prd *aprd;
1205 struct scatterlist *sg;
1206
1207 VPRINTK("ENTER\n");
1208
1209 idx = 0;
1210
1211 ata_for_each_sg(sg, qc) {
1212 aprd = (idx < 5) ? &cpb->aprd[idx] : &pp->aprd[NV_ADMA_SGTBL_LEN * qc->tag + (idx-5)];
1213 nv_adma_fill_aprd(qc, sg, idx, aprd);
1214 idx++;
1215 }
1216 if (idx > 5)
1217 cpb->next_aprd = cpu_to_le64(((u64)(pp->aprd_dma + NV_ADMA_SGTBL_SZ * qc->tag)));
Robert Hancock41949ed2007-02-19 19:02:27 -06001218 else
1219 cpb->next_aprd = cpu_to_le64(0);
Robert Hancockfbbb2622006-10-27 19:08:41 -07001220}
1221
Robert Hancock382a6652007-02-05 16:26:02 -08001222static int nv_adma_use_reg_mode(struct ata_queued_cmd *qc)
1223{
1224 struct nv_adma_port_priv *pp = qc->ap->private_data;
1225
1226 /* ADMA engine can only be used for non-ATAPI DMA commands,
Robert Hancockf2fb3442007-03-26 21:43:36 -08001227 or interrupt-driven no-data commands, where a result taskfile
1228 is not required. */
Robert Hancock382a6652007-02-05 16:26:02 -08001229 if((pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE) ||
Robert Hancockf2fb3442007-03-26 21:43:36 -08001230 (qc->tf.flags & ATA_TFLAG_POLLING) ||
1231 (qc->flags & ATA_QCFLAG_RESULT_TF))
Robert Hancock382a6652007-02-05 16:26:02 -08001232 return 1;
1233
1234 if((qc->flags & ATA_QCFLAG_DMAMAP) ||
1235 (qc->tf.protocol == ATA_PROT_NODATA))
1236 return 0;
1237
1238 return 1;
1239}
1240
Robert Hancockfbbb2622006-10-27 19:08:41 -07001241static void nv_adma_qc_prep(struct ata_queued_cmd *qc)
1242{
1243 struct nv_adma_port_priv *pp = qc->ap->private_data;
1244 struct nv_adma_cpb *cpb = &pp->cpb[qc->tag];
1245 u8 ctl_flags = NV_CPB_CTL_CPB_VALID |
Robert Hancockfbbb2622006-10-27 19:08:41 -07001246 NV_CPB_CTL_IEN;
1247
Robert Hancock382a6652007-02-05 16:26:02 -08001248 if (nv_adma_use_reg_mode(qc)) {
Robert Hancock2dec7552006-11-26 14:20:19 -06001249 nv_adma_register_mode(qc->ap);
Robert Hancockfbbb2622006-10-27 19:08:41 -07001250 ata_qc_prep(qc);
1251 return;
1252 }
1253
Robert Hancock41949ed2007-02-19 19:02:27 -06001254 cpb->resp_flags = NV_CPB_RESP_DONE;
1255 wmb();
1256 cpb->ctl_flags = 0;
1257 wmb();
Robert Hancockfbbb2622006-10-27 19:08:41 -07001258
1259 cpb->len = 3;
1260 cpb->tag = qc->tag;
1261 cpb->next_cpb_idx = 0;
1262
1263 /* turn on NCQ flags for NCQ commands */
1264 if (qc->tf.protocol == ATA_PROT_NCQ)
1265 ctl_flags |= NV_CPB_CTL_QUEUE | NV_CPB_CTL_FPDMA;
1266
Robert Hancockcdf56bc2007-01-03 18:13:57 -06001267 VPRINTK("qc->flags = 0x%lx\n", qc->flags);
1268
Robert Hancockfbbb2622006-10-27 19:08:41 -07001269 nv_adma_tf_to_cpb(&qc->tf, cpb->tf);
1270
Robert Hancock382a6652007-02-05 16:26:02 -08001271 if(qc->flags & ATA_QCFLAG_DMAMAP) {
1272 nv_adma_fill_sg(qc, cpb);
1273 ctl_flags |= NV_CPB_CTL_APRD_VALID;
1274 } else
1275 memset(&cpb->aprd[0], 0, sizeof(struct nv_adma_prd) * 5);
Robert Hancockfbbb2622006-10-27 19:08:41 -07001276
1277 /* Be paranoid and don't let the device see NV_CPB_CTL_CPB_VALID until we are
1278 finished filling in all of the contents */
1279 wmb();
1280 cpb->ctl_flags = ctl_flags;
Robert Hancock41949ed2007-02-19 19:02:27 -06001281 wmb();
1282 cpb->resp_flags = 0;
Robert Hancockfbbb2622006-10-27 19:08:41 -07001283}
1284
1285static unsigned int nv_adma_qc_issue(struct ata_queued_cmd *qc)
1286{
Robert Hancock2dec7552006-11-26 14:20:19 -06001287 struct nv_adma_port_priv *pp = qc->ap->private_data;
Robert Hancockcdf56bc2007-01-03 18:13:57 -06001288 void __iomem *mmio = pp->ctl_block;
Robert Hancock5e5c74a2007-02-19 18:42:30 -06001289 int curr_ncq = (qc->tf.protocol == ATA_PROT_NCQ);
Robert Hancockfbbb2622006-10-27 19:08:41 -07001290
1291 VPRINTK("ENTER\n");
1292
Robert Hancock382a6652007-02-05 16:26:02 -08001293 if (nv_adma_use_reg_mode(qc)) {
Robert Hancockfbbb2622006-10-27 19:08:41 -07001294 /* use ATA register mode */
Robert Hancock382a6652007-02-05 16:26:02 -08001295 VPRINTK("using ATA register mode: 0x%lx\n", qc->flags);
Robert Hancockfbbb2622006-10-27 19:08:41 -07001296 nv_adma_register_mode(qc->ap);
1297 return ata_qc_issue_prot(qc);
1298 } else
1299 nv_adma_mode(qc->ap);
1300
1301 /* write append register, command tag in lower 8 bits
1302 and (number of cpbs to append -1) in top 8 bits */
1303 wmb();
Robert Hancock5e5c74a2007-02-19 18:42:30 -06001304
1305 if(curr_ncq != pp->last_issue_ncq) {
1306 /* Seems to need some delay before switching between NCQ and non-NCQ
1307 commands, else we get command timeouts and such. */
1308 udelay(20);
1309 pp->last_issue_ncq = curr_ncq;
1310 }
1311
Robert Hancockfbbb2622006-10-27 19:08:41 -07001312 writew(qc->tag, mmio + NV_ADMA_APPEND);
1313
1314 DPRINTK("Issued tag %u\n",qc->tag);
1315
1316 return 0;
1317}
1318
David Howells7d12e782006-10-05 14:55:46 +01001319static irqreturn_t nv_generic_interrupt(int irq, void *dev_instance)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001320{
Jeff Garzikcca39742006-08-24 03:19:22 -04001321 struct ata_host *host = dev_instance;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001322 unsigned int i;
1323 unsigned int handled = 0;
1324 unsigned long flags;
1325
Jeff Garzikcca39742006-08-24 03:19:22 -04001326 spin_lock_irqsave(&host->lock, flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001327
Jeff Garzikcca39742006-08-24 03:19:22 -04001328 for (i = 0; i < host->n_ports; i++) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001329 struct ata_port *ap;
1330
Jeff Garzikcca39742006-08-24 03:19:22 -04001331 ap = host->ports[i];
Tejun Heoc1389502005-08-22 14:59:24 +09001332 if (ap &&
Jeff Garzik029f5462006-04-02 10:30:40 -04001333 !(ap->flags & ATA_FLAG_DISABLED)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001334 struct ata_queued_cmd *qc;
1335
1336 qc = ata_qc_from_tag(ap, ap->active_tag);
Albert Leee50362e2005-09-27 17:39:50 +08001337 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)))
Linus Torvalds1da177e2005-04-16 15:20:36 -07001338 handled += ata_host_intr(ap, qc);
Andrew Chewb8870302006-01-04 19:13:04 -08001339 else
1340 // No request pending? Clear interrupt status
1341 // anyway, in case there's one pending.
1342 ap->ops->check_status(ap);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001343 }
1344
1345 }
1346
Jeff Garzikcca39742006-08-24 03:19:22 -04001347 spin_unlock_irqrestore(&host->lock, flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001348
1349 return IRQ_RETVAL(handled);
1350}
1351
Jeff Garzikcca39742006-08-24 03:19:22 -04001352static irqreturn_t nv_do_interrupt(struct ata_host *host, u8 irq_stat)
Tejun Heoada364e2006-06-17 15:49:56 +09001353{
1354 int i, handled = 0;
1355
Jeff Garzikcca39742006-08-24 03:19:22 -04001356 for (i = 0; i < host->n_ports; i++) {
1357 struct ata_port *ap = host->ports[i];
Tejun Heoada364e2006-06-17 15:49:56 +09001358
1359 if (ap && !(ap->flags & ATA_FLAG_DISABLED))
1360 handled += nv_host_intr(ap, irq_stat);
1361
1362 irq_stat >>= NV_INT_PORT_SHIFT;
1363 }
1364
1365 return IRQ_RETVAL(handled);
1366}
1367
David Howells7d12e782006-10-05 14:55:46 +01001368static irqreturn_t nv_nf2_interrupt(int irq, void *dev_instance)
Tejun Heoada364e2006-06-17 15:49:56 +09001369{
Jeff Garzikcca39742006-08-24 03:19:22 -04001370 struct ata_host *host = dev_instance;
Tejun Heoada364e2006-06-17 15:49:56 +09001371 u8 irq_stat;
1372 irqreturn_t ret;
1373
Jeff Garzikcca39742006-08-24 03:19:22 -04001374 spin_lock(&host->lock);
Tejun Heo0d5ff562007-02-01 15:06:36 +09001375 irq_stat = ioread8(host->ports[0]->ioaddr.scr_addr + NV_INT_STATUS);
Jeff Garzikcca39742006-08-24 03:19:22 -04001376 ret = nv_do_interrupt(host, irq_stat);
1377 spin_unlock(&host->lock);
Tejun Heoada364e2006-06-17 15:49:56 +09001378
1379 return ret;
1380}
1381
David Howells7d12e782006-10-05 14:55:46 +01001382static irqreturn_t nv_ck804_interrupt(int irq, void *dev_instance)
Tejun Heoada364e2006-06-17 15:49:56 +09001383{
Jeff Garzikcca39742006-08-24 03:19:22 -04001384 struct ata_host *host = dev_instance;
Tejun Heoada364e2006-06-17 15:49:56 +09001385 u8 irq_stat;
1386 irqreturn_t ret;
1387
Jeff Garzikcca39742006-08-24 03:19:22 -04001388 spin_lock(&host->lock);
Tejun Heo0d5ff562007-02-01 15:06:36 +09001389 irq_stat = readb(host->iomap[NV_MMIO_BAR] + NV_INT_STATUS_CK804);
Jeff Garzikcca39742006-08-24 03:19:22 -04001390 ret = nv_do_interrupt(host, irq_stat);
1391 spin_unlock(&host->lock);
Tejun Heoada364e2006-06-17 15:49:56 +09001392
1393 return ret;
1394}
1395
Tejun Heoda3dbb12007-07-16 14:29:40 +09001396static int nv_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001397{
Linus Torvalds1da177e2005-04-16 15:20:36 -07001398 if (sc_reg > SCR_CONTROL)
Tejun Heoda3dbb12007-07-16 14:29:40 +09001399 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001400
Tejun Heoda3dbb12007-07-16 14:29:40 +09001401 *val = ioread32(ap->ioaddr.scr_addr + (sc_reg * 4));
1402 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001403}
1404
Tejun Heoda3dbb12007-07-16 14:29:40 +09001405static int nv_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001406{
Linus Torvalds1da177e2005-04-16 15:20:36 -07001407 if (sc_reg > SCR_CONTROL)
Tejun Heoda3dbb12007-07-16 14:29:40 +09001408 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001409
Tejun Heo0d5ff562007-02-01 15:06:36 +09001410 iowrite32(val, ap->ioaddr.scr_addr + (sc_reg * 4));
Tejun Heoda3dbb12007-07-16 14:29:40 +09001411 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001412}
1413
Tejun Heo39f87582006-06-17 15:49:56 +09001414static void nv_nf2_freeze(struct ata_port *ap)
1415{
Tejun Heo0d5ff562007-02-01 15:06:36 +09001416 void __iomem *scr_addr = ap->host->ports[0]->ioaddr.scr_addr;
Tejun Heo39f87582006-06-17 15:49:56 +09001417 int shift = ap->port_no * NV_INT_PORT_SHIFT;
1418 u8 mask;
1419
Tejun Heo0d5ff562007-02-01 15:06:36 +09001420 mask = ioread8(scr_addr + NV_INT_ENABLE);
Tejun Heo39f87582006-06-17 15:49:56 +09001421 mask &= ~(NV_INT_ALL << shift);
Tejun Heo0d5ff562007-02-01 15:06:36 +09001422 iowrite8(mask, scr_addr + NV_INT_ENABLE);
Tejun Heo39f87582006-06-17 15:49:56 +09001423}
1424
1425static void nv_nf2_thaw(struct ata_port *ap)
1426{
Tejun Heo0d5ff562007-02-01 15:06:36 +09001427 void __iomem *scr_addr = ap->host->ports[0]->ioaddr.scr_addr;
Tejun Heo39f87582006-06-17 15:49:56 +09001428 int shift = ap->port_no * NV_INT_PORT_SHIFT;
1429 u8 mask;
1430
Tejun Heo0d5ff562007-02-01 15:06:36 +09001431 iowrite8(NV_INT_ALL << shift, scr_addr + NV_INT_STATUS);
Tejun Heo39f87582006-06-17 15:49:56 +09001432
Tejun Heo0d5ff562007-02-01 15:06:36 +09001433 mask = ioread8(scr_addr + NV_INT_ENABLE);
Tejun Heo39f87582006-06-17 15:49:56 +09001434 mask |= (NV_INT_MASK << shift);
Tejun Heo0d5ff562007-02-01 15:06:36 +09001435 iowrite8(mask, scr_addr + NV_INT_ENABLE);
Tejun Heo39f87582006-06-17 15:49:56 +09001436}
1437
1438static void nv_ck804_freeze(struct ata_port *ap)
1439{
Tejun Heo0d5ff562007-02-01 15:06:36 +09001440 void __iomem *mmio_base = ap->host->iomap[NV_MMIO_BAR];
Tejun Heo39f87582006-06-17 15:49:56 +09001441 int shift = ap->port_no * NV_INT_PORT_SHIFT;
1442 u8 mask;
1443
1444 mask = readb(mmio_base + NV_INT_ENABLE_CK804);
1445 mask &= ~(NV_INT_ALL << shift);
1446 writeb(mask, mmio_base + NV_INT_ENABLE_CK804);
1447}
1448
1449static void nv_ck804_thaw(struct ata_port *ap)
1450{
Tejun Heo0d5ff562007-02-01 15:06:36 +09001451 void __iomem *mmio_base = ap->host->iomap[NV_MMIO_BAR];
Tejun Heo39f87582006-06-17 15:49:56 +09001452 int shift = ap->port_no * NV_INT_PORT_SHIFT;
1453 u8 mask;
1454
1455 writeb(NV_INT_ALL << shift, mmio_base + NV_INT_STATUS_CK804);
1456
1457 mask = readb(mmio_base + NV_INT_ENABLE_CK804);
1458 mask |= (NV_INT_MASK << shift);
1459 writeb(mask, mmio_base + NV_INT_ENABLE_CK804);
1460}
1461
Tejun Heod4b2bab2007-02-02 16:50:52 +09001462static int nv_hardreset(struct ata_port *ap, unsigned int *class,
1463 unsigned long deadline)
Tejun Heo39f87582006-06-17 15:49:56 +09001464{
1465 unsigned int dummy;
1466
1467 /* SATA hardreset fails to retrieve proper device signature on
1468 * some controllers. Don't classify on hardreset. For more
1469 * info, see http://bugme.osdl.org/show_bug.cgi?id=3352
1470 */
Tejun Heod4b2bab2007-02-02 16:50:52 +09001471 return sata_std_hardreset(ap, &dummy, deadline);
Tejun Heo39f87582006-06-17 15:49:56 +09001472}
1473
1474static void nv_error_handler(struct ata_port *ap)
1475{
1476 ata_bmdma_drive_eh(ap, ata_std_prereset, ata_std_softreset,
1477 nv_hardreset, ata_std_postreset);
1478}
1479
Robert Hancockfbbb2622006-10-27 19:08:41 -07001480static void nv_adma_error_handler(struct ata_port *ap)
1481{
1482 struct nv_adma_port_priv *pp = ap->private_data;
1483 if(!(pp->flags & NV_ADMA_PORT_REGISTER_MODE)) {
Robert Hancockcdf56bc2007-01-03 18:13:57 -06001484 void __iomem *mmio = pp->ctl_block;
Robert Hancockfbbb2622006-10-27 19:08:41 -07001485 int i;
1486 u16 tmp;
Jeff Garzika84471f2007-02-26 05:51:33 -05001487
Robert Hancock2cb27852007-02-11 18:34:44 -06001488 if(ata_tag_valid(ap->active_tag) || ap->sactive) {
1489 u32 notifier = readl(mmio + NV_ADMA_NOTIFIER);
1490 u32 notifier_error = readl(mmio + NV_ADMA_NOTIFIER_ERROR);
1491 u32 gen_ctl = readl(pp->gen_block + NV_ADMA_GEN_CTL);
1492 u32 status = readw(mmio + NV_ADMA_STAT);
Robert Hancock08af7412007-02-19 19:01:59 -06001493 u8 cpb_count = readb(mmio + NV_ADMA_CPB_COUNT);
1494 u8 next_cpb_idx = readb(mmio + NV_ADMA_NEXT_CPB_IDX);
Robert Hancock2cb27852007-02-11 18:34:44 -06001495
1496 ata_port_printk(ap, KERN_ERR, "EH in ADMA mode, notifier 0x%X "
Robert Hancock08af7412007-02-19 19:01:59 -06001497 "notifier_error 0x%X gen_ctl 0x%X status 0x%X "
1498 "next cpb count 0x%X next cpb idx 0x%x\n",
1499 notifier, notifier_error, gen_ctl, status,
1500 cpb_count, next_cpb_idx);
Robert Hancock2cb27852007-02-11 18:34:44 -06001501
1502 for( i=0;i<NV_ADMA_MAX_CPBS;i++) {
1503 struct nv_adma_cpb *cpb = &pp->cpb[i];
1504 if( (ata_tag_valid(ap->active_tag) && i == ap->active_tag) ||
1505 ap->sactive & (1 << i) )
1506 ata_port_printk(ap, KERN_ERR,
1507 "CPB %d: ctl_flags 0x%x, resp_flags 0x%x\n",
1508 i, cpb->ctl_flags, cpb->resp_flags);
1509 }
1510 }
Robert Hancockfbbb2622006-10-27 19:08:41 -07001511
Robert Hancockfbbb2622006-10-27 19:08:41 -07001512 /* Push us back into port register mode for error handling. */
1513 nv_adma_register_mode(ap);
1514
Robert Hancockfbbb2622006-10-27 19:08:41 -07001515 /* Mark all of the CPBs as invalid to prevent them from being executed */
1516 for( i=0;i<NV_ADMA_MAX_CPBS;i++)
1517 pp->cpb[i].ctl_flags &= ~NV_CPB_CTL_CPB_VALID;
1518
1519 /* clear CPB fetch count */
1520 writew(0, mmio + NV_ADMA_CPB_COUNT);
1521
1522 /* Reset channel */
1523 tmp = readw(mmio + NV_ADMA_CTL);
1524 writew(tmp | NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);
Robert Hancock5ce0cf62007-02-19 19:03:27 -06001525 readw( mmio + NV_ADMA_CTL ); /* flush posted write */
Robert Hancockfbbb2622006-10-27 19:08:41 -07001526 udelay(1);
1527 writew(tmp & ~NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);
Robert Hancock5ce0cf62007-02-19 19:03:27 -06001528 readw( mmio + NV_ADMA_CTL ); /* flush posted write */
Robert Hancockfbbb2622006-10-27 19:08:41 -07001529 }
1530
1531 ata_bmdma_drive_eh(ap, ata_std_prereset, ata_std_softreset,
1532 nv_hardreset, ata_std_postreset);
1533}
1534
Linus Torvalds1da177e2005-04-16 15:20:36 -07001535static int nv_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1536{
1537 static int printed_version = 0;
Tejun Heo1626aeb2007-05-04 12:43:58 +02001538 const struct ata_port_info *ppi[] = { NULL, NULL };
Tejun Heo9a829cc2007-04-17 23:44:08 +09001539 struct ata_host *host;
Robert Hancockcdf56bc2007-01-03 18:13:57 -06001540 struct nv_host_priv *hpriv;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001541 int rc;
1542 u32 bar;
Tejun Heo0d5ff562007-02-01 15:06:36 +09001543 void __iomem *base;
Robert Hancockfbbb2622006-10-27 19:08:41 -07001544 unsigned long type = ent->driver_data;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001545
1546 // Make sure this is a SATA controller by counting the number of bars
1547 // (NVIDIA SATA controllers will always have six bars). Otherwise,
1548 // it's an IDE controller and we ignore it.
1549 for (bar=0; bar<6; bar++)
1550 if (pci_resource_start(pdev, bar) == 0)
1551 return -ENODEV;
1552
Robert Hancockcdf56bc2007-01-03 18:13:57 -06001553 if (!printed_version++)
Jeff Garzika9524a72005-10-30 14:39:11 -05001554 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001555
Tejun Heo24dc5f32007-01-20 16:00:28 +09001556 rc = pcim_enable_device(pdev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001557 if (rc)
Tejun Heo24dc5f32007-01-20 16:00:28 +09001558 return rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001559
Tejun Heo9a829cc2007-04-17 23:44:08 +09001560 /* determine type and allocate host */
1561 if (type >= CK804 && adma_enabled) {
Robert Hancockfbbb2622006-10-27 19:08:41 -07001562 dev_printk(KERN_NOTICE, &pdev->dev, "Using ADMA mode\n");
1563 type = ADMA;
Robert Hancockfbbb2622006-10-27 19:08:41 -07001564 }
1565
Tejun Heo1626aeb2007-05-04 12:43:58 +02001566 ppi[0] = &nv_port_info[type];
Tejun Heod583bc12007-07-04 18:02:07 +09001567 rc = ata_pci_prepare_sff_host(pdev, ppi, &host);
Tejun Heo9a829cc2007-04-17 23:44:08 +09001568 if (rc)
1569 return rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001570
Tejun Heo24dc5f32007-01-20 16:00:28 +09001571 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
Robert Hancockcdf56bc2007-01-03 18:13:57 -06001572 if (!hpriv)
Tejun Heo24dc5f32007-01-20 16:00:28 +09001573 return -ENOMEM;
Robert Hancockcdf56bc2007-01-03 18:13:57 -06001574 hpriv->type = type;
Tejun Heo9a829cc2007-04-17 23:44:08 +09001575 host->private_data = hpriv;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001576
Tejun Heo9a829cc2007-04-17 23:44:08 +09001577 /* set 64bit dma masks, may fail */
1578 if (type == ADMA) {
1579 if (pci_set_dma_mask(pdev, DMA_64BIT_MASK) == 0)
1580 pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1581 }
1582
1583 /* request and iomap NV_MMIO_BAR */
1584 rc = pcim_iomap_regions(pdev, 1 << NV_MMIO_BAR, DRV_NAME);
1585 if (rc)
1586 return rc;
1587
1588 /* configure SCR access */
1589 base = host->iomap[NV_MMIO_BAR];
1590 host->ports[0]->ioaddr.scr_addr = base + NV_PORT0_SCR_REG_OFFSET;
1591 host->ports[1]->ioaddr.scr_addr = base + NV_PORT1_SCR_REG_OFFSET;
Jeff Garzik02cbd922006-03-22 23:59:46 -05001592
Tejun Heoada364e2006-06-17 15:49:56 +09001593 /* enable SATA space for CK804 */
Robert Hancockfbbb2622006-10-27 19:08:41 -07001594 if (type >= CK804) {
Tejun Heoada364e2006-06-17 15:49:56 +09001595 u8 regval;
1596
1597 pci_read_config_byte(pdev, NV_MCP_SATA_CFG_20, &regval);
1598 regval |= NV_MCP_SATA_CFG_20_SATA_SPACE_EN;
1599 pci_write_config_byte(pdev, NV_MCP_SATA_CFG_20, regval);
1600 }
1601
Tejun Heo9a829cc2007-04-17 23:44:08 +09001602 /* init ADMA */
Robert Hancockfbbb2622006-10-27 19:08:41 -07001603 if (type == ADMA) {
Tejun Heo9a829cc2007-04-17 23:44:08 +09001604 rc = nv_adma_host_init(host);
Robert Hancockfbbb2622006-10-27 19:08:41 -07001605 if (rc)
Tejun Heo24dc5f32007-01-20 16:00:28 +09001606 return rc;
Robert Hancockfbbb2622006-10-27 19:08:41 -07001607 }
1608
Tejun Heo9a829cc2007-04-17 23:44:08 +09001609 pci_set_master(pdev);
1610 return ata_host_activate(host, pdev->irq, ppi[0]->irq_handler,
1611 IRQF_SHARED, ppi[0]->sht);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001612}
1613
Tejun Heo438ac6d2007-03-02 17:31:26 +09001614#ifdef CONFIG_PM
Robert Hancockcdf56bc2007-01-03 18:13:57 -06001615static int nv_pci_device_resume(struct pci_dev *pdev)
1616{
1617 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1618 struct nv_host_priv *hpriv = host->private_data;
Robert Hancockce053fa2007-02-05 16:26:04 -08001619 int rc;
Robert Hancockcdf56bc2007-01-03 18:13:57 -06001620
Robert Hancockce053fa2007-02-05 16:26:04 -08001621 rc = ata_pci_device_do_resume(pdev);
1622 if(rc)
1623 return rc;
Robert Hancockcdf56bc2007-01-03 18:13:57 -06001624
1625 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
1626 if(hpriv->type >= CK804) {
1627 u8 regval;
1628
1629 pci_read_config_byte(pdev, NV_MCP_SATA_CFG_20, &regval);
1630 regval |= NV_MCP_SATA_CFG_20_SATA_SPACE_EN;
1631 pci_write_config_byte(pdev, NV_MCP_SATA_CFG_20, regval);
1632 }
1633 if(hpriv->type == ADMA) {
1634 u32 tmp32;
1635 struct nv_adma_port_priv *pp;
1636 /* enable/disable ADMA on the ports appropriately */
1637 pci_read_config_dword(pdev, NV_MCP_SATA_CFG_20, &tmp32);
1638
1639 pp = host->ports[0]->private_data;
1640 if(pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE)
1641 tmp32 &= ~(NV_MCP_SATA_CFG_20_PORT0_EN |
1642 NV_MCP_SATA_CFG_20_PORT0_PWB_EN);
1643 else
1644 tmp32 |= (NV_MCP_SATA_CFG_20_PORT0_EN |
1645 NV_MCP_SATA_CFG_20_PORT0_PWB_EN);
1646 pp = host->ports[1]->private_data;
1647 if(pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE)
1648 tmp32 &= ~(NV_MCP_SATA_CFG_20_PORT1_EN |
1649 NV_MCP_SATA_CFG_20_PORT1_PWB_EN);
1650 else
1651 tmp32 |= (NV_MCP_SATA_CFG_20_PORT1_EN |
1652 NV_MCP_SATA_CFG_20_PORT1_PWB_EN);
1653
1654 pci_write_config_dword(pdev, NV_MCP_SATA_CFG_20, tmp32);
1655 }
1656 }
1657
1658 ata_host_resume(host);
1659
1660 return 0;
1661}
Tejun Heo438ac6d2007-03-02 17:31:26 +09001662#endif
Robert Hancockcdf56bc2007-01-03 18:13:57 -06001663
Jeff Garzikcca39742006-08-24 03:19:22 -04001664static void nv_ck804_host_stop(struct ata_host *host)
Tejun Heoada364e2006-06-17 15:49:56 +09001665{
Jeff Garzikcca39742006-08-24 03:19:22 -04001666 struct pci_dev *pdev = to_pci_dev(host->dev);
Tejun Heoada364e2006-06-17 15:49:56 +09001667 u8 regval;
1668
1669 /* disable SATA space for CK804 */
1670 pci_read_config_byte(pdev, NV_MCP_SATA_CFG_20, &regval);
1671 regval &= ~NV_MCP_SATA_CFG_20_SATA_SPACE_EN;
1672 pci_write_config_byte(pdev, NV_MCP_SATA_CFG_20, regval);
Tejun Heoada364e2006-06-17 15:49:56 +09001673}
1674
Robert Hancockfbbb2622006-10-27 19:08:41 -07001675static void nv_adma_host_stop(struct ata_host *host)
1676{
1677 struct pci_dev *pdev = to_pci_dev(host->dev);
Robert Hancockfbbb2622006-10-27 19:08:41 -07001678 u32 tmp32;
1679
Robert Hancockfbbb2622006-10-27 19:08:41 -07001680 /* disable ADMA on the ports */
1681 pci_read_config_dword(pdev, NV_MCP_SATA_CFG_20, &tmp32);
1682 tmp32 &= ~(NV_MCP_SATA_CFG_20_PORT0_EN |
1683 NV_MCP_SATA_CFG_20_PORT0_PWB_EN |
1684 NV_MCP_SATA_CFG_20_PORT1_EN |
1685 NV_MCP_SATA_CFG_20_PORT1_PWB_EN);
1686
1687 pci_write_config_dword(pdev, NV_MCP_SATA_CFG_20, tmp32);
1688
1689 nv_ck804_host_stop(host);
1690}
1691
Linus Torvalds1da177e2005-04-16 15:20:36 -07001692static int __init nv_init(void)
1693{
Pavel Roskinb7887192006-08-10 18:13:18 +09001694 return pci_register_driver(&nv_pci_driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001695}
1696
1697static void __exit nv_exit(void)
1698{
1699 pci_unregister_driver(&nv_pci_driver);
1700}
1701
1702module_init(nv_init);
1703module_exit(nv_exit);
Robert Hancockfbbb2622006-10-27 19:08:41 -07001704module_param_named(adma, adma_enabled, bool, 0444);
1705MODULE_PARM_DESC(adma, "Enable use of ADMA (Default: true)");