Duy Truong | 790f06d | 2013-02-13 16:38:12 -0800 | [diff] [blame] | 1 | /* Copyright (c) 2010-2012, The Linux Foundation. All rights reserved. |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | * |
| 12 | */ |
| 13 | #include <linux/module.h> |
| 14 | #include <linux/delay.h> |
| 15 | #include <linux/err.h> |
| 16 | #include <linux/platform_device.h> |
| 17 | #include <linux/mfd/msm-adie-codec.h> |
| 18 | #include <linux/mfd/marimba.h> |
| 19 | #include <linux/mfd/timpani-audio.h> |
| 20 | #include <linux/debugfs.h> |
| 21 | #include <linux/uaccess.h> |
| 22 | #include <linux/string.h> |
| 23 | |
| 24 | /* Timpani codec driver is activated through Marimba core driver */ |
| 25 | |
| 26 | #define MAX_MDELAY_US 20000 |
| 27 | |
| 28 | #define TIMPANI_PATH_MASK(x) (1 << (x)) |
| 29 | |
| 30 | #define TIMPANI_CODEC_AUXPGA_GAIN_RANGE (0x0F) |
| 31 | |
| 32 | #define TIMPANI_RX1_ST_MASK (TIMPANI_CDC_RX1_CTL_SIDETONE_EN1_L_M |\ |
| 33 | TIMPANI_CDC_RX1_CTL_SIDETONE_EN1_R_M) |
| 34 | #define TIMPANI_RX1_ST_ENABLE ((1 << TIMPANI_CDC_RX1_CTL_SIDETONE_EN1_L_S) |\ |
| 35 | (1 << TIMPANI_CDC_RX1_CTL_SIDETONE_EN1_R_S)) |
| 36 | #define TIMPANI_CDC_ST_MIXING_TX1_MASK (TIMPANI_CDC_ST_MIXING_TX1_L_M |\ |
| 37 | TIMPANI_CDC_ST_MIXING_TX1_R_M) |
| 38 | #define TIMPANI_CDC_ST_MIXING_TX1_ENABLE ((1 << TIMPANI_CDC_ST_MIXING_TX1_L_S)\ |
| 39 | | (1 << TIMPANI_CDC_ST_MIXING_TX1_R_S)) |
| 40 | #define TIMPANI_CDC_ST_MIXING_TX2_MASK (TIMPANI_CDC_ST_MIXING_TX2_L_M |\ |
| 41 | TIMPANI_CDC_ST_MIXING_TX2_R_M) |
| 42 | #define TIMPANI_CDC_ST_MIXING_TX2_ENABLE ((1 << TIMPANI_CDC_ST_MIXING_TX2_L_S)\ |
| 43 | | (1 << TIMPANI_CDC_ST_MIXING_TX2_R_S)) |
| 44 | |
| 45 | enum refcnt { |
| 46 | DEC = 0, |
| 47 | INC = 1, |
| 48 | IGNORE = 2, |
| 49 | }; |
| 50 | #define TIMPANI_ARRAY_SIZE (TIMPANI_A_CDC_COMP_HALT + 1) |
Santosh Mardi | 2247938 | 2011-10-14 02:50:12 +0530 | [diff] [blame] | 51 | #define MAX_SHADOW_RIGISTERS TIMPANI_A_CDC_COMP_HALT |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 52 | |
| 53 | static u8 timpani_shadow[TIMPANI_ARRAY_SIZE]; |
| 54 | |
| 55 | struct adie_codec_path { |
| 56 | struct adie_codec_dev_profile *profile; |
| 57 | struct adie_codec_register_image img; |
| 58 | u32 hwsetting_idx; |
| 59 | u32 stage_idx; |
| 60 | u32 curr_stage; |
| 61 | u32 reg_owner; |
| 62 | }; |
| 63 | |
| 64 | enum /* regaccess blk id */ |
| 65 | { |
| 66 | RA_BLOCK_RX1 = 0, |
| 67 | RA_BLOCK_RX2, |
| 68 | RA_BLOCK_TX1, |
| 69 | RA_BLOCK_TX2, |
| 70 | RA_BLOCK_LB, |
| 71 | RA_BLOCK_SHARED_RX_LB, |
| 72 | RA_BLOCK_SHARED_TX, |
| 73 | RA_BLOCK_TXFE1, |
| 74 | RA_BLOCK_TXFE2, |
| 75 | RA_BLOCK_PA_COMMON, |
| 76 | RA_BLOCK_PA_EAR, |
| 77 | RA_BLOCK_PA_HPH, |
| 78 | RA_BLOCK_PA_LINE, |
| 79 | RA_BLOCK_PA_AUX, |
| 80 | RA_BLOCK_ADC, |
| 81 | RA_BLOCK_DMIC, |
| 82 | RA_BLOCK_TX_I2S, |
| 83 | RA_BLOCK_DRV, |
| 84 | RA_BLOCK_TEST, |
| 85 | RA_BLOCK_RESERVED, |
| 86 | RA_BLOCK_NUM, |
| 87 | }; |
| 88 | |
| 89 | enum /* regaccess onwer ID */ |
| 90 | { |
| 91 | RA_OWNER_NONE = 0, |
| 92 | RA_OWNER_PATH_RX1, |
| 93 | RA_OWNER_PATH_RX2, |
| 94 | RA_OWNER_PATH_TX1, |
| 95 | RA_OWNER_PATH_TX2, |
| 96 | RA_OWNER_PATH_LB, |
| 97 | RA_OWNER_DRV, |
| 98 | RA_OWNER_NUM, |
| 99 | }; |
| 100 | |
| 101 | struct reg_acc_blk_cfg { |
| 102 | u8 valid_owners[RA_OWNER_NUM]; |
| 103 | }; |
| 104 | |
| 105 | struct reg_ref_cnt { |
| 106 | u8 mask; |
| 107 | u8 path_mask; |
| 108 | }; |
| 109 | |
| 110 | #define TIMPANI_MAX_FIELDS 5 |
| 111 | |
| 112 | struct timpani_regaccess { |
| 113 | u8 reg_addr; |
| 114 | u8 blk_mask[RA_BLOCK_NUM]; |
| 115 | u8 reg_mask; |
| 116 | u8 reg_default; |
| 117 | struct reg_ref_cnt fld_ref_cnt[TIMPANI_MAX_FIELDS]; |
| 118 | }; |
| 119 | |
| 120 | struct timpani_regaccess timpani_regset[] = { |
| 121 | { |
| 122 | TIMPANI_A_MREF, |
| 123 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 124 | 0x0, 0x0, 0x0, 0x0, 0x0, 0xFC, 0x0, 0x3}, |
| 125 | TIMPANI_MREF_M, |
| 126 | TIMPANI_MREF_POR, |
| 127 | { |
| 128 | { .mask = 0xFC, .path_mask = 0}, |
| 129 | { .mask = 0x03, .path_mask = 0}, |
| 130 | { .mask = 0x00, .path_mask = 0}, |
| 131 | { .mask = 0x00, .path_mask = 0}, |
| 132 | { .mask = 0x00, .path_mask = 0}, |
| 133 | } |
| 134 | }, |
| 135 | { |
| 136 | TIMPANI_A_CDAC_IDAC_REF_CUR, |
| 137 | {0xFC, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 138 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, |
| 139 | TIMPANI_CDAC_IDAC_REF_CUR_M, |
| 140 | TIMPANI_CDAC_IDAC_REF_CUR_POR, |
| 141 | { |
| 142 | { .mask = 0xFC, .path_mask = 0}, |
| 143 | { .mask = 0x03, .path_mask = 0}, |
| 144 | { .mask = 0x00, .path_mask = 0}, |
| 145 | { .mask = 0x00, .path_mask = 0}, |
| 146 | { .mask = 0x00, .path_mask = 0}, |
| 147 | } |
| 148 | }, |
| 149 | { |
| 150 | TIMPANI_A_TXADC12_REF_CURR, |
| 151 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 152 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xFF}, |
| 153 | TIMPANI_TXADC12_REF_CURR_M, |
| 154 | TIMPANI_TXADC12_REF_CURR_POR, |
| 155 | { |
| 156 | { .mask = 0xFF, .path_mask = 0}, |
| 157 | { .mask = 0x00, .path_mask = 0}, |
| 158 | { .mask = 0x00, .path_mask = 0}, |
| 159 | { .mask = 0x00, .path_mask = 0}, |
| 160 | { .mask = 0x00, .path_mask = 0}, |
| 161 | } |
| 162 | }, |
| 163 | { |
| 164 | TIMPANI_A_TXADC3_EN, |
| 165 | { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xFE, 0x0, 0x0, 0x0, |
| 166 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1}, |
| 167 | TIMPANI_TXADC3_EN_M, |
| 168 | TIMPANI_TXADC3_EN_POR, |
| 169 | { |
| 170 | { .mask = 0xFE, .path_mask = 0}, |
| 171 | { .mask = 0x01, .path_mask = 0}, |
| 172 | { .mask = 0x00, .path_mask = 0}, |
| 173 | { .mask = 0x00, .path_mask = 0}, |
| 174 | { .mask = 0x00, .path_mask = 0}, |
| 175 | } |
| 176 | }, |
| 177 | { |
| 178 | TIMPANI_A_TXADC4_EN, |
| 179 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xFE, 0x0, 0x0, 0x0, |
| 180 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1}, |
| 181 | TIMPANI_TXADC4_EN_M, |
| 182 | TIMPANI_TXADC4_EN_POR, |
| 183 | { |
| 184 | { .mask = 0xFE, .path_mask = 0}, |
| 185 | { .mask = 0x01, .path_mask = 0}, |
| 186 | { .mask = 0x00, .path_mask = 0}, |
| 187 | { .mask = 0x00, .path_mask = 0}, |
| 188 | { .mask = 0x00, .path_mask = 0}, |
| 189 | } |
| 190 | }, |
| 191 | { |
| 192 | TIMPANI_A_CODEC_TXADC_STATUS_REGISTER_1, |
| 193 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xC0, 0x30, 0x0, 0x0, 0x0, |
| 194 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xF}, |
| 195 | TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_M, |
| 196 | TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_POR, |
| 197 | { |
| 198 | { .mask = 0xC0, .path_mask = 0}, |
| 199 | { .mask = 0x30, .path_mask = 0}, |
| 200 | { .mask = 0x0F, .path_mask = 0}, |
| 201 | { .mask = 0x00, .path_mask = 0}, |
| 202 | { .mask = 0x00, .path_mask = 0}, |
| 203 | } |
| 204 | }, |
| 205 | { |
| 206 | TIMPANI_A_TXFE1, |
| 207 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xFF, 0x0, 0x0, 0x0, 0x0, |
| 208 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, |
| 209 | TIMPANI_TXFE1_M, |
| 210 | TIMPANI_TXFE1_POR, |
| 211 | { |
| 212 | { .mask = 0xFF, .path_mask = 0}, |
| 213 | { .mask = 0x00, .path_mask = 0}, |
| 214 | { .mask = 0x00, .path_mask = 0}, |
| 215 | { .mask = 0x00, .path_mask = 0}, |
| 216 | { .mask = 0x00, .path_mask = 0}, |
| 217 | } |
| 218 | }, |
| 219 | { |
| 220 | TIMPANI_A_TXFE2, |
| 221 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xFF, 0x0, 0x0, 0x0, 0x0, |
| 222 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, |
| 223 | TIMPANI_TXFE2_M, |
| 224 | TIMPANI_TXFE2_POR, |
| 225 | { |
| 226 | { .mask = 0xFF, .path_mask = 0}, |
| 227 | { .mask = 0x00, .path_mask = 0}, |
| 228 | { .mask = 0x00, .path_mask = 0}, |
| 229 | { .mask = 0x00, .path_mask = 0}, |
| 230 | { .mask = 0x00, .path_mask = 0}, |
| 231 | } |
| 232 | }, |
| 233 | { |
| 234 | TIMPANI_A_TXFE12_ATEST, |
| 235 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xFF, 0x0, 0x0, 0x0, 0x0, |
| 236 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, |
| 237 | TIMPANI_TXFE12_ATEST_M, |
| 238 | TIMPANI_TXFE12_ATEST_POR, |
| 239 | { |
| 240 | { .mask = 0xFF, .path_mask = 0}, |
| 241 | { .mask = 0x00, .path_mask = 0}, |
| 242 | { .mask = 0x00, .path_mask = 0}, |
| 243 | { .mask = 0x00, .path_mask = 0}, |
| 244 | { .mask = 0x00, .path_mask = 0}, |
| 245 | } |
| 246 | }, |
| 247 | { |
| 248 | TIMPANI_A_TXFE_CLT, |
| 249 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xF8, 0x0, 0x0, 0x0, 0x0, |
| 250 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x7}, |
| 251 | TIMPANI_TXFE_CLT_M, |
| 252 | TIMPANI_TXFE_CLT_POR, |
| 253 | { |
| 254 | { .mask = 0xF8, .path_mask = 0}, |
| 255 | { .mask = 0x07, .path_mask = 0}, |
| 256 | { .mask = 0x00, .path_mask = 0}, |
| 257 | { .mask = 0x00, .path_mask = 0}, |
| 258 | { .mask = 0x00, .path_mask = 0}, |
| 259 | } |
| 260 | }, |
| 261 | { |
| 262 | TIMPANI_A_TXADC1_EN, |
| 263 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xFE, 0x0, 0x0, 0x0, 0x0, |
| 264 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1}, |
| 265 | TIMPANI_TXADC1_EN_M, |
| 266 | TIMPANI_TXADC1_EN_POR, |
| 267 | { |
| 268 | { .mask = 0xFE, .path_mask = 0}, |
| 269 | { .mask = 0x01, .path_mask = 0}, |
| 270 | { .mask = 0x00, .path_mask = 0}, |
| 271 | { .mask = 0x00, .path_mask = 0}, |
| 272 | { .mask = 0x00, .path_mask = 0}, |
| 273 | } |
| 274 | }, |
| 275 | { |
| 276 | TIMPANI_A_TXADC2_EN, |
| 277 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xFE, 0x0, 0x0, 0x0, 0x0, |
| 278 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1}, |
| 279 | TIMPANI_TXADC2_EN_M, |
| 280 | TIMPANI_TXADC2_EN_POR, |
| 281 | { |
| 282 | { .mask = 0xFE, .path_mask = 0}, |
| 283 | { .mask = 0x01, .path_mask = 0}, |
| 284 | { .mask = 0x00, .path_mask = 0}, |
| 285 | { .mask = 0x00, .path_mask = 0}, |
| 286 | { .mask = 0x00, .path_mask = 0}, |
| 287 | } |
| 288 | }, |
| 289 | { |
| 290 | TIMPANI_A_TXADC_CTL, |
| 291 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 292 | 0x0, 0x0, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0}, |
| 293 | TIMPANI_TXADC_CTL_M, |
| 294 | TIMPANI_TXADC_CTL_POR, |
| 295 | { |
| 296 | { .mask = 0xFF, .path_mask = 0}, |
| 297 | { .mask = 0x00, .path_mask = 0}, |
| 298 | { .mask = 0x00, .path_mask = 0}, |
| 299 | { .mask = 0x00, .path_mask = 0}, |
| 300 | { .mask = 0x00, .path_mask = 0}, |
| 301 | } |
| 302 | }, |
| 303 | { |
| 304 | TIMPANI_A_TXADC_CTL2, |
| 305 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 306 | 0x0, 0x0, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0}, |
| 307 | TIMPANI_TXADC_CTL2_M, |
| 308 | TIMPANI_TXADC_CTL2_POR, |
| 309 | { |
| 310 | { .mask = 0xFF, .path_mask = 0}, |
| 311 | { .mask = 0x00, .path_mask = 0}, |
| 312 | { .mask = 0x00, .path_mask = 0}, |
| 313 | { .mask = 0x00, .path_mask = 0}, |
| 314 | { .mask = 0x00, .path_mask = 0}, |
| 315 | } |
| 316 | }, |
| 317 | { |
| 318 | TIMPANI_A_TXADC_CTL3, |
| 319 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 320 | 0x0, 0x0, 0xFE, 0x0, 0x0, 0x0, 0x0, 0x1}, |
| 321 | TIMPANI_TXADC_CTL3_M, |
| 322 | TIMPANI_TXADC_CTL3_POR, |
| 323 | { |
| 324 | { .mask = 0xFE, .path_mask = 0}, |
| 325 | { .mask = 0x01, .path_mask = 0}, |
| 326 | { .mask = 0x00, .path_mask = 0}, |
| 327 | { .mask = 0x00, .path_mask = 0}, |
| 328 | { .mask = 0x00, .path_mask = 0}, |
| 329 | } |
| 330 | }, |
| 331 | { |
| 332 | TIMPANI_A_TXADC_CHOP_CTL, |
| 333 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 334 | 0x0, 0x0, 0xFC, 0x0, 0x0, 0x0, 0x0, 0x3}, |
| 335 | TIMPANI_TXADC_CHOP_CTL_M, |
| 336 | TIMPANI_TXADC_CHOP_CTL_POR, |
| 337 | { |
| 338 | { .mask = 0xFC, .path_mask = 0}, |
| 339 | { .mask = 0x03, .path_mask = 0}, |
| 340 | { .mask = 0x00, .path_mask = 0}, |
| 341 | { .mask = 0x00, .path_mask = 0}, |
| 342 | { .mask = 0x00, .path_mask = 0}, |
| 343 | } |
| 344 | }, |
| 345 | { |
| 346 | TIMPANI_A_TXFE3, |
| 347 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xE2, 0x0, 0x0, 0x0, |
| 348 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1D}, |
| 349 | TIMPANI_TXFE3_M, |
| 350 | TIMPANI_TXFE3_POR, |
| 351 | { |
| 352 | { .mask = 0xE2, .path_mask = 0}, |
| 353 | { .mask = 0x1D, .path_mask = 0}, |
| 354 | { .mask = 0x00, .path_mask = 0}, |
| 355 | { .mask = 0x00, .path_mask = 0}, |
| 356 | { .mask = 0x00, .path_mask = 0}, |
| 357 | } |
| 358 | }, |
| 359 | { |
| 360 | TIMPANI_A_TXFE4, |
| 361 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xE2, 0x0, 0x0, 0x0, |
| 362 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1D}, |
| 363 | TIMPANI_TXFE4_M, |
| 364 | TIMPANI_TXFE4_POR, |
| 365 | { |
| 366 | { .mask = 0xE2, .path_mask = 0}, |
| 367 | { .mask = 0x1D, .path_mask = 0}, |
| 368 | { .mask = 0x00, .path_mask = 0}, |
| 369 | { .mask = 0x00, .path_mask = 0}, |
| 370 | { .mask = 0x00, .path_mask = 0}, |
| 371 | } |
| 372 | }, |
| 373 | { |
| 374 | TIMPANI_A_TXFE3_ATEST, |
| 375 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xFF, 0x0, 0x0, 0x0, |
| 376 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, |
| 377 | TIMPANI_TXFE3_ATEST_M, |
| 378 | TIMPANI_TXFE3_ATEST_POR, |
| 379 | { |
| 380 | { .mask = 0xFF, .path_mask = 0}, |
| 381 | { .mask = 0x00, .path_mask = 0}, |
| 382 | { .mask = 0x00, .path_mask = 0}, |
| 383 | { .mask = 0x00, .path_mask = 0}, |
| 384 | { .mask = 0x00, .path_mask = 0}, |
| 385 | } |
| 386 | }, |
| 387 | { |
| 388 | TIMPANI_A_TXFE_DIFF_SE, |
| 389 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x3, 0xC, 0x0, 0x0, 0x0, |
| 390 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xF0}, |
| 391 | TIMPANI_TXFE_DIFF_SE_M, |
| 392 | TIMPANI_TXFE_DIFF_SE_POR, |
| 393 | { |
| 394 | { .mask = 0x03, .path_mask = 0}, |
| 395 | { .mask = 0x0C, .path_mask = 0}, |
| 396 | { .mask = 0xF0, .path_mask = 0}, |
| 397 | { .mask = 0x00, .path_mask = 0}, |
| 398 | { .mask = 0x00, .path_mask = 0}, |
| 399 | } |
| 400 | }, |
| 401 | { |
| 402 | TIMPANI_A_CDAC_RX_CLK_CTL, |
| 403 | {0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 404 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, |
| 405 | TIMPANI_CDAC_RX_CLK_CTL_M, |
| 406 | TIMPANI_CDAC_RX_CLK_CTL_POR, |
| 407 | { |
| 408 | { .mask = 0xFF, .path_mask = 0}, |
| 409 | { .mask = 0x00, .path_mask = 0}, |
| 410 | { .mask = 0x00, .path_mask = 0}, |
| 411 | { .mask = 0x00, .path_mask = 0}, |
| 412 | { .mask = 0x00, .path_mask = 0}, |
| 413 | } |
| 414 | }, |
| 415 | { |
| 416 | TIMPANI_A_CDAC_BUFF_CTL, |
| 417 | {0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 418 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, |
| 419 | TIMPANI_CDAC_BUFF_CTL_M, |
| 420 | TIMPANI_CDAC_BUFF_CTL_POR, |
| 421 | { |
| 422 | { .mask = 0xFF, .path_mask = 0}, |
| 423 | { .mask = 0x00, .path_mask = 0}, |
| 424 | { .mask = 0x00, .path_mask = 0}, |
| 425 | { .mask = 0x00, .path_mask = 0}, |
| 426 | { .mask = 0x00, .path_mask = 0}, |
| 427 | } |
| 428 | }, |
| 429 | { |
| 430 | TIMPANI_A_CDAC_REF_CTL1, |
| 431 | {0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 432 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, |
| 433 | TIMPANI_CDAC_REF_CTL1_M, |
| 434 | TIMPANI_CDAC_REF_CTL1_POR, |
| 435 | { |
| 436 | { .mask = 0xFF, .path_mask = 0}, |
| 437 | { .mask = 0x00, .path_mask = 0}, |
| 438 | { .mask = 0x00, .path_mask = 0}, |
| 439 | { .mask = 0x00, .path_mask = 0}, |
| 440 | { .mask = 0x00, .path_mask = 0}, |
| 441 | } |
| 442 | }, |
| 443 | { |
| 444 | TIMPANI_A_IDAC_DWA_FIR_CTL, |
| 445 | {0xF8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 446 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x7}, |
| 447 | TIMPANI_IDAC_DWA_FIR_CTL_M, |
| 448 | TIMPANI_IDAC_DWA_FIR_CTL_POR, |
| 449 | { |
| 450 | { .mask = 0xF8, .path_mask = 0}, |
| 451 | { .mask = 0x07, .path_mask = 0}, |
| 452 | { .mask = 0x00, .path_mask = 0}, |
| 453 | { .mask = 0x00, .path_mask = 0}, |
| 454 | { .mask = 0x00, .path_mask = 0}, |
| 455 | } |
| 456 | }, |
| 457 | { |
| 458 | TIMPANI_A_CDAC_REF_CTL2, |
| 459 | {0x6F, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 460 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x90}, |
| 461 | TIMPANI_CDAC_REF_CTL2_M, |
| 462 | TIMPANI_CDAC_REF_CTL2_POR, |
| 463 | { |
| 464 | { .mask = 0x6F, .path_mask = 0}, |
| 465 | { .mask = 0x90, .path_mask = 0}, |
| 466 | { .mask = 0x00, .path_mask = 0}, |
| 467 | { .mask = 0x00, .path_mask = 0}, |
| 468 | { .mask = 0x00, .path_mask = 0}, |
| 469 | } |
| 470 | }, |
| 471 | { |
| 472 | TIMPANI_A_CDAC_CTL1, |
| 473 | {0x7F, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 474 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x80}, |
| 475 | TIMPANI_CDAC_CTL1_M, |
| 476 | TIMPANI_CDAC_CTL1_POR, |
| 477 | { |
| 478 | { .mask = 0x7F, .path_mask = 0}, |
| 479 | { .mask = 0x80, .path_mask = 0}, |
| 480 | { .mask = 0x00, .path_mask = 0}, |
| 481 | { .mask = 0x00, .path_mask = 0}, |
| 482 | { .mask = 0x00, .path_mask = 0}, |
| 483 | } |
| 484 | }, |
| 485 | { |
| 486 | TIMPANI_A_CDAC_CTL2, |
| 487 | {0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 488 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, |
| 489 | TIMPANI_CDAC_CTL2_M, |
| 490 | TIMPANI_CDAC_CTL2_POR, |
| 491 | { |
| 492 | { .mask = 0xFF, .path_mask = 0}, |
| 493 | { .mask = 0x00, .path_mask = 0}, |
| 494 | { .mask = 0x00, .path_mask = 0}, |
| 495 | { .mask = 0x00, .path_mask = 0}, |
| 496 | { .mask = 0x00, .path_mask = 0}, |
| 497 | } |
| 498 | }, |
| 499 | { |
| 500 | TIMPANI_A_IDAC_L_CTL, |
| 501 | {0x0, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 502 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, |
| 503 | TIMPANI_IDAC_L_CTL_M, |
| 504 | TIMPANI_IDAC_L_CTL_POR, |
| 505 | { |
| 506 | { .mask = 0xFF, .path_mask = 0}, |
| 507 | { .mask = 0x00, .path_mask = 0}, |
| 508 | { .mask = 0x00, .path_mask = 0}, |
| 509 | { .mask = 0x00, .path_mask = 0}, |
| 510 | { .mask = 0x00, .path_mask = 0}, |
| 511 | } |
| 512 | }, |
| 513 | { |
| 514 | TIMPANI_A_IDAC_R_CTL, |
| 515 | {0x0, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 516 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, |
| 517 | TIMPANI_IDAC_R_CTL_M, |
| 518 | TIMPANI_IDAC_R_CTL_POR, |
| 519 | { |
| 520 | { .mask = 0xFF, .path_mask = 0}, |
| 521 | { .mask = 0x00, .path_mask = 0}, |
| 522 | { .mask = 0x00, .path_mask = 0}, |
| 523 | { .mask = 0x00, .path_mask = 0}, |
| 524 | { .mask = 0x00, .path_mask = 0}, |
| 525 | } |
| 526 | }, |
| 527 | { |
| 528 | TIMPANI_A_PA_MASTER_BIAS, |
| 529 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1F, |
| 530 | 0xE0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, |
| 531 | TIMPANI_PA_MASTER_BIAS_M, |
| 532 | TIMPANI_PA_MASTER_BIAS_POR, |
| 533 | { |
| 534 | { .mask = 0x1F, .path_mask = 0}, |
| 535 | { .mask = 0xE0, .path_mask = 0}, |
| 536 | { .mask = 0x00, .path_mask = 0}, |
| 537 | { .mask = 0x00, .path_mask = 0}, |
| 538 | { .mask = 0x00, .path_mask = 0}, |
| 539 | } |
| 540 | }, |
| 541 | { |
| 542 | TIMPANI_A_PA_CLASSD_BIAS, |
| 543 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xFF, |
| 544 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, |
| 545 | TIMPANI_PA_CLASSD_BIAS_M, |
| 546 | TIMPANI_PA_CLASSD_BIAS_POR, |
| 547 | { |
| 548 | { .mask = 0xFF, .path_mask = 0}, |
| 549 | { .mask = 0x00, .path_mask = 0}, |
| 550 | { .mask = 0x00, .path_mask = 0}, |
| 551 | { .mask = 0x00, .path_mask = 0}, |
| 552 | { .mask = 0x00, .path_mask = 0}, |
| 553 | } |
| 554 | }, |
| 555 | { |
| 556 | TIMPANI_A_AUXPGA_CUR, |
| 557 | {0x0, 0x0, 0x0, 0x0, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 558 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, |
| 559 | TIMPANI_AUXPGA_CUR_M, |
| 560 | TIMPANI_AUXPGA_CUR_POR, |
| 561 | { |
| 562 | { .mask = 0xFF, .path_mask = 0}, |
| 563 | { .mask = 0x00, .path_mask = 0}, |
| 564 | { .mask = 0x00, .path_mask = 0}, |
| 565 | { .mask = 0x00, .path_mask = 0}, |
| 566 | { .mask = 0x00, .path_mask = 0}, |
| 567 | } |
| 568 | }, |
| 569 | { |
| 570 | TIMPANI_A_AUXPGA_CM, |
| 571 | {0x0, 0x0, 0x0, 0x0, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 572 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, |
| 573 | TIMPANI_AUXPGA_CM_M, |
| 574 | TIMPANI_AUXPGA_CM_POR, |
| 575 | { |
| 576 | { .mask = 0xFF, .path_mask = 0}, |
| 577 | { .mask = 0x00, .path_mask = 0}, |
| 578 | { .mask = 0x00, .path_mask = 0}, |
| 579 | { .mask = 0x00, .path_mask = 0}, |
| 580 | { .mask = 0x00, .path_mask = 0}, |
| 581 | } |
| 582 | }, |
| 583 | { |
| 584 | TIMPANI_A_PA_HPH_EARPA_MSTB_EN, |
| 585 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1, 0x2, 0xFC, |
| 586 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, |
| 587 | TIMPANI_PA_HPH_EARPA_MSTB_EN_M, |
| 588 | TIMPANI_PA_HPH_EARPA_MSTB_EN_POR, |
| 589 | { |
| 590 | { .mask = 0x01, .path_mask = 0}, |
| 591 | { .mask = 0x02, .path_mask = 0}, |
| 592 | { .mask = 0xFC, .path_mask = 0}, |
| 593 | { .mask = 0x00, .path_mask = 0}, |
| 594 | { .mask = 0x00, .path_mask = 0}, |
| 595 | } |
| 596 | }, |
| 597 | { |
| 598 | TIMPANI_A_PA_LINE_AUXO_EN, |
| 599 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 600 | 0xF8, 0x7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, |
| 601 | TIMPANI_PA_LINE_AUXO_EN_M, |
| 602 | TIMPANI_PA_LINE_AUXO_EN_POR, |
| 603 | { |
| 604 | { .mask = 0xF8, .path_mask = 0}, |
| 605 | { .mask = 0x07, .path_mask = 0}, |
| 606 | { .mask = 0x00, .path_mask = 0}, |
| 607 | { .mask = 0x00, .path_mask = 0}, |
| 608 | { .mask = 0x00, .path_mask = 0}, |
| 609 | } |
| 610 | }, |
| 611 | { |
| 612 | TIMPANI_A_PA_CLASSD_AUXPGA_EN, |
| 613 | {0x0, 0x0, 0x0, 0x0, 0x30, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xF, |
| 614 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xC0}, |
| 615 | TIMPANI_PA_CLASSD_AUXPGA_EN_M, |
| 616 | TIMPANI_PA_CLASSD_AUXPGA_EN_POR, |
| 617 | { |
| 618 | { .mask = 0x30, .path_mask = 0}, |
| 619 | { .mask = 0x0F, .path_mask = 0}, |
| 620 | { .mask = 0xC0, .path_mask = 0}, |
| 621 | { .mask = 0x00, .path_mask = 0}, |
| 622 | { .mask = 0x00, .path_mask = 0}, |
| 623 | } |
| 624 | }, |
| 625 | { |
| 626 | TIMPANI_A_PA_LINE_L_GAIN, |
| 627 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 628 | 0x0, 0x0, 0x0, 0x0, 0x0, 0xFC, 0x0, 0x3}, |
| 629 | TIMPANI_PA_LINE_L_GAIN_M, |
| 630 | TIMPANI_PA_LINE_L_GAIN_POR, |
| 631 | { |
| 632 | { .mask = 0xFC, .path_mask = 0}, |
| 633 | { .mask = 0x03, .path_mask = 0}, |
| 634 | { .mask = 0x00, .path_mask = 0}, |
| 635 | { .mask = 0x00, .path_mask = 0}, |
| 636 | { .mask = 0x00, .path_mask = 0}, |
| 637 | } |
| 638 | }, |
| 639 | { |
| 640 | TIMPANI_A_PA_LINE_R_GAIN, |
| 641 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 642 | 0x0, 0x0, 0x0, 0x0, 0x0, 0xFC, 0x0, 0x3}, |
| 643 | TIMPANI_PA_LINE_R_GAIN_M, |
| 644 | TIMPANI_PA_LINE_R_GAIN_POR, |
| 645 | { |
| 646 | { .mask = 0xFC, .path_mask = 0}, |
| 647 | { .mask = 0x03, .path_mask = 0}, |
| 648 | { .mask = 0x00, .path_mask = 0}, |
| 649 | { .mask = 0x00, .path_mask = 0}, |
| 650 | { .mask = 0x00, .path_mask = 0}, |
| 651 | } |
| 652 | }, |
| 653 | { |
| 654 | TIMPANI_A_PA_HPH_L_GAIN, |
| 655 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 656 | 0x0, 0x0, 0x0, 0x0, 0x0, 0xFE, 0x0, 0x1}, |
| 657 | TIMPANI_PA_HPH_L_GAIN_M, |
| 658 | TIMPANI_PA_HPH_L_GAIN_POR, |
| 659 | { |
| 660 | { .mask = 0xFE, .path_mask = 0}, |
| 661 | { .mask = 0x01, .path_mask = 0}, |
| 662 | { .mask = 0x00, .path_mask = 0}, |
| 663 | { .mask = 0x00, .path_mask = 0}, |
| 664 | { .mask = 0x00, .path_mask = 0}, |
| 665 | } |
| 666 | }, |
| 667 | { |
| 668 | TIMPANI_A_PA_HPH_R_GAIN, |
| 669 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 670 | 0x0, 0x0, 0x0, 0x0, 0x0, 0xFE, 0x0, 0x1}, |
| 671 | TIMPANI_PA_HPH_R_GAIN_M, |
| 672 | TIMPANI_PA_HPH_R_GAIN_POR, |
| 673 | { |
| 674 | { .mask = 0xFE, .path_mask = 0}, |
| 675 | { .mask = 0x01, .path_mask = 0}, |
| 676 | { .mask = 0x00, .path_mask = 0}, |
| 677 | { .mask = 0x00, .path_mask = 0}, |
| 678 | { .mask = 0x00, .path_mask = 0}, |
| 679 | } |
| 680 | }, |
| 681 | { |
| 682 | TIMPANI_A_AUXPGA_LR_GAIN, |
| 683 | {0x0, 0x0, 0x0, 0x0, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 684 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, |
| 685 | TIMPANI_AUXPGA_LR_GAIN_M, |
| 686 | TIMPANI_AUXPGA_LR_GAIN_POR, |
| 687 | { |
| 688 | { .mask = 0xFF, .path_mask = 0}, |
| 689 | { .mask = 0x00, .path_mask = 0}, |
| 690 | { .mask = 0x00, .path_mask = 0}, |
| 691 | { .mask = 0x00, .path_mask = 0}, |
| 692 | { .mask = 0x00, .path_mask = 0}, |
| 693 | } |
| 694 | }, |
| 695 | { |
| 696 | TIMPANI_A_PA_AUXO_EARPA_CONN, |
| 697 | {0x21, 0x42, 0x0, 0x0, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 698 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x18}, |
| 699 | TIMPANI_PA_AUXO_EARPA_CONN_M, |
| 700 | TIMPANI_PA_AUXO_EARPA_CONN_POR, |
| 701 | { |
| 702 | { .mask = 0x21, .path_mask = 0}, |
| 703 | { .mask = 0x42, .path_mask = 0}, |
| 704 | { .mask = 0x84, .path_mask = 0}, |
| 705 | { .mask = 0x18, .path_mask = 0}, |
| 706 | { .mask = 0x00, .path_mask = 0}, |
| 707 | } |
| 708 | }, |
| 709 | { |
| 710 | TIMPANI_A_PA_LINE_ST_CONN, |
| 711 | {0x24, 0x48, 0x0, 0x0, 0x93, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 712 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, |
| 713 | TIMPANI_PA_LINE_ST_CONN_M, |
| 714 | TIMPANI_PA_LINE_ST_CONN_POR, |
| 715 | { |
| 716 | { .mask = 0x24, .path_mask = 0}, |
| 717 | { .mask = 0x48, .path_mask = 0}, |
| 718 | { .mask = 0x93, .path_mask = 0}, |
| 719 | { .mask = 0x00, .path_mask = 0}, |
| 720 | { .mask = 0x00, .path_mask = 0}, |
| 721 | } |
| 722 | }, |
| 723 | { |
| 724 | TIMPANI_A_PA_LINE_MONO_CONN, |
| 725 | {0x24, 0x48, 0x0, 0x0, 0x93, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 726 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, |
| 727 | TIMPANI_PA_LINE_MONO_CONN_M, |
| 728 | TIMPANI_PA_LINE_MONO_CONN_POR, |
| 729 | { |
| 730 | { .mask = 0x24, .path_mask = 0}, |
| 731 | { .mask = 0x48, .path_mask = 0}, |
| 732 | { .mask = 0x93, .path_mask = 0}, |
| 733 | { .mask = 0x00, .path_mask = 0}, |
| 734 | { .mask = 0x00, .path_mask = 0}, |
| 735 | } |
| 736 | }, |
| 737 | { |
| 738 | TIMPANI_A_PA_HPH_ST_CONN, |
| 739 | {0x24, 0x48, 0x0, 0x0, 0x90, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x3, |
| 740 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, |
| 741 | TIMPANI_PA_HPH_ST_CONN_M, |
| 742 | TIMPANI_PA_HPH_ST_CONN_POR, |
| 743 | { |
| 744 | { .mask = 0x24, .path_mask = 0}, |
| 745 | { .mask = 0x48, .path_mask = 0}, |
| 746 | { .mask = 0x90, .path_mask = 0}, |
| 747 | { .mask = 0x03, .path_mask = 0}, |
| 748 | { .mask = 0x00, .path_mask = 0}, |
| 749 | } |
| 750 | }, |
| 751 | { |
| 752 | TIMPANI_A_PA_HPH_MONO_CONN, |
| 753 | {0x24, 0x48, 0x0, 0x0, 0x90, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 754 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x3}, |
| 755 | TIMPANI_PA_HPH_MONO_CONN_M, |
| 756 | TIMPANI_PA_HPH_MONO_CONN_POR, |
| 757 | { |
| 758 | { .mask = 0x24, .path_mask = 0}, |
| 759 | { .mask = 0x48, .path_mask = 0}, |
| 760 | { .mask = 0x90, .path_mask = 0}, |
| 761 | { .mask = 0x03, .path_mask = 0}, |
| 762 | { .mask = 0x00, .path_mask = 0}, |
| 763 | } |
| 764 | }, |
| 765 | { |
| 766 | TIMPANI_A_PA_CLASSD_CONN, |
| 767 | {0x80, 0x40, 0x0, 0x0, 0x20, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x10, |
| 768 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xF}, |
| 769 | TIMPANI_PA_CLASSD_CONN_M, |
| 770 | TIMPANI_PA_CLASSD_CONN_POR, |
| 771 | { |
| 772 | { .mask = 0x80, .path_mask = 0}, |
| 773 | { .mask = 0x40, .path_mask = 0}, |
| 774 | { .mask = 0x20, .path_mask = 0}, |
| 775 | { .mask = 0x10, .path_mask = 0}, |
| 776 | { .mask = 0x0F, .path_mask = 0}, |
| 777 | } |
| 778 | }, |
| 779 | { |
| 780 | TIMPANI_A_PA_CNP_CTL, |
| 781 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xCF, |
| 782 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x30}, |
| 783 | TIMPANI_PA_CNP_CTL_M, |
| 784 | TIMPANI_PA_CNP_CTL_POR, |
| 785 | { |
| 786 | { .mask = 0xCF, .path_mask = 0}, |
| 787 | { .mask = 0x30, .path_mask = 0}, |
| 788 | { .mask = 0x00, .path_mask = 0}, |
| 789 | { .mask = 0x00, .path_mask = 0}, |
| 790 | { .mask = 0x00, .path_mask = 0}, |
| 791 | } |
| 792 | }, |
| 793 | { |
| 794 | TIMPANI_A_PA_CLASSD_L_CTL, |
| 795 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x3F, |
| 796 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xC0}, |
| 797 | TIMPANI_PA_CLASSD_L_CTL_M, |
| 798 | TIMPANI_PA_CLASSD_L_CTL_POR, |
| 799 | { |
| 800 | { .mask = 0x3F, .path_mask = 0}, |
| 801 | { .mask = 0xC0, .path_mask = 0}, |
| 802 | { .mask = 0x00, .path_mask = 0}, |
| 803 | { .mask = 0x00, .path_mask = 0}, |
| 804 | { .mask = 0x00, .path_mask = 0}, |
| 805 | } |
| 806 | }, |
| 807 | { |
| 808 | TIMPANI_A_PA_CLASSD_R_CTL, |
| 809 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x3F, |
| 810 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xC0}, |
| 811 | TIMPANI_PA_CLASSD_R_CTL_M, |
| 812 | TIMPANI_PA_CLASSD_R_CTL_POR, |
| 813 | { |
| 814 | { .mask = 0x3F, .path_mask = 0}, |
| 815 | { .mask = 0xC0, .path_mask = 0}, |
| 816 | { .mask = 0x00, .path_mask = 0}, |
| 817 | { .mask = 0x00, .path_mask = 0}, |
| 818 | { .mask = 0x00, .path_mask = 0}, |
| 819 | } |
| 820 | }, |
| 821 | { |
| 822 | TIMPANI_A_PA_CLASSD_INT2_CTL, |
| 823 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xFF, |
| 824 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, |
| 825 | TIMPANI_PA_CLASSD_INT2_CTL_M, |
| 826 | TIMPANI_PA_CLASSD_INT2_CTL_POR, |
| 827 | { |
| 828 | { .mask = 0xFF, .path_mask = 0}, |
| 829 | { .mask = 0x00, .path_mask = 0}, |
| 830 | { .mask = 0x00, .path_mask = 0}, |
| 831 | { .mask = 0x00, .path_mask = 0}, |
| 832 | { .mask = 0x00, .path_mask = 0}, |
| 833 | } |
| 834 | }, |
| 835 | { |
| 836 | TIMPANI_A_PA_HPH_L_OCP_CLK_CTL, |
| 837 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xFF, |
| 838 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, |
| 839 | TIMPANI_PA_HPH_L_OCP_CLK_CTL_M, |
| 840 | TIMPANI_PA_HPH_L_OCP_CLK_CTL_POR, |
| 841 | { |
| 842 | { .mask = 0xFF, .path_mask = 0}, |
| 843 | { .mask = 0x00, .path_mask = 0}, |
| 844 | { .mask = 0x00, .path_mask = 0}, |
| 845 | { .mask = 0x00, .path_mask = 0}, |
| 846 | { .mask = 0x00, .path_mask = 0}, |
| 847 | } |
| 848 | }, |
| 849 | { |
| 850 | TIMPANI_A_PA_CLASSD_L_SW_CTL, |
| 851 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xF7, |
| 852 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x8}, |
| 853 | TIMPANI_PA_CLASSD_L_SW_CTL_M, |
| 854 | TIMPANI_PA_CLASSD_L_SW_CTL_POR, |
| 855 | { |
| 856 | { .mask = 0xF7, .path_mask = 0}, |
| 857 | { .mask = 0x08, .path_mask = 0}, |
| 858 | { .mask = 0x00, .path_mask = 0}, |
| 859 | { .mask = 0x00, .path_mask = 0}, |
| 860 | { .mask = 0x00, .path_mask = 0}, |
| 861 | } |
| 862 | }, |
| 863 | { |
| 864 | TIMPANI_A_PA_CLASSD_L_OCP1, |
| 865 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xFF, |
| 866 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, |
| 867 | TIMPANI_PA_CLASSD_L_OCP1_M, |
| 868 | TIMPANI_PA_CLASSD_L_OCP1_POR, |
| 869 | { |
| 870 | { .mask = 0xFF, .path_mask = 0}, |
| 871 | { .mask = 0x00, .path_mask = 0}, |
| 872 | { .mask = 0x00, .path_mask = 0}, |
| 873 | { .mask = 0x00, .path_mask = 0}, |
| 874 | { .mask = 0x00, .path_mask = 0}, |
| 875 | } |
| 876 | }, |
| 877 | { |
| 878 | TIMPANI_A_PA_CLASSD_L_OCP2, |
| 879 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xFF, |
| 880 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, |
| 881 | TIMPANI_PA_CLASSD_L_OCP2_M, |
| 882 | TIMPANI_PA_CLASSD_L_OCP2_POR, |
| 883 | { |
| 884 | { .mask = 0xFF, .path_mask = 0}, |
| 885 | { .mask = 0x00, .path_mask = 0}, |
| 886 | { .mask = 0x00, .path_mask = 0}, |
| 887 | { .mask = 0x00, .path_mask = 0}, |
| 888 | { .mask = 0x00, .path_mask = 0}, |
| 889 | } |
| 890 | }, |
| 891 | { |
| 892 | TIMPANI_A_PA_HPH_R_OCP_CLK_CTL, |
| 893 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xFF, |
| 894 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, |
| 895 | TIMPANI_PA_HPH_R_OCP_CLK_CTL_M, |
| 896 | TIMPANI_PA_HPH_R_OCP_CLK_CTL_POR, |
| 897 | { |
| 898 | { .mask = 0xFF, .path_mask = 0}, |
| 899 | { .mask = 0x00, .path_mask = 0}, |
| 900 | { .mask = 0x00, .path_mask = 0}, |
| 901 | { .mask = 0x00, .path_mask = 0}, |
| 902 | { .mask = 0x00, .path_mask = 0}, |
| 903 | } |
| 904 | }, |
| 905 | { |
| 906 | TIMPANI_A_PA_CLASSD_R_SW_CTL, |
| 907 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xF7, |
| 908 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x8}, |
| 909 | TIMPANI_PA_CLASSD_R_SW_CTL_M, |
| 910 | TIMPANI_PA_CLASSD_R_SW_CTL_POR, |
| 911 | { |
| 912 | { .mask = 0xF7, .path_mask = 0}, |
| 913 | { .mask = 0x08, .path_mask = 0}, |
| 914 | { .mask = 0x00, .path_mask = 0}, |
| 915 | { .mask = 0x00, .path_mask = 0}, |
| 916 | { .mask = 0x00, .path_mask = 0}, |
| 917 | } |
| 918 | }, |
| 919 | { |
| 920 | TIMPANI_A_PA_CLASSD_R_OCP1, |
| 921 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xFF, |
| 922 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, |
| 923 | TIMPANI_PA_CLASSD_R_OCP1_M, |
| 924 | TIMPANI_PA_CLASSD_R_OCP1_POR, |
| 925 | { |
| 926 | { .mask = 0xFF, .path_mask = 0}, |
| 927 | { .mask = 0x00, .path_mask = 0}, |
| 928 | { .mask = 0x00, .path_mask = 0}, |
| 929 | { .mask = 0x00, .path_mask = 0}, |
| 930 | { .mask = 0x00, .path_mask = 0}, |
| 931 | } |
| 932 | }, |
| 933 | { |
| 934 | TIMPANI_A_PA_CLASSD_R_OCP2, |
| 935 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xFF, |
| 936 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, |
| 937 | TIMPANI_PA_CLASSD_R_OCP2_M, |
| 938 | TIMPANI_PA_CLASSD_R_OCP2_POR, |
| 939 | { |
| 940 | { .mask = 0xFF, .path_mask = 0}, |
| 941 | { .mask = 0x00, .path_mask = 0}, |
| 942 | { .mask = 0x00, .path_mask = 0}, |
| 943 | { .mask = 0x00, .path_mask = 0}, |
| 944 | { .mask = 0x00, .path_mask = 0}, |
| 945 | } |
| 946 | }, |
| 947 | { |
| 948 | TIMPANI_A_PA_HPH_CTL1, |
| 949 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 950 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xFF}, |
| 951 | TIMPANI_PA_HPH_CTL1_M, |
| 952 | TIMPANI_PA_HPH_CTL1_POR, |
| 953 | { |
| 954 | { .mask = 0xFF, .path_mask = 0}, |
| 955 | { .mask = 0x00, .path_mask = 0}, |
| 956 | { .mask = 0x00, .path_mask = 0}, |
| 957 | { .mask = 0x00, .path_mask = 0}, |
| 958 | { .mask = 0x00, .path_mask = 0}, |
| 959 | } |
| 960 | }, |
| 961 | { |
| 962 | TIMPANI_A_PA_HPH_CTL2, |
| 963 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xFE, |
| 964 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1}, |
| 965 | TIMPANI_PA_HPH_CTL2_M, |
| 966 | TIMPANI_PA_HPH_CTL2_POR, |
| 967 | { |
| 968 | { .mask = 0xFE, .path_mask = 0}, |
| 969 | { .mask = 0x01, .path_mask = 0}, |
| 970 | { .mask = 0x00, .path_mask = 0}, |
| 971 | { .mask = 0x00, .path_mask = 0}, |
| 972 | { .mask = 0x00, .path_mask = 0}, |
| 973 | } |
| 974 | }, |
| 975 | { |
| 976 | TIMPANI_A_PA_LINE_AUXO_CTL, |
| 977 | {0x0, 0x0, 0x0, 0x0, 0x0, 0xC3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 978 | 0x3C, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, |
| 979 | TIMPANI_PA_LINE_AUXO_CTL_M, |
| 980 | TIMPANI_PA_LINE_AUXO_CTL_POR, |
| 981 | { |
| 982 | { .mask = 0xC3, .path_mask = 0}, |
| 983 | { .mask = 0x3C, .path_mask = 0}, |
| 984 | { .mask = 0x00, .path_mask = 0}, |
| 985 | { .mask = 0x00, .path_mask = 0}, |
| 986 | { .mask = 0x00, .path_mask = 0}, |
| 987 | } |
| 988 | }, |
| 989 | { |
| 990 | TIMPANI_A_PA_AUXO_EARPA_CTL, |
| 991 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x7, 0x0, |
| 992 | 0x0, 0x38, 0x0, 0x0, 0x0, 0x0, 0x0, 0xC0}, |
| 993 | TIMPANI_PA_AUXO_EARPA_CTL_M, |
| 994 | TIMPANI_PA_AUXO_EARPA_CTL_POR, |
| 995 | { |
| 996 | { .mask = 0x07, .path_mask = 0}, |
| 997 | { .mask = 0x38, .path_mask = 0}, |
| 998 | { .mask = 0xC0, .path_mask = 0}, |
| 999 | { .mask = 0x00, .path_mask = 0}, |
| 1000 | { .mask = 0x00, .path_mask = 0}, |
| 1001 | } |
| 1002 | }, |
| 1003 | { |
| 1004 | TIMPANI_A_PA_EARO_CTL, |
| 1005 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xFF, 0x0, |
| 1006 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, |
| 1007 | TIMPANI_PA_EARO_CTL_M, |
| 1008 | TIMPANI_PA_EARO_CTL_POR, |
| 1009 | { |
| 1010 | { .mask = 0xFF, .path_mask = 0}, |
| 1011 | { .mask = 0x00, .path_mask = 0}, |
| 1012 | { .mask = 0x00, .path_mask = 0}, |
| 1013 | { .mask = 0x00, .path_mask = 0}, |
| 1014 | { .mask = 0x00, .path_mask = 0}, |
| 1015 | } |
| 1016 | }, |
| 1017 | { |
| 1018 | TIMPANI_A_PA_MASTER_BIAS_CUR, |
| 1019 | {0x0, 0x0, 0x0, 0x0, 0x60, 0x0, 0x0, 0x0, 0x0, 0x80, 0x0, 0x18, |
| 1020 | 0x6, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1}, |
| 1021 | TIMPANI_PA_MASTER_BIAS_CUR_M, |
| 1022 | TIMPANI_PA_MASTER_BIAS_CUR_POR, |
| 1023 | { |
| 1024 | { .mask = 0x60, .path_mask = 0}, |
| 1025 | { .mask = 0x80, .path_mask = 0}, |
| 1026 | { .mask = 0x18, .path_mask = 0}, |
| 1027 | { .mask = 0x06, .path_mask = 0}, |
| 1028 | { .mask = 0x01, .path_mask = 0}, |
| 1029 | } |
| 1030 | }, |
| 1031 | { |
| 1032 | TIMPANI_A_PA_CLASSD_SC_STATUS, |
| 1033 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xCC, |
| 1034 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x33}, |
| 1035 | TIMPANI_PA_CLASSD_SC_STATUS_M, |
| 1036 | TIMPANI_PA_CLASSD_SC_STATUS_POR, |
| 1037 | { |
| 1038 | { .mask = 0xCC, .path_mask = 0}, |
| 1039 | { .mask = 0x33, .path_mask = 0}, |
| 1040 | { .mask = 0x00, .path_mask = 0}, |
| 1041 | { .mask = 0x00, .path_mask = 0}, |
| 1042 | { .mask = 0x00, .path_mask = 0}, |
| 1043 | } |
| 1044 | }, |
| 1045 | { |
| 1046 | TIMPANI_A_PA_HPH_SC_STATUS, |
| 1047 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x88, |
| 1048 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x77}, |
| 1049 | TIMPANI_PA_HPH_SC_STATUS_M, |
| 1050 | TIMPANI_PA_HPH_SC_STATUS_POR, |
| 1051 | { |
| 1052 | { .mask = 0x88, .path_mask = 0}, |
| 1053 | { .mask = 0x77, .path_mask = 0}, |
| 1054 | { .mask = 0x00, .path_mask = 0}, |
| 1055 | { .mask = 0x00, .path_mask = 0}, |
| 1056 | { .mask = 0x00, .path_mask = 0}, |
| 1057 | } |
| 1058 | }, |
| 1059 | { |
| 1060 | TIMPANI_A_ATEST_EN, |
| 1061 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 1062 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x80, 0x7F}, |
| 1063 | TIMPANI_ATEST_EN_M, |
| 1064 | TIMPANI_ATEST_EN_POR, |
| 1065 | { |
| 1066 | { .mask = 0x80, .path_mask = 0}, |
| 1067 | { .mask = 0x7F, .path_mask = 0}, |
| 1068 | { .mask = 0x00, .path_mask = 0}, |
| 1069 | { .mask = 0x00, .path_mask = 0}, |
| 1070 | { .mask = 0x00, .path_mask = 0}, |
| 1071 | } |
| 1072 | }, |
| 1073 | { |
| 1074 | TIMPANI_A_ATEST_TSHKADC, |
| 1075 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 1076 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xF, 0xF0}, |
| 1077 | TIMPANI_ATEST_TSHKADC_M, |
| 1078 | TIMPANI_ATEST_TSHKADC_POR, |
| 1079 | { |
| 1080 | { .mask = 0x0F, .path_mask = 0}, |
| 1081 | { .mask = 0xF0, .path_mask = 0}, |
| 1082 | { .mask = 0x00, .path_mask = 0}, |
| 1083 | { .mask = 0x00, .path_mask = 0}, |
| 1084 | { .mask = 0x00, .path_mask = 0}, |
| 1085 | } |
| 1086 | }, |
| 1087 | { |
| 1088 | TIMPANI_A_ATEST_TXADC13, |
| 1089 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 1090 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x7F, 0x80}, |
| 1091 | TIMPANI_ATEST_TXADC13_M, |
| 1092 | TIMPANI_ATEST_TXADC13_POR, |
| 1093 | { |
| 1094 | { .mask = 0x7F, .path_mask = 0}, |
| 1095 | { .mask = 0x80, .path_mask = 0}, |
| 1096 | { .mask = 0x00, .path_mask = 0}, |
| 1097 | { .mask = 0x00, .path_mask = 0}, |
| 1098 | { .mask = 0x00, .path_mask = 0}, |
| 1099 | } |
| 1100 | }, |
| 1101 | { |
| 1102 | TIMPANI_A_ATEST_TXADC24, |
| 1103 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 1104 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x7F, 0x80}, |
| 1105 | TIMPANI_ATEST_TXADC24_M, |
| 1106 | TIMPANI_ATEST_TXADC24_POR, |
| 1107 | { |
| 1108 | { .mask = 0x7F, .path_mask = 0}, |
| 1109 | { .mask = 0x80, .path_mask = 0}, |
| 1110 | { .mask = 0x00, .path_mask = 0}, |
| 1111 | { .mask = 0x00, .path_mask = 0}, |
| 1112 | { .mask = 0x00, .path_mask = 0}, |
| 1113 | } |
| 1114 | }, |
| 1115 | { |
| 1116 | TIMPANI_A_ATEST_AUXPGA, |
| 1117 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 1118 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xF8, 0x7}, |
| 1119 | TIMPANI_ATEST_AUXPGA_M, |
| 1120 | TIMPANI_ATEST_AUXPGA_POR, |
| 1121 | { |
| 1122 | { .mask = 0xF8, .path_mask = 0}, |
| 1123 | { .mask = 0x07, .path_mask = 0}, |
| 1124 | { .mask = 0x00, .path_mask = 0}, |
| 1125 | { .mask = 0x00, .path_mask = 0}, |
| 1126 | { .mask = 0x00, .path_mask = 0}, |
| 1127 | } |
| 1128 | }, |
| 1129 | { |
| 1130 | TIMPANI_A_ATEST_CDAC, |
| 1131 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 1132 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xFF, 0x0}, |
| 1133 | TIMPANI_ATEST_CDAC_M, |
| 1134 | TIMPANI_ATEST_CDAC_POR, |
| 1135 | { |
| 1136 | { .mask = 0xFF, .path_mask = 0}, |
| 1137 | { .mask = 0x00, .path_mask = 0}, |
| 1138 | { .mask = 0x00, .path_mask = 0}, |
| 1139 | { .mask = 0x00, .path_mask = 0}, |
| 1140 | { .mask = 0x00, .path_mask = 0}, |
| 1141 | } |
| 1142 | }, |
| 1143 | { |
| 1144 | TIMPANI_A_ATEST_IDAC, |
| 1145 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 1146 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xFF, 0x0}, |
| 1147 | TIMPANI_ATEST_IDAC_M, |
| 1148 | TIMPANI_ATEST_IDAC_POR, |
| 1149 | { |
| 1150 | { .mask = 0xFF, .path_mask = 0}, |
| 1151 | { .mask = 0x00, .path_mask = 0}, |
| 1152 | { .mask = 0x00, .path_mask = 0}, |
| 1153 | { .mask = 0x00, .path_mask = 0}, |
| 1154 | { .mask = 0x00, .path_mask = 0}, |
| 1155 | } |
| 1156 | }, |
| 1157 | { |
| 1158 | TIMPANI_A_ATEST_PA1, |
| 1159 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 1160 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xFF, 0x0}, |
| 1161 | TIMPANI_ATEST_PA1_M, |
| 1162 | TIMPANI_ATEST_PA1_POR, |
| 1163 | { |
| 1164 | { .mask = 0xFF, .path_mask = 0}, |
| 1165 | { .mask = 0x00, .path_mask = 0}, |
| 1166 | { .mask = 0x00, .path_mask = 0}, |
| 1167 | { .mask = 0x00, .path_mask = 0}, |
| 1168 | { .mask = 0x00, .path_mask = 0}, |
| 1169 | } |
| 1170 | }, |
| 1171 | { |
| 1172 | TIMPANI_A_ATEST_CLASSD, |
| 1173 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 1174 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xFF, 0x0}, |
| 1175 | TIMPANI_ATEST_CLASSD_M, |
| 1176 | TIMPANI_ATEST_CLASSD_POR, |
| 1177 | { |
| 1178 | { .mask = 0xFF, .path_mask = 0}, |
| 1179 | { .mask = 0x00, .path_mask = 0}, |
| 1180 | { .mask = 0x00, .path_mask = 0}, |
| 1181 | { .mask = 0x00, .path_mask = 0}, |
| 1182 | { .mask = 0x00, .path_mask = 0}, |
| 1183 | } |
| 1184 | }, |
| 1185 | { |
| 1186 | TIMPANI_A_ATEST_LINEO_AUXO, |
| 1187 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 1188 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xFF, 0x0}, |
| 1189 | TIMPANI_ATEST_LINEO_AUXO_M, |
| 1190 | TIMPANI_ATEST_LINEO_AUXO_POR, |
| 1191 | { |
| 1192 | { .mask = 0xFF, .path_mask = 0}, |
| 1193 | { .mask = 0x00, .path_mask = 0}, |
| 1194 | { .mask = 0x00, .path_mask = 0}, |
| 1195 | { .mask = 0x00, .path_mask = 0}, |
| 1196 | { .mask = 0x00, .path_mask = 0}, |
| 1197 | } |
| 1198 | }, |
| 1199 | { |
| 1200 | TIMPANI_A_CDC_RESET_CTL, |
| 1201 | {0x2, 0x8, 0x5, 0x30, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 1202 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xC0}, |
| 1203 | TIMPANI_CDC_RESET_CTL_M, |
| 1204 | TIMPANI_CDC_RESET_CTL_POR, |
| 1205 | { |
| 1206 | { .mask = 0x02, .path_mask = 0}, |
| 1207 | { .mask = 0x08, .path_mask = 0}, |
| 1208 | { .mask = 0x05, .path_mask = 0}, |
| 1209 | { .mask = 0x30, .path_mask = 0}, |
| 1210 | { .mask = 0xC0, .path_mask = 0}, |
| 1211 | } |
| 1212 | }, |
| 1213 | { |
| 1214 | TIMPANI_A_CDC_RX1_CTL, |
| 1215 | {0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 1216 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, |
| 1217 | TIMPANI_CDC_RX1_CTL_M, |
| 1218 | TIMPANI_CDC_RX1_CTL_POR, |
| 1219 | { |
| 1220 | { .mask = 0xFF, .path_mask = 0}, |
| 1221 | { .mask = 0x00, .path_mask = 0}, |
| 1222 | { .mask = 0x00, .path_mask = 0}, |
| 1223 | { .mask = 0x00, .path_mask = 0}, |
| 1224 | { .mask = 0x00, .path_mask = 0}, |
| 1225 | } |
| 1226 | }, |
| 1227 | { |
| 1228 | TIMPANI_A_CDC_TX_I2S_CTL, |
| 1229 | {0x0, 0x0, 0x10, 0x20, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 1230 | 0x0, 0x0, 0x0, 0x0, 0xF, 0x0, 0x0, 0xC0}, |
| 1231 | TIMPANI_CDC_TX_I2S_CTL_M, |
| 1232 | TIMPANI_CDC_TX_I2S_CTL_POR, |
| 1233 | { |
| 1234 | { .mask = 0x10, .path_mask = 0}, |
| 1235 | { .mask = 0x20, .path_mask = 0}, |
| 1236 | { .mask = 0x0F, .path_mask = 0}, |
| 1237 | { .mask = 0xC0, .path_mask = 0}, |
| 1238 | { .mask = 0x00, .path_mask = 0}, |
| 1239 | } |
| 1240 | }, |
| 1241 | { |
| 1242 | TIMPANI_A_CDC_CH_CTL, |
| 1243 | {0x3, 0x30, 0xC, 0xC0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 1244 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, |
| 1245 | TIMPANI_CDC_CH_CTL_M, |
| 1246 | TIMPANI_CDC_CH_CTL_POR, |
| 1247 | { |
| 1248 | { .mask = 0x03, .path_mask = 0}, |
| 1249 | { .mask = 0x30, .path_mask = 0}, |
| 1250 | { .mask = 0x0C, .path_mask = 0}, |
| 1251 | { .mask = 0xC0, .path_mask = 0}, |
| 1252 | { .mask = 0x00, .path_mask = 0}, |
| 1253 | } |
| 1254 | }, |
| 1255 | { |
| 1256 | TIMPANI_A_CDC_RX1LG, |
| 1257 | {0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 1258 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, |
| 1259 | TIMPANI_CDC_RX1LG_M, |
| 1260 | TIMPANI_CDC_RX1LG_POR, |
| 1261 | { |
| 1262 | { .mask = 0xFF, .path_mask = 0}, |
| 1263 | { .mask = 0x00, .path_mask = 0}, |
| 1264 | { .mask = 0x00, .path_mask = 0}, |
| 1265 | { .mask = 0x00, .path_mask = 0}, |
| 1266 | { .mask = 0x00, .path_mask = 0}, |
| 1267 | } |
| 1268 | }, |
| 1269 | { |
| 1270 | TIMPANI_A_CDC_RX1RG, |
| 1271 | {0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 1272 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, |
| 1273 | TIMPANI_CDC_RX1RG_M, |
| 1274 | TIMPANI_CDC_RX1RG_POR, |
| 1275 | { |
| 1276 | { .mask = 0xFF, .path_mask = 0}, |
| 1277 | { .mask = 0x00, .path_mask = 0}, |
| 1278 | { .mask = 0x00, .path_mask = 0}, |
| 1279 | { .mask = 0x00, .path_mask = 0}, |
| 1280 | { .mask = 0x00, .path_mask = 0}, |
| 1281 | } |
| 1282 | }, |
| 1283 | { |
| 1284 | TIMPANI_A_CDC_TX1LG, |
| 1285 | {0x0, 0x0, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 1286 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, |
| 1287 | TIMPANI_CDC_TX1LG_M, |
| 1288 | TIMPANI_CDC_TX1LG_POR, |
| 1289 | { |
| 1290 | { .mask = 0xFF, .path_mask = 0}, |
| 1291 | { .mask = 0x00, .path_mask = 0}, |
| 1292 | { .mask = 0x00, .path_mask = 0}, |
| 1293 | { .mask = 0x00, .path_mask = 0}, |
| 1294 | { .mask = 0x00, .path_mask = 0}, |
| 1295 | } |
| 1296 | }, |
| 1297 | { |
| 1298 | TIMPANI_A_CDC_TX1RG, |
| 1299 | {0x0, 0x0, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 1300 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, |
| 1301 | TIMPANI_CDC_TX1RG_M, |
| 1302 | TIMPANI_CDC_TX1RG_POR, |
| 1303 | { |
| 1304 | { .mask = 0xFF, .path_mask = 0}, |
| 1305 | { .mask = 0x00, .path_mask = 0}, |
| 1306 | { .mask = 0x00, .path_mask = 0}, |
| 1307 | { .mask = 0x00, .path_mask = 0}, |
| 1308 | { .mask = 0x00, .path_mask = 0}, |
| 1309 | } |
| 1310 | }, |
| 1311 | { |
| 1312 | TIMPANI_A_CDC_RX_PGA_TIMER, |
| 1313 | {0x0, 0x0, 0x0, 0x0, 0x0, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 1314 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, |
| 1315 | TIMPANI_CDC_RX_PGA_TIMER_M, |
| 1316 | TIMPANI_CDC_RX_PGA_TIMER_POR, |
| 1317 | { |
| 1318 | { .mask = 0xFF, .path_mask = 0}, |
| 1319 | { .mask = 0x00, .path_mask = 0}, |
| 1320 | { .mask = 0x00, .path_mask = 0}, |
| 1321 | { .mask = 0x00, .path_mask = 0}, |
| 1322 | { .mask = 0x00, .path_mask = 0}, |
| 1323 | } |
| 1324 | }, |
| 1325 | { |
| 1326 | TIMPANI_A_CDC_TX_PGA_TIMER, |
| 1327 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 1328 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, |
| 1329 | TIMPANI_CDC_TX_PGA_TIMER_M, |
| 1330 | TIMPANI_CDC_TX_PGA_TIMER_POR, |
| 1331 | { |
| 1332 | { .mask = 0xFF, .path_mask = 0}, |
| 1333 | { .mask = 0x00, .path_mask = 0}, |
| 1334 | { .mask = 0x00, .path_mask = 0}, |
| 1335 | { .mask = 0x00, .path_mask = 0}, |
| 1336 | { .mask = 0x00, .path_mask = 0}, |
| 1337 | } |
| 1338 | }, |
| 1339 | { |
| 1340 | TIMPANI_A_CDC_GCTL1, |
| 1341 | {0xF, 0x0, 0xF0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 1342 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, |
| 1343 | TIMPANI_CDC_GCTL1_M, |
| 1344 | TIMPANI_CDC_GCTL1_POR, |
| 1345 | { |
| 1346 | { .mask = 0x0F, .path_mask = 0}, |
| 1347 | { .mask = 0xF0, .path_mask = 0}, |
| 1348 | { .mask = 0x00, .path_mask = 0}, |
| 1349 | { .mask = 0x00, .path_mask = 0}, |
| 1350 | { .mask = 0x00, .path_mask = 0}, |
| 1351 | } |
| 1352 | }, |
| 1353 | { |
| 1354 | TIMPANI_A_CDC_TX1L_STG, |
| 1355 | {0x0, 0x0, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 1356 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, |
| 1357 | TIMPANI_CDC_TX1L_STG_M, |
| 1358 | TIMPANI_CDC_TX1L_STG_POR, |
| 1359 | { |
| 1360 | { .mask = 0xFF, .path_mask = 0}, |
| 1361 | { .mask = 0x00, .path_mask = 0}, |
| 1362 | { .mask = 0x00, .path_mask = 0}, |
| 1363 | { .mask = 0x00, .path_mask = 0}, |
| 1364 | { .mask = 0x00, .path_mask = 0}, |
| 1365 | } |
| 1366 | }, |
| 1367 | { |
| 1368 | TIMPANI_A_CDC_ST_CTL, |
| 1369 | {0x0, 0xF, 0x0, 0xF0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 1370 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, |
| 1371 | TIMPANI_CDC_ST_CTL_M, |
| 1372 | TIMPANI_CDC_ST_CTL_POR, |
| 1373 | { |
| 1374 | { .mask = 0x0F, .path_mask = 0}, |
| 1375 | { .mask = 0xF0, .path_mask = 0}, |
| 1376 | { .mask = 0x00, .path_mask = 0}, |
| 1377 | { .mask = 0x00, .path_mask = 0}, |
| 1378 | { .mask = 0x00, .path_mask = 0}, |
| 1379 | } |
| 1380 | }, |
| 1381 | { |
| 1382 | TIMPANI_A_CDC_RX1L_DCOFFSET, |
| 1383 | {0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 1384 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, |
| 1385 | TIMPANI_CDC_RX1L_DCOFFSET_M, |
| 1386 | TIMPANI_CDC_RX1L_DCOFFSET_POR, |
| 1387 | { |
| 1388 | { .mask = 0xFF, .path_mask = 0}, |
| 1389 | { .mask = 0x00, .path_mask = 0}, |
| 1390 | { .mask = 0x00, .path_mask = 0}, |
| 1391 | { .mask = 0x00, .path_mask = 0}, |
| 1392 | { .mask = 0x00, .path_mask = 0}, |
| 1393 | } |
| 1394 | }, |
| 1395 | { |
| 1396 | TIMPANI_A_CDC_RX1R_DCOFFSET, |
| 1397 | {0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 1398 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, |
| 1399 | TIMPANI_CDC_RX1R_DCOFFSET_M, |
| 1400 | TIMPANI_CDC_RX1R_DCOFFSET_POR, |
| 1401 | { |
| 1402 | { .mask = 0xFF, .path_mask = 0}, |
| 1403 | { .mask = 0x00, .path_mask = 0}, |
| 1404 | { .mask = 0x00, .path_mask = 0}, |
| 1405 | { .mask = 0x00, .path_mask = 0}, |
| 1406 | { .mask = 0x00, .path_mask = 0}, |
| 1407 | } |
| 1408 | }, |
| 1409 | { |
| 1410 | TIMPANI_A_CDC_BYPASS_CTL1, |
| 1411 | {0xF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 1412 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xF0}, |
| 1413 | TIMPANI_CDC_BYPASS_CTL1_M, |
| 1414 | TIMPANI_CDC_BYPASS_CTL1_POR, |
| 1415 | { |
| 1416 | { .mask = 0x0F, .path_mask = 0}, |
| 1417 | { .mask = 0xF0, .path_mask = 0}, |
| 1418 | { .mask = 0x00, .path_mask = 0}, |
| 1419 | { .mask = 0x00, .path_mask = 0}, |
| 1420 | { .mask = 0x00, .path_mask = 0}, |
| 1421 | } |
| 1422 | }, |
| 1423 | { |
| 1424 | TIMPANI_A_CDC_PDM_CONFIG, |
| 1425 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 1426 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xF, 0xF0}, |
| 1427 | TIMPANI_CDC_PDM_CONFIG_M, |
| 1428 | TIMPANI_CDC_PDM_CONFIG_POR, |
| 1429 | { |
| 1430 | { .mask = 0x0F, .path_mask = 0}, |
| 1431 | { .mask = 0xF0, .path_mask = 0}, |
| 1432 | { .mask = 0x00, .path_mask = 0}, |
| 1433 | { .mask = 0x00, .path_mask = 0}, |
| 1434 | { .mask = 0x00, .path_mask = 0}, |
| 1435 | } |
| 1436 | }, |
| 1437 | { |
| 1438 | TIMPANI_A_CDC_TESTMODE1, |
| 1439 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 1440 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x3F, 0xC0}, |
| 1441 | TIMPANI_CDC_TESTMODE1_M, |
| 1442 | TIMPANI_CDC_TESTMODE1_POR, |
| 1443 | { |
| 1444 | { .mask = 0x3F, .path_mask = 0}, |
| 1445 | { .mask = 0xC0, .path_mask = 0}, |
| 1446 | { .mask = 0x00, .path_mask = 0}, |
| 1447 | { .mask = 0x00, .path_mask = 0}, |
| 1448 | { .mask = 0x00, .path_mask = 0}, |
| 1449 | } |
| 1450 | }, |
| 1451 | { |
| 1452 | TIMPANI_A_CDC_DMIC_CLK_CTL, |
| 1453 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 1454 | 0x0, 0x0, 0x0, 0x3F, 0x0, 0x0, 0x0, 0xC0}, |
| 1455 | TIMPANI_CDC_DMIC_CLK_CTL_M, |
| 1456 | TIMPANI_CDC_DMIC_CLK_CTL_POR, |
| 1457 | { |
| 1458 | { .mask = 0x3F, .path_mask = 0}, |
| 1459 | { .mask = 0xC0, .path_mask = 0}, |
| 1460 | { .mask = 0x00, .path_mask = 0}, |
| 1461 | { .mask = 0x00, .path_mask = 0}, |
| 1462 | { .mask = 0x00, .path_mask = 0}, |
| 1463 | } |
| 1464 | }, |
| 1465 | { |
| 1466 | TIMPANI_A_CDC_ADC12_CLK_CTL, |
| 1467 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xFF, 0x0, 0x0, 0x0, 0x0, |
| 1468 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, |
| 1469 | TIMPANI_CDC_ADC12_CLK_CTL_M, |
| 1470 | TIMPANI_CDC_ADC12_CLK_CTL_POR, |
| 1471 | { |
| 1472 | { .mask = 0xFF, .path_mask = 0}, |
| 1473 | { .mask = 0x00, .path_mask = 0}, |
| 1474 | { .mask = 0x00, .path_mask = 0}, |
| 1475 | { .mask = 0x00, .path_mask = 0}, |
| 1476 | { .mask = 0x00, .path_mask = 0}, |
| 1477 | } |
| 1478 | }, |
| 1479 | { |
| 1480 | TIMPANI_A_CDC_TX1_CTL, |
| 1481 | {0x0, 0x0, 0x3F, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 1482 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xC0}, |
| 1483 | TIMPANI_CDC_TX1_CTL_M, |
| 1484 | TIMPANI_CDC_TX1_CTL_POR, |
| 1485 | { |
| 1486 | { .mask = 0x3F, .path_mask = 0}, |
| 1487 | { .mask = 0xC0, .path_mask = 0}, |
| 1488 | { .mask = 0x00, .path_mask = 0}, |
| 1489 | { .mask = 0x00, .path_mask = 0}, |
| 1490 | { .mask = 0x00, .path_mask = 0}, |
| 1491 | } |
| 1492 | }, |
| 1493 | { |
| 1494 | TIMPANI_A_CDC_ADC34_CLK_CTL, |
| 1495 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xFF, 0x0, 0x0, 0x0, |
| 1496 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, |
| 1497 | TIMPANI_CDC_ADC34_CLK_CTL_M, |
| 1498 | TIMPANI_CDC_ADC34_CLK_CTL_POR, |
| 1499 | { |
| 1500 | { .mask = 0xFF, .path_mask = 0}, |
| 1501 | { .mask = 0x00, .path_mask = 0}, |
| 1502 | { .mask = 0x00, .path_mask = 0}, |
| 1503 | { .mask = 0x00, .path_mask = 0}, |
| 1504 | { .mask = 0x00, .path_mask = 0}, |
| 1505 | } |
| 1506 | }, |
| 1507 | { |
| 1508 | TIMPANI_A_CDC_TX2_CTL, |
| 1509 | {0x0, 0x0, 0x0, 0x3F, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 1510 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xC0}, |
| 1511 | TIMPANI_CDC_TX2_CTL_M, |
| 1512 | TIMPANI_CDC_TX2_CTL_POR, |
| 1513 | { |
| 1514 | { .mask = 0x3F, .path_mask = 0}, |
| 1515 | { .mask = 0xC0, .path_mask = 0}, |
| 1516 | { .mask = 0x00, .path_mask = 0}, |
| 1517 | { .mask = 0x00, .path_mask = 0}, |
| 1518 | { .mask = 0x00, .path_mask = 0}, |
| 1519 | } |
| 1520 | }, |
| 1521 | { |
| 1522 | TIMPANI_A_CDC_RX1_CLK_CTL, |
| 1523 | {0x1F, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 1524 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xE0}, |
| 1525 | TIMPANI_CDC_RX1_CLK_CTL_M, |
| 1526 | TIMPANI_CDC_RX1_CLK_CTL_POR, |
| 1527 | { |
| 1528 | { .mask = 0x1F, .path_mask = 0}, |
| 1529 | { .mask = 0xE0, .path_mask = 0}, |
| 1530 | { .mask = 0x00, .path_mask = 0}, |
| 1531 | { .mask = 0x00, .path_mask = 0}, |
| 1532 | { .mask = 0x00, .path_mask = 0}, |
| 1533 | } |
| 1534 | }, |
| 1535 | { |
| 1536 | TIMPANI_A_CDC_RX2_CLK_CTL, |
| 1537 | {0x1F, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 1538 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xE0}, |
| 1539 | TIMPANI_CDC_RX2_CLK_CTL_M, |
| 1540 | TIMPANI_CDC_RX2_CLK_CTL_POR, |
| 1541 | { |
| 1542 | { .mask = 0x1F, .path_mask = 0}, |
| 1543 | { .mask = 0xE0, .path_mask = 0}, |
| 1544 | { .mask = 0x00, .path_mask = 0}, |
| 1545 | { .mask = 0x00, .path_mask = 0}, |
| 1546 | { .mask = 0x00, .path_mask = 0}, |
| 1547 | } |
| 1548 | }, |
| 1549 | { |
| 1550 | TIMPANI_A_CDC_DEC_ADC_SEL, |
| 1551 | {0x0, 0x0, 0xF, 0xF0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 1552 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, |
| 1553 | TIMPANI_CDC_DEC_ADC_SEL_M, |
| 1554 | TIMPANI_CDC_DEC_ADC_SEL_POR, |
| 1555 | { |
| 1556 | { .mask = 0x0F, .path_mask = 0}, |
| 1557 | { .mask = 0xF0, .path_mask = 0}, |
| 1558 | { .mask = 0x00, .path_mask = 0}, |
| 1559 | { .mask = 0x00, .path_mask = 0}, |
| 1560 | { .mask = 0x00, .path_mask = 0}, |
| 1561 | } |
| 1562 | }, |
| 1563 | { |
| 1564 | TIMPANI_A_CDC_ANC_INPUT_MUX, |
| 1565 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 1566 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x3F, 0x0, 0xC0}, |
| 1567 | TIMPANI_CDC_ANC_INPUT_MUX_M, |
| 1568 | TIMPANI_CDC_ANC_INPUT_MUX_POR, |
| 1569 | { |
| 1570 | { .mask = 0x3F, .path_mask = 0}, |
| 1571 | { .mask = 0xC0, .path_mask = 0}, |
| 1572 | { .mask = 0x00, .path_mask = 0}, |
| 1573 | { .mask = 0x00, .path_mask = 0}, |
| 1574 | { .mask = 0x00, .path_mask = 0}, |
| 1575 | } |
| 1576 | }, |
| 1577 | { |
| 1578 | TIMPANI_A_CDC_ANC_RX_CLK_NS_SEL, |
| 1579 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 1580 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x1, 0x0, 0xFE}, |
| 1581 | TIMPANI_CDC_ANC_RX_CLK_NS_SEL_M, |
| 1582 | TIMPANI_CDC_ANC_RX_CLK_NS_SEL_POR, |
| 1583 | { |
| 1584 | { .mask = 0x01, .path_mask = 0}, |
| 1585 | { .mask = 0xFE, .path_mask = 0}, |
| 1586 | { .mask = 0x00, .path_mask = 0}, |
| 1587 | { .mask = 0x00, .path_mask = 0}, |
| 1588 | { .mask = 0x00, .path_mask = 0}, |
| 1589 | } |
| 1590 | }, |
| 1591 | { |
| 1592 | TIMPANI_A_CDC_ANC_FB_TUNE_SEL, |
| 1593 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 1594 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xFF}, |
| 1595 | TIMPANI_CDC_ANC_FB_TUNE_SEL_M, |
| 1596 | TIMPANI_CDC_ANC_FB_TUNE_SEL_POR, |
| 1597 | { |
| 1598 | { .mask = 0xFF, .path_mask = 0}, |
| 1599 | { .mask = 0x00, .path_mask = 0}, |
| 1600 | { .mask = 0x00, .path_mask = 0}, |
| 1601 | { .mask = 0x00, .path_mask = 0}, |
| 1602 | { .mask = 0x00, .path_mask = 0}, |
| 1603 | } |
| 1604 | }, |
| 1605 | { |
| 1606 | TIMPANI_A_CLK_DIV_SYNC_CTL, |
| 1607 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 1608 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x3, 0x0, 0xFC}, |
| 1609 | TIMPANI_CLK_DIV_SYNC_CTL_M, |
| 1610 | TIMPANI_CLK_DIV_SYNC_CTL_POR, |
| 1611 | { |
| 1612 | { .mask = 0x03, .path_mask = 0}, |
| 1613 | { .mask = 0xFC, .path_mask = 0}, |
| 1614 | { .mask = 0x00, .path_mask = 0}, |
| 1615 | { .mask = 0x00, .path_mask = 0}, |
| 1616 | { .mask = 0x00, .path_mask = 0}, |
| 1617 | } |
| 1618 | }, |
| 1619 | { |
| 1620 | TIMPANI_A_CDC_ADC_CLK_EN, |
| 1621 | {0x0, 0x0, 0x3, 0xC, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 1622 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xF0}, |
| 1623 | TIMPANI_CDC_ADC_CLK_EN_M, |
| 1624 | TIMPANI_CDC_ADC_CLK_EN_POR, |
| 1625 | { |
| 1626 | { .mask = 0x03, .path_mask = 0}, |
| 1627 | { .mask = 0x0C, .path_mask = 0}, |
| 1628 | { .mask = 0xF0, .path_mask = 0}, |
| 1629 | { .mask = 0x00, .path_mask = 0}, |
| 1630 | { .mask = 0x00, .path_mask = 0}, |
| 1631 | } |
| 1632 | }, |
| 1633 | { |
| 1634 | TIMPANI_A_CDC_ST_MIXING, |
| 1635 | {0x0, 0x0, 0x3, 0xC, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 1636 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xF0}, |
| 1637 | TIMPANI_CDC_ST_MIXING_M, |
| 1638 | TIMPANI_CDC_ST_MIXING_POR, |
| 1639 | { |
| 1640 | { .mask = 0x03, .path_mask = 0}, |
| 1641 | { .mask = 0x0C, .path_mask = 0}, |
| 1642 | { .mask = 0xF0, .path_mask = 0}, |
| 1643 | { .mask = 0x00, .path_mask = 0}, |
| 1644 | { .mask = 0x00, .path_mask = 0}, |
| 1645 | } |
| 1646 | }, |
| 1647 | { |
| 1648 | TIMPANI_A_CDC_RX2_CTL, |
| 1649 | {0x0, 0x7F, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 1650 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x80}, |
| 1651 | TIMPANI_CDC_RX2_CTL_M, |
| 1652 | TIMPANI_CDC_RX2_CTL_POR, |
| 1653 | { |
| 1654 | { .mask = 0x7F, .path_mask = 0}, |
| 1655 | { .mask = 0x80, .path_mask = 0}, |
| 1656 | { .mask = 0x00, .path_mask = 0}, |
| 1657 | { .mask = 0x00, .path_mask = 0}, |
| 1658 | { .mask = 0x00, .path_mask = 0}, |
| 1659 | } |
| 1660 | }, |
| 1661 | { |
| 1662 | TIMPANI_A_CDC_ARB_CLK_EN, |
| 1663 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 1664 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xFF}, |
| 1665 | TIMPANI_CDC_ARB_CLK_EN_M, |
| 1666 | TIMPANI_CDC_ARB_CLK_EN_POR, |
| 1667 | { |
| 1668 | { .mask = 0xFF, .path_mask = 0}, |
| 1669 | { .mask = 0x00, .path_mask = 0}, |
| 1670 | { .mask = 0x00, .path_mask = 0}, |
| 1671 | { .mask = 0x00, .path_mask = 0}, |
| 1672 | { .mask = 0x00, .path_mask = 0}, |
| 1673 | } |
| 1674 | }, |
| 1675 | { |
| 1676 | TIMPANI_A_CDC_I2S_CTL2, |
| 1677 | {0x2, 0x4, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 1678 | 0x0, 0x0, 0x0, 0x0, 0x39, 0x0, 0x0, 0xC0}, |
| 1679 | TIMPANI_CDC_I2S_CTL2_M, |
| 1680 | TIMPANI_CDC_I2S_CTL2_POR, |
| 1681 | { |
| 1682 | { .mask = 0x02, .path_mask = 0}, |
| 1683 | { .mask = 0x04, .path_mask = 0}, |
| 1684 | { .mask = 0x39, .path_mask = 0}, |
| 1685 | { .mask = 0xC0, .path_mask = 0}, |
| 1686 | { .mask = 0x00, .path_mask = 0}, |
| 1687 | } |
| 1688 | }, |
| 1689 | { |
| 1690 | TIMPANI_A_CDC_RX2LG, |
| 1691 | {0x0, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 1692 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, |
| 1693 | TIMPANI_CDC_RX2LG_M, |
| 1694 | TIMPANI_CDC_RX2LG_POR, |
| 1695 | { |
| 1696 | { .mask = 0xFF, .path_mask = 0}, |
| 1697 | { .mask = 0x00, .path_mask = 0}, |
| 1698 | { .mask = 0x00, .path_mask = 0}, |
| 1699 | { .mask = 0x00, .path_mask = 0}, |
| 1700 | { .mask = 0x00, .path_mask = 0}, |
| 1701 | } |
| 1702 | }, |
| 1703 | { |
| 1704 | TIMPANI_A_CDC_RX2RG, |
| 1705 | {0x0, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 1706 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, |
| 1707 | TIMPANI_CDC_RX2RG_M, |
| 1708 | TIMPANI_CDC_RX2RG_POR, |
| 1709 | { |
| 1710 | { .mask = 0xFF, .path_mask = 0}, |
| 1711 | { .mask = 0x00, .path_mask = 0}, |
| 1712 | { .mask = 0x00, .path_mask = 0}, |
| 1713 | { .mask = 0x00, .path_mask = 0}, |
| 1714 | { .mask = 0x00, .path_mask = 0}, |
| 1715 | } |
| 1716 | }, |
| 1717 | { |
| 1718 | TIMPANI_A_CDC_TX2LG, |
| 1719 | {0x0, 0x0, 0x0, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 1720 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, |
| 1721 | TIMPANI_CDC_TX2LG_M, |
| 1722 | TIMPANI_CDC_TX2LG_POR, |
| 1723 | { |
| 1724 | { .mask = 0xFF, .path_mask = 0}, |
| 1725 | { .mask = 0x00, .path_mask = 0}, |
| 1726 | { .mask = 0x00, .path_mask = 0}, |
| 1727 | { .mask = 0x00, .path_mask = 0}, |
| 1728 | { .mask = 0x00, .path_mask = 0}, |
| 1729 | } |
| 1730 | }, |
| 1731 | { |
| 1732 | TIMPANI_A_CDC_TX2RG, |
| 1733 | {0x0, 0x0, 0x0, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 1734 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, |
| 1735 | TIMPANI_CDC_TX2RG_M, |
| 1736 | TIMPANI_CDC_TX2RG_POR, |
| 1737 | { |
| 1738 | { .mask = 0xFF, .path_mask = 0}, |
| 1739 | { .mask = 0x00, .path_mask = 0}, |
| 1740 | { .mask = 0x00, .path_mask = 0}, |
| 1741 | { .mask = 0x00, .path_mask = 0}, |
| 1742 | { .mask = 0x00, .path_mask = 0}, |
| 1743 | } |
| 1744 | }, |
| 1745 | { |
| 1746 | TIMPANI_A_CDC_DMIC_MUX, |
| 1747 | {0x0, 0x0, 0xF, 0xF0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 1748 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, |
| 1749 | TIMPANI_CDC_DMIC_MUX_M, |
| 1750 | TIMPANI_CDC_DMIC_MUX_POR, |
| 1751 | { |
| 1752 | { .mask = 0x0F, .path_mask = 0}, |
| 1753 | { .mask = 0xF0, .path_mask = 0}, |
| 1754 | { .mask = 0x00, .path_mask = 0}, |
| 1755 | { .mask = 0x00, .path_mask = 0}, |
| 1756 | { .mask = 0x00, .path_mask = 0}, |
| 1757 | } |
| 1758 | }, |
| 1759 | { |
| 1760 | TIMPANI_A_CDC_ARB_CLK_CTL, |
| 1761 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 1762 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x3, 0x0, 0xFC}, |
| 1763 | TIMPANI_CDC_ARB_CLK_CTL_M, |
| 1764 | TIMPANI_CDC_ARB_CLK_CTL_POR, |
| 1765 | { |
| 1766 | { .mask = 0x03, .path_mask = 0}, |
| 1767 | { .mask = 0xFC, .path_mask = 0}, |
| 1768 | { .mask = 0x00, .path_mask = 0}, |
| 1769 | { .mask = 0x00, .path_mask = 0}, |
| 1770 | { .mask = 0x00, .path_mask = 0}, |
| 1771 | } |
| 1772 | }, |
| 1773 | { |
| 1774 | TIMPANI_A_CDC_GCTL2, |
| 1775 | {0x0, 0xF, 0x0, 0xF0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 1776 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, |
| 1777 | TIMPANI_CDC_GCTL2_M, |
| 1778 | TIMPANI_CDC_GCTL2_POR, |
| 1779 | { |
| 1780 | { .mask = 0x0F, .path_mask = 0}, |
| 1781 | { .mask = 0xF0, .path_mask = 0}, |
| 1782 | { .mask = 0x00, .path_mask = 0}, |
| 1783 | { .mask = 0x00, .path_mask = 0}, |
| 1784 | { .mask = 0x00, .path_mask = 0}, |
| 1785 | } |
| 1786 | }, |
| 1787 | { |
| 1788 | TIMPANI_A_CDC_BYPASS_CTL2, |
| 1789 | {0x0, 0x0, 0x3F, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 1790 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xC0}, |
| 1791 | TIMPANI_CDC_BYPASS_CTL2_M, |
| 1792 | TIMPANI_CDC_BYPASS_CTL2_POR, |
| 1793 | { |
| 1794 | { .mask = 0x3F, .path_mask = 0}, |
| 1795 | { .mask = 0xC0, .path_mask = 0}, |
| 1796 | { .mask = 0x00, .path_mask = 0}, |
| 1797 | { .mask = 0x00, .path_mask = 0}, |
| 1798 | { .mask = 0x00, .path_mask = 0}, |
| 1799 | } |
| 1800 | }, |
| 1801 | { |
| 1802 | TIMPANI_A_CDC_BYPASS_CTL3, |
| 1803 | {0x0, 0x0, 0x0, 0x3F, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 1804 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xC0}, |
| 1805 | TIMPANI_CDC_BYPASS_CTL3_M, |
| 1806 | TIMPANI_CDC_BYPASS_CTL3_POR, |
| 1807 | { |
| 1808 | { .mask = 0x3F, .path_mask = 0}, |
| 1809 | { .mask = 0xC0, .path_mask = 0}, |
| 1810 | { .mask = 0x00, .path_mask = 0}, |
| 1811 | { .mask = 0x00, .path_mask = 0}, |
| 1812 | { .mask = 0x00, .path_mask = 0}, |
| 1813 | } |
| 1814 | }, |
| 1815 | { |
| 1816 | TIMPANI_A_CDC_BYPASS_CTL4, |
| 1817 | {0x0, 0xF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 1818 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xF0}, |
| 1819 | TIMPANI_CDC_BYPASS_CTL4_M, |
| 1820 | TIMPANI_CDC_BYPASS_CTL4_POR, |
| 1821 | { |
| 1822 | { .mask = 0x0F, .path_mask = 0}, |
| 1823 | { .mask = 0xF0, .path_mask = 0}, |
| 1824 | { .mask = 0x00, .path_mask = 0}, |
| 1825 | { .mask = 0x00, .path_mask = 0}, |
| 1826 | { .mask = 0x00, .path_mask = 0}, |
| 1827 | } |
| 1828 | }, |
| 1829 | { |
| 1830 | TIMPANI_A_CDC_RX2L_DCOFFSET, |
| 1831 | {0x0, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 1832 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, |
| 1833 | TIMPANI_CDC_RX2L_DCOFFSET_M, |
| 1834 | TIMPANI_CDC_RX2L_DCOFFSET_POR, |
| 1835 | { |
| 1836 | { .mask = 0xFF, .path_mask = 0}, |
| 1837 | { .mask = 0x00, .path_mask = 0}, |
| 1838 | { .mask = 0x00, .path_mask = 0}, |
| 1839 | { .mask = 0x00, .path_mask = 0}, |
| 1840 | { .mask = 0x00, .path_mask = 0}, |
| 1841 | } |
| 1842 | }, |
| 1843 | { |
| 1844 | TIMPANI_A_CDC_RX2R_DCOFFSET, |
| 1845 | {0x0, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 1846 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, |
| 1847 | TIMPANI_CDC_RX2R_DCOFFSET_M, |
| 1848 | TIMPANI_CDC_RX2R_DCOFFSET_POR, |
| 1849 | { |
| 1850 | { .mask = 0xFF, .path_mask = 0}, |
| 1851 | { .mask = 0x00, .path_mask = 0}, |
| 1852 | { .mask = 0x00, .path_mask = 0}, |
| 1853 | { .mask = 0x00, .path_mask = 0}, |
| 1854 | { .mask = 0x00, .path_mask = 0}, |
| 1855 | } |
| 1856 | }, |
| 1857 | { |
| 1858 | TIMPANI_A_CDC_RX_MIX_CTL, |
| 1859 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 1860 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x3, 0x0, 0xFC}, |
| 1861 | TIMPANI_CDC_RX_MIX_CTL_M, |
| 1862 | TIMPANI_CDC_RX_MIX_CTL_POR, |
| 1863 | { |
| 1864 | { .mask = 0x03, .path_mask = 0}, |
| 1865 | { .mask = 0xFC, .path_mask = 0}, |
| 1866 | { .mask = 0x00, .path_mask = 0}, |
| 1867 | { .mask = 0x00, .path_mask = 0}, |
| 1868 | { .mask = 0x00, .path_mask = 0}, |
| 1869 | } |
| 1870 | }, |
| 1871 | { |
| 1872 | TIMPANI_A_CDC_SPARE_CTL, |
| 1873 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 1874 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1, 0xFE}, |
| 1875 | TIMPANI_CDC_SPARE_CTL_M, |
| 1876 | TIMPANI_CDC_SPARE_CTL_POR, |
| 1877 | { |
| 1878 | { .mask = 0x01, .path_mask = 0}, |
| 1879 | { .mask = 0xFE, .path_mask = 0}, |
| 1880 | { .mask = 0x00, .path_mask = 0}, |
| 1881 | { .mask = 0x00, .path_mask = 0}, |
| 1882 | { .mask = 0x00, .path_mask = 0}, |
| 1883 | } |
| 1884 | }, |
| 1885 | { |
| 1886 | TIMPANI_A_CDC_TESTMODE2, |
| 1887 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 1888 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1F, 0xE0}, |
| 1889 | TIMPANI_CDC_TESTMODE2_M, |
| 1890 | TIMPANI_CDC_TESTMODE2_POR, |
| 1891 | { |
| 1892 | { .mask = 0x1F, .path_mask = 0}, |
| 1893 | { .mask = 0xE0, .path_mask = 0}, |
| 1894 | { .mask = 0x00, .path_mask = 0}, |
| 1895 | { .mask = 0x00, .path_mask = 0}, |
| 1896 | { .mask = 0x00, .path_mask = 0}, |
| 1897 | } |
| 1898 | }, |
| 1899 | { |
| 1900 | TIMPANI_A_CDC_PDM_OE, |
| 1901 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 1902 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xFF, 0x0}, |
| 1903 | TIMPANI_CDC_PDM_OE_M, |
| 1904 | TIMPANI_CDC_PDM_OE_POR, |
| 1905 | { |
| 1906 | { .mask = 0xFF, .path_mask = 0}, |
| 1907 | { .mask = 0x00, .path_mask = 0}, |
| 1908 | { .mask = 0x00, .path_mask = 0}, |
| 1909 | { .mask = 0x00, .path_mask = 0}, |
| 1910 | { .mask = 0x00, .path_mask = 0}, |
| 1911 | } |
| 1912 | }, |
| 1913 | { |
| 1914 | TIMPANI_A_CDC_TX1R_STG, |
| 1915 | {0x0, 0x0, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 1916 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, |
| 1917 | TIMPANI_CDC_TX1R_STG_M, |
| 1918 | TIMPANI_CDC_TX1R_STG_POR, |
| 1919 | { |
| 1920 | { .mask = 0xFF, .path_mask = 0}, |
| 1921 | { .mask = 0x00, .path_mask = 0}, |
| 1922 | { .mask = 0x00, .path_mask = 0}, |
| 1923 | { .mask = 0x00, .path_mask = 0}, |
| 1924 | { .mask = 0x00, .path_mask = 0}, |
| 1925 | } |
| 1926 | }, |
| 1927 | { |
| 1928 | TIMPANI_A_CDC_TX2L_STG, |
| 1929 | {0x0, 0x0, 0x0, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 1930 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, |
| 1931 | TIMPANI_CDC_TX2L_STG_M, |
| 1932 | TIMPANI_CDC_TX2L_STG_POR, |
| 1933 | { |
| 1934 | { .mask = 0xFF, .path_mask = 0}, |
| 1935 | { .mask = 0x00, .path_mask = 0}, |
| 1936 | { .mask = 0x00, .path_mask = 0}, |
| 1937 | { .mask = 0x00, .path_mask = 0}, |
| 1938 | { .mask = 0x00, .path_mask = 0}, |
| 1939 | } |
| 1940 | }, |
| 1941 | { |
| 1942 | TIMPANI_A_CDC_TX2R_STG, |
| 1943 | {0x0, 0x0, 0x0, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 1944 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, |
| 1945 | TIMPANI_CDC_TX2R_STG_M, |
| 1946 | TIMPANI_CDC_TX2R_STG_POR, |
| 1947 | { |
| 1948 | { .mask = 0xFF, .path_mask = 0}, |
| 1949 | { .mask = 0x00, .path_mask = 0}, |
| 1950 | { .mask = 0x00, .path_mask = 0}, |
| 1951 | { .mask = 0x00, .path_mask = 0}, |
| 1952 | { .mask = 0x00, .path_mask = 0}, |
| 1953 | } |
| 1954 | }, |
| 1955 | { |
| 1956 | TIMPANI_A_CDC_ARB_BYPASS_CTL, |
| 1957 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 1958 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xFF}, |
| 1959 | TIMPANI_CDC_ARB_BYPASS_CTL_M, |
| 1960 | TIMPANI_CDC_ARB_BYPASS_CTL_POR, |
| 1961 | { |
| 1962 | { .mask = 0xFF, .path_mask = 0}, |
| 1963 | { .mask = 0x00, .path_mask = 0}, |
| 1964 | { .mask = 0x00, .path_mask = 0}, |
| 1965 | { .mask = 0x00, .path_mask = 0}, |
| 1966 | { .mask = 0x00, .path_mask = 0}, |
| 1967 | } |
| 1968 | }, |
| 1969 | { |
| 1970 | TIMPANI_A_CDC_ANC1_CTL1, |
| 1971 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 1972 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x1F, 0x0, 0xE0}, |
| 1973 | TIMPANI_CDC_ANC1_CTL1_M, |
| 1974 | TIMPANI_CDC_ANC1_CTL1_POR, |
| 1975 | { |
| 1976 | { .mask = 0x1F, .path_mask = 0}, |
| 1977 | { .mask = 0xE0, .path_mask = 0}, |
| 1978 | { .mask = 0x00, .path_mask = 0}, |
| 1979 | { .mask = 0x00, .path_mask = 0}, |
| 1980 | { .mask = 0x00, .path_mask = 0}, |
| 1981 | } |
| 1982 | }, |
| 1983 | { |
| 1984 | TIMPANI_A_CDC_ANC1_CTL2, |
| 1985 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 1986 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x3F, 0x0, 0xC0}, |
| 1987 | TIMPANI_CDC_ANC1_CTL2_M, |
| 1988 | TIMPANI_CDC_ANC1_CTL2_POR, |
| 1989 | { |
| 1990 | { .mask = 0x3F, .path_mask = 0}, |
| 1991 | { .mask = 0xC0, .path_mask = 0}, |
| 1992 | { .mask = 0x00, .path_mask = 0}, |
| 1993 | { .mask = 0x00, .path_mask = 0}, |
| 1994 | { .mask = 0x00, .path_mask = 0}, |
| 1995 | } |
| 1996 | }, |
| 1997 | { |
| 1998 | TIMPANI_A_CDC_ANC1_FF_FB_SHIFT, |
| 1999 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 2000 | 0x0, 0x0, 0x0, 0x0, 0x0, 0xFF, 0x0, 0x0}, |
| 2001 | TIMPANI_CDC_ANC1_FF_FB_SHIFT_M, |
| 2002 | TIMPANI_CDC_ANC1_FF_FB_SHIFT_POR, |
| 2003 | { |
| 2004 | { .mask = 0xFF, .path_mask = 0}, |
| 2005 | { .mask = 0x00, .path_mask = 0}, |
| 2006 | { .mask = 0x00, .path_mask = 0}, |
| 2007 | { .mask = 0x00, .path_mask = 0}, |
| 2008 | { .mask = 0x00, .path_mask = 0}, |
| 2009 | } |
| 2010 | }, |
| 2011 | { |
| 2012 | TIMPANI_A_CDC_ANC1_RX_NS, |
| 2013 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 2014 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x7, 0x0, 0xF8}, |
| 2015 | TIMPANI_CDC_ANC1_RX_NS_M, |
| 2016 | TIMPANI_CDC_ANC1_RX_NS_POR, |
| 2017 | { |
| 2018 | { .mask = 0x07, .path_mask = 0}, |
| 2019 | { .mask = 0xF8, .path_mask = 0}, |
| 2020 | { .mask = 0x00, .path_mask = 0}, |
| 2021 | { .mask = 0x00, .path_mask = 0}, |
| 2022 | { .mask = 0x00, .path_mask = 0}, |
| 2023 | } |
| 2024 | }, |
| 2025 | { |
| 2026 | TIMPANI_A_CDC_ANC1_SPARE, |
| 2027 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 2028 | 0x0, 0x0, 0x0, 0x0, 0x0, 0xFF, 0x0, 0x0}, |
| 2029 | TIMPANI_CDC_ANC1_SPARE_M, |
| 2030 | TIMPANI_CDC_ANC1_SPARE_POR, |
| 2031 | { |
| 2032 | { .mask = 0xFF, .path_mask = 0}, |
| 2033 | { .mask = 0x00, .path_mask = 0}, |
| 2034 | { .mask = 0x00, .path_mask = 0}, |
| 2035 | { .mask = 0x00, .path_mask = 0}, |
| 2036 | { .mask = 0x00, .path_mask = 0}, |
| 2037 | } |
| 2038 | }, |
| 2039 | { |
| 2040 | TIMPANI_A_CDC_ANC1_IIR_COEFF_PTR, |
| 2041 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 2042 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x1F, 0x0, 0xE0}, |
| 2043 | TIMPANI_CDC_ANC1_IIR_COEFF_PTR_M, |
| 2044 | TIMPANI_CDC_ANC1_IIR_COEFF_PTR_POR, |
| 2045 | { |
| 2046 | { .mask = 0x1F, .path_mask = 0}, |
| 2047 | { .mask = 0xE0, .path_mask = 0}, |
| 2048 | { .mask = 0x00, .path_mask = 0}, |
| 2049 | { .mask = 0x00, .path_mask = 0}, |
| 2050 | { .mask = 0x00, .path_mask = 0}, |
| 2051 | } |
| 2052 | }, |
| 2053 | { |
| 2054 | TIMPANI_A_CDC_ANC1_IIR_COEFF_MSB, |
| 2055 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 2056 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x1, 0x0, 0xFE}, |
| 2057 | TIMPANI_CDC_ANC1_IIR_COEFF_MSB_M, |
| 2058 | TIMPANI_CDC_ANC1_IIR_COEFF_MSB_POR, |
| 2059 | { |
| 2060 | { .mask = 0x01, .path_mask = 0}, |
| 2061 | { .mask = 0xFE, .path_mask = 0}, |
| 2062 | { .mask = 0x00, .path_mask = 0}, |
| 2063 | { .mask = 0x00, .path_mask = 0}, |
| 2064 | { .mask = 0x00, .path_mask = 0}, |
| 2065 | } |
| 2066 | }, |
| 2067 | { |
| 2068 | TIMPANI_A_CDC_ANC1_IIR_COEFF_LSB, |
| 2069 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 2070 | 0x0, 0x0, 0x0, 0x0, 0x0, 0xFF, 0x0, 0x0}, |
| 2071 | TIMPANI_CDC_ANC1_IIR_COEFF_LSB_M, |
| 2072 | TIMPANI_CDC_ANC1_IIR_COEFF_LSB_POR, |
| 2073 | { |
| 2074 | { .mask = 0xFF, .path_mask = 0}, |
| 2075 | { .mask = 0x00, .path_mask = 0}, |
| 2076 | { .mask = 0x00, .path_mask = 0}, |
| 2077 | { .mask = 0x00, .path_mask = 0}, |
| 2078 | { .mask = 0x00, .path_mask = 0}, |
| 2079 | } |
| 2080 | }, |
| 2081 | { |
| 2082 | TIMPANI_A_CDC_ANC1_IIR_COEFF_CTL, |
| 2083 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 2084 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x3, 0x0, 0xFC}, |
| 2085 | TIMPANI_CDC_ANC1_IIR_COEFF_CTL_M, |
| 2086 | TIMPANI_CDC_ANC1_IIR_COEFF_CTL_POR, |
| 2087 | { |
| 2088 | { .mask = 0x03, .path_mask = 0}, |
| 2089 | { .mask = 0xFC, .path_mask = 0}, |
| 2090 | { .mask = 0x00, .path_mask = 0}, |
| 2091 | { .mask = 0x00, .path_mask = 0}, |
| 2092 | { .mask = 0x00, .path_mask = 0}, |
| 2093 | } |
| 2094 | }, |
| 2095 | { |
| 2096 | TIMPANI_A_CDC_ANC1_LPF_COEFF_PTR, |
| 2097 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 2098 | 0x0, 0x0, 0x0, 0x0, 0x0, 0xF, 0x0, 0xF0}, |
| 2099 | TIMPANI_CDC_ANC1_LPF_COEFF_PTR_M, |
| 2100 | TIMPANI_CDC_ANC1_LPF_COEFF_PTR_POR, |
| 2101 | { |
| 2102 | { .mask = 0x0F, .path_mask = 0}, |
| 2103 | { .mask = 0xF0, .path_mask = 0}, |
| 2104 | { .mask = 0x00, .path_mask = 0}, |
| 2105 | { .mask = 0x00, .path_mask = 0}, |
| 2106 | { .mask = 0x00, .path_mask = 0}, |
| 2107 | } |
| 2108 | }, |
| 2109 | { |
| 2110 | TIMPANI_A_CDC_ANC1_LPF_COEFF_MSB, |
| 2111 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 2112 | 0x0, 0x0, 0x0, 0x0, 0x0, 0xF, 0x0, 0xF0}, |
| 2113 | TIMPANI_CDC_ANC1_LPF_COEFF_MSB_M, |
| 2114 | TIMPANI_CDC_ANC1_LPF_COEFF_MSB_POR, |
| 2115 | { |
| 2116 | { .mask = 0x0F, .path_mask = 0}, |
| 2117 | { .mask = 0xF0, .path_mask = 0}, |
| 2118 | { .mask = 0x00, .path_mask = 0}, |
| 2119 | { .mask = 0x00, .path_mask = 0}, |
| 2120 | { .mask = 0x00, .path_mask = 0}, |
| 2121 | } |
| 2122 | }, |
| 2123 | { |
| 2124 | TIMPANI_A_CDC_ANC1_LPF_COEFF_LSB, |
| 2125 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 2126 | 0x0, 0x0, 0x0, 0x0, 0x0, 0xFF, 0x0, 0x0}, |
| 2127 | TIMPANI_CDC_ANC1_LPF_COEFF_LSB_M, |
| 2128 | TIMPANI_CDC_ANC1_LPF_COEFF_LSB_POR, |
| 2129 | { |
| 2130 | { .mask = 0xFF, .path_mask = 0}, |
| 2131 | { .mask = 0x00, .path_mask = 0}, |
| 2132 | { .mask = 0x00, .path_mask = 0}, |
| 2133 | { .mask = 0x00, .path_mask = 0}, |
| 2134 | { .mask = 0x00, .path_mask = 0}, |
| 2135 | } |
| 2136 | }, |
| 2137 | { |
| 2138 | TIMPANI_A_CDC_ANC1_SCALE_PTR, |
| 2139 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 2140 | 0x0, 0x0, 0x0, 0x0, 0x0, 0xFF, 0x0, 0x0}, |
| 2141 | TIMPANI_CDC_ANC1_SCALE_PTR_M, |
| 2142 | TIMPANI_CDC_ANC1_SCALE_PTR_POR, |
| 2143 | { |
| 2144 | { .mask = 0xFF, .path_mask = 0}, |
| 2145 | { .mask = 0x00, .path_mask = 0}, |
| 2146 | { .mask = 0x00, .path_mask = 0}, |
| 2147 | { .mask = 0x00, .path_mask = 0}, |
| 2148 | { .mask = 0x00, .path_mask = 0}, |
| 2149 | } |
| 2150 | }, |
| 2151 | { |
| 2152 | TIMPANI_A_CDC_ANC1_SCALE, |
| 2153 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 2154 | 0x0, 0x0, 0x0, 0x0, 0x0, 0xFF, 0x0, 0x0}, |
| 2155 | TIMPANI_CDC_ANC1_SCALE_M, |
| 2156 | TIMPANI_CDC_ANC1_SCALE_POR, |
| 2157 | { |
| 2158 | { .mask = 0xFF, .path_mask = 0}, |
| 2159 | { .mask = 0x00, .path_mask = 0}, |
| 2160 | { .mask = 0x00, .path_mask = 0}, |
| 2161 | { .mask = 0x00, .path_mask = 0}, |
| 2162 | { .mask = 0x00, .path_mask = 0}, |
| 2163 | } |
| 2164 | }, |
| 2165 | { |
| 2166 | TIMPANI_A_CDC_ANC1_DEBUG, |
| 2167 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 2168 | 0x0, 0x0, 0x0, 0x0, 0x0, 0xF, 0x0, 0xF0}, |
| 2169 | TIMPANI_CDC_ANC1_DEBUG_M, |
| 2170 | TIMPANI_CDC_ANC1_DEBUG_POR, |
| 2171 | { |
| 2172 | { .mask = 0x0F, .path_mask = 0}, |
| 2173 | { .mask = 0xF0, .path_mask = 0}, |
| 2174 | { .mask = 0x00, .path_mask = 0}, |
| 2175 | { .mask = 0x00, .path_mask = 0}, |
| 2176 | { .mask = 0x00, .path_mask = 0}, |
| 2177 | } |
| 2178 | }, |
| 2179 | { |
| 2180 | TIMPANI_A_CDC_ANC2_CTL1, |
| 2181 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 2182 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x1F, 0x0, 0xE0}, |
| 2183 | TIMPANI_CDC_ANC2_CTL1_M, |
| 2184 | TIMPANI_CDC_ANC2_CTL1_POR, |
| 2185 | { |
| 2186 | { .mask = 0x1F, .path_mask = 0}, |
| 2187 | { .mask = 0xE0, .path_mask = 0}, |
| 2188 | { .mask = 0x00, .path_mask = 0}, |
| 2189 | { .mask = 0x00, .path_mask = 0}, |
| 2190 | { .mask = 0x00, .path_mask = 0}, |
| 2191 | } |
| 2192 | }, |
| 2193 | { |
| 2194 | TIMPANI_A_CDC_ANC2_CTL2, |
| 2195 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 2196 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x3F, 0x0, 0xC0}, |
| 2197 | TIMPANI_CDC_ANC2_CTL2_M, |
| 2198 | TIMPANI_CDC_ANC2_CTL2_POR, |
| 2199 | { |
| 2200 | { .mask = 0x3F, .path_mask = 0}, |
| 2201 | { .mask = 0xC0, .path_mask = 0}, |
| 2202 | { .mask = 0x00, .path_mask = 0}, |
| 2203 | { .mask = 0x00, .path_mask = 0}, |
| 2204 | { .mask = 0x00, .path_mask = 0}, |
| 2205 | } |
| 2206 | }, |
| 2207 | { |
| 2208 | TIMPANI_A_CDC_ANC2_FF_FB_SHIFT, |
| 2209 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 2210 | 0x0, 0x0, 0x0, 0x0, 0x0, 0xFF, 0x0, 0x0}, |
| 2211 | TIMPANI_CDC_ANC2_FF_FB_SHIFT_M, |
| 2212 | TIMPANI_CDC_ANC2_FF_FB_SHIFT_POR, |
| 2213 | { |
| 2214 | { .mask = 0xFF, .path_mask = 0}, |
| 2215 | { .mask = 0x00, .path_mask = 0}, |
| 2216 | { .mask = 0x00, .path_mask = 0}, |
| 2217 | { .mask = 0x00, .path_mask = 0}, |
| 2218 | { .mask = 0x00, .path_mask = 0}, |
| 2219 | } |
| 2220 | }, |
| 2221 | { |
| 2222 | TIMPANI_A_CDC_ANC2_RX_NS, |
| 2223 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 2224 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x7, 0x0, 0xF8}, |
| 2225 | TIMPANI_CDC_ANC2_RX_NS_M, |
| 2226 | TIMPANI_CDC_ANC2_RX_NS_POR, |
| 2227 | { |
| 2228 | { .mask = 0x07, .path_mask = 0}, |
| 2229 | { .mask = 0xF8, .path_mask = 0}, |
| 2230 | { .mask = 0x00, .path_mask = 0}, |
| 2231 | { .mask = 0x00, .path_mask = 0}, |
| 2232 | { .mask = 0x00, .path_mask = 0}, |
| 2233 | } |
| 2234 | }, |
| 2235 | { |
| 2236 | TIMPANI_A_CDC_ANC2_SPARE, |
| 2237 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 2238 | 0x0, 0x0, 0x0, 0x0, 0x0, 0xFF, 0x0, 0x0}, |
| 2239 | TIMPANI_CDC_ANC2_SPARE_M, |
| 2240 | TIMPANI_CDC_ANC2_SPARE_POR, |
| 2241 | { |
| 2242 | { .mask = 0xFF, .path_mask = 0}, |
| 2243 | { .mask = 0x00, .path_mask = 0}, |
| 2244 | { .mask = 0x00, .path_mask = 0}, |
| 2245 | { .mask = 0x00, .path_mask = 0}, |
| 2246 | { .mask = 0x00, .path_mask = 0}, |
| 2247 | } |
| 2248 | }, |
| 2249 | { |
| 2250 | TIMPANI_A_CDC_ANC2_IIR_COEFF_PTR, |
| 2251 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 2252 | 0x0, 0x0, 0x0, 0x0, 0x0, 0xF, 0x0, 0xF0}, |
| 2253 | TIMPANI_CDC_ANC2_IIR_COEFF_PTR_M, |
| 2254 | TIMPANI_CDC_ANC2_IIR_COEFF_PTR_POR, |
| 2255 | { |
| 2256 | { .mask = 0x0F, .path_mask = 0}, |
| 2257 | { .mask = 0xF0, .path_mask = 0}, |
| 2258 | { .mask = 0x00, .path_mask = 0}, |
| 2259 | { .mask = 0x00, .path_mask = 0}, |
| 2260 | { .mask = 0x00, .path_mask = 0}, |
| 2261 | } |
| 2262 | }, |
| 2263 | { |
| 2264 | TIMPANI_A_CDC_ANC2_IIR_COEFF_MSB, |
| 2265 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 2266 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x1, 0x0, 0xFE}, |
| 2267 | TIMPANI_CDC_ANC2_IIR_COEFF_MSB_M, |
| 2268 | TIMPANI_CDC_ANC2_IIR_COEFF_MSB_POR, |
| 2269 | { |
| 2270 | { .mask = 0x01, .path_mask = 0}, |
| 2271 | { .mask = 0xFE, .path_mask = 0}, |
| 2272 | { .mask = 0x00, .path_mask = 0}, |
| 2273 | { .mask = 0x00, .path_mask = 0}, |
| 2274 | { .mask = 0x00, .path_mask = 0}, |
| 2275 | } |
| 2276 | }, |
| 2277 | { |
| 2278 | TIMPANI_A_CDC_ANC2_IIR_COEFF_LSB, |
| 2279 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 2280 | 0x0, 0x0, 0x0, 0x0, 0x0, 0xFF, 0x0, 0x0}, |
| 2281 | TIMPANI_CDC_ANC2_IIR_COEFF_LSB_M, |
| 2282 | TIMPANI_CDC_ANC2_IIR_COEFF_LSB_POR, |
| 2283 | { |
| 2284 | { .mask = 0xFF, .path_mask = 0}, |
| 2285 | { .mask = 0x00, .path_mask = 0}, |
| 2286 | { .mask = 0x00, .path_mask = 0}, |
| 2287 | { .mask = 0x00, .path_mask = 0}, |
| 2288 | { .mask = 0x00, .path_mask = 0}, |
| 2289 | } |
| 2290 | }, |
| 2291 | { |
| 2292 | TIMPANI_A_CDC_ANC2_IIR_COEFF_CTL, |
| 2293 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 2294 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x3, 0x0, 0xFC}, |
| 2295 | TIMPANI_CDC_ANC2_IIR_COEFF_CTL_M, |
| 2296 | TIMPANI_CDC_ANC2_IIR_COEFF_CTL_POR, |
| 2297 | { |
| 2298 | { .mask = 0x03, .path_mask = 0}, |
| 2299 | { .mask = 0xFC, .path_mask = 0}, |
| 2300 | { .mask = 0x00, .path_mask = 0}, |
| 2301 | { .mask = 0x00, .path_mask = 0}, |
| 2302 | { .mask = 0x00, .path_mask = 0}, |
| 2303 | } |
| 2304 | }, |
| 2305 | { |
| 2306 | TIMPANI_A_CDC_ANC2_LPF_COEFF_PTR, |
| 2307 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 2308 | 0x0, 0x0, 0x0, 0x0, 0x0, 0xF, 0x0, 0xF0}, |
| 2309 | TIMPANI_CDC_ANC2_LPF_COEFF_PTR_M, |
| 2310 | TIMPANI_CDC_ANC2_LPF_COEFF_PTR_POR, |
| 2311 | { |
| 2312 | { .mask = 0x0F, .path_mask = 0}, |
| 2313 | { .mask = 0xF0, .path_mask = 0}, |
| 2314 | { .mask = 0x00, .path_mask = 0}, |
| 2315 | { .mask = 0x00, .path_mask = 0}, |
| 2316 | { .mask = 0x00, .path_mask = 0}, |
| 2317 | } |
| 2318 | }, |
| 2319 | { |
| 2320 | TIMPANI_A_CDC_ANC2_LPF_COEFF_MSB, |
| 2321 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 2322 | 0x0, 0x0, 0x0, 0x0, 0x0, 0xF, 0x0, 0xF0}, |
| 2323 | TIMPANI_CDC_ANC2_LPF_COEFF_MSB_M, |
| 2324 | TIMPANI_CDC_ANC2_LPF_COEFF_MSB_POR, |
| 2325 | { |
| 2326 | { .mask = 0x0F, .path_mask = 0}, |
| 2327 | { .mask = 0xF0, .path_mask = 0}, |
| 2328 | { .mask = 0x00, .path_mask = 0}, |
| 2329 | { .mask = 0x00, .path_mask = 0}, |
| 2330 | { .mask = 0x00, .path_mask = 0}, |
| 2331 | } |
| 2332 | }, |
| 2333 | { |
| 2334 | TIMPANI_A_CDC_ANC2_LPF_COEFF_LSB, |
| 2335 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 2336 | 0x0, 0x0, 0x0, 0x0, 0x0, 0xFF, 0x0, 0x0}, |
| 2337 | TIMPANI_CDC_ANC2_LPF_COEFF_LSB_M, |
| 2338 | TIMPANI_CDC_ANC2_LPF_COEFF_LSB_POR, |
| 2339 | { |
| 2340 | { .mask = 0xFF, .path_mask = 0}, |
| 2341 | { .mask = 0x00, .path_mask = 0}, |
| 2342 | { .mask = 0x00, .path_mask = 0}, |
| 2343 | { .mask = 0x00, .path_mask = 0}, |
| 2344 | { .mask = 0x00, .path_mask = 0}, |
| 2345 | } |
| 2346 | }, |
| 2347 | { |
| 2348 | TIMPANI_A_CDC_ANC2_SCALE_PTR, |
| 2349 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 2350 | 0x0, 0x0, 0x0, 0x0, 0x0, 0xFF, 0x0, 0x0}, |
| 2351 | TIMPANI_CDC_ANC2_SCALE_PTR_M, |
| 2352 | TIMPANI_CDC_ANC2_SCALE_PTR_POR, |
| 2353 | { |
| 2354 | { .mask = 0xFF, .path_mask = 0}, |
| 2355 | { .mask = 0x00, .path_mask = 0}, |
| 2356 | { .mask = 0x00, .path_mask = 0}, |
| 2357 | { .mask = 0x00, .path_mask = 0}, |
| 2358 | { .mask = 0x00, .path_mask = 0}, |
| 2359 | } |
| 2360 | }, |
| 2361 | { |
| 2362 | TIMPANI_A_CDC_ANC2_SCALE, |
| 2363 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 2364 | 0x0, 0x0, 0x0, 0x0, 0x0, 0xFF, 0x0, 0x0}, |
| 2365 | TIMPANI_CDC_ANC2_SCALE_M, |
| 2366 | TIMPANI_CDC_ANC2_SCALE_POR, |
| 2367 | { |
| 2368 | { .mask = 0xFF, .path_mask = 0}, |
| 2369 | { .mask = 0x00, .path_mask = 0}, |
| 2370 | { .mask = 0x00, .path_mask = 0}, |
| 2371 | { .mask = 0x00, .path_mask = 0}, |
| 2372 | { .mask = 0x00, .path_mask = 0}, |
| 2373 | } |
| 2374 | }, |
| 2375 | { |
| 2376 | TIMPANI_A_CDC_ANC2_DEBUG, |
| 2377 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 2378 | 0x0, 0x0, 0x0, 0x0, 0x0, 0xF, 0x0, 0xF0}, |
| 2379 | TIMPANI_CDC_ANC2_DEBUG_M, |
| 2380 | TIMPANI_CDC_ANC2_DEBUG_POR, |
| 2381 | { |
| 2382 | { .mask = 0x0F, .path_mask = 0}, |
| 2383 | { .mask = 0xF0, .path_mask = 0}, |
| 2384 | { .mask = 0x00, .path_mask = 0}, |
| 2385 | { .mask = 0x00, .path_mask = 0}, |
| 2386 | { .mask = 0x00, .path_mask = 0}, |
| 2387 | } |
| 2388 | }, |
| 2389 | { |
| 2390 | TIMPANI_A_CDC_LINE_L_AVOL, |
| 2391 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 2392 | 0xFC, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x3}, |
| 2393 | TIMPANI_CDC_LINE_L_AVOL_M, |
| 2394 | TIMPANI_CDC_LINE_L_AVOL_POR, |
| 2395 | { |
| 2396 | { .mask = 0xFC, .path_mask = 0}, |
| 2397 | { .mask = 0x03, .path_mask = 0}, |
| 2398 | { .mask = 0x00, .path_mask = 0}, |
| 2399 | { .mask = 0x00, .path_mask = 0}, |
| 2400 | { .mask = 0x00, .path_mask = 0}, |
| 2401 | } |
| 2402 | }, |
| 2403 | { |
| 2404 | TIMPANI_A_CDC_LINE_R_AVOL, |
| 2405 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 2406 | 0xFC, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x3}, |
| 2407 | TIMPANI_CDC_LINE_R_AVOL_M, |
| 2408 | TIMPANI_CDC_LINE_R_AVOL_POR, |
| 2409 | { |
| 2410 | { .mask = 0xFC, .path_mask = 0}, |
| 2411 | { .mask = 0x03, .path_mask = 0}, |
| 2412 | { .mask = 0x00, .path_mask = 0}, |
| 2413 | { .mask = 0x00, .path_mask = 0}, |
| 2414 | { .mask = 0x00, .path_mask = 0}, |
| 2415 | } |
| 2416 | }, |
| 2417 | { |
| 2418 | TIMPANI_A_CDC_HPH_L_AVOL, |
| 2419 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xFE, |
| 2420 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1}, |
| 2421 | TIMPANI_CDC_HPH_L_AVOL_M, |
| 2422 | TIMPANI_CDC_HPH_L_AVOL_POR, |
| 2423 | { |
| 2424 | { .mask = 0xFE, .path_mask = 0}, |
| 2425 | { .mask = 0x01, .path_mask = 0}, |
| 2426 | { .mask = 0x00, .path_mask = 0}, |
| 2427 | { .mask = 0x00, .path_mask = 0}, |
| 2428 | { .mask = 0x00, .path_mask = 0}, |
| 2429 | } |
| 2430 | }, |
| 2431 | { |
| 2432 | TIMPANI_A_CDC_HPH_R_AVOL, |
| 2433 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xFE, |
| 2434 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1}, |
| 2435 | TIMPANI_CDC_HPH_R_AVOL_M, |
| 2436 | TIMPANI_CDC_HPH_R_AVOL_POR, |
| 2437 | { |
| 2438 | { .mask = 0xFE, .path_mask = 0}, |
| 2439 | { .mask = 0x01, .path_mask = 0}, |
| 2440 | { .mask = 0x00, .path_mask = 0}, |
| 2441 | { .mask = 0x00, .path_mask = 0}, |
| 2442 | { .mask = 0x00, .path_mask = 0}, |
| 2443 | } |
| 2444 | }, |
| 2445 | { |
| 2446 | TIMPANI_A_CDC_COMP_CTL1, |
| 2447 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 2448 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x3F, 0x0, 0xC0}, |
| 2449 | TIMPANI_CDC_COMP_CTL1_M, |
| 2450 | TIMPANI_CDC_COMP_CTL1_POR, |
| 2451 | { |
| 2452 | { .mask = 0x3F, .path_mask = 0}, |
| 2453 | { .mask = 0xC0, .path_mask = 0}, |
| 2454 | { .mask = 0x00, .path_mask = 0}, |
| 2455 | { .mask = 0x00, .path_mask = 0}, |
| 2456 | { .mask = 0x00, .path_mask = 0}, |
| 2457 | } |
| 2458 | }, |
| 2459 | { |
| 2460 | TIMPANI_A_CDC_COMP_CTL2, |
| 2461 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 2462 | 0x0, 0x0, 0x0, 0x0, 0x0, 0xF, 0x0, 0xF0}, |
| 2463 | TIMPANI_CDC_COMP_CTL2_M, |
| 2464 | TIMPANI_CDC_COMP_CTL2_POR, |
| 2465 | { |
| 2466 | { .mask = 0x0F, .path_mask = 0}, |
| 2467 | { .mask = 0xF0, .path_mask = 0}, |
| 2468 | { .mask = 0x00, .path_mask = 0}, |
| 2469 | { .mask = 0x00, .path_mask = 0}, |
| 2470 | { .mask = 0x00, .path_mask = 0}, |
| 2471 | } |
| 2472 | }, |
| 2473 | { |
| 2474 | TIMPANI_A_CDC_COMP_PEAK_METER, |
| 2475 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 2476 | 0x0, 0x0, 0x0, 0x0, 0x0, 0xF, 0x0, 0xF0}, |
| 2477 | TIMPANI_CDC_COMP_PEAK_METER_M, |
| 2478 | TIMPANI_CDC_COMP_PEAK_METER_POR, |
| 2479 | { |
| 2480 | { .mask = 0x0F, .path_mask = 0}, |
| 2481 | { .mask = 0xF0, .path_mask = 0}, |
| 2482 | { .mask = 0x00, .path_mask = 0}, |
| 2483 | { .mask = 0x00, .path_mask = 0}, |
| 2484 | { .mask = 0x00, .path_mask = 0}, |
| 2485 | } |
| 2486 | }, |
| 2487 | { |
| 2488 | TIMPANI_A_CDC_COMP_LEVEL_METER_CTL1, |
| 2489 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 2490 | 0x0, 0x0, 0x0, 0x0, 0x0, 0xF, 0x0, 0xF0}, |
| 2491 | TIMPANI_CDC_COMP_LEVEL_METER_CTL1_M, |
| 2492 | TIMPANI_CDC_COMP_LEVEL_METER_CTL1_POR, |
| 2493 | { |
| 2494 | { .mask = 0x0F, .path_mask = 0}, |
| 2495 | { .mask = 0xF0, .path_mask = 0}, |
| 2496 | { .mask = 0x00, .path_mask = 0}, |
| 2497 | { .mask = 0x00, .path_mask = 0}, |
| 2498 | { .mask = 0x00, .path_mask = 0}, |
| 2499 | } |
| 2500 | }, |
| 2501 | { |
| 2502 | TIMPANI_A_CDC_COMP_LEVEL_METER_CTL2, |
| 2503 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 2504 | 0x0, 0x0, 0x0, 0x0, 0x0, 0xFF, 0x0, 0x0}, |
| 2505 | TIMPANI_CDC_COMP_LEVEL_METER_CTL2_M, |
| 2506 | TIMPANI_CDC_COMP_LEVEL_METER_CTL2_POR, |
| 2507 | { |
| 2508 | { .mask = 0xFF, .path_mask = 0}, |
| 2509 | { .mask = 0x00, .path_mask = 0}, |
| 2510 | { .mask = 0x00, .path_mask = 0}, |
| 2511 | { .mask = 0x00, .path_mask = 0}, |
| 2512 | { .mask = 0x00, .path_mask = 0}, |
| 2513 | } |
| 2514 | }, |
| 2515 | { |
| 2516 | TIMPANI_A_CDC_COMP_ZONE_SELECT, |
| 2517 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 2518 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x7F, 0x0, 0x80}, |
| 2519 | TIMPANI_CDC_COMP_ZONE_SELECT_M, |
| 2520 | TIMPANI_CDC_COMP_ZONE_SELECT_POR, |
| 2521 | { |
| 2522 | { .mask = 0x7F, .path_mask = 0}, |
| 2523 | { .mask = 0x80, .path_mask = 0}, |
| 2524 | { .mask = 0x00, .path_mask = 0}, |
| 2525 | { .mask = 0x00, .path_mask = 0}, |
| 2526 | { .mask = 0x00, .path_mask = 0}, |
| 2527 | } |
| 2528 | }, |
| 2529 | { |
| 2530 | TIMPANI_A_CDC_COMP_ZC_MSB, |
| 2531 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 2532 | 0x0, 0x0, 0x0, 0x0, 0x0, 0xFF, 0x0, 0x0}, |
| 2533 | TIMPANI_CDC_COMP_ZC_MSB_M, |
| 2534 | TIMPANI_CDC_COMP_ZC_MSB_POR, |
| 2535 | { |
| 2536 | { .mask = 0xFF, .path_mask = 0}, |
| 2537 | { .mask = 0x00, .path_mask = 0}, |
| 2538 | { .mask = 0x00, .path_mask = 0}, |
| 2539 | { .mask = 0x00, .path_mask = 0}, |
| 2540 | { .mask = 0x00, .path_mask = 0}, |
| 2541 | } |
| 2542 | }, |
| 2543 | { |
| 2544 | TIMPANI_A_CDC_COMP_ZC_LSB, |
| 2545 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 2546 | 0x0, 0x0, 0x0, 0x0, 0x0, 0xFF, 0x0, 0x0}, |
| 2547 | TIMPANI_CDC_COMP_ZC_LSB_M, |
| 2548 | TIMPANI_CDC_COMP_ZC_LSB_POR, |
| 2549 | { |
| 2550 | { .mask = 0xFF, .path_mask = 0}, |
| 2551 | { .mask = 0x00, .path_mask = 0}, |
| 2552 | { .mask = 0x00, .path_mask = 0}, |
| 2553 | { .mask = 0x00, .path_mask = 0}, |
| 2554 | { .mask = 0x00, .path_mask = 0}, |
| 2555 | } |
| 2556 | }, |
| 2557 | { |
| 2558 | TIMPANI_A_CDC_COMP_SHUT_DOWN, |
| 2559 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 2560 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xFF}, |
| 2561 | TIMPANI_CDC_COMP_SHUT_DOWN_M, |
| 2562 | TIMPANI_CDC_COMP_SHUT_DOWN_POR, |
| 2563 | { |
| 2564 | { .mask = 0xFF, .path_mask = 0}, |
| 2565 | { .mask = 0x00, .path_mask = 0}, |
| 2566 | { .mask = 0x00, .path_mask = 0}, |
| 2567 | { .mask = 0x00, .path_mask = 0}, |
| 2568 | { .mask = 0x00, .path_mask = 0}, |
| 2569 | } |
| 2570 | }, |
| 2571 | { |
| 2572 | TIMPANI_A_CDC_COMP_SHUT_DOWN_STATUS, |
| 2573 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 2574 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xFF}, |
| 2575 | TIMPANI_CDC_COMP_SHUT_DOWN_STATUS_M, |
| 2576 | TIMPANI_CDC_COMP_SHUT_DOWN_STATUS_POR, |
| 2577 | { |
| 2578 | { .mask = 0xFF, .path_mask = 0}, |
| 2579 | { .mask = 0x00, .path_mask = 0}, |
| 2580 | { .mask = 0x00, .path_mask = 0}, |
| 2581 | { .mask = 0x00, .path_mask = 0}, |
| 2582 | { .mask = 0x00, .path_mask = 0}, |
| 2583 | } |
| 2584 | }, |
| 2585 | { |
| 2586 | TIMPANI_A_CDC_COMP_HALT, |
| 2587 | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, |
| 2588 | 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xFF}, |
| 2589 | TIMPANI_CDC_COMP_HALT_M, |
| 2590 | TIMPANI_CDC_COMP_HALT_POR, |
| 2591 | { |
| 2592 | { .mask = 0xFF, .path_mask = 0}, |
| 2593 | { .mask = 0x00, .path_mask = 0}, |
| 2594 | { .mask = 0x00, .path_mask = 0}, |
| 2595 | { .mask = 0x00, .path_mask = 0}, |
| 2596 | { .mask = 0x00, .path_mask = 0}, |
| 2597 | } |
| 2598 | } |
| 2599 | }; |
| 2600 | |
| 2601 | struct reg_acc_blk_cfg timpani_blkcfg[RA_BLOCK_NUM] = { |
| 2602 | { |
| 2603 | .valid_owners = {RA_OWNER_NONE, RA_OWNER_PATH_RX1, |
| 2604 | 0, 0, 0, 0, RA_OWNER_DRV} |
| 2605 | }, |
| 2606 | /* RA_BLOCK_RX1 */ |
| 2607 | { |
| 2608 | .valid_owners = {RA_OWNER_NONE, 0, RA_OWNER_PATH_RX2, |
| 2609 | 0, 0, 0, RA_OWNER_DRV} |
| 2610 | }, |
| 2611 | /* RA_BLOCK_RX2 */ |
| 2612 | { |
| 2613 | .valid_owners = {RA_OWNER_NONE, 0, 0, RA_OWNER_PATH_TX1, |
| 2614 | 0, 0, RA_OWNER_DRV} |
| 2615 | }, |
| 2616 | /* RA_BLOCK_TX1 */ |
| 2617 | { |
| 2618 | .valid_owners = {RA_OWNER_NONE, 0, 0, 0, RA_OWNER_PATH_TX2, |
| 2619 | 0, RA_OWNER_DRV} |
| 2620 | }, |
| 2621 | /* RA_BLOCK_TX2 */ |
| 2622 | { |
| 2623 | .valid_owners = {RA_OWNER_NONE, 0, 0, 0, 0, |
| 2624 | RA_OWNER_PATH_LB, RA_OWNER_DRV} |
| 2625 | }, |
| 2626 | /* RA_BLOCK_LB */ |
| 2627 | { |
| 2628 | .valid_owners = {RA_OWNER_NONE, RA_OWNER_PATH_RX1, |
| 2629 | RA_OWNER_PATH_RX2, 0, 0, RA_OWNER_PATH_LB, RA_OWNER_DRV} |
| 2630 | }, |
| 2631 | /* RA_BLOCK_SHARED_RX_LB */ |
| 2632 | { |
| 2633 | .valid_owners = {RA_OWNER_NONE, 0, 0, RA_OWNER_PATH_TX1, |
| 2634 | RA_OWNER_PATH_TX2, 0, RA_OWNER_DRV} |
| 2635 | }, |
| 2636 | /* RA_BLOCK_SHARED_TX */ |
| 2637 | { |
| 2638 | .valid_owners = {RA_OWNER_NONE, 0, 0, RA_OWNER_PATH_TX1, |
| 2639 | RA_OWNER_PATH_TX2, 0, RA_OWNER_DRV} |
| 2640 | }, |
| 2641 | /* RA_BLOCK_TXFE1 */ |
| 2642 | { |
| 2643 | .valid_owners = {RA_OWNER_NONE, 0, 0, RA_OWNER_PATH_TX1, |
| 2644 | RA_OWNER_PATH_TX2, 0, RA_OWNER_DRV} |
| 2645 | }, |
| 2646 | /* RA_BLOCK_TXFE2 */ |
| 2647 | { |
| 2648 | .valid_owners = {RA_OWNER_NONE, RA_OWNER_PATH_RX1, |
| 2649 | RA_OWNER_PATH_RX2, 0, 0, RA_OWNER_PATH_LB, RA_OWNER_DRV} |
| 2650 | }, |
| 2651 | /* RA_BLOCK_PA_COMMON */ |
| 2652 | { |
| 2653 | .valid_owners = {RA_OWNER_NONE, RA_OWNER_PATH_RX1, |
| 2654 | RA_OWNER_PATH_RX2, 0, 0, RA_OWNER_PATH_LB, RA_OWNER_DRV} |
| 2655 | }, |
| 2656 | /* RA_BLOCK_PA_EAR */ |
| 2657 | { |
| 2658 | .valid_owners = {RA_OWNER_NONE, RA_OWNER_PATH_RX1, |
| 2659 | RA_OWNER_PATH_RX2, 0, 0, RA_OWNER_PATH_LB, RA_OWNER_DRV} |
| 2660 | }, |
| 2661 | /* RA_BLOCK_PA_HPH */ |
| 2662 | { |
| 2663 | .valid_owners = {RA_OWNER_NONE, RA_OWNER_PATH_RX1, |
| 2664 | RA_OWNER_PATH_RX2, 0, 0, RA_OWNER_PATH_LB, RA_OWNER_DRV} |
| 2665 | }, |
| 2666 | /* RA_BLOCK_PA_LINE */ |
| 2667 | { |
| 2668 | .valid_owners = {RA_OWNER_NONE, RA_OWNER_PATH_RX1, |
| 2669 | RA_OWNER_PATH_RX2, 0, 0, RA_OWNER_PATH_LB, RA_OWNER_DRV} |
| 2670 | }, |
| 2671 | /* RA_BLOCK_PA_AUX */ |
| 2672 | { |
| 2673 | .valid_owners = {RA_OWNER_NONE, 0, 0, RA_OWNER_PATH_TX1, |
| 2674 | RA_OWNER_PATH_TX2, 0, RA_OWNER_DRV} |
| 2675 | }, |
| 2676 | /* RA_BLOCK_ADC */ |
| 2677 | { |
| 2678 | .valid_owners = {RA_OWNER_NONE, 0, 0, RA_OWNER_PATH_TX1, |
| 2679 | RA_OWNER_PATH_TX2, 0, RA_OWNER_DRV} |
| 2680 | }, |
| 2681 | /* RA_BLOCK_DMIC */ |
| 2682 | { |
| 2683 | .valid_owners = {RA_OWNER_NONE, 0, 0, RA_OWNER_PATH_TX1, |
| 2684 | RA_OWNER_PATH_TX2, 0, RA_OWNER_DRV} |
| 2685 | }, |
| 2686 | /* RA_BLOCK_TX_I2S */ |
| 2687 | { |
| 2688 | .valid_owners = {RA_OWNER_NONE, 0, 0, 0, 0, 0, RA_OWNER_DRV} |
| 2689 | }, |
| 2690 | /*RA_BLOCK_DRV */ |
| 2691 | { |
| 2692 | .valid_owners = {RA_OWNER_NONE, 0, 0, 0, 0, 0, RA_OWNER_DRV} |
| 2693 | }, |
| 2694 | /* RA_BLOCK_TEST */ |
| 2695 | { |
| 2696 | .valid_owners = {RA_OWNER_NONE, 0, 0, 0, 0, 0, RA_OWNER_DRV} |
| 2697 | }, |
| 2698 | /* RA_BLOCK_RESERVED */ |
| 2699 | }; |
| 2700 | |
| 2701 | struct adie_codec_state { |
| 2702 | struct adie_codec_path path[ADIE_CODEC_MAX]; |
| 2703 | u32 ref_cnt; |
| 2704 | struct marimba *pdrv_ptr; |
| 2705 | struct marimba_codec_platform_data *codec_pdata; |
| 2706 | struct mutex lock; |
| 2707 | }; |
| 2708 | |
| 2709 | static struct adie_codec_state adie_codec; |
| 2710 | |
| 2711 | /* A cacheable register is one that if the register's current value is being |
| 2712 | * written to it again, then it is permissable to skip that register write |
| 2713 | * because it does not actually change the value of the hardware register. |
| 2714 | * |
| 2715 | * Some registers are uncacheable, meaning that even they are being written |
| 2716 | * again with their current value, the write has another purpose and must go |
| 2717 | * through. |
| 2718 | * |
| 2719 | * Knowing the codec's uncacheable registers allows the driver to avoid |
| 2720 | * unnecessary codec register writes while making sure important register writes |
| 2721 | * are not skipped. |
| 2722 | */ |
| 2723 | |
| 2724 | static bool timpani_register_is_cacheable(u8 reg) |
| 2725 | { |
| 2726 | switch (reg) { |
| 2727 | case TIMPANI_A_PA_LINE_L_GAIN: |
| 2728 | case TIMPANI_A_PA_LINE_R_GAIN: |
| 2729 | case TIMPANI_A_PA_HPH_L_GAIN: |
| 2730 | case TIMPANI_A_PA_HPH_R_GAIN: |
| 2731 | case TIMPANI_A_CDC_GCTL1: |
| 2732 | case TIMPANI_A_CDC_ST_CTL: |
| 2733 | case TIMPANI_A_CDC_GCTL2: |
| 2734 | case TIMPANI_A_CDC_ARB_BYPASS_CTL: |
| 2735 | case TIMPANI_A_CDC_CH_CTL: |
| 2736 | case TIMPANI_A_CDC_ANC1_IIR_COEFF_PTR: |
| 2737 | case TIMPANI_A_CDC_ANC1_IIR_COEFF_MSB: |
| 2738 | case TIMPANI_A_CDC_ANC1_IIR_COEFF_LSB: |
| 2739 | case TIMPANI_A_CDC_ANC1_LPF_COEFF_PTR: |
| 2740 | case TIMPANI_A_CDC_ANC1_LPF_COEFF_MSB: |
| 2741 | case TIMPANI_A_CDC_ANC1_LPF_COEFF_LSB: |
| 2742 | case TIMPANI_A_CDC_ANC1_SCALE_PTR: |
| 2743 | case TIMPANI_A_CDC_ANC1_SCALE: |
| 2744 | case TIMPANI_A_CDC_ANC2_IIR_COEFF_PTR: |
| 2745 | case TIMPANI_A_CDC_ANC2_IIR_COEFF_MSB: |
| 2746 | case TIMPANI_A_CDC_ANC2_IIR_COEFF_LSB: |
| 2747 | case TIMPANI_A_CDC_ANC2_LPF_COEFF_PTR: |
| 2748 | case TIMPANI_A_CDC_ANC2_LPF_COEFF_MSB: |
| 2749 | case TIMPANI_A_CDC_ANC2_LPF_COEFF_LSB: |
| 2750 | case TIMPANI_A_CDC_ANC2_SCALE_PTR: |
| 2751 | case TIMPANI_A_CDC_ANC2_SCALE: |
| 2752 | case TIMPANI_A_CDC_ANC1_CTL1: |
| 2753 | case TIMPANI_A_CDC_ANC1_CTL2: |
| 2754 | case TIMPANI_A_CDC_ANC1_FF_FB_SHIFT: |
| 2755 | case TIMPANI_A_CDC_ANC2_CTL1: |
| 2756 | case TIMPANI_A_CDC_ANC2_CTL2: |
| 2757 | case TIMPANI_A_CDC_ANC2_FF_FB_SHIFT: |
Vinay Vaka | df2d021 | 2011-11-17 15:21:24 +0530 | [diff] [blame] | 2758 | case TIMPANI_A_AUXPGA_LR_GAIN: |
Deepa Madiregama | e6ffdf4 | 2012-04-17 17:16:38 +0530 | [diff] [blame] | 2759 | case TIMPANI_A_CDC_ANC_INPUT_MUX: |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2760 | return false; |
| 2761 | default: |
| 2762 | return true; |
| 2763 | } |
| 2764 | } |
| 2765 | |
| 2766 | static int adie_codec_write(u8 reg, u8 mask, u8 val) |
| 2767 | { |
| 2768 | int rc = 0; |
| 2769 | u8 new_val; |
| 2770 | |
Santosh Mardi | 2247938 | 2011-10-14 02:50:12 +0530 | [diff] [blame] | 2771 | if (reg > MAX_SHADOW_RIGISTERS) { |
| 2772 | pr_debug("register number is out of bound for shadow" |
| 2773 | " registers reg = %d\n", reg); |
| 2774 | new_val = (val & mask); |
| 2775 | rc = marimba_write_bit_mask(adie_codec.pdrv_ptr, reg, &new_val, |
| 2776 | 1, 0xFF); |
| 2777 | if (IS_ERR_VALUE(rc)) { |
| 2778 | pr_err("%s: fail to write reg %x\n", __func__, reg); |
| 2779 | rc = -EIO; |
| 2780 | goto error; |
| 2781 | } |
| 2782 | return rc; |
| 2783 | } |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2784 | new_val = (val & mask) | (timpani_shadow[reg] & ~mask); |
| 2785 | if (!(timpani_register_is_cacheable(reg) && |
| 2786 | (new_val == timpani_shadow[reg]))) { |
| 2787 | |
| 2788 | rc = marimba_write_bit_mask(adie_codec.pdrv_ptr, reg, &new_val, |
| 2789 | 1, 0xFF); |
| 2790 | if (IS_ERR_VALUE(rc)) { |
| 2791 | pr_err("%s: fail to write reg %x\n", __func__, reg); |
| 2792 | rc = -EIO; |
| 2793 | goto error; |
| 2794 | } |
| 2795 | timpani_shadow[reg] = new_val; |
| 2796 | pr_debug("%s: write reg %x val %x new value %x\n", __func__, |
| 2797 | reg, val, new_val); |
| 2798 | } |
| 2799 | |
| 2800 | error: |
| 2801 | return rc; |
| 2802 | } |
| 2803 | |
| 2804 | |
| 2805 | static int reg_in_use(u8 reg_ref, u8 path_type) |
| 2806 | { |
| 2807 | if ((reg_ref & ~path_type) == 0) |
| 2808 | return 0; |
| 2809 | else |
| 2810 | return 1; |
| 2811 | } |
| 2812 | |
| 2813 | static int adie_codec_refcnt_write(u8 reg, u8 mask, u8 val, enum refcnt cnt, |
| 2814 | u8 path_type) |
| 2815 | { |
| 2816 | u8 i; |
| 2817 | int j; |
| 2818 | u8 fld_mask; |
| 2819 | u8 path_mask; |
| 2820 | u8 reg_mask = 0; |
| 2821 | int rc = 0; |
| 2822 | |
Santosh Mardi | efd780d | 2012-01-16 19:23:50 +0530 | [diff] [blame] | 2823 | for (i = 0; i < ARRAY_SIZE(timpani_regset); i++) { |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2824 | if (timpani_regset[i].reg_addr == reg) { |
| 2825 | for (j = 0; j < TIMPANI_MAX_FIELDS; j++) { |
| 2826 | fld_mask = timpani_regset[i].fld_ref_cnt[j].mask |
| 2827 | & mask; |
| 2828 | path_mask = timpani_regset[i].fld_ref_cnt[j] |
| 2829 | .path_mask; |
| 2830 | if (fld_mask) { |
| 2831 | if (!reg_in_use(path_mask, path_type)) |
| 2832 | reg_mask |= fld_mask; |
| 2833 | if (cnt == INC) |
| 2834 | timpani_regset[i].fld_ref_cnt[j] |
| 2835 | .path_mask |= path_type; |
| 2836 | else if (cnt == DEC) |
| 2837 | timpani_regset[i].fld_ref_cnt[j] |
| 2838 | .path_mask &= |
| 2839 | ~path_type; |
| 2840 | } |
| 2841 | } |
| 2842 | |
| 2843 | if (reg_mask) |
| 2844 | rc = adie_codec_write(reg, reg_mask, val); |
| 2845 | reg_mask = 0; |
| 2846 | break; |
| 2847 | } |
| 2848 | } |
| 2849 | |
| 2850 | return rc; |
| 2851 | } |
| 2852 | |
| 2853 | static int adie_codec_read(u8 reg, u8 *val) |
| 2854 | { |
| 2855 | return marimba_read(adie_codec.pdrv_ptr, reg, val, 1); |
| 2856 | } |
| 2857 | |
| 2858 | static int timpani_adie_codec_setpath(struct adie_codec_path *path_ptr, |
| 2859 | u32 freq_plan, u32 osr) |
| 2860 | { |
| 2861 | int rc = 0; |
| 2862 | u32 i, freq_idx = 0, freq = 0; |
| 2863 | |
| 2864 | if (path_ptr == NULL) |
| 2865 | return -EINVAL; |
| 2866 | |
| 2867 | if (path_ptr->curr_stage != ADIE_CODEC_DIGITAL_OFF) { |
| 2868 | rc = -EBUSY; |
| 2869 | goto error; |
| 2870 | } |
| 2871 | |
| 2872 | for (i = 0; i < path_ptr->profile->setting_sz; i++) { |
| 2873 | if (path_ptr->profile->settings[i].osr == osr) { |
| 2874 | if (path_ptr->profile->settings[i].freq_plan >= |
| 2875 | freq_plan) { |
| 2876 | if (freq == 0) { |
| 2877 | freq = path_ptr->profile->settings[i]. |
| 2878 | freq_plan; |
| 2879 | freq_idx = i; |
| 2880 | } else if (path_ptr->profile->settings[i]. |
| 2881 | freq_plan < freq) { |
| 2882 | freq = path_ptr->profile->settings[i]. |
| 2883 | freq_plan; |
| 2884 | freq_idx = i; |
| 2885 | } |
| 2886 | } |
| 2887 | } |
| 2888 | } |
| 2889 | |
| 2890 | if (freq_idx >= path_ptr->profile->setting_sz) |
| 2891 | rc = -ENODEV; |
| 2892 | else { |
| 2893 | path_ptr->hwsetting_idx = freq_idx; |
| 2894 | path_ptr->stage_idx = 0; |
| 2895 | } |
| 2896 | |
| 2897 | error: |
| 2898 | return rc; |
| 2899 | } |
| 2900 | |
| 2901 | static u32 timpani_adie_codec_freq_supported( |
| 2902 | struct adie_codec_dev_profile *profile, |
| 2903 | u32 requested_freq) |
| 2904 | { |
| 2905 | u32 i, rc = -EINVAL; |
| 2906 | |
| 2907 | for (i = 0; i < profile->setting_sz; i++) { |
| 2908 | if (profile->settings[i].freq_plan >= requested_freq) { |
| 2909 | rc = 0; |
| 2910 | break; |
| 2911 | } |
| 2912 | } |
| 2913 | return rc; |
| 2914 | } |
| 2915 | int timpani_adie_codec_enable_sidetone(struct adie_codec_path *rx_path_ptr, |
| 2916 | u32 enable) |
| 2917 | { |
| 2918 | int rc = 0; |
| 2919 | |
| 2920 | pr_debug("%s()\n", __func__); |
| 2921 | |
| 2922 | mutex_lock(&adie_codec.lock); |
| 2923 | |
| 2924 | if (!rx_path_ptr || &adie_codec.path[ADIE_CODEC_RX] != rx_path_ptr) { |
| 2925 | pr_err("%s: invalid path pointer\n", __func__); |
| 2926 | rc = -EINVAL; |
| 2927 | goto error; |
| 2928 | } else if (rx_path_ptr->curr_stage != |
| 2929 | ADIE_CODEC_DIGITAL_ANALOG_READY) { |
| 2930 | pr_err("%s: bad state\n", __func__); |
| 2931 | rc = -EPERM; |
| 2932 | goto error; |
| 2933 | } |
| 2934 | |
| 2935 | if (enable) { |
| 2936 | rc = adie_codec_write(TIMPANI_A_CDC_RX1_CTL, |
| 2937 | TIMPANI_RX1_ST_MASK, TIMPANI_RX1_ST_ENABLE); |
| 2938 | |
| 2939 | if (rx_path_ptr->reg_owner == RA_OWNER_PATH_RX1) |
| 2940 | adie_codec_write(TIMPANI_A_CDC_ST_MIXING, |
| 2941 | TIMPANI_CDC_ST_MIXING_TX1_MASK, |
| 2942 | TIMPANI_CDC_ST_MIXING_TX1_ENABLE); |
| 2943 | else if (rx_path_ptr->reg_owner == RA_OWNER_PATH_RX2) |
| 2944 | adie_codec_write(TIMPANI_A_CDC_ST_MIXING, |
| 2945 | TIMPANI_CDC_ST_MIXING_TX2_MASK, |
| 2946 | TIMPANI_CDC_ST_MIXING_TX2_ENABLE); |
| 2947 | } else { |
| 2948 | rc = adie_codec_write(TIMPANI_A_CDC_RX1_CTL, |
| 2949 | TIMPANI_RX1_ST_MASK, 0); |
| 2950 | |
| 2951 | if (rx_path_ptr->reg_owner == RA_OWNER_PATH_RX1) |
| 2952 | adie_codec_write(TIMPANI_A_CDC_ST_MIXING, |
| 2953 | TIMPANI_CDC_ST_MIXING_TX1_MASK, 0); |
| 2954 | else if (rx_path_ptr->reg_owner == RA_OWNER_PATH_RX2) |
| 2955 | adie_codec_write(TIMPANI_A_CDC_ST_MIXING, |
| 2956 | TIMPANI_CDC_ST_MIXING_TX2_MASK, 0); |
| 2957 | } |
| 2958 | |
| 2959 | error: |
| 2960 | mutex_unlock(&adie_codec.lock); |
| 2961 | return rc; |
| 2962 | } |
| 2963 | static int timpani_adie_codec_enable_anc(struct adie_codec_path *rx_path_ptr, |
| 2964 | u32 enable, struct adie_codec_anc_data *calibration_writes) |
| 2965 | { |
| 2966 | int index = 0; |
| 2967 | int rc = 0; |
| 2968 | u8 reg, mask, val; |
| 2969 | pr_debug("%s: enable = %d\n", __func__, enable); |
| 2970 | |
| 2971 | mutex_lock(&adie_codec.lock); |
| 2972 | |
| 2973 | if (!rx_path_ptr || &adie_codec.path[ADIE_CODEC_RX] != rx_path_ptr) { |
| 2974 | pr_err("%s: invalid path pointer\n", __func__); |
| 2975 | rc = -EINVAL; |
| 2976 | goto error; |
| 2977 | } else if (rx_path_ptr->curr_stage != |
| 2978 | ADIE_CODEC_DIGITAL_ANALOG_READY) { |
| 2979 | pr_err("%s: bad state\n", __func__); |
| 2980 | rc = -EPERM; |
| 2981 | goto error; |
| 2982 | } |
| 2983 | if (enable) { |
| 2984 | if (!calibration_writes || !calibration_writes->writes) { |
| 2985 | pr_err("%s: No ANC calibration data\n", __func__); |
| 2986 | rc = -EPERM; |
| 2987 | goto error; |
| 2988 | } |
| 2989 | while (index < calibration_writes->size) { |
| 2990 | ADIE_CODEC_UNPACK_ENTRY(calibration_writes-> |
| 2991 | writes[index], reg, mask, val); |
| 2992 | adie_codec_write(reg, mask, val); |
| 2993 | index++; |
| 2994 | } |
| 2995 | } else { |
| 2996 | adie_codec_write(TIMPANI_A_CDC_ANC1_CTL1, |
| 2997 | TIMPANI_CDC_ANC1_CTL1_ANC1_EN_M, |
| 2998 | TIMPANI_CDC_ANC1_CTL1_ANC1_EN_ANC_DIS << |
| 2999 | TIMPANI_CDC_ANC1_CTL1_ANC1_EN_S); |
| 3000 | |
| 3001 | adie_codec_write(TIMPANI_A_CDC_ANC2_CTL1, |
| 3002 | TIMPANI_CDC_ANC2_CTL1_ANC2_EN_M, |
| 3003 | TIMPANI_CDC_ANC2_CTL1_ANC2_EN_ANC_DIS << |
| 3004 | TIMPANI_CDC_ANC2_CTL1_ANC2_EN_S); |
| 3005 | } |
| 3006 | |
| 3007 | error: |
| 3008 | mutex_unlock(&adie_codec.lock); |
| 3009 | return rc; |
| 3010 | } |
| 3011 | |
| 3012 | static void adie_codec_restore_regdefault(u8 path_mask, u32 blk) |
| 3013 | { |
| 3014 | u32 ireg; |
| 3015 | u32 regset_sz = |
| 3016 | (sizeof(timpani_regset)/sizeof(struct timpani_regaccess)); |
| 3017 | |
| 3018 | for (ireg = 0; ireg < regset_sz; ireg++) { |
| 3019 | if (timpani_regset[ireg].blk_mask[blk]) { |
| 3020 | /* only process register belong to the block */ |
| 3021 | u8 reg = timpani_regset[ireg].reg_addr; |
| 3022 | u8 mask = timpani_regset[ireg].blk_mask[blk]; |
| 3023 | u8 val = timpani_regset[ireg].reg_default; |
| 3024 | adie_codec_refcnt_write(reg, mask, val, IGNORE, |
| 3025 | path_mask); |
| 3026 | } |
| 3027 | } |
| 3028 | } |
| 3029 | |
| 3030 | static void adie_codec_reach_stage_action(struct adie_codec_path *path_ptr, |
| 3031 | u32 stage) |
| 3032 | { |
| 3033 | u32 iblk, iowner; /* iterators */ |
| 3034 | u8 path_mask; |
| 3035 | |
| 3036 | if (path_ptr == NULL) |
| 3037 | return; |
| 3038 | |
| 3039 | path_mask = TIMPANI_PATH_MASK(path_ptr->reg_owner); |
| 3040 | |
| 3041 | if (stage != ADIE_CODEC_DIGITAL_OFF) |
| 3042 | return; |
| 3043 | |
| 3044 | for (iblk = 0 ; iblk <= RA_BLOCK_RESERVED ; iblk++) { |
| 3045 | for (iowner = 0; iowner < RA_OWNER_NUM; iowner++) { |
| 3046 | if (timpani_blkcfg[iblk].valid_owners[iowner] == |
| 3047 | path_ptr->reg_owner) { |
| 3048 | adie_codec_restore_regdefault(path_mask, iblk); |
| 3049 | break; /* This path owns this block */ |
| 3050 | } |
| 3051 | } |
| 3052 | } |
| 3053 | } |
| 3054 | |
| 3055 | static int timpani_adie_codec_proceed_stage(struct adie_codec_path *path_ptr, |
| 3056 | u32 state) |
| 3057 | { |
| 3058 | int rc = 0, loop_exit = 0; |
| 3059 | struct adie_codec_action_unit *curr_action; |
| 3060 | struct adie_codec_hwsetting_entry *setting; |
| 3061 | u8 reg, mask, val; |
| 3062 | u8 path_mask; |
| 3063 | |
| 3064 | if (path_ptr == NULL) |
| 3065 | return -EINVAL; |
| 3066 | |
| 3067 | path_mask = TIMPANI_PATH_MASK(path_ptr->reg_owner); |
| 3068 | |
| 3069 | mutex_lock(&adie_codec.lock); |
| 3070 | setting = &path_ptr->profile->settings[path_ptr->hwsetting_idx]; |
| 3071 | while (!loop_exit) { |
| 3072 | |
| 3073 | curr_action = &setting->actions[path_ptr->stage_idx]; |
| 3074 | |
| 3075 | switch (curr_action->type) { |
| 3076 | case ADIE_CODEC_ACTION_ENTRY: |
| 3077 | ADIE_CODEC_UNPACK_ENTRY(curr_action->action, |
| 3078 | reg, mask, val); |
| 3079 | if (state == ADIE_CODEC_DIGITAL_OFF) |
| 3080 | adie_codec_refcnt_write(reg, mask, val, DEC, |
| 3081 | path_mask); |
| 3082 | else |
| 3083 | adie_codec_refcnt_write(reg, mask, val, INC, |
| 3084 | path_mask); |
| 3085 | break; |
| 3086 | case ADIE_CODEC_ACTION_DELAY_WAIT: |
| 3087 | if (curr_action->action > MAX_MDELAY_US) |
| 3088 | msleep(curr_action->action/1000); |
| 3089 | else |
| 3090 | usleep_range(curr_action->action, |
| 3091 | curr_action->action); |
| 3092 | break; |
| 3093 | case ADIE_CODEC_ACTION_STAGE_REACHED: |
| 3094 | adie_codec_reach_stage_action(path_ptr, |
| 3095 | curr_action->action); |
| 3096 | if (curr_action->action == state) { |
| 3097 | path_ptr->curr_stage = state; |
| 3098 | loop_exit = 1; |
| 3099 | } |
| 3100 | break; |
| 3101 | default: |
| 3102 | BUG(); |
| 3103 | } |
| 3104 | |
| 3105 | path_ptr->stage_idx++; |
| 3106 | if (path_ptr->stage_idx == setting->action_sz) |
| 3107 | path_ptr->stage_idx = 0; |
| 3108 | } |
| 3109 | mutex_unlock(&adie_codec.lock); |
| 3110 | |
| 3111 | return rc; |
| 3112 | } |
| 3113 | |
| 3114 | static void timpani_codec_bring_up(void) |
| 3115 | { |
| 3116 | /* Codec power up sequence */ |
| 3117 | adie_codec_write(0xFF, 0xFF, 0x08); |
| 3118 | adie_codec_write(0xFF, 0xFF, 0x0A); |
| 3119 | adie_codec_write(0xFF, 0xFF, 0x0E); |
| 3120 | adie_codec_write(0xFF, 0xFF, 0x07); |
| 3121 | adie_codec_write(0xFF, 0xFF, 0x17); |
| 3122 | adie_codec_write(TIMPANI_A_MREF, 0xFF, 0xF2); |
| 3123 | msleep(15); |
| 3124 | adie_codec_write(TIMPANI_A_MREF, 0xFF, 0x22); |
| 3125 | |
| 3126 | /* Bypass TX HPFs to prevent pops */ |
| 3127 | adie_codec_write(TIMPANI_A_CDC_BYPASS_CTL2, TIMPANI_CDC_BYPASS_CTL2_M, |
| 3128 | TIMPANI_CDC_BYPASS_CTL2_POR); |
| 3129 | adie_codec_write(TIMPANI_A_CDC_BYPASS_CTL3, TIMPANI_CDC_BYPASS_CTL3_M, |
| 3130 | TIMPANI_CDC_BYPASS_CTL3_POR); |
| 3131 | } |
| 3132 | |
| 3133 | static void timpani_codec_bring_down(void) |
| 3134 | { |
| 3135 | adie_codec_write(TIMPANI_A_MREF, 0xFF, TIMPANI_MREF_POR); |
| 3136 | adie_codec_write(0xFF, 0xFF, 0x07); |
| 3137 | adie_codec_write(0xFF, 0xFF, 0x06); |
| 3138 | adie_codec_write(0xFF, 0xFF, 0x0E); |
| 3139 | adie_codec_write(0xFF, 0xFF, 0x08); |
| 3140 | } |
| 3141 | |
| 3142 | static int timpani_adie_codec_open(struct adie_codec_dev_profile *profile, |
| 3143 | struct adie_codec_path **path_pptr) |
| 3144 | { |
| 3145 | int rc = 0; |
| 3146 | |
| 3147 | mutex_lock(&adie_codec.lock); |
| 3148 | |
| 3149 | if (!profile || !path_pptr) { |
| 3150 | rc = -EINVAL; |
| 3151 | goto error; |
| 3152 | } |
| 3153 | |
| 3154 | if (adie_codec.path[profile->path_type].profile) { |
| 3155 | rc = -EBUSY; |
| 3156 | goto error; |
| 3157 | } |
| 3158 | |
| 3159 | if (!adie_codec.ref_cnt) { |
| 3160 | |
| 3161 | if (adie_codec.codec_pdata && |
| 3162 | adie_codec.codec_pdata->marimba_codec_power) { |
| 3163 | |
| 3164 | rc = adie_codec.codec_pdata->marimba_codec_power(1); |
| 3165 | if (rc) { |
| 3166 | pr_err("%s: could not power up timpani " |
| 3167 | "codec\n", __func__); |
| 3168 | goto error; |
| 3169 | } |
| 3170 | timpani_codec_bring_up(); |
| 3171 | } else { |
| 3172 | pr_err("%s: couldn't detect timpani codec\n", __func__); |
| 3173 | rc = -ENODEV; |
| 3174 | goto error; |
| 3175 | } |
| 3176 | |
| 3177 | } |
| 3178 | |
| 3179 | adie_codec.path[profile->path_type].profile = profile; |
| 3180 | *path_pptr = (void *) &adie_codec.path[profile->path_type]; |
| 3181 | adie_codec.ref_cnt++; |
| 3182 | adie_codec.path[profile->path_type].hwsetting_idx = 0; |
| 3183 | adie_codec.path[profile->path_type].curr_stage = ADIE_CODEC_DIGITAL_OFF; |
| 3184 | adie_codec.path[profile->path_type].stage_idx = 0; |
| 3185 | |
| 3186 | |
| 3187 | error: |
| 3188 | mutex_unlock(&adie_codec.lock); |
| 3189 | return rc; |
| 3190 | } |
| 3191 | |
| 3192 | static int timpani_adie_codec_close(struct adie_codec_path *path_ptr) |
| 3193 | { |
| 3194 | int rc = 0; |
| 3195 | |
| 3196 | mutex_lock(&adie_codec.lock); |
| 3197 | |
| 3198 | if (!path_ptr) { |
| 3199 | rc = -EINVAL; |
| 3200 | goto error; |
| 3201 | } |
| 3202 | if (path_ptr->curr_stage != ADIE_CODEC_DIGITAL_OFF) |
| 3203 | adie_codec_proceed_stage(path_ptr, ADIE_CODEC_DIGITAL_OFF); |
| 3204 | |
| 3205 | BUG_ON(!adie_codec.ref_cnt); |
| 3206 | |
| 3207 | path_ptr->profile = NULL; |
| 3208 | adie_codec.ref_cnt--; |
| 3209 | |
| 3210 | if (!adie_codec.ref_cnt) { |
| 3211 | /* Timpani CDC power down sequence */ |
| 3212 | timpani_codec_bring_down(); |
| 3213 | |
| 3214 | if (adie_codec.codec_pdata && |
| 3215 | adie_codec.codec_pdata->marimba_codec_power) { |
| 3216 | |
| 3217 | rc = adie_codec.codec_pdata->marimba_codec_power(0); |
| 3218 | if (rc) { |
| 3219 | pr_err("%s: could not power down timpani " |
| 3220 | "codec\n", __func__); |
| 3221 | goto error; |
| 3222 | } |
| 3223 | } |
| 3224 | } |
| 3225 | |
| 3226 | error: |
| 3227 | mutex_unlock(&adie_codec.lock); |
| 3228 | return rc; |
| 3229 | } |
| 3230 | |
| 3231 | static int timpani_adie_codec_set_master_mode(struct adie_codec_path *path_ptr, |
| 3232 | u8 master) |
| 3233 | { |
| 3234 | u8 val = master ? 1 : 0; |
| 3235 | |
| 3236 | if (!path_ptr) |
| 3237 | return -EINVAL; |
| 3238 | |
| 3239 | if (path_ptr->reg_owner == RA_OWNER_PATH_RX1) |
| 3240 | adie_codec_write(TIMPANI_A_CDC_RX1_CTL, 0x01, val); |
| 3241 | else if (path_ptr->reg_owner == RA_OWNER_PATH_TX1) |
| 3242 | adie_codec_write(TIMPANI_A_CDC_TX_I2S_CTL, 0x01, val); |
| 3243 | else |
| 3244 | return -EINVAL; |
| 3245 | |
| 3246 | return 0; |
| 3247 | } |
| 3248 | |
| 3249 | int timpani_adie_codec_set_device_analog_volume( |
| 3250 | struct adie_codec_path *path_ptr, |
| 3251 | u32 num_channels, u32 volume) |
| 3252 | { |
| 3253 | u8 val; |
| 3254 | u8 curr_val; |
| 3255 | u8 i; |
| 3256 | |
| 3257 | adie_codec_read(TIMPANI_A_AUXPGA_LR_GAIN, &curr_val); |
| 3258 | |
| 3259 | /* Volume is expressed as a percentage. */ |
| 3260 | /* The upper nibble is the left channel, lower right channel. */ |
| 3261 | val = (u8)((volume * TIMPANI_CODEC_AUXPGA_GAIN_RANGE) / 100); |
| 3262 | val |= val << 4; |
| 3263 | |
| 3264 | if ((curr_val & 0x0F) < (val & 0x0F)) { |
| 3265 | for (i = curr_val; i < val; i += 0x11) |
| 3266 | adie_codec_write(TIMPANI_A_AUXPGA_LR_GAIN, 0xFF, i); |
| 3267 | } else if ((curr_val & 0x0F) > (val & 0x0F)) { |
| 3268 | for (i = curr_val; i > val; i -= 0x11) |
| 3269 | adie_codec_write(TIMPANI_A_AUXPGA_LR_GAIN, 0xFF, i); |
| 3270 | } |
| 3271 | |
| 3272 | return 0; |
| 3273 | } |
| 3274 | |
| 3275 | enum adie_vol_type { |
| 3276 | ADIE_CODEC_RX_DIG_VOL, |
| 3277 | ADIE_CODEC_TX_DIG_VOL, |
| 3278 | ADIE_CODEC_VOL_TYPE_MAX |
| 3279 | }; |
| 3280 | |
| 3281 | #define CDC_RX1LG 0x84 |
| 3282 | #define CDC_RX1RG 0x85 |
| 3283 | #define CDC_TX1LG 0x86 |
| 3284 | #define CDC_TX1RG 0x87 |
| 3285 | #define DIG_VOL_MASK 0xFF |
| 3286 | |
| 3287 | #define CDC_GCTL1 0x8A |
| 3288 | #define RX1_PGA_UPDATE_L 0x04 |
| 3289 | #define RX1_PGA_UPDATE_R 0x08 |
| 3290 | #define TX1_PGA_UPDATE_L 0x40 |
| 3291 | #define TX1_PGA_UPDATE_R 0x80 |
| 3292 | #define CDC_GCTL1_RX_MASK 0x0F |
| 3293 | #define CDC_GCTL1_TX_MASK 0xF0 |
| 3294 | |
| 3295 | enum { |
| 3296 | TIMPANI_MIN_DIG_VOL = -84, /* in DB*/ |
| 3297 | TIMPANI_MAX_DIG_VOL = 16, /* in DB*/ |
| 3298 | TIMPANI_DIG_VOL_STEP = 3 /* in DB*/ |
| 3299 | }; |
| 3300 | |
| 3301 | static int timpani_adie_codec_set_dig_vol(enum adie_vol_type vol_type, |
| 3302 | u32 num_chan, u32 vol_per) |
| 3303 | { |
| 3304 | u8 reg_left, reg_right; |
| 3305 | u8 gain_reg_val, gain_reg_mask; |
| 3306 | s8 new_reg_val, cur_reg_val; |
| 3307 | s8 step_size; |
| 3308 | |
| 3309 | adie_codec_read(CDC_GCTL1, &gain_reg_val); |
| 3310 | |
| 3311 | if (vol_type == ADIE_CODEC_RX_DIG_VOL) { |
| 3312 | |
| 3313 | pr_debug("%s : RX DIG VOL. num_chan = %u\n", __func__, |
| 3314 | num_chan); |
| 3315 | reg_left = CDC_RX1LG; |
| 3316 | reg_right = CDC_RX1RG; |
| 3317 | |
| 3318 | if (num_chan == 1) |
| 3319 | gain_reg_val |= RX1_PGA_UPDATE_L; |
| 3320 | else |
| 3321 | gain_reg_val |= (RX1_PGA_UPDATE_L | RX1_PGA_UPDATE_R); |
| 3322 | |
| 3323 | gain_reg_mask = CDC_GCTL1_RX_MASK; |
| 3324 | } else { |
| 3325 | |
| 3326 | pr_debug("%s : TX DIG VOL. num_chan = %u\n", __func__, |
| 3327 | num_chan); |
| 3328 | reg_left = CDC_TX1LG; |
| 3329 | reg_right = CDC_TX1RG; |
| 3330 | |
| 3331 | if (num_chan == 1) |
| 3332 | gain_reg_val |= TX1_PGA_UPDATE_L; |
| 3333 | else |
| 3334 | gain_reg_val |= (TX1_PGA_UPDATE_L | TX1_PGA_UPDATE_R); |
| 3335 | |
| 3336 | gain_reg_mask = CDC_GCTL1_TX_MASK; |
| 3337 | } |
| 3338 | |
| 3339 | adie_codec_read(reg_left, &cur_reg_val); |
| 3340 | |
| 3341 | pr_debug("%s: vol_per = %d cur_reg_val = %d 0x%x\n", __func__, vol_per, |
| 3342 | cur_reg_val, cur_reg_val); |
| 3343 | |
| 3344 | new_reg_val = TIMPANI_MIN_DIG_VOL + |
| 3345 | (((TIMPANI_MAX_DIG_VOL - TIMPANI_MIN_DIG_VOL) * vol_per) / 100); |
| 3346 | |
| 3347 | pr_debug("new_reg_val = %d 0x%x\n", new_reg_val, new_reg_val); |
| 3348 | |
| 3349 | if (new_reg_val > cur_reg_val) { |
| 3350 | step_size = TIMPANI_DIG_VOL_STEP; |
| 3351 | } else if (new_reg_val < cur_reg_val) { |
| 3352 | step_size = -TIMPANI_DIG_VOL_STEP; |
| 3353 | } else { |
| 3354 | pr_debug("new_reg_val and cur_reg_val are same 0x%x\n", |
| 3355 | new_reg_val); |
| 3356 | return 0; |
| 3357 | } |
| 3358 | |
| 3359 | while (cur_reg_val != new_reg_val) { |
| 3360 | |
| 3361 | if (((new_reg_val > cur_reg_val) && |
| 3362 | ((new_reg_val - cur_reg_val) < TIMPANI_DIG_VOL_STEP)) || |
| 3363 | ((cur_reg_val > new_reg_val) && |
| 3364 | ((cur_reg_val - new_reg_val) |
| 3365 | < TIMPANI_DIG_VOL_STEP))) { |
| 3366 | |
| 3367 | cur_reg_val = new_reg_val; |
| 3368 | |
| 3369 | pr_debug("diff less than step. write new_reg_val = %d" |
| 3370 | " 0x%x\n", new_reg_val, new_reg_val); |
| 3371 | |
| 3372 | } else { |
| 3373 | cur_reg_val = cur_reg_val + step_size; |
| 3374 | |
| 3375 | pr_debug("cur_reg_val = %d 0x%x\n", |
| 3376 | cur_reg_val, cur_reg_val); |
| 3377 | } |
| 3378 | |
| 3379 | adie_codec_write(reg_left, DIG_VOL_MASK, cur_reg_val); |
| 3380 | |
| 3381 | if (num_chan == 2) |
| 3382 | adie_codec_write(reg_right, DIG_VOL_MASK, cur_reg_val); |
| 3383 | |
| 3384 | adie_codec_write(CDC_GCTL1, gain_reg_mask, gain_reg_val); |
| 3385 | } |
| 3386 | return 0; |
| 3387 | } |
| 3388 | |
| 3389 | static int timpani_adie_codec_set_device_digital_volume( |
| 3390 | struct adie_codec_path *path_ptr, |
| 3391 | u32 num_channels, u32 vol_percentage /* in percentage */) |
| 3392 | { |
| 3393 | enum adie_vol_type vol_type; |
| 3394 | |
| 3395 | if (!path_ptr || (path_ptr->curr_stage != |
| 3396 | ADIE_CODEC_DIGITAL_ANALOG_READY)) { |
| 3397 | pr_info("%s: timpani codec not ready for volume control\n", |
| 3398 | __func__); |
| 3399 | return -EPERM; |
| 3400 | } |
| 3401 | |
| 3402 | if (num_channels > 2) { |
| 3403 | pr_err("%s: timpani odec only supports max two channels\n", |
| 3404 | __func__); |
| 3405 | return -EINVAL; |
| 3406 | } |
| 3407 | |
| 3408 | if (path_ptr->profile->path_type == ADIE_CODEC_RX) { |
| 3409 | vol_type = ADIE_CODEC_RX_DIG_VOL; |
| 3410 | } else if (path_ptr->profile->path_type == ADIE_CODEC_TX) { |
| 3411 | vol_type = ADIE_CODEC_TX_DIG_VOL; |
| 3412 | } else { |
| 3413 | pr_err("%s: invalid device data neither RX nor TX\n", |
| 3414 | __func__); |
| 3415 | return -EINVAL; |
| 3416 | } |
| 3417 | |
| 3418 | timpani_adie_codec_set_dig_vol(vol_type, num_channels, vol_percentage); |
| 3419 | |
| 3420 | return 0; |
| 3421 | } |
| 3422 | |
| 3423 | static const struct adie_codec_operations timpani_adie_ops = { |
| 3424 | .codec_id = TIMPANI_ID, |
| 3425 | .codec_open = timpani_adie_codec_open, |
| 3426 | .codec_close = timpani_adie_codec_close, |
| 3427 | .codec_setpath = timpani_adie_codec_setpath, |
| 3428 | .codec_proceed_stage = timpani_adie_codec_proceed_stage, |
| 3429 | .codec_freq_supported = timpani_adie_codec_freq_supported, |
| 3430 | .codec_enable_sidetone = timpani_adie_codec_enable_sidetone, |
| 3431 | .codec_set_master_mode = timpani_adie_codec_set_master_mode, |
| 3432 | .codec_enable_anc = timpani_adie_codec_enable_anc, |
| 3433 | .codec_set_device_analog_volume = |
| 3434 | timpani_adie_codec_set_device_analog_volume, |
| 3435 | .codec_set_device_digital_volume = |
| 3436 | timpani_adie_codec_set_device_digital_volume, |
| 3437 | }; |
| 3438 | |
| 3439 | static void timpani_codec_populate_shadow_registers(void) |
| 3440 | { |
| 3441 | int i; |
| 3442 | |
| 3443 | for (i = 0; i < ARRAY_SIZE(timpani_regset); i++) { |
| 3444 | if (timpani_regset[i].reg_addr < TIMPANI_ARRAY_SIZE) { |
| 3445 | timpani_shadow[timpani_regset[i].reg_addr] = |
| 3446 | timpani_regset[i].reg_default; |
| 3447 | } |
| 3448 | } |
| 3449 | } |
| 3450 | |
| 3451 | #ifdef CONFIG_DEBUG_FS |
| 3452 | static struct dentry *debugfs_timpani_dent; |
| 3453 | static struct dentry *debugfs_peek; |
| 3454 | static struct dentry *debugfs_poke; |
| 3455 | static struct dentry *debugfs_power; |
| 3456 | static struct dentry *debugfs_dump; |
| 3457 | |
| 3458 | static unsigned char read_data; |
| 3459 | |
| 3460 | static int codec_debug_open(struct inode *inode, struct file *file) |
| 3461 | { |
| 3462 | file->private_data = inode->i_private; |
| 3463 | return 0; |
| 3464 | } |
| 3465 | |
| 3466 | static int get_parameters(char *buf, long int *param1, int num_of_par) |
| 3467 | { |
| 3468 | char *token; |
| 3469 | int base, cnt; |
| 3470 | |
| 3471 | token = strsep(&buf, " "); |
| 3472 | |
| 3473 | for (cnt = 0; cnt < num_of_par; cnt++) { |
| 3474 | if (token != NULL) { |
| 3475 | if ((token[1] == 'x') || (token[1] == 'X')) |
| 3476 | base = 16; |
| 3477 | else |
| 3478 | base = 10; |
| 3479 | |
| 3480 | if (strict_strtoul(token, base, ¶m1[cnt]) != 0) |
| 3481 | return -EINVAL; |
| 3482 | |
| 3483 | token = strsep(&buf, " "); |
| 3484 | } |
| 3485 | else |
| 3486 | return -EINVAL; |
| 3487 | } |
| 3488 | return 0; |
| 3489 | } |
| 3490 | |
| 3491 | static ssize_t codec_debug_read(struct file *file, char __user *ubuf, |
| 3492 | size_t count, loff_t *ppos) |
| 3493 | { |
| 3494 | char lbuf[8]; |
| 3495 | |
| 3496 | snprintf(lbuf, sizeof(lbuf), "0x%x\n", read_data); |
| 3497 | return simple_read_from_buffer(ubuf, count, ppos, lbuf, strlen(lbuf)); |
| 3498 | } |
| 3499 | |
| 3500 | static ssize_t codec_debug_write(struct file *filp, |
| 3501 | const char __user *ubuf, size_t cnt, loff_t *ppos) |
| 3502 | { |
| 3503 | char *access_str = filp->private_data; |
| 3504 | char lbuf[32]; |
| 3505 | int rc; |
| 3506 | int i; |
| 3507 | int read_result; |
| 3508 | u8 reg_val; |
| 3509 | long int param[5]; |
| 3510 | |
| 3511 | if (cnt > sizeof(lbuf) - 1) |
| 3512 | return -EINVAL; |
| 3513 | |
| 3514 | rc = copy_from_user(lbuf, ubuf, cnt); |
| 3515 | if (rc) |
| 3516 | return -EFAULT; |
| 3517 | |
| 3518 | lbuf[cnt] = '\0'; |
| 3519 | |
| 3520 | if (!strcmp(access_str, "power")) { |
| 3521 | if (get_parameters(lbuf, param, 1) == 0) { |
| 3522 | switch (param[0]) { |
| 3523 | case 1: |
| 3524 | adie_codec.codec_pdata->marimba_codec_power(1); |
| 3525 | timpani_codec_bring_up(); |
| 3526 | break; |
| 3527 | case 0: |
| 3528 | timpani_codec_bring_down(); |
| 3529 | adie_codec.codec_pdata->marimba_codec_power(0); |
| 3530 | break; |
| 3531 | default: |
| 3532 | rc = -EINVAL; |
| 3533 | break; |
| 3534 | } |
| 3535 | } else |
| 3536 | rc = -EINVAL; |
| 3537 | } else if (!strcmp(access_str, "poke")) { |
| 3538 | /* write */ |
| 3539 | rc = get_parameters(lbuf, param, 2); |
| 3540 | if ((param[0] <= 0xFF) && (param[1] <= 0xFF) && |
| 3541 | (rc == 0)) |
| 3542 | adie_codec_write(param[0], 0xFF, param[1]); |
| 3543 | else |
| 3544 | rc = -EINVAL; |
| 3545 | } else if (!strcmp(access_str, "peek")) { |
| 3546 | /* read */ |
| 3547 | rc = get_parameters(lbuf, param, 1); |
| 3548 | if ((param[0] <= 0xFF) && (rc == 0)) |
| 3549 | adie_codec_read(param[0], &read_data); |
| 3550 | else |
| 3551 | rc = -EINVAL; |
| 3552 | } else if (!strcmp(access_str, "dump")) { |
| 3553 | pr_info("************** timpani regs *************\n"); |
| 3554 | for (i = 0; i < 0xFF; i++) { |
| 3555 | read_result = adie_codec_read(i, ®_val); |
| 3556 | if (read_result < 0) { |
| 3557 | pr_info("failed to read codec register\n"); |
| 3558 | break; |
| 3559 | } else |
| 3560 | pr_info("reg 0x%02X val 0x%02X\n", i, reg_val); |
| 3561 | } |
| 3562 | pr_info("*****************************************\n"); |
| 3563 | } |
| 3564 | |
| 3565 | if (rc == 0) |
| 3566 | rc = cnt; |
| 3567 | else |
| 3568 | pr_err("%s: rc = %d\n", __func__, rc); |
| 3569 | |
| 3570 | return rc; |
| 3571 | } |
| 3572 | |
| 3573 | static const struct file_operations codec_debug_ops = { |
| 3574 | .open = codec_debug_open, |
| 3575 | .write = codec_debug_write, |
| 3576 | .read = codec_debug_read |
| 3577 | }; |
| 3578 | #endif |
| 3579 | |
| 3580 | static int timpani_codec_probe(struct platform_device *pdev) |
| 3581 | { |
| 3582 | int rc; |
| 3583 | |
| 3584 | adie_codec.pdrv_ptr = platform_get_drvdata(pdev); |
| 3585 | adie_codec.codec_pdata = pdev->dev.platform_data; |
| 3586 | |
| 3587 | if (adie_codec.codec_pdata->snddev_profile_init) |
| 3588 | adie_codec.codec_pdata->snddev_profile_init(); |
| 3589 | |
| 3590 | timpani_codec_populate_shadow_registers(); |
| 3591 | |
| 3592 | /* Register the timpani ADIE operations */ |
| 3593 | rc = adie_codec_register_codec_operations(&timpani_adie_ops); |
| 3594 | |
| 3595 | #ifdef CONFIG_DEBUG_FS |
| 3596 | debugfs_timpani_dent = debugfs_create_dir("msm_adie_codec", 0); |
| 3597 | if (!IS_ERR(debugfs_timpani_dent)) { |
| 3598 | debugfs_peek = debugfs_create_file("peek", |
| 3599 | S_IFREG | S_IRUGO, debugfs_timpani_dent, |
| 3600 | (void *) "peek", &codec_debug_ops); |
| 3601 | |
| 3602 | debugfs_poke = debugfs_create_file("poke", |
| 3603 | S_IFREG | S_IRUGO, debugfs_timpani_dent, |
| 3604 | (void *) "poke", &codec_debug_ops); |
| 3605 | |
| 3606 | debugfs_power = debugfs_create_file("power", |
| 3607 | S_IFREG | S_IRUGO, debugfs_timpani_dent, |
| 3608 | (void *) "power", &codec_debug_ops); |
| 3609 | |
| 3610 | debugfs_dump = debugfs_create_file("dump", |
| 3611 | S_IFREG | S_IRUGO, debugfs_timpani_dent, |
| 3612 | (void *) "dump", &codec_debug_ops); |
| 3613 | |
| 3614 | } |
| 3615 | #endif |
| 3616 | |
| 3617 | return rc; |
| 3618 | } |
| 3619 | |
| 3620 | static struct platform_driver timpani_codec_driver = { |
| 3621 | .probe = timpani_codec_probe, |
| 3622 | .driver = { |
| 3623 | .name = "timpani_codec", |
| 3624 | .owner = THIS_MODULE, |
| 3625 | }, |
| 3626 | }; |
| 3627 | |
| 3628 | static int __init timpani_codec_init(void) |
| 3629 | { |
| 3630 | s32 rc; |
| 3631 | |
| 3632 | rc = platform_driver_register(&timpani_codec_driver); |
| 3633 | if (IS_ERR_VALUE(rc)) |
| 3634 | goto error; |
| 3635 | |
| 3636 | adie_codec.path[ADIE_CODEC_TX].reg_owner = RA_OWNER_PATH_TX1; |
| 3637 | adie_codec.path[ADIE_CODEC_RX].reg_owner = RA_OWNER_PATH_RX1; |
| 3638 | adie_codec.path[ADIE_CODEC_LB].reg_owner = RA_OWNER_PATH_LB; |
| 3639 | mutex_init(&adie_codec.lock); |
| 3640 | error: |
| 3641 | return rc; |
| 3642 | } |
| 3643 | |
| 3644 | static void __exit timpani_codec_exit(void) |
| 3645 | { |
| 3646 | #ifdef CONFIG_DEBUG_FS |
| 3647 | debugfs_remove(debugfs_peek); |
| 3648 | debugfs_remove(debugfs_poke); |
| 3649 | debugfs_remove(debugfs_power); |
| 3650 | debugfs_remove(debugfs_dump); |
| 3651 | debugfs_remove(debugfs_timpani_dent); |
| 3652 | #endif |
| 3653 | platform_driver_unregister(&timpani_codec_driver); |
| 3654 | } |
| 3655 | |
| 3656 | module_init(timpani_codec_init); |
| 3657 | module_exit(timpani_codec_exit); |
| 3658 | |
| 3659 | MODULE_DESCRIPTION("Timpani codec driver"); |
| 3660 | MODULE_VERSION("1.0"); |
| 3661 | MODULE_LICENSE("GPL v2"); |