Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2008 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Eric Anholt <eric@anholt.net> |
| 25 | * |
| 26 | */ |
| 27 | |
| 28 | #include "drmP.h" |
| 29 | #include "drm.h" |
| 30 | #include "i915_drm.h" |
| 31 | #include "i915_drv.h" |
| 32 | #include <linux/swap.h> |
| 33 | |
Eric Anholt | 28dfe52 | 2008-11-13 15:00:55 -0800 | [diff] [blame] | 34 | #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT)) |
| 35 | |
Keith Packard | c0d9082 | 2008-11-20 23:11:08 -0800 | [diff] [blame] | 36 | static void |
| 37 | i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj, |
| 38 | uint32_t read_domains, |
| 39 | uint32_t write_domain); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 40 | static void i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj); |
| 41 | static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj); |
| 42 | static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj); |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 43 | static int i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, |
| 44 | int write); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 45 | static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, |
| 46 | int write); |
| 47 | static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj, |
| 48 | uint64_t offset, |
| 49 | uint64_t size); |
| 50 | static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 51 | static int i915_gem_object_get_page_list(struct drm_gem_object *obj); |
| 52 | static void i915_gem_object_free_page_list(struct drm_gem_object *obj); |
| 53 | static int i915_gem_object_wait_rendering(struct drm_gem_object *obj); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame^] | 54 | static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, |
| 55 | unsigned alignment); |
| 56 | static void i915_gem_object_get_fence_reg(struct drm_gem_object *obj); |
| 57 | static void i915_gem_clear_fence_reg(struct drm_gem_object *obj); |
| 58 | static int i915_gem_evict_something(struct drm_device *dev); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 59 | |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 60 | static void |
| 61 | i915_gem_cleanup_ringbuffer(struct drm_device *dev); |
| 62 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 63 | int |
| 64 | i915_gem_init_ioctl(struct drm_device *dev, void *data, |
| 65 | struct drm_file *file_priv) |
| 66 | { |
| 67 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 68 | struct drm_i915_gem_init *args = data; |
| 69 | |
| 70 | mutex_lock(&dev->struct_mutex); |
| 71 | |
| 72 | if (args->gtt_start >= args->gtt_end || |
| 73 | (args->gtt_start & (PAGE_SIZE - 1)) != 0 || |
| 74 | (args->gtt_end & (PAGE_SIZE - 1)) != 0) { |
| 75 | mutex_unlock(&dev->struct_mutex); |
| 76 | return -EINVAL; |
| 77 | } |
| 78 | |
| 79 | drm_mm_init(&dev_priv->mm.gtt_space, args->gtt_start, |
| 80 | args->gtt_end - args->gtt_start); |
| 81 | |
| 82 | dev->gtt_total = (uint32_t) (args->gtt_end - args->gtt_start); |
| 83 | |
| 84 | mutex_unlock(&dev->struct_mutex); |
| 85 | |
| 86 | return 0; |
| 87 | } |
| 88 | |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 89 | int |
| 90 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, |
| 91 | struct drm_file *file_priv) |
| 92 | { |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 93 | struct drm_i915_gem_get_aperture *args = data; |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 94 | |
| 95 | if (!(dev->driver->driver_features & DRIVER_GEM)) |
| 96 | return -ENODEV; |
| 97 | |
| 98 | args->aper_size = dev->gtt_total; |
Keith Packard | 2678d9d | 2008-11-20 22:54:54 -0800 | [diff] [blame] | 99 | args->aper_available_size = (args->aper_size - |
| 100 | atomic_read(&dev->pin_memory)); |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 101 | |
| 102 | return 0; |
| 103 | } |
| 104 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 105 | |
| 106 | /** |
| 107 | * Creates a new mm object and returns a handle to it. |
| 108 | */ |
| 109 | int |
| 110 | i915_gem_create_ioctl(struct drm_device *dev, void *data, |
| 111 | struct drm_file *file_priv) |
| 112 | { |
| 113 | struct drm_i915_gem_create *args = data; |
| 114 | struct drm_gem_object *obj; |
| 115 | int handle, ret; |
| 116 | |
| 117 | args->size = roundup(args->size, PAGE_SIZE); |
| 118 | |
| 119 | /* Allocate the new object */ |
| 120 | obj = drm_gem_object_alloc(dev, args->size); |
| 121 | if (obj == NULL) |
| 122 | return -ENOMEM; |
| 123 | |
| 124 | ret = drm_gem_handle_create(file_priv, obj, &handle); |
| 125 | mutex_lock(&dev->struct_mutex); |
| 126 | drm_gem_object_handle_unreference(obj); |
| 127 | mutex_unlock(&dev->struct_mutex); |
| 128 | |
| 129 | if (ret) |
| 130 | return ret; |
| 131 | |
| 132 | args->handle = handle; |
| 133 | |
| 134 | return 0; |
| 135 | } |
| 136 | |
| 137 | /** |
| 138 | * Reads data from the object referenced by handle. |
| 139 | * |
| 140 | * On error, the contents of *data are undefined. |
| 141 | */ |
| 142 | int |
| 143 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, |
| 144 | struct drm_file *file_priv) |
| 145 | { |
| 146 | struct drm_i915_gem_pread *args = data; |
| 147 | struct drm_gem_object *obj; |
| 148 | struct drm_i915_gem_object *obj_priv; |
| 149 | ssize_t read; |
| 150 | loff_t offset; |
| 151 | int ret; |
| 152 | |
| 153 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
| 154 | if (obj == NULL) |
| 155 | return -EBADF; |
| 156 | obj_priv = obj->driver_private; |
| 157 | |
| 158 | /* Bounds check source. |
| 159 | * |
| 160 | * XXX: This could use review for overflow issues... |
| 161 | */ |
| 162 | if (args->offset > obj->size || args->size > obj->size || |
| 163 | args->offset + args->size > obj->size) { |
| 164 | drm_gem_object_unreference(obj); |
| 165 | return -EINVAL; |
| 166 | } |
| 167 | |
| 168 | mutex_lock(&dev->struct_mutex); |
| 169 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 170 | ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset, |
| 171 | args->size); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 172 | if (ret != 0) { |
| 173 | drm_gem_object_unreference(obj); |
| 174 | mutex_unlock(&dev->struct_mutex); |
Dave Airlie | e7d22bc | 2008-10-07 13:40:36 +1000 | [diff] [blame] | 175 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 176 | } |
| 177 | |
| 178 | offset = args->offset; |
| 179 | |
| 180 | read = vfs_read(obj->filp, (char __user *)(uintptr_t)args->data_ptr, |
| 181 | args->size, &offset); |
| 182 | if (read != args->size) { |
| 183 | drm_gem_object_unreference(obj); |
| 184 | mutex_unlock(&dev->struct_mutex); |
| 185 | if (read < 0) |
| 186 | return read; |
| 187 | else |
| 188 | return -EINVAL; |
| 189 | } |
| 190 | |
| 191 | drm_gem_object_unreference(obj); |
| 192 | mutex_unlock(&dev->struct_mutex); |
| 193 | |
| 194 | return 0; |
| 195 | } |
| 196 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 197 | /* This is the fast write path which cannot handle |
| 198 | * page faults in the source data |
Linus Torvalds | 9b7530cc | 2008-10-20 14:16:43 -0700 | [diff] [blame] | 199 | */ |
Linus Torvalds | 9b7530cc | 2008-10-20 14:16:43 -0700 | [diff] [blame] | 200 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 201 | static inline int |
| 202 | fast_user_write(struct io_mapping *mapping, |
| 203 | loff_t page_base, int page_offset, |
| 204 | char __user *user_data, |
| 205 | int length) |
| 206 | { |
| 207 | char *vaddr_atomic; |
| 208 | unsigned long unwritten; |
| 209 | |
| 210 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
| 211 | unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset, |
| 212 | user_data, length); |
| 213 | io_mapping_unmap_atomic(vaddr_atomic); |
| 214 | if (unwritten) |
| 215 | return -EFAULT; |
Linus Torvalds | 9b7530cc | 2008-10-20 14:16:43 -0700 | [diff] [blame] | 216 | return 0; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 217 | } |
| 218 | |
| 219 | /* Here's the write path which can sleep for |
| 220 | * page faults |
| 221 | */ |
| 222 | |
| 223 | static inline int |
| 224 | slow_user_write(struct io_mapping *mapping, |
| 225 | loff_t page_base, int page_offset, |
| 226 | char __user *user_data, |
| 227 | int length) |
| 228 | { |
| 229 | char __iomem *vaddr; |
| 230 | unsigned long unwritten; |
| 231 | |
| 232 | vaddr = io_mapping_map_wc(mapping, page_base); |
| 233 | if (vaddr == NULL) |
| 234 | return -EFAULT; |
| 235 | unwritten = __copy_from_user(vaddr + page_offset, |
| 236 | user_data, length); |
| 237 | io_mapping_unmap(vaddr); |
| 238 | if (unwritten) |
| 239 | return -EFAULT; |
| 240 | return 0; |
Linus Torvalds | 9b7530cc | 2008-10-20 14:16:43 -0700 | [diff] [blame] | 241 | } |
| 242 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 243 | static int |
| 244 | i915_gem_gtt_pwrite(struct drm_device *dev, struct drm_gem_object *obj, |
| 245 | struct drm_i915_gem_pwrite *args, |
| 246 | struct drm_file *file_priv) |
| 247 | { |
| 248 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 249 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 250 | ssize_t remain; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 251 | loff_t offset, page_base; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 252 | char __user *user_data; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 253 | int page_offset, page_length; |
| 254 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 255 | |
| 256 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
| 257 | remain = args->size; |
| 258 | if (!access_ok(VERIFY_READ, user_data, remain)) |
| 259 | return -EFAULT; |
| 260 | |
| 261 | |
| 262 | mutex_lock(&dev->struct_mutex); |
| 263 | ret = i915_gem_object_pin(obj, 0); |
| 264 | if (ret) { |
| 265 | mutex_unlock(&dev->struct_mutex); |
| 266 | return ret; |
| 267 | } |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 268 | ret = i915_gem_object_set_to_gtt_domain(obj, 1); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 269 | if (ret) |
| 270 | goto fail; |
| 271 | |
| 272 | obj_priv = obj->driver_private; |
| 273 | offset = obj_priv->gtt_offset + args->offset; |
| 274 | obj_priv->dirty = 1; |
| 275 | |
| 276 | while (remain > 0) { |
| 277 | /* Operation in this page |
| 278 | * |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 279 | * page_base = page offset within aperture |
| 280 | * page_offset = offset within page |
| 281 | * page_length = bytes to copy for this page |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 282 | */ |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 283 | page_base = (offset & ~(PAGE_SIZE-1)); |
| 284 | page_offset = offset & (PAGE_SIZE-1); |
| 285 | page_length = remain; |
| 286 | if ((page_offset + remain) > PAGE_SIZE) |
| 287 | page_length = PAGE_SIZE - page_offset; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 288 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 289 | ret = fast_user_write (dev_priv->mm.gtt_mapping, page_base, |
| 290 | page_offset, user_data, page_length); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 291 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 292 | /* If we get a fault while copying data, then (presumably) our |
| 293 | * source page isn't available. In this case, use the |
| 294 | * non-atomic function |
| 295 | */ |
| 296 | if (ret) { |
| 297 | ret = slow_user_write (dev_priv->mm.gtt_mapping, |
| 298 | page_base, page_offset, |
| 299 | user_data, page_length); |
| 300 | if (ret) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 301 | goto fail; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 302 | } |
| 303 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 304 | remain -= page_length; |
| 305 | user_data += page_length; |
| 306 | offset += page_length; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 307 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 308 | |
| 309 | fail: |
| 310 | i915_gem_object_unpin(obj); |
| 311 | mutex_unlock(&dev->struct_mutex); |
| 312 | |
| 313 | return ret; |
| 314 | } |
| 315 | |
Eric Anholt | 3043c60 | 2008-10-02 12:24:47 -0700 | [diff] [blame] | 316 | static int |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 317 | i915_gem_shmem_pwrite(struct drm_device *dev, struct drm_gem_object *obj, |
| 318 | struct drm_i915_gem_pwrite *args, |
| 319 | struct drm_file *file_priv) |
| 320 | { |
| 321 | int ret; |
| 322 | loff_t offset; |
| 323 | ssize_t written; |
| 324 | |
| 325 | mutex_lock(&dev->struct_mutex); |
| 326 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 327 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 328 | if (ret) { |
| 329 | mutex_unlock(&dev->struct_mutex); |
| 330 | return ret; |
| 331 | } |
| 332 | |
| 333 | offset = args->offset; |
| 334 | |
| 335 | written = vfs_write(obj->filp, |
| 336 | (char __user *)(uintptr_t) args->data_ptr, |
| 337 | args->size, &offset); |
| 338 | if (written != args->size) { |
| 339 | mutex_unlock(&dev->struct_mutex); |
| 340 | if (written < 0) |
| 341 | return written; |
| 342 | else |
| 343 | return -EINVAL; |
| 344 | } |
| 345 | |
| 346 | mutex_unlock(&dev->struct_mutex); |
| 347 | |
| 348 | return 0; |
| 349 | } |
| 350 | |
| 351 | /** |
| 352 | * Writes data to the object referenced by handle. |
| 353 | * |
| 354 | * On error, the contents of the buffer that were to be modified are undefined. |
| 355 | */ |
| 356 | int |
| 357 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, |
| 358 | struct drm_file *file_priv) |
| 359 | { |
| 360 | struct drm_i915_gem_pwrite *args = data; |
| 361 | struct drm_gem_object *obj; |
| 362 | struct drm_i915_gem_object *obj_priv; |
| 363 | int ret = 0; |
| 364 | |
| 365 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
| 366 | if (obj == NULL) |
| 367 | return -EBADF; |
| 368 | obj_priv = obj->driver_private; |
| 369 | |
| 370 | /* Bounds check destination. |
| 371 | * |
| 372 | * XXX: This could use review for overflow issues... |
| 373 | */ |
| 374 | if (args->offset > obj->size || args->size > obj->size || |
| 375 | args->offset + args->size > obj->size) { |
| 376 | drm_gem_object_unreference(obj); |
| 377 | return -EINVAL; |
| 378 | } |
| 379 | |
| 380 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
| 381 | * it would end up going through the fenced access, and we'll get |
| 382 | * different detiling behavior between reading and writing. |
| 383 | * pread/pwrite currently are reading and writing from the CPU |
| 384 | * perspective, requiring manual detiling by the client. |
| 385 | */ |
| 386 | if (obj_priv->tiling_mode == I915_TILING_NONE && |
| 387 | dev->gtt_total != 0) |
| 388 | ret = i915_gem_gtt_pwrite(dev, obj, args, file_priv); |
| 389 | else |
| 390 | ret = i915_gem_shmem_pwrite(dev, obj, args, file_priv); |
| 391 | |
| 392 | #if WATCH_PWRITE |
| 393 | if (ret) |
| 394 | DRM_INFO("pwrite failed %d\n", ret); |
| 395 | #endif |
| 396 | |
| 397 | drm_gem_object_unreference(obj); |
| 398 | |
| 399 | return ret; |
| 400 | } |
| 401 | |
| 402 | /** |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 403 | * Called when user space prepares to use an object with the CPU, either |
| 404 | * through the mmap ioctl's mapping or a GTT mapping. |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 405 | */ |
| 406 | int |
| 407 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
| 408 | struct drm_file *file_priv) |
| 409 | { |
| 410 | struct drm_i915_gem_set_domain *args = data; |
| 411 | struct drm_gem_object *obj; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 412 | uint32_t read_domains = args->read_domains; |
| 413 | uint32_t write_domain = args->write_domain; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 414 | int ret; |
| 415 | |
| 416 | if (!(dev->driver->driver_features & DRIVER_GEM)) |
| 417 | return -ENODEV; |
| 418 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 419 | /* Only handle setting domains to types used by the CPU. */ |
| 420 | if (write_domain & ~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT)) |
| 421 | return -EINVAL; |
| 422 | |
| 423 | if (read_domains & ~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT)) |
| 424 | return -EINVAL; |
| 425 | |
| 426 | /* Having something in the write domain implies it's in the read |
| 427 | * domain, and only that read domain. Enforce that in the request. |
| 428 | */ |
| 429 | if (write_domain != 0 && read_domains != write_domain) |
| 430 | return -EINVAL; |
| 431 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 432 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
| 433 | if (obj == NULL) |
| 434 | return -EBADF; |
| 435 | |
| 436 | mutex_lock(&dev->struct_mutex); |
| 437 | #if WATCH_BUF |
| 438 | DRM_INFO("set_domain_ioctl %p(%d), %08x %08x\n", |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 439 | obj, obj->size, read_domains, write_domain); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 440 | #endif |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 441 | if (read_domains & I915_GEM_DOMAIN_GTT) { |
| 442 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); |
Eric Anholt | 0235439 | 2008-11-26 13:58:13 -0800 | [diff] [blame] | 443 | |
| 444 | /* Silently promote "you're not bound, there was nothing to do" |
| 445 | * to success, since the client was just asking us to |
| 446 | * make sure everything was done. |
| 447 | */ |
| 448 | if (ret == -EINVAL) |
| 449 | ret = 0; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 450 | } else { |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 451 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 452 | } |
| 453 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 454 | drm_gem_object_unreference(obj); |
| 455 | mutex_unlock(&dev->struct_mutex); |
| 456 | return ret; |
| 457 | } |
| 458 | |
| 459 | /** |
| 460 | * Called when user space has done writes to this buffer |
| 461 | */ |
| 462 | int |
| 463 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, |
| 464 | struct drm_file *file_priv) |
| 465 | { |
| 466 | struct drm_i915_gem_sw_finish *args = data; |
| 467 | struct drm_gem_object *obj; |
| 468 | struct drm_i915_gem_object *obj_priv; |
| 469 | int ret = 0; |
| 470 | |
| 471 | if (!(dev->driver->driver_features & DRIVER_GEM)) |
| 472 | return -ENODEV; |
| 473 | |
| 474 | mutex_lock(&dev->struct_mutex); |
| 475 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
| 476 | if (obj == NULL) { |
| 477 | mutex_unlock(&dev->struct_mutex); |
| 478 | return -EBADF; |
| 479 | } |
| 480 | |
| 481 | #if WATCH_BUF |
| 482 | DRM_INFO("%s: sw_finish %d (%p %d)\n", |
| 483 | __func__, args->handle, obj, obj->size); |
| 484 | #endif |
| 485 | obj_priv = obj->driver_private; |
| 486 | |
| 487 | /* Pinned buffers may be scanout, so flush the cache */ |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 488 | if (obj_priv->pin_count) |
| 489 | i915_gem_object_flush_cpu_write_domain(obj); |
| 490 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 491 | drm_gem_object_unreference(obj); |
| 492 | mutex_unlock(&dev->struct_mutex); |
| 493 | return ret; |
| 494 | } |
| 495 | |
| 496 | /** |
| 497 | * Maps the contents of an object, returning the address it is mapped |
| 498 | * into. |
| 499 | * |
| 500 | * While the mapping holds a reference on the contents of the object, it doesn't |
| 501 | * imply a ref on the object itself. |
| 502 | */ |
| 503 | int |
| 504 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, |
| 505 | struct drm_file *file_priv) |
| 506 | { |
| 507 | struct drm_i915_gem_mmap *args = data; |
| 508 | struct drm_gem_object *obj; |
| 509 | loff_t offset; |
| 510 | unsigned long addr; |
| 511 | |
| 512 | if (!(dev->driver->driver_features & DRIVER_GEM)) |
| 513 | return -ENODEV; |
| 514 | |
| 515 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
| 516 | if (obj == NULL) |
| 517 | return -EBADF; |
| 518 | |
| 519 | offset = args->offset; |
| 520 | |
| 521 | down_write(¤t->mm->mmap_sem); |
| 522 | addr = do_mmap(obj->filp, 0, args->size, |
| 523 | PROT_READ | PROT_WRITE, MAP_SHARED, |
| 524 | args->offset); |
| 525 | up_write(¤t->mm->mmap_sem); |
| 526 | mutex_lock(&dev->struct_mutex); |
| 527 | drm_gem_object_unreference(obj); |
| 528 | mutex_unlock(&dev->struct_mutex); |
| 529 | if (IS_ERR((void *)addr)) |
| 530 | return addr; |
| 531 | |
| 532 | args->addr_ptr = (uint64_t) addr; |
| 533 | |
| 534 | return 0; |
| 535 | } |
| 536 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame^] | 537 | /** |
| 538 | * i915_gem_fault - fault a page into the GTT |
| 539 | * vma: VMA in question |
| 540 | * vmf: fault info |
| 541 | * |
| 542 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped |
| 543 | * from userspace. The fault handler takes care of binding the object to |
| 544 | * the GTT (if needed), allocating and programming a fence register (again, |
| 545 | * only if needed based on whether the old reg is still valid or the object |
| 546 | * is tiled) and inserting a new PTE into the faulting process. |
| 547 | * |
| 548 | * Note that the faulting process may involve evicting existing objects |
| 549 | * from the GTT and/or fence registers to make room. So performance may |
| 550 | * suffer if the GTT working set is large or there are few fence registers |
| 551 | * left. |
| 552 | */ |
| 553 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) |
| 554 | { |
| 555 | struct drm_gem_object *obj = vma->vm_private_data; |
| 556 | struct drm_device *dev = obj->dev; |
| 557 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 558 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 559 | pgoff_t page_offset; |
| 560 | unsigned long pfn; |
| 561 | int ret = 0; |
| 562 | |
| 563 | /* We don't use vmf->pgoff since that has the fake offset */ |
| 564 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> |
| 565 | PAGE_SHIFT; |
| 566 | |
| 567 | /* Now bind it into the GTT if needed */ |
| 568 | mutex_lock(&dev->struct_mutex); |
| 569 | if (!obj_priv->gtt_space) { |
| 570 | ret = i915_gem_object_bind_to_gtt(obj, obj_priv->gtt_alignment); |
| 571 | if (ret) { |
| 572 | mutex_unlock(&dev->struct_mutex); |
| 573 | return VM_FAULT_SIGBUS; |
| 574 | } |
| 575 | list_add(&obj_priv->list, &dev_priv->mm.inactive_list); |
| 576 | } |
| 577 | |
| 578 | /* Need a new fence register? */ |
| 579 | if (obj_priv->fence_reg == I915_FENCE_REG_NONE && |
| 580 | obj_priv->tiling_mode != I915_TILING_NONE) |
| 581 | i915_gem_object_get_fence_reg(obj); |
| 582 | |
| 583 | pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) + |
| 584 | page_offset; |
| 585 | |
| 586 | /* Finally, remap it using the new GTT offset */ |
| 587 | ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn); |
| 588 | |
| 589 | mutex_unlock(&dev->struct_mutex); |
| 590 | |
| 591 | switch (ret) { |
| 592 | case -ENOMEM: |
| 593 | case -EAGAIN: |
| 594 | return VM_FAULT_OOM; |
| 595 | case -EFAULT: |
| 596 | case -EBUSY: |
| 597 | DRM_ERROR("can't insert pfn?? fault or busy...\n"); |
| 598 | return VM_FAULT_SIGBUS; |
| 599 | default: |
| 600 | return VM_FAULT_NOPAGE; |
| 601 | } |
| 602 | } |
| 603 | |
| 604 | /** |
| 605 | * i915_gem_create_mmap_offset - create a fake mmap offset for an object |
| 606 | * @obj: obj in question |
| 607 | * |
| 608 | * GEM memory mapping works by handing back to userspace a fake mmap offset |
| 609 | * it can use in a subsequent mmap(2) call. The DRM core code then looks |
| 610 | * up the object based on the offset and sets up the various memory mapping |
| 611 | * structures. |
| 612 | * |
| 613 | * This routine allocates and attaches a fake offset for @obj. |
| 614 | */ |
| 615 | static int |
| 616 | i915_gem_create_mmap_offset(struct drm_gem_object *obj) |
| 617 | { |
| 618 | struct drm_device *dev = obj->dev; |
| 619 | struct drm_gem_mm *mm = dev->mm_private; |
| 620 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 621 | struct drm_map_list *list; |
| 622 | struct drm_map *map; |
| 623 | int ret = 0; |
| 624 | |
| 625 | /* Set the object up for mmap'ing */ |
| 626 | list = &obj->map_list; |
| 627 | list->map = drm_calloc(1, sizeof(struct drm_map_list), |
| 628 | DRM_MEM_DRIVER); |
| 629 | if (!list->map) |
| 630 | return -ENOMEM; |
| 631 | |
| 632 | map = list->map; |
| 633 | map->type = _DRM_GEM; |
| 634 | map->size = obj->size; |
| 635 | map->handle = obj; |
| 636 | |
| 637 | /* Get a DRM GEM mmap offset allocated... */ |
| 638 | list->file_offset_node = drm_mm_search_free(&mm->offset_manager, |
| 639 | obj->size / PAGE_SIZE, 0, 0); |
| 640 | if (!list->file_offset_node) { |
| 641 | DRM_ERROR("failed to allocate offset for bo %d\n", obj->name); |
| 642 | ret = -ENOMEM; |
| 643 | goto out_free_list; |
| 644 | } |
| 645 | |
| 646 | list->file_offset_node = drm_mm_get_block(list->file_offset_node, |
| 647 | obj->size / PAGE_SIZE, 0); |
| 648 | if (!list->file_offset_node) { |
| 649 | ret = -ENOMEM; |
| 650 | goto out_free_list; |
| 651 | } |
| 652 | |
| 653 | list->hash.key = list->file_offset_node->start; |
| 654 | if (drm_ht_insert_item(&mm->offset_hash, &list->hash)) { |
| 655 | DRM_ERROR("failed to add to map hash\n"); |
| 656 | goto out_free_mm; |
| 657 | } |
| 658 | |
| 659 | /* By now we should be all set, any drm_mmap request on the offset |
| 660 | * below will get to our mmap & fault handler */ |
| 661 | obj_priv->mmap_offset = ((uint64_t) list->hash.key) << PAGE_SHIFT; |
| 662 | |
| 663 | return 0; |
| 664 | |
| 665 | out_free_mm: |
| 666 | drm_mm_put_block(list->file_offset_node); |
| 667 | out_free_list: |
| 668 | drm_free(list->map, sizeof(struct drm_map_list), DRM_MEM_DRIVER); |
| 669 | |
| 670 | return ret; |
| 671 | } |
| 672 | |
| 673 | /** |
| 674 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object |
| 675 | * @obj: object to check |
| 676 | * |
| 677 | * Return the required GTT alignment for an object, taking into account |
| 678 | * potential fence register mapping if needed. |
| 679 | */ |
| 680 | static uint32_t |
| 681 | i915_gem_get_gtt_alignment(struct drm_gem_object *obj) |
| 682 | { |
| 683 | struct drm_device *dev = obj->dev; |
| 684 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 685 | int start, i; |
| 686 | |
| 687 | /* |
| 688 | * Minimum alignment is 4k (GTT page size), but might be greater |
| 689 | * if a fence register is needed for the object. |
| 690 | */ |
| 691 | if (IS_I965G(dev) || obj_priv->tiling_mode == I915_TILING_NONE) |
| 692 | return 4096; |
| 693 | |
| 694 | /* |
| 695 | * Previous chips need to be aligned to the size of the smallest |
| 696 | * fence register that can contain the object. |
| 697 | */ |
| 698 | if (IS_I9XX(dev)) |
| 699 | start = 1024*1024; |
| 700 | else |
| 701 | start = 512*1024; |
| 702 | |
| 703 | for (i = start; i < obj->size; i <<= 1) |
| 704 | ; |
| 705 | |
| 706 | return i; |
| 707 | } |
| 708 | |
| 709 | /** |
| 710 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing |
| 711 | * @dev: DRM device |
| 712 | * @data: GTT mapping ioctl data |
| 713 | * @file_priv: GEM object info |
| 714 | * |
| 715 | * Simply returns the fake offset to userspace so it can mmap it. |
| 716 | * The mmap call will end up in drm_gem_mmap(), which will set things |
| 717 | * up so we can get faults in the handler above. |
| 718 | * |
| 719 | * The fault handler will take care of binding the object into the GTT |
| 720 | * (since it may have been evicted to make room for something), allocating |
| 721 | * a fence register, and mapping the appropriate aperture address into |
| 722 | * userspace. |
| 723 | */ |
| 724 | int |
| 725 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, |
| 726 | struct drm_file *file_priv) |
| 727 | { |
| 728 | struct drm_i915_gem_mmap_gtt *args = data; |
| 729 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 730 | struct drm_gem_object *obj; |
| 731 | struct drm_i915_gem_object *obj_priv; |
| 732 | int ret; |
| 733 | |
| 734 | if (!(dev->driver->driver_features & DRIVER_GEM)) |
| 735 | return -ENODEV; |
| 736 | |
| 737 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
| 738 | if (obj == NULL) |
| 739 | return -EBADF; |
| 740 | |
| 741 | mutex_lock(&dev->struct_mutex); |
| 742 | |
| 743 | obj_priv = obj->driver_private; |
| 744 | |
| 745 | if (!obj_priv->mmap_offset) { |
| 746 | ret = i915_gem_create_mmap_offset(obj); |
| 747 | if (ret) |
| 748 | return ret; |
| 749 | } |
| 750 | |
| 751 | args->offset = obj_priv->mmap_offset; |
| 752 | |
| 753 | obj_priv->gtt_alignment = i915_gem_get_gtt_alignment(obj); |
| 754 | |
| 755 | /* Make sure the alignment is correct for fence regs etc */ |
| 756 | if (obj_priv->agp_mem && |
| 757 | (obj_priv->gtt_offset & (obj_priv->gtt_alignment - 1))) { |
| 758 | drm_gem_object_unreference(obj); |
| 759 | mutex_unlock(&dev->struct_mutex); |
| 760 | return -EINVAL; |
| 761 | } |
| 762 | |
| 763 | /* |
| 764 | * Pull it into the GTT so that we have a page list (makes the |
| 765 | * initial fault faster and any subsequent flushing possible). |
| 766 | */ |
| 767 | if (!obj_priv->agp_mem) { |
| 768 | ret = i915_gem_object_bind_to_gtt(obj, obj_priv->gtt_alignment); |
| 769 | if (ret) { |
| 770 | drm_gem_object_unreference(obj); |
| 771 | mutex_unlock(&dev->struct_mutex); |
| 772 | return ret; |
| 773 | } |
| 774 | list_add(&obj_priv->list, &dev_priv->mm.inactive_list); |
| 775 | } |
| 776 | |
| 777 | drm_gem_object_unreference(obj); |
| 778 | mutex_unlock(&dev->struct_mutex); |
| 779 | |
| 780 | return 0; |
| 781 | } |
| 782 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 783 | static void |
| 784 | i915_gem_object_free_page_list(struct drm_gem_object *obj) |
| 785 | { |
| 786 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 787 | int page_count = obj->size / PAGE_SIZE; |
| 788 | int i; |
| 789 | |
| 790 | if (obj_priv->page_list == NULL) |
| 791 | return; |
| 792 | |
| 793 | |
| 794 | for (i = 0; i < page_count; i++) |
| 795 | if (obj_priv->page_list[i] != NULL) { |
| 796 | if (obj_priv->dirty) |
| 797 | set_page_dirty(obj_priv->page_list[i]); |
| 798 | mark_page_accessed(obj_priv->page_list[i]); |
| 799 | page_cache_release(obj_priv->page_list[i]); |
| 800 | } |
| 801 | obj_priv->dirty = 0; |
| 802 | |
| 803 | drm_free(obj_priv->page_list, |
| 804 | page_count * sizeof(struct page *), |
| 805 | DRM_MEM_DRIVER); |
| 806 | obj_priv->page_list = NULL; |
| 807 | } |
| 808 | |
| 809 | static void |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 810 | i915_gem_object_move_to_active(struct drm_gem_object *obj, uint32_t seqno) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 811 | { |
| 812 | struct drm_device *dev = obj->dev; |
| 813 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 814 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 815 | |
| 816 | /* Add a reference if we're newly entering the active list. */ |
| 817 | if (!obj_priv->active) { |
| 818 | drm_gem_object_reference(obj); |
| 819 | obj_priv->active = 1; |
| 820 | } |
| 821 | /* Move from whatever list we were on to the tail of execution. */ |
| 822 | list_move_tail(&obj_priv->list, |
| 823 | &dev_priv->mm.active_list); |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 824 | obj_priv->last_rendering_seqno = seqno; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 825 | } |
| 826 | |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 827 | static void |
| 828 | i915_gem_object_move_to_flushing(struct drm_gem_object *obj) |
| 829 | { |
| 830 | struct drm_device *dev = obj->dev; |
| 831 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 832 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 833 | |
| 834 | BUG_ON(!obj_priv->active); |
| 835 | list_move_tail(&obj_priv->list, &dev_priv->mm.flushing_list); |
| 836 | obj_priv->last_rendering_seqno = 0; |
| 837 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 838 | |
| 839 | static void |
| 840 | i915_gem_object_move_to_inactive(struct drm_gem_object *obj) |
| 841 | { |
| 842 | struct drm_device *dev = obj->dev; |
| 843 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 844 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 845 | |
| 846 | i915_verify_inactive(dev, __FILE__, __LINE__); |
| 847 | if (obj_priv->pin_count != 0) |
| 848 | list_del_init(&obj_priv->list); |
| 849 | else |
| 850 | list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list); |
| 851 | |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 852 | obj_priv->last_rendering_seqno = 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 853 | if (obj_priv->active) { |
| 854 | obj_priv->active = 0; |
| 855 | drm_gem_object_unreference(obj); |
| 856 | } |
| 857 | i915_verify_inactive(dev, __FILE__, __LINE__); |
| 858 | } |
| 859 | |
| 860 | /** |
| 861 | * Creates a new sequence number, emitting a write of it to the status page |
| 862 | * plus an interrupt, which will trigger i915_user_interrupt_handler. |
| 863 | * |
| 864 | * Must be called with struct_lock held. |
| 865 | * |
| 866 | * Returned sequence numbers are nonzero on success. |
| 867 | */ |
| 868 | static uint32_t |
| 869 | i915_add_request(struct drm_device *dev, uint32_t flush_domains) |
| 870 | { |
| 871 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 872 | struct drm_i915_gem_request *request; |
| 873 | uint32_t seqno; |
| 874 | int was_empty; |
| 875 | RING_LOCALS; |
| 876 | |
| 877 | request = drm_calloc(1, sizeof(*request), DRM_MEM_DRIVER); |
| 878 | if (request == NULL) |
| 879 | return 0; |
| 880 | |
| 881 | /* Grab the seqno we're going to make this request be, and bump the |
| 882 | * next (skipping 0 so it can be the reserved no-seqno value). |
| 883 | */ |
| 884 | seqno = dev_priv->mm.next_gem_seqno; |
| 885 | dev_priv->mm.next_gem_seqno++; |
| 886 | if (dev_priv->mm.next_gem_seqno == 0) |
| 887 | dev_priv->mm.next_gem_seqno++; |
| 888 | |
| 889 | BEGIN_LP_RING(4); |
| 890 | OUT_RING(MI_STORE_DWORD_INDEX); |
| 891 | OUT_RING(I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); |
| 892 | OUT_RING(seqno); |
| 893 | |
| 894 | OUT_RING(MI_USER_INTERRUPT); |
| 895 | ADVANCE_LP_RING(); |
| 896 | |
| 897 | DRM_DEBUG("%d\n", seqno); |
| 898 | |
| 899 | request->seqno = seqno; |
| 900 | request->emitted_jiffies = jiffies; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 901 | was_empty = list_empty(&dev_priv->mm.request_list); |
| 902 | list_add_tail(&request->list, &dev_priv->mm.request_list); |
| 903 | |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 904 | /* Associate any objects on the flushing list matching the write |
| 905 | * domain we're flushing with our flush. |
| 906 | */ |
| 907 | if (flush_domains != 0) { |
| 908 | struct drm_i915_gem_object *obj_priv, *next; |
| 909 | |
| 910 | list_for_each_entry_safe(obj_priv, next, |
| 911 | &dev_priv->mm.flushing_list, list) { |
| 912 | struct drm_gem_object *obj = obj_priv->obj; |
| 913 | |
| 914 | if ((obj->write_domain & flush_domains) == |
| 915 | obj->write_domain) { |
| 916 | obj->write_domain = 0; |
| 917 | i915_gem_object_move_to_active(obj, seqno); |
| 918 | } |
| 919 | } |
| 920 | |
| 921 | } |
| 922 | |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 923 | if (was_empty && !dev_priv->mm.suspended) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 924 | schedule_delayed_work(&dev_priv->mm.retire_work, HZ); |
| 925 | return seqno; |
| 926 | } |
| 927 | |
| 928 | /** |
| 929 | * Command execution barrier |
| 930 | * |
| 931 | * Ensures that all commands in the ring are finished |
| 932 | * before signalling the CPU |
| 933 | */ |
Eric Anholt | 3043c60 | 2008-10-02 12:24:47 -0700 | [diff] [blame] | 934 | static uint32_t |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 935 | i915_retire_commands(struct drm_device *dev) |
| 936 | { |
| 937 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 938 | uint32_t cmd = MI_FLUSH | MI_NO_WRITE_FLUSH; |
| 939 | uint32_t flush_domains = 0; |
| 940 | RING_LOCALS; |
| 941 | |
| 942 | /* The sampler always gets flushed on i965 (sigh) */ |
| 943 | if (IS_I965G(dev)) |
| 944 | flush_domains |= I915_GEM_DOMAIN_SAMPLER; |
| 945 | BEGIN_LP_RING(2); |
| 946 | OUT_RING(cmd); |
| 947 | OUT_RING(0); /* noop */ |
| 948 | ADVANCE_LP_RING(); |
| 949 | return flush_domains; |
| 950 | } |
| 951 | |
| 952 | /** |
| 953 | * Moves buffers associated only with the given active seqno from the active |
| 954 | * to inactive list, potentially freeing them. |
| 955 | */ |
| 956 | static void |
| 957 | i915_gem_retire_request(struct drm_device *dev, |
| 958 | struct drm_i915_gem_request *request) |
| 959 | { |
| 960 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 961 | |
| 962 | /* Move any buffers on the active list that are no longer referenced |
| 963 | * by the ringbuffer to the flushing/inactive lists as appropriate. |
| 964 | */ |
| 965 | while (!list_empty(&dev_priv->mm.active_list)) { |
| 966 | struct drm_gem_object *obj; |
| 967 | struct drm_i915_gem_object *obj_priv; |
| 968 | |
| 969 | obj_priv = list_first_entry(&dev_priv->mm.active_list, |
| 970 | struct drm_i915_gem_object, |
| 971 | list); |
| 972 | obj = obj_priv->obj; |
| 973 | |
| 974 | /* If the seqno being retired doesn't match the oldest in the |
| 975 | * list, then the oldest in the list must still be newer than |
| 976 | * this seqno. |
| 977 | */ |
| 978 | if (obj_priv->last_rendering_seqno != request->seqno) |
| 979 | return; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame^] | 980 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 981 | #if WATCH_LRU |
| 982 | DRM_INFO("%s: retire %d moves to inactive list %p\n", |
| 983 | __func__, request->seqno, obj); |
| 984 | #endif |
| 985 | |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 986 | if (obj->write_domain != 0) |
| 987 | i915_gem_object_move_to_flushing(obj); |
| 988 | else |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 989 | i915_gem_object_move_to_inactive(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 990 | } |
| 991 | } |
| 992 | |
| 993 | /** |
| 994 | * Returns true if seq1 is later than seq2. |
| 995 | */ |
| 996 | static int |
| 997 | i915_seqno_passed(uint32_t seq1, uint32_t seq2) |
| 998 | { |
| 999 | return (int32_t)(seq1 - seq2) >= 0; |
| 1000 | } |
| 1001 | |
| 1002 | uint32_t |
| 1003 | i915_get_gem_seqno(struct drm_device *dev) |
| 1004 | { |
| 1005 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1006 | |
| 1007 | return READ_HWSP(dev_priv, I915_GEM_HWS_INDEX); |
| 1008 | } |
| 1009 | |
| 1010 | /** |
| 1011 | * This function clears the request list as sequence numbers are passed. |
| 1012 | */ |
| 1013 | void |
| 1014 | i915_gem_retire_requests(struct drm_device *dev) |
| 1015 | { |
| 1016 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1017 | uint32_t seqno; |
| 1018 | |
| 1019 | seqno = i915_get_gem_seqno(dev); |
| 1020 | |
| 1021 | while (!list_empty(&dev_priv->mm.request_list)) { |
| 1022 | struct drm_i915_gem_request *request; |
| 1023 | uint32_t retiring_seqno; |
| 1024 | |
| 1025 | request = list_first_entry(&dev_priv->mm.request_list, |
| 1026 | struct drm_i915_gem_request, |
| 1027 | list); |
| 1028 | retiring_seqno = request->seqno; |
| 1029 | |
| 1030 | if (i915_seqno_passed(seqno, retiring_seqno) || |
| 1031 | dev_priv->mm.wedged) { |
| 1032 | i915_gem_retire_request(dev, request); |
| 1033 | |
| 1034 | list_del(&request->list); |
| 1035 | drm_free(request, sizeof(*request), DRM_MEM_DRIVER); |
| 1036 | } else |
| 1037 | break; |
| 1038 | } |
| 1039 | } |
| 1040 | |
| 1041 | void |
| 1042 | i915_gem_retire_work_handler(struct work_struct *work) |
| 1043 | { |
| 1044 | drm_i915_private_t *dev_priv; |
| 1045 | struct drm_device *dev; |
| 1046 | |
| 1047 | dev_priv = container_of(work, drm_i915_private_t, |
| 1048 | mm.retire_work.work); |
| 1049 | dev = dev_priv->dev; |
| 1050 | |
| 1051 | mutex_lock(&dev->struct_mutex); |
| 1052 | i915_gem_retire_requests(dev); |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 1053 | if (!dev_priv->mm.suspended && |
| 1054 | !list_empty(&dev_priv->mm.request_list)) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1055 | schedule_delayed_work(&dev_priv->mm.retire_work, HZ); |
| 1056 | mutex_unlock(&dev->struct_mutex); |
| 1057 | } |
| 1058 | |
| 1059 | /** |
| 1060 | * Waits for a sequence number to be signaled, and cleans up the |
| 1061 | * request and object lists appropriately for that event. |
| 1062 | */ |
Eric Anholt | 3043c60 | 2008-10-02 12:24:47 -0700 | [diff] [blame] | 1063 | static int |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1064 | i915_wait_request(struct drm_device *dev, uint32_t seqno) |
| 1065 | { |
| 1066 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1067 | int ret = 0; |
| 1068 | |
| 1069 | BUG_ON(seqno == 0); |
| 1070 | |
| 1071 | if (!i915_seqno_passed(i915_get_gem_seqno(dev), seqno)) { |
| 1072 | dev_priv->mm.waiting_gem_seqno = seqno; |
| 1073 | i915_user_irq_get(dev); |
| 1074 | ret = wait_event_interruptible(dev_priv->irq_queue, |
| 1075 | i915_seqno_passed(i915_get_gem_seqno(dev), |
| 1076 | seqno) || |
| 1077 | dev_priv->mm.wedged); |
| 1078 | i915_user_irq_put(dev); |
| 1079 | dev_priv->mm.waiting_gem_seqno = 0; |
| 1080 | } |
| 1081 | if (dev_priv->mm.wedged) |
| 1082 | ret = -EIO; |
| 1083 | |
| 1084 | if (ret && ret != -ERESTARTSYS) |
| 1085 | DRM_ERROR("%s returns %d (awaiting %d at %d)\n", |
| 1086 | __func__, ret, seqno, i915_get_gem_seqno(dev)); |
| 1087 | |
| 1088 | /* Directly dispatch request retiring. While we have the work queue |
| 1089 | * to handle this, the waiter on a request often wants an associated |
| 1090 | * buffer to have made it to the inactive list, and we would need |
| 1091 | * a separate wait queue to handle that. |
| 1092 | */ |
| 1093 | if (ret == 0) |
| 1094 | i915_gem_retire_requests(dev); |
| 1095 | |
| 1096 | return ret; |
| 1097 | } |
| 1098 | |
| 1099 | static void |
| 1100 | i915_gem_flush(struct drm_device *dev, |
| 1101 | uint32_t invalidate_domains, |
| 1102 | uint32_t flush_domains) |
| 1103 | { |
| 1104 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1105 | uint32_t cmd; |
| 1106 | RING_LOCALS; |
| 1107 | |
| 1108 | #if WATCH_EXEC |
| 1109 | DRM_INFO("%s: invalidate %08x flush %08x\n", __func__, |
| 1110 | invalidate_domains, flush_domains); |
| 1111 | #endif |
| 1112 | |
| 1113 | if (flush_domains & I915_GEM_DOMAIN_CPU) |
| 1114 | drm_agp_chipset_flush(dev); |
| 1115 | |
| 1116 | if ((invalidate_domains | flush_domains) & ~(I915_GEM_DOMAIN_CPU | |
| 1117 | I915_GEM_DOMAIN_GTT)) { |
| 1118 | /* |
| 1119 | * read/write caches: |
| 1120 | * |
| 1121 | * I915_GEM_DOMAIN_RENDER is always invalidated, but is |
| 1122 | * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is |
| 1123 | * also flushed at 2d versus 3d pipeline switches. |
| 1124 | * |
| 1125 | * read-only caches: |
| 1126 | * |
| 1127 | * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if |
| 1128 | * MI_READ_FLUSH is set, and is always flushed on 965. |
| 1129 | * |
| 1130 | * I915_GEM_DOMAIN_COMMAND may not exist? |
| 1131 | * |
| 1132 | * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is |
| 1133 | * invalidated when MI_EXE_FLUSH is set. |
| 1134 | * |
| 1135 | * I915_GEM_DOMAIN_VERTEX, which exists on 965, is |
| 1136 | * invalidated with every MI_FLUSH. |
| 1137 | * |
| 1138 | * TLBs: |
| 1139 | * |
| 1140 | * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND |
| 1141 | * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and |
| 1142 | * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER |
| 1143 | * are flushed at any MI_FLUSH. |
| 1144 | */ |
| 1145 | |
| 1146 | cmd = MI_FLUSH | MI_NO_WRITE_FLUSH; |
| 1147 | if ((invalidate_domains|flush_domains) & |
| 1148 | I915_GEM_DOMAIN_RENDER) |
| 1149 | cmd &= ~MI_NO_WRITE_FLUSH; |
| 1150 | if (!IS_I965G(dev)) { |
| 1151 | /* |
| 1152 | * On the 965, the sampler cache always gets flushed |
| 1153 | * and this bit is reserved. |
| 1154 | */ |
| 1155 | if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER) |
| 1156 | cmd |= MI_READ_FLUSH; |
| 1157 | } |
| 1158 | if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION) |
| 1159 | cmd |= MI_EXE_FLUSH; |
| 1160 | |
| 1161 | #if WATCH_EXEC |
| 1162 | DRM_INFO("%s: queue flush %08x to ring\n", __func__, cmd); |
| 1163 | #endif |
| 1164 | BEGIN_LP_RING(2); |
| 1165 | OUT_RING(cmd); |
| 1166 | OUT_RING(0); /* noop */ |
| 1167 | ADVANCE_LP_RING(); |
| 1168 | } |
| 1169 | } |
| 1170 | |
| 1171 | /** |
| 1172 | * Ensures that all rendering to the object has completed and the object is |
| 1173 | * safe to unbind from the GTT or access from the CPU. |
| 1174 | */ |
| 1175 | static int |
| 1176 | i915_gem_object_wait_rendering(struct drm_gem_object *obj) |
| 1177 | { |
| 1178 | struct drm_device *dev = obj->dev; |
| 1179 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 1180 | int ret; |
| 1181 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 1182 | /* This function only exists to support waiting for existing rendering, |
| 1183 | * not for emitting required flushes. |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1184 | */ |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 1185 | BUG_ON((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1186 | |
| 1187 | /* If there is rendering queued on the buffer being evicted, wait for |
| 1188 | * it. |
| 1189 | */ |
| 1190 | if (obj_priv->active) { |
| 1191 | #if WATCH_BUF |
| 1192 | DRM_INFO("%s: object %p wait for seqno %08x\n", |
| 1193 | __func__, obj, obj_priv->last_rendering_seqno); |
| 1194 | #endif |
| 1195 | ret = i915_wait_request(dev, obj_priv->last_rendering_seqno); |
| 1196 | if (ret != 0) |
| 1197 | return ret; |
| 1198 | } |
| 1199 | |
| 1200 | return 0; |
| 1201 | } |
| 1202 | |
| 1203 | /** |
| 1204 | * Unbinds an object from the GTT aperture. |
| 1205 | */ |
| 1206 | static int |
| 1207 | i915_gem_object_unbind(struct drm_gem_object *obj) |
| 1208 | { |
| 1209 | struct drm_device *dev = obj->dev; |
| 1210 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame^] | 1211 | loff_t offset; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1212 | int ret = 0; |
| 1213 | |
| 1214 | #if WATCH_BUF |
| 1215 | DRM_INFO("%s:%d %p\n", __func__, __LINE__, obj); |
| 1216 | DRM_INFO("gtt_space %p\n", obj_priv->gtt_space); |
| 1217 | #endif |
| 1218 | if (obj_priv->gtt_space == NULL) |
| 1219 | return 0; |
| 1220 | |
| 1221 | if (obj_priv->pin_count != 0) { |
| 1222 | DRM_ERROR("Attempting to unbind pinned buffer\n"); |
| 1223 | return -EINVAL; |
| 1224 | } |
| 1225 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1226 | /* Move the object to the CPU domain to ensure that |
| 1227 | * any possible CPU writes while it's not in the GTT |
| 1228 | * are flushed when we go to remap it. This will |
| 1229 | * also ensure that all pending GPU writes are finished |
| 1230 | * before we unbind. |
| 1231 | */ |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 1232 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1233 | if (ret) { |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 1234 | if (ret != -ERESTARTSYS) |
| 1235 | DRM_ERROR("set_domain failed: %d\n", ret); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1236 | return ret; |
| 1237 | } |
| 1238 | |
| 1239 | if (obj_priv->agp_mem != NULL) { |
| 1240 | drm_unbind_agp(obj_priv->agp_mem); |
| 1241 | drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE); |
| 1242 | obj_priv->agp_mem = NULL; |
| 1243 | } |
| 1244 | |
| 1245 | BUG_ON(obj_priv->active); |
| 1246 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame^] | 1247 | /* blow away mappings if mapped through GTT */ |
| 1248 | offset = ((loff_t) obj->map_list.hash.key) << PAGE_SHIFT; |
| 1249 | unmap_mapping_range(dev->dev_mapping, offset, obj->size, 1); |
| 1250 | |
| 1251 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) |
| 1252 | i915_gem_clear_fence_reg(obj); |
| 1253 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1254 | i915_gem_object_free_page_list(obj); |
| 1255 | |
| 1256 | if (obj_priv->gtt_space) { |
| 1257 | atomic_dec(&dev->gtt_count); |
| 1258 | atomic_sub(obj->size, &dev->gtt_memory); |
| 1259 | |
| 1260 | drm_mm_put_block(obj_priv->gtt_space); |
| 1261 | obj_priv->gtt_space = NULL; |
| 1262 | } |
| 1263 | |
| 1264 | /* Remove ourselves from the LRU list if present. */ |
| 1265 | if (!list_empty(&obj_priv->list)) |
| 1266 | list_del_init(&obj_priv->list); |
| 1267 | |
| 1268 | return 0; |
| 1269 | } |
| 1270 | |
| 1271 | static int |
| 1272 | i915_gem_evict_something(struct drm_device *dev) |
| 1273 | { |
| 1274 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1275 | struct drm_gem_object *obj; |
| 1276 | struct drm_i915_gem_object *obj_priv; |
| 1277 | int ret = 0; |
| 1278 | |
| 1279 | for (;;) { |
| 1280 | /* If there's an inactive buffer available now, grab it |
| 1281 | * and be done. |
| 1282 | */ |
| 1283 | if (!list_empty(&dev_priv->mm.inactive_list)) { |
| 1284 | obj_priv = list_first_entry(&dev_priv->mm.inactive_list, |
| 1285 | struct drm_i915_gem_object, |
| 1286 | list); |
| 1287 | obj = obj_priv->obj; |
| 1288 | BUG_ON(obj_priv->pin_count != 0); |
| 1289 | #if WATCH_LRU |
| 1290 | DRM_INFO("%s: evicting %p\n", __func__, obj); |
| 1291 | #endif |
| 1292 | BUG_ON(obj_priv->active); |
| 1293 | |
| 1294 | /* Wait on the rendering and unbind the buffer. */ |
| 1295 | ret = i915_gem_object_unbind(obj); |
| 1296 | break; |
| 1297 | } |
| 1298 | |
| 1299 | /* If we didn't get anything, but the ring is still processing |
| 1300 | * things, wait for one of those things to finish and hopefully |
| 1301 | * leave us a buffer to evict. |
| 1302 | */ |
| 1303 | if (!list_empty(&dev_priv->mm.request_list)) { |
| 1304 | struct drm_i915_gem_request *request; |
| 1305 | |
| 1306 | request = list_first_entry(&dev_priv->mm.request_list, |
| 1307 | struct drm_i915_gem_request, |
| 1308 | list); |
| 1309 | |
| 1310 | ret = i915_wait_request(dev, request->seqno); |
| 1311 | if (ret) |
| 1312 | break; |
| 1313 | |
| 1314 | /* if waiting caused an object to become inactive, |
| 1315 | * then loop around and wait for it. Otherwise, we |
| 1316 | * assume that waiting freed and unbound something, |
| 1317 | * so there should now be some space in the GTT |
| 1318 | */ |
| 1319 | if (!list_empty(&dev_priv->mm.inactive_list)) |
| 1320 | continue; |
| 1321 | break; |
| 1322 | } |
| 1323 | |
| 1324 | /* If we didn't have anything on the request list but there |
| 1325 | * are buffers awaiting a flush, emit one and try again. |
| 1326 | * When we wait on it, those buffers waiting for that flush |
| 1327 | * will get moved to inactive. |
| 1328 | */ |
| 1329 | if (!list_empty(&dev_priv->mm.flushing_list)) { |
| 1330 | obj_priv = list_first_entry(&dev_priv->mm.flushing_list, |
| 1331 | struct drm_i915_gem_object, |
| 1332 | list); |
| 1333 | obj = obj_priv->obj; |
| 1334 | |
| 1335 | i915_gem_flush(dev, |
| 1336 | obj->write_domain, |
| 1337 | obj->write_domain); |
| 1338 | i915_add_request(dev, obj->write_domain); |
| 1339 | |
| 1340 | obj = NULL; |
| 1341 | continue; |
| 1342 | } |
| 1343 | |
| 1344 | DRM_ERROR("inactive empty %d request empty %d " |
| 1345 | "flushing empty %d\n", |
| 1346 | list_empty(&dev_priv->mm.inactive_list), |
| 1347 | list_empty(&dev_priv->mm.request_list), |
| 1348 | list_empty(&dev_priv->mm.flushing_list)); |
| 1349 | /* If we didn't do any of the above, there's nothing to be done |
| 1350 | * and we just can't fit it in. |
| 1351 | */ |
| 1352 | return -ENOMEM; |
| 1353 | } |
| 1354 | return ret; |
| 1355 | } |
| 1356 | |
| 1357 | static int |
Keith Packard | ac94a96 | 2008-11-20 23:30:27 -0800 | [diff] [blame] | 1358 | i915_gem_evict_everything(struct drm_device *dev) |
| 1359 | { |
| 1360 | int ret; |
| 1361 | |
| 1362 | for (;;) { |
| 1363 | ret = i915_gem_evict_something(dev); |
| 1364 | if (ret != 0) |
| 1365 | break; |
| 1366 | } |
Owain Ainsworth | 15c3533 | 2008-12-06 20:42:20 -0800 | [diff] [blame] | 1367 | if (ret == -ENOMEM) |
| 1368 | return 0; |
Keith Packard | ac94a96 | 2008-11-20 23:30:27 -0800 | [diff] [blame] | 1369 | return ret; |
| 1370 | } |
| 1371 | |
| 1372 | static int |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1373 | i915_gem_object_get_page_list(struct drm_gem_object *obj) |
| 1374 | { |
| 1375 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 1376 | int page_count, i; |
| 1377 | struct address_space *mapping; |
| 1378 | struct inode *inode; |
| 1379 | struct page *page; |
| 1380 | int ret; |
| 1381 | |
| 1382 | if (obj_priv->page_list) |
| 1383 | return 0; |
| 1384 | |
| 1385 | /* Get the list of pages out of our struct file. They'll be pinned |
| 1386 | * at this point until we release them. |
| 1387 | */ |
| 1388 | page_count = obj->size / PAGE_SIZE; |
| 1389 | BUG_ON(obj_priv->page_list != NULL); |
| 1390 | obj_priv->page_list = drm_calloc(page_count, sizeof(struct page *), |
| 1391 | DRM_MEM_DRIVER); |
| 1392 | if (obj_priv->page_list == NULL) { |
| 1393 | DRM_ERROR("Faled to allocate page list\n"); |
| 1394 | return -ENOMEM; |
| 1395 | } |
| 1396 | |
| 1397 | inode = obj->filp->f_path.dentry->d_inode; |
| 1398 | mapping = inode->i_mapping; |
| 1399 | for (i = 0; i < page_count; i++) { |
| 1400 | page = read_mapping_page(mapping, i, NULL); |
| 1401 | if (IS_ERR(page)) { |
| 1402 | ret = PTR_ERR(page); |
| 1403 | DRM_ERROR("read_mapping_page failed: %d\n", ret); |
| 1404 | i915_gem_object_free_page_list(obj); |
| 1405 | return ret; |
| 1406 | } |
| 1407 | obj_priv->page_list[i] = page; |
| 1408 | } |
| 1409 | return 0; |
| 1410 | } |
| 1411 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame^] | 1412 | static void i965_write_fence_reg(struct drm_i915_fence_reg *reg) |
| 1413 | { |
| 1414 | struct drm_gem_object *obj = reg->obj; |
| 1415 | struct drm_device *dev = obj->dev; |
| 1416 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1417 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 1418 | int regnum = obj_priv->fence_reg; |
| 1419 | uint64_t val; |
| 1420 | |
| 1421 | val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) & |
| 1422 | 0xfffff000) << 32; |
| 1423 | val |= obj_priv->gtt_offset & 0xfffff000; |
| 1424 | val |= ((obj_priv->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT; |
| 1425 | if (obj_priv->tiling_mode == I915_TILING_Y) |
| 1426 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; |
| 1427 | val |= I965_FENCE_REG_VALID; |
| 1428 | |
| 1429 | I915_WRITE64(FENCE_REG_965_0 + (regnum * 8), val); |
| 1430 | } |
| 1431 | |
| 1432 | static void i915_write_fence_reg(struct drm_i915_fence_reg *reg) |
| 1433 | { |
| 1434 | struct drm_gem_object *obj = reg->obj; |
| 1435 | struct drm_device *dev = obj->dev; |
| 1436 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1437 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 1438 | int regnum = obj_priv->fence_reg; |
| 1439 | uint32_t val; |
| 1440 | uint32_t pitch_val; |
| 1441 | |
| 1442 | if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) || |
| 1443 | (obj_priv->gtt_offset & (obj->size - 1))) { |
| 1444 | WARN(1, "%s: object not 1M or size aligned\n", __FUNCTION__); |
| 1445 | return; |
| 1446 | } |
| 1447 | |
| 1448 | if (obj_priv->tiling_mode == I915_TILING_Y && (IS_I945G(dev) || |
| 1449 | IS_I945GM(dev) || |
| 1450 | IS_G33(dev))) |
| 1451 | pitch_val = (obj_priv->stride / 128) - 1; |
| 1452 | else |
| 1453 | pitch_val = (obj_priv->stride / 512) - 1; |
| 1454 | |
| 1455 | val = obj_priv->gtt_offset; |
| 1456 | if (obj_priv->tiling_mode == I915_TILING_Y) |
| 1457 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; |
| 1458 | val |= I915_FENCE_SIZE_BITS(obj->size); |
| 1459 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
| 1460 | val |= I830_FENCE_REG_VALID; |
| 1461 | |
| 1462 | I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val); |
| 1463 | } |
| 1464 | |
| 1465 | static void i830_write_fence_reg(struct drm_i915_fence_reg *reg) |
| 1466 | { |
| 1467 | struct drm_gem_object *obj = reg->obj; |
| 1468 | struct drm_device *dev = obj->dev; |
| 1469 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1470 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 1471 | int regnum = obj_priv->fence_reg; |
| 1472 | uint32_t val; |
| 1473 | uint32_t pitch_val; |
| 1474 | |
| 1475 | if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) || |
| 1476 | (obj_priv->gtt_offset & (obj->size - 1))) { |
| 1477 | WARN(1, "%s: object not 1M or size aligned\n", __FUNCTION__); |
| 1478 | return; |
| 1479 | } |
| 1480 | |
| 1481 | pitch_val = (obj_priv->stride / 128) - 1; |
| 1482 | |
| 1483 | val = obj_priv->gtt_offset; |
| 1484 | if (obj_priv->tiling_mode == I915_TILING_Y) |
| 1485 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; |
| 1486 | val |= I830_FENCE_SIZE_BITS(obj->size); |
| 1487 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
| 1488 | val |= I830_FENCE_REG_VALID; |
| 1489 | |
| 1490 | I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val); |
| 1491 | |
| 1492 | } |
| 1493 | |
| 1494 | /** |
| 1495 | * i915_gem_object_get_fence_reg - set up a fence reg for an object |
| 1496 | * @obj: object to map through a fence reg |
| 1497 | * |
| 1498 | * When mapping objects through the GTT, userspace wants to be able to write |
| 1499 | * to them without having to worry about swizzling if the object is tiled. |
| 1500 | * |
| 1501 | * This function walks the fence regs looking for a free one for @obj, |
| 1502 | * stealing one if it can't find any. |
| 1503 | * |
| 1504 | * It then sets up the reg based on the object's properties: address, pitch |
| 1505 | * and tiling format. |
| 1506 | */ |
| 1507 | static void |
| 1508 | i915_gem_object_get_fence_reg(struct drm_gem_object *obj) |
| 1509 | { |
| 1510 | struct drm_device *dev = obj->dev; |
| 1511 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1512 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 1513 | struct drm_i915_fence_reg *reg = NULL; |
| 1514 | int i, ret; |
| 1515 | |
| 1516 | switch (obj_priv->tiling_mode) { |
| 1517 | case I915_TILING_NONE: |
| 1518 | WARN(1, "allocating a fence for non-tiled object?\n"); |
| 1519 | break; |
| 1520 | case I915_TILING_X: |
| 1521 | WARN(obj_priv->stride & (512 - 1), |
| 1522 | "object is X tiled but has non-512B pitch\n"); |
| 1523 | break; |
| 1524 | case I915_TILING_Y: |
| 1525 | WARN(obj_priv->stride & (128 - 1), |
| 1526 | "object is Y tiled but has non-128B pitch\n"); |
| 1527 | break; |
| 1528 | } |
| 1529 | |
| 1530 | /* First try to find a free reg */ |
| 1531 | for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { |
| 1532 | reg = &dev_priv->fence_regs[i]; |
| 1533 | if (!reg->obj) |
| 1534 | break; |
| 1535 | } |
| 1536 | |
| 1537 | /* None available, try to steal one or wait for a user to finish */ |
| 1538 | if (i == dev_priv->num_fence_regs) { |
| 1539 | struct drm_i915_gem_object *old_obj_priv = NULL; |
| 1540 | loff_t offset; |
| 1541 | |
| 1542 | try_again: |
| 1543 | /* Could try to use LRU here instead... */ |
| 1544 | for (i = dev_priv->fence_reg_start; |
| 1545 | i < dev_priv->num_fence_regs; i++) { |
| 1546 | reg = &dev_priv->fence_regs[i]; |
| 1547 | old_obj_priv = reg->obj->driver_private; |
| 1548 | if (!old_obj_priv->pin_count) |
| 1549 | break; |
| 1550 | } |
| 1551 | |
| 1552 | /* |
| 1553 | * Now things get ugly... we have to wait for one of the |
| 1554 | * objects to finish before trying again. |
| 1555 | */ |
| 1556 | if (i == dev_priv->num_fence_regs) { |
| 1557 | ret = i915_gem_object_wait_rendering(reg->obj); |
| 1558 | if (ret) { |
| 1559 | WARN(ret, "wait_rendering failed: %d\n", ret); |
| 1560 | return; |
| 1561 | } |
| 1562 | goto try_again; |
| 1563 | } |
| 1564 | |
| 1565 | /* |
| 1566 | * Zap this virtual mapping so we can set up a fence again |
| 1567 | * for this object next time we need it. |
| 1568 | */ |
| 1569 | offset = ((loff_t) reg->obj->map_list.hash.key) << PAGE_SHIFT; |
| 1570 | unmap_mapping_range(dev->dev_mapping, offset, |
| 1571 | reg->obj->size, 1); |
| 1572 | old_obj_priv->fence_reg = I915_FENCE_REG_NONE; |
| 1573 | } |
| 1574 | |
| 1575 | obj_priv->fence_reg = i; |
| 1576 | reg->obj = obj; |
| 1577 | |
| 1578 | if (IS_I965G(dev)) |
| 1579 | i965_write_fence_reg(reg); |
| 1580 | else if (IS_I9XX(dev)) |
| 1581 | i915_write_fence_reg(reg); |
| 1582 | else |
| 1583 | i830_write_fence_reg(reg); |
| 1584 | } |
| 1585 | |
| 1586 | /** |
| 1587 | * i915_gem_clear_fence_reg - clear out fence register info |
| 1588 | * @obj: object to clear |
| 1589 | * |
| 1590 | * Zeroes out the fence register itself and clears out the associated |
| 1591 | * data structures in dev_priv and obj_priv. |
| 1592 | */ |
| 1593 | static void |
| 1594 | i915_gem_clear_fence_reg(struct drm_gem_object *obj) |
| 1595 | { |
| 1596 | struct drm_device *dev = obj->dev; |
| 1597 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1598 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 1599 | |
| 1600 | if (IS_I965G(dev)) |
| 1601 | I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0); |
| 1602 | else |
| 1603 | I915_WRITE(FENCE_REG_830_0 + (obj_priv->fence_reg * 4), 0); |
| 1604 | |
| 1605 | dev_priv->fence_regs[obj_priv->fence_reg].obj = NULL; |
| 1606 | obj_priv->fence_reg = I915_FENCE_REG_NONE; |
| 1607 | } |
| 1608 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1609 | /** |
| 1610 | * Finds free space in the GTT aperture and binds the object there. |
| 1611 | */ |
| 1612 | static int |
| 1613 | i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment) |
| 1614 | { |
| 1615 | struct drm_device *dev = obj->dev; |
| 1616 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1617 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 1618 | struct drm_mm_node *free_space; |
| 1619 | int page_count, ret; |
| 1620 | |
| 1621 | if (alignment == 0) |
| 1622 | alignment = PAGE_SIZE; |
| 1623 | if (alignment & (PAGE_SIZE - 1)) { |
| 1624 | DRM_ERROR("Invalid object alignment requested %u\n", alignment); |
| 1625 | return -EINVAL; |
| 1626 | } |
| 1627 | |
| 1628 | search_free: |
| 1629 | free_space = drm_mm_search_free(&dev_priv->mm.gtt_space, |
| 1630 | obj->size, alignment, 0); |
| 1631 | if (free_space != NULL) { |
| 1632 | obj_priv->gtt_space = drm_mm_get_block(free_space, obj->size, |
| 1633 | alignment); |
| 1634 | if (obj_priv->gtt_space != NULL) { |
| 1635 | obj_priv->gtt_space->private = obj; |
| 1636 | obj_priv->gtt_offset = obj_priv->gtt_space->start; |
| 1637 | } |
| 1638 | } |
| 1639 | if (obj_priv->gtt_space == NULL) { |
| 1640 | /* If the gtt is empty and we're still having trouble |
| 1641 | * fitting our object in, we're out of memory. |
| 1642 | */ |
| 1643 | #if WATCH_LRU |
| 1644 | DRM_INFO("%s: GTT full, evicting something\n", __func__); |
| 1645 | #endif |
| 1646 | if (list_empty(&dev_priv->mm.inactive_list) && |
| 1647 | list_empty(&dev_priv->mm.flushing_list) && |
| 1648 | list_empty(&dev_priv->mm.active_list)) { |
| 1649 | DRM_ERROR("GTT full, but LRU list empty\n"); |
| 1650 | return -ENOMEM; |
| 1651 | } |
| 1652 | |
| 1653 | ret = i915_gem_evict_something(dev); |
| 1654 | if (ret != 0) { |
Keith Packard | ac94a96 | 2008-11-20 23:30:27 -0800 | [diff] [blame] | 1655 | if (ret != -ERESTARTSYS) |
| 1656 | DRM_ERROR("Failed to evict a buffer %d\n", ret); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1657 | return ret; |
| 1658 | } |
| 1659 | goto search_free; |
| 1660 | } |
| 1661 | |
| 1662 | #if WATCH_BUF |
| 1663 | DRM_INFO("Binding object of size %d at 0x%08x\n", |
| 1664 | obj->size, obj_priv->gtt_offset); |
| 1665 | #endif |
| 1666 | ret = i915_gem_object_get_page_list(obj); |
| 1667 | if (ret) { |
| 1668 | drm_mm_put_block(obj_priv->gtt_space); |
| 1669 | obj_priv->gtt_space = NULL; |
| 1670 | return ret; |
| 1671 | } |
| 1672 | |
| 1673 | page_count = obj->size / PAGE_SIZE; |
| 1674 | /* Create an AGP memory structure pointing at our pages, and bind it |
| 1675 | * into the GTT. |
| 1676 | */ |
| 1677 | obj_priv->agp_mem = drm_agp_bind_pages(dev, |
| 1678 | obj_priv->page_list, |
| 1679 | page_count, |
Keith Packard | ba1eb1d | 2008-10-14 19:55:10 -0700 | [diff] [blame] | 1680 | obj_priv->gtt_offset, |
| 1681 | obj_priv->agp_type); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1682 | if (obj_priv->agp_mem == NULL) { |
| 1683 | i915_gem_object_free_page_list(obj); |
| 1684 | drm_mm_put_block(obj_priv->gtt_space); |
| 1685 | obj_priv->gtt_space = NULL; |
| 1686 | return -ENOMEM; |
| 1687 | } |
| 1688 | atomic_inc(&dev->gtt_count); |
| 1689 | atomic_add(obj->size, &dev->gtt_memory); |
| 1690 | |
| 1691 | /* Assert that the object is not currently in any GPU domain. As it |
| 1692 | * wasn't in the GTT, there shouldn't be any way it could have been in |
| 1693 | * a GPU cache |
| 1694 | */ |
| 1695 | BUG_ON(obj->read_domains & ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT)); |
| 1696 | BUG_ON(obj->write_domain & ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT)); |
| 1697 | |
| 1698 | return 0; |
| 1699 | } |
| 1700 | |
| 1701 | void |
| 1702 | i915_gem_clflush_object(struct drm_gem_object *obj) |
| 1703 | { |
| 1704 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 1705 | |
| 1706 | /* If we don't have a page list set up, then we're not pinned |
| 1707 | * to GPU, and we can ignore the cache flush because it'll happen |
| 1708 | * again at bind time. |
| 1709 | */ |
| 1710 | if (obj_priv->page_list == NULL) |
| 1711 | return; |
| 1712 | |
| 1713 | drm_clflush_pages(obj_priv->page_list, obj->size / PAGE_SIZE); |
| 1714 | } |
| 1715 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 1716 | /** Flushes any GPU write domain for the object if it's dirty. */ |
| 1717 | static void |
| 1718 | i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj) |
| 1719 | { |
| 1720 | struct drm_device *dev = obj->dev; |
| 1721 | uint32_t seqno; |
| 1722 | |
| 1723 | if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0) |
| 1724 | return; |
| 1725 | |
| 1726 | /* Queue the GPU write cache flushing we need. */ |
| 1727 | i915_gem_flush(dev, 0, obj->write_domain); |
| 1728 | seqno = i915_add_request(dev, obj->write_domain); |
| 1729 | obj->write_domain = 0; |
| 1730 | i915_gem_object_move_to_active(obj, seqno); |
| 1731 | } |
| 1732 | |
| 1733 | /** Flushes the GTT write domain for the object if it's dirty. */ |
| 1734 | static void |
| 1735 | i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj) |
| 1736 | { |
| 1737 | if (obj->write_domain != I915_GEM_DOMAIN_GTT) |
| 1738 | return; |
| 1739 | |
| 1740 | /* No actual flushing is required for the GTT write domain. Writes |
| 1741 | * to it immediately go to main memory as far as we know, so there's |
| 1742 | * no chipset flush. It also doesn't land in render cache. |
| 1743 | */ |
| 1744 | obj->write_domain = 0; |
| 1745 | } |
| 1746 | |
| 1747 | /** Flushes the CPU write domain for the object if it's dirty. */ |
| 1748 | static void |
| 1749 | i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj) |
| 1750 | { |
| 1751 | struct drm_device *dev = obj->dev; |
| 1752 | |
| 1753 | if (obj->write_domain != I915_GEM_DOMAIN_CPU) |
| 1754 | return; |
| 1755 | |
| 1756 | i915_gem_clflush_object(obj); |
| 1757 | drm_agp_chipset_flush(dev); |
| 1758 | obj->write_domain = 0; |
| 1759 | } |
| 1760 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1761 | /** |
| 1762 | * Moves a single object to the GTT read, and possibly write domain. |
| 1763 | * |
| 1764 | * This function returns when the move is complete, including waiting on |
| 1765 | * flushes to occur. |
| 1766 | */ |
| 1767 | static int |
| 1768 | i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write) |
| 1769 | { |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1770 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 1771 | int ret; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1772 | |
Eric Anholt | 0235439 | 2008-11-26 13:58:13 -0800 | [diff] [blame] | 1773 | /* Not valid to be called on unbound objects. */ |
| 1774 | if (obj_priv->gtt_space == NULL) |
| 1775 | return -EINVAL; |
| 1776 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 1777 | i915_gem_object_flush_gpu_write_domain(obj); |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1778 | /* Wait on any GPU rendering and flushing to occur. */ |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 1779 | ret = i915_gem_object_wait_rendering(obj); |
| 1780 | if (ret != 0) |
| 1781 | return ret; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1782 | |
| 1783 | /* If we're writing through the GTT domain, then CPU and GPU caches |
| 1784 | * will need to be invalidated at next use. |
| 1785 | */ |
| 1786 | if (write) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 1787 | obj->read_domains &= I915_GEM_DOMAIN_GTT; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1788 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 1789 | i915_gem_object_flush_cpu_write_domain(obj); |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1790 | |
| 1791 | /* It should now be out of any other write domains, and we can update |
| 1792 | * the domain values for our changes. |
| 1793 | */ |
| 1794 | BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
| 1795 | obj->read_domains |= I915_GEM_DOMAIN_GTT; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 1796 | if (write) { |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1797 | obj->write_domain = I915_GEM_DOMAIN_GTT; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 1798 | obj_priv->dirty = 1; |
| 1799 | } |
| 1800 | |
| 1801 | return 0; |
| 1802 | } |
| 1803 | |
| 1804 | /** |
| 1805 | * Moves a single object to the CPU read, and possibly write domain. |
| 1806 | * |
| 1807 | * This function returns when the move is complete, including waiting on |
| 1808 | * flushes to occur. |
| 1809 | */ |
| 1810 | static int |
| 1811 | i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write) |
| 1812 | { |
| 1813 | struct drm_device *dev = obj->dev; |
| 1814 | int ret; |
| 1815 | |
| 1816 | i915_gem_object_flush_gpu_write_domain(obj); |
| 1817 | /* Wait on any GPU rendering and flushing to occur. */ |
| 1818 | ret = i915_gem_object_wait_rendering(obj); |
| 1819 | if (ret != 0) |
| 1820 | return ret; |
| 1821 | |
| 1822 | i915_gem_object_flush_gtt_write_domain(obj); |
| 1823 | |
| 1824 | /* If we have a partially-valid cache of the object in the CPU, |
| 1825 | * finish invalidating it and free the per-page flags. |
| 1826 | */ |
| 1827 | i915_gem_object_set_to_full_cpu_read_domain(obj); |
| 1828 | |
| 1829 | /* Flush the CPU cache if it's still invalid. */ |
| 1830 | if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
| 1831 | i915_gem_clflush_object(obj); |
| 1832 | drm_agp_chipset_flush(dev); |
| 1833 | |
| 1834 | obj->read_domains |= I915_GEM_DOMAIN_CPU; |
| 1835 | } |
| 1836 | |
| 1837 | /* It should now be out of any other write domains, and we can update |
| 1838 | * the domain values for our changes. |
| 1839 | */ |
| 1840 | BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
| 1841 | |
| 1842 | /* If we're writing through the CPU, then the GPU read domains will |
| 1843 | * need to be invalidated at next use. |
| 1844 | */ |
| 1845 | if (write) { |
| 1846 | obj->read_domains &= I915_GEM_DOMAIN_CPU; |
| 1847 | obj->write_domain = I915_GEM_DOMAIN_CPU; |
| 1848 | } |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1849 | |
| 1850 | return 0; |
| 1851 | } |
| 1852 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1853 | /* |
| 1854 | * Set the next domain for the specified object. This |
| 1855 | * may not actually perform the necessary flushing/invaliding though, |
| 1856 | * as that may want to be batched with other set_domain operations |
| 1857 | * |
| 1858 | * This is (we hope) the only really tricky part of gem. The goal |
| 1859 | * is fairly simple -- track which caches hold bits of the object |
| 1860 | * and make sure they remain coherent. A few concrete examples may |
| 1861 | * help to explain how it works. For shorthand, we use the notation |
| 1862 | * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the |
| 1863 | * a pair of read and write domain masks. |
| 1864 | * |
| 1865 | * Case 1: the batch buffer |
| 1866 | * |
| 1867 | * 1. Allocated |
| 1868 | * 2. Written by CPU |
| 1869 | * 3. Mapped to GTT |
| 1870 | * 4. Read by GPU |
| 1871 | * 5. Unmapped from GTT |
| 1872 | * 6. Freed |
| 1873 | * |
| 1874 | * Let's take these a step at a time |
| 1875 | * |
| 1876 | * 1. Allocated |
| 1877 | * Pages allocated from the kernel may still have |
| 1878 | * cache contents, so we set them to (CPU, CPU) always. |
| 1879 | * 2. Written by CPU (using pwrite) |
| 1880 | * The pwrite function calls set_domain (CPU, CPU) and |
| 1881 | * this function does nothing (as nothing changes) |
| 1882 | * 3. Mapped by GTT |
| 1883 | * This function asserts that the object is not |
| 1884 | * currently in any GPU-based read or write domains |
| 1885 | * 4. Read by GPU |
| 1886 | * i915_gem_execbuffer calls set_domain (COMMAND, 0). |
| 1887 | * As write_domain is zero, this function adds in the |
| 1888 | * current read domains (CPU+COMMAND, 0). |
| 1889 | * flush_domains is set to CPU. |
| 1890 | * invalidate_domains is set to COMMAND |
| 1891 | * clflush is run to get data out of the CPU caches |
| 1892 | * then i915_dev_set_domain calls i915_gem_flush to |
| 1893 | * emit an MI_FLUSH and drm_agp_chipset_flush |
| 1894 | * 5. Unmapped from GTT |
| 1895 | * i915_gem_object_unbind calls set_domain (CPU, CPU) |
| 1896 | * flush_domains and invalidate_domains end up both zero |
| 1897 | * so no flushing/invalidating happens |
| 1898 | * 6. Freed |
| 1899 | * yay, done |
| 1900 | * |
| 1901 | * Case 2: The shared render buffer |
| 1902 | * |
| 1903 | * 1. Allocated |
| 1904 | * 2. Mapped to GTT |
| 1905 | * 3. Read/written by GPU |
| 1906 | * 4. set_domain to (CPU,CPU) |
| 1907 | * 5. Read/written by CPU |
| 1908 | * 6. Read/written by GPU |
| 1909 | * |
| 1910 | * 1. Allocated |
| 1911 | * Same as last example, (CPU, CPU) |
| 1912 | * 2. Mapped to GTT |
| 1913 | * Nothing changes (assertions find that it is not in the GPU) |
| 1914 | * 3. Read/written by GPU |
| 1915 | * execbuffer calls set_domain (RENDER, RENDER) |
| 1916 | * flush_domains gets CPU |
| 1917 | * invalidate_domains gets GPU |
| 1918 | * clflush (obj) |
| 1919 | * MI_FLUSH and drm_agp_chipset_flush |
| 1920 | * 4. set_domain (CPU, CPU) |
| 1921 | * flush_domains gets GPU |
| 1922 | * invalidate_domains gets CPU |
| 1923 | * wait_rendering (obj) to make sure all drawing is complete. |
| 1924 | * This will include an MI_FLUSH to get the data from GPU |
| 1925 | * to memory |
| 1926 | * clflush (obj) to invalidate the CPU cache |
| 1927 | * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?) |
| 1928 | * 5. Read/written by CPU |
| 1929 | * cache lines are loaded and dirtied |
| 1930 | * 6. Read written by GPU |
| 1931 | * Same as last GPU access |
| 1932 | * |
| 1933 | * Case 3: The constant buffer |
| 1934 | * |
| 1935 | * 1. Allocated |
| 1936 | * 2. Written by CPU |
| 1937 | * 3. Read by GPU |
| 1938 | * 4. Updated (written) by CPU again |
| 1939 | * 5. Read by GPU |
| 1940 | * |
| 1941 | * 1. Allocated |
| 1942 | * (CPU, CPU) |
| 1943 | * 2. Written by CPU |
| 1944 | * (CPU, CPU) |
| 1945 | * 3. Read by GPU |
| 1946 | * (CPU+RENDER, 0) |
| 1947 | * flush_domains = CPU |
| 1948 | * invalidate_domains = RENDER |
| 1949 | * clflush (obj) |
| 1950 | * MI_FLUSH |
| 1951 | * drm_agp_chipset_flush |
| 1952 | * 4. Updated (written) by CPU again |
| 1953 | * (CPU, CPU) |
| 1954 | * flush_domains = 0 (no previous write domain) |
| 1955 | * invalidate_domains = 0 (no new read domains) |
| 1956 | * 5. Read by GPU |
| 1957 | * (CPU+RENDER, 0) |
| 1958 | * flush_domains = CPU |
| 1959 | * invalidate_domains = RENDER |
| 1960 | * clflush (obj) |
| 1961 | * MI_FLUSH |
| 1962 | * drm_agp_chipset_flush |
| 1963 | */ |
Keith Packard | c0d9082 | 2008-11-20 23:11:08 -0800 | [diff] [blame] | 1964 | static void |
| 1965 | i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj, |
| 1966 | uint32_t read_domains, |
| 1967 | uint32_t write_domain) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1968 | { |
| 1969 | struct drm_device *dev = obj->dev; |
| 1970 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 1971 | uint32_t invalidate_domains = 0; |
| 1972 | uint32_t flush_domains = 0; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 1973 | |
| 1974 | BUG_ON(read_domains & I915_GEM_DOMAIN_CPU); |
| 1975 | BUG_ON(write_domain == I915_GEM_DOMAIN_CPU); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1976 | |
| 1977 | #if WATCH_BUF |
| 1978 | DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n", |
| 1979 | __func__, obj, |
| 1980 | obj->read_domains, read_domains, |
| 1981 | obj->write_domain, write_domain); |
| 1982 | #endif |
| 1983 | /* |
| 1984 | * If the object isn't moving to a new write domain, |
| 1985 | * let the object stay in multiple read domains |
| 1986 | */ |
| 1987 | if (write_domain == 0) |
| 1988 | read_domains |= obj->read_domains; |
| 1989 | else |
| 1990 | obj_priv->dirty = 1; |
| 1991 | |
| 1992 | /* |
| 1993 | * Flush the current write domain if |
| 1994 | * the new read domains don't match. Invalidate |
| 1995 | * any read domains which differ from the old |
| 1996 | * write domain |
| 1997 | */ |
| 1998 | if (obj->write_domain && obj->write_domain != read_domains) { |
| 1999 | flush_domains |= obj->write_domain; |
| 2000 | invalidate_domains |= read_domains & ~obj->write_domain; |
| 2001 | } |
| 2002 | /* |
| 2003 | * Invalidate any read caches which may have |
| 2004 | * stale data. That is, any new read domains. |
| 2005 | */ |
| 2006 | invalidate_domains |= read_domains & ~obj->read_domains; |
| 2007 | if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) { |
| 2008 | #if WATCH_BUF |
| 2009 | DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n", |
| 2010 | __func__, flush_domains, invalidate_domains); |
| 2011 | #endif |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2012 | i915_gem_clflush_object(obj); |
| 2013 | } |
| 2014 | |
| 2015 | if ((write_domain | flush_domains) != 0) |
| 2016 | obj->write_domain = write_domain; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2017 | obj->read_domains = read_domains; |
| 2018 | |
| 2019 | dev->invalidate_domains |= invalidate_domains; |
| 2020 | dev->flush_domains |= flush_domains; |
| 2021 | #if WATCH_BUF |
| 2022 | DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n", |
| 2023 | __func__, |
| 2024 | obj->read_domains, obj->write_domain, |
| 2025 | dev->invalidate_domains, dev->flush_domains); |
| 2026 | #endif |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2027 | } |
| 2028 | |
| 2029 | /** |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2030 | * Moves the object from a partially CPU read to a full one. |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2031 | * |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2032 | * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(), |
| 2033 | * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU). |
| 2034 | */ |
| 2035 | static void |
| 2036 | i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj) |
| 2037 | { |
| 2038 | struct drm_device *dev = obj->dev; |
| 2039 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 2040 | |
| 2041 | if (!obj_priv->page_cpu_valid) |
| 2042 | return; |
| 2043 | |
| 2044 | /* If we're partially in the CPU read domain, finish moving it in. |
| 2045 | */ |
| 2046 | if (obj->read_domains & I915_GEM_DOMAIN_CPU) { |
| 2047 | int i; |
| 2048 | |
| 2049 | for (i = 0; i <= (obj->size - 1) / PAGE_SIZE; i++) { |
| 2050 | if (obj_priv->page_cpu_valid[i]) |
| 2051 | continue; |
| 2052 | drm_clflush_pages(obj_priv->page_list + i, 1); |
| 2053 | } |
| 2054 | drm_agp_chipset_flush(dev); |
| 2055 | } |
| 2056 | |
| 2057 | /* Free the page_cpu_valid mappings which are now stale, whether |
| 2058 | * or not we've got I915_GEM_DOMAIN_CPU. |
| 2059 | */ |
| 2060 | drm_free(obj_priv->page_cpu_valid, obj->size / PAGE_SIZE, |
| 2061 | DRM_MEM_DRIVER); |
| 2062 | obj_priv->page_cpu_valid = NULL; |
| 2063 | } |
| 2064 | |
| 2065 | /** |
| 2066 | * Set the CPU read domain on a range of the object. |
| 2067 | * |
| 2068 | * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's |
| 2069 | * not entirely valid. The page_cpu_valid member of the object flags which |
| 2070 | * pages have been flushed, and will be respected by |
| 2071 | * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping |
| 2072 | * of the whole object. |
| 2073 | * |
| 2074 | * This function returns when the move is complete, including waiting on |
| 2075 | * flushes to occur. |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2076 | */ |
| 2077 | static int |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2078 | i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj, |
| 2079 | uint64_t offset, uint64_t size) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2080 | { |
| 2081 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2082 | int i, ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2083 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2084 | if (offset == 0 && size == obj->size) |
| 2085 | return i915_gem_object_set_to_cpu_domain(obj, 0); |
| 2086 | |
| 2087 | i915_gem_object_flush_gpu_write_domain(obj); |
| 2088 | /* Wait on any GPU rendering and flushing to occur. */ |
| 2089 | ret = i915_gem_object_wait_rendering(obj); |
| 2090 | if (ret != 0) |
| 2091 | return ret; |
| 2092 | i915_gem_object_flush_gtt_write_domain(obj); |
| 2093 | |
| 2094 | /* If we're already fully in the CPU read domain, we're done. */ |
| 2095 | if (obj_priv->page_cpu_valid == NULL && |
| 2096 | (obj->read_domains & I915_GEM_DOMAIN_CPU) != 0) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2097 | return 0; |
| 2098 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2099 | /* Otherwise, create/clear the per-page CPU read domain flag if we're |
| 2100 | * newly adding I915_GEM_DOMAIN_CPU |
| 2101 | */ |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2102 | if (obj_priv->page_cpu_valid == NULL) { |
| 2103 | obj_priv->page_cpu_valid = drm_calloc(1, obj->size / PAGE_SIZE, |
| 2104 | DRM_MEM_DRIVER); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2105 | if (obj_priv->page_cpu_valid == NULL) |
| 2106 | return -ENOMEM; |
| 2107 | } else if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) |
| 2108 | memset(obj_priv->page_cpu_valid, 0, obj->size / PAGE_SIZE); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2109 | |
| 2110 | /* Flush the cache on any pages that are still invalid from the CPU's |
| 2111 | * perspective. |
| 2112 | */ |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2113 | for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE; |
| 2114 | i++) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2115 | if (obj_priv->page_cpu_valid[i]) |
| 2116 | continue; |
| 2117 | |
| 2118 | drm_clflush_pages(obj_priv->page_list + i, 1); |
| 2119 | |
| 2120 | obj_priv->page_cpu_valid[i] = 1; |
| 2121 | } |
| 2122 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2123 | /* It should now be out of any other write domains, and we can update |
| 2124 | * the domain values for our changes. |
| 2125 | */ |
| 2126 | BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
| 2127 | |
| 2128 | obj->read_domains |= I915_GEM_DOMAIN_CPU; |
| 2129 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2130 | return 0; |
| 2131 | } |
| 2132 | |
| 2133 | /** |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2134 | * Pin an object to the GTT and evaluate the relocations landing in it. |
| 2135 | */ |
| 2136 | static int |
| 2137 | i915_gem_object_pin_and_relocate(struct drm_gem_object *obj, |
| 2138 | struct drm_file *file_priv, |
| 2139 | struct drm_i915_gem_exec_object *entry) |
| 2140 | { |
| 2141 | struct drm_device *dev = obj->dev; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 2142 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2143 | struct drm_i915_gem_relocation_entry reloc; |
| 2144 | struct drm_i915_gem_relocation_entry __user *relocs; |
| 2145 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 2146 | int i, ret; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 2147 | void __iomem *reloc_page; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2148 | |
| 2149 | /* Choose the GTT offset for our buffer and put it there. */ |
| 2150 | ret = i915_gem_object_pin(obj, (uint32_t) entry->alignment); |
| 2151 | if (ret) |
| 2152 | return ret; |
| 2153 | |
| 2154 | entry->offset = obj_priv->gtt_offset; |
| 2155 | |
| 2156 | relocs = (struct drm_i915_gem_relocation_entry __user *) |
| 2157 | (uintptr_t) entry->relocs_ptr; |
| 2158 | /* Apply the relocations, using the GTT aperture to avoid cache |
| 2159 | * flushing requirements. |
| 2160 | */ |
| 2161 | for (i = 0; i < entry->relocation_count; i++) { |
| 2162 | struct drm_gem_object *target_obj; |
| 2163 | struct drm_i915_gem_object *target_obj_priv; |
Eric Anholt | 3043c60 | 2008-10-02 12:24:47 -0700 | [diff] [blame] | 2164 | uint32_t reloc_val, reloc_offset; |
| 2165 | uint32_t __iomem *reloc_entry; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2166 | |
| 2167 | ret = copy_from_user(&reloc, relocs + i, sizeof(reloc)); |
| 2168 | if (ret != 0) { |
| 2169 | i915_gem_object_unpin(obj); |
| 2170 | return ret; |
| 2171 | } |
| 2172 | |
| 2173 | target_obj = drm_gem_object_lookup(obj->dev, file_priv, |
| 2174 | reloc.target_handle); |
| 2175 | if (target_obj == NULL) { |
| 2176 | i915_gem_object_unpin(obj); |
| 2177 | return -EBADF; |
| 2178 | } |
| 2179 | target_obj_priv = target_obj->driver_private; |
| 2180 | |
| 2181 | /* The target buffer should have appeared before us in the |
| 2182 | * exec_object list, so it should have a GTT space bound by now. |
| 2183 | */ |
| 2184 | if (target_obj_priv->gtt_space == NULL) { |
| 2185 | DRM_ERROR("No GTT space found for object %d\n", |
| 2186 | reloc.target_handle); |
| 2187 | drm_gem_object_unreference(target_obj); |
| 2188 | i915_gem_object_unpin(obj); |
| 2189 | return -EINVAL; |
| 2190 | } |
| 2191 | |
| 2192 | if (reloc.offset > obj->size - 4) { |
| 2193 | DRM_ERROR("Relocation beyond object bounds: " |
| 2194 | "obj %p target %d offset %d size %d.\n", |
| 2195 | obj, reloc.target_handle, |
| 2196 | (int) reloc.offset, (int) obj->size); |
| 2197 | drm_gem_object_unreference(target_obj); |
| 2198 | i915_gem_object_unpin(obj); |
| 2199 | return -EINVAL; |
| 2200 | } |
| 2201 | if (reloc.offset & 3) { |
| 2202 | DRM_ERROR("Relocation not 4-byte aligned: " |
| 2203 | "obj %p target %d offset %d.\n", |
| 2204 | obj, reloc.target_handle, |
| 2205 | (int) reloc.offset); |
| 2206 | drm_gem_object_unreference(target_obj); |
| 2207 | i915_gem_object_unpin(obj); |
| 2208 | return -EINVAL; |
| 2209 | } |
| 2210 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2211 | if (reloc.write_domain & I915_GEM_DOMAIN_CPU || |
| 2212 | reloc.read_domains & I915_GEM_DOMAIN_CPU) { |
| 2213 | DRM_ERROR("reloc with read/write CPU domains: " |
| 2214 | "obj %p target %d offset %d " |
| 2215 | "read %08x write %08x", |
| 2216 | obj, reloc.target_handle, |
| 2217 | (int) reloc.offset, |
| 2218 | reloc.read_domains, |
| 2219 | reloc.write_domain); |
| 2220 | return -EINVAL; |
| 2221 | } |
| 2222 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2223 | if (reloc.write_domain && target_obj->pending_write_domain && |
| 2224 | reloc.write_domain != target_obj->pending_write_domain) { |
| 2225 | DRM_ERROR("Write domain conflict: " |
| 2226 | "obj %p target %d offset %d " |
| 2227 | "new %08x old %08x\n", |
| 2228 | obj, reloc.target_handle, |
| 2229 | (int) reloc.offset, |
| 2230 | reloc.write_domain, |
| 2231 | target_obj->pending_write_domain); |
| 2232 | drm_gem_object_unreference(target_obj); |
| 2233 | i915_gem_object_unpin(obj); |
| 2234 | return -EINVAL; |
| 2235 | } |
| 2236 | |
| 2237 | #if WATCH_RELOC |
| 2238 | DRM_INFO("%s: obj %p offset %08x target %d " |
| 2239 | "read %08x write %08x gtt %08x " |
| 2240 | "presumed %08x delta %08x\n", |
| 2241 | __func__, |
| 2242 | obj, |
| 2243 | (int) reloc.offset, |
| 2244 | (int) reloc.target_handle, |
| 2245 | (int) reloc.read_domains, |
| 2246 | (int) reloc.write_domain, |
| 2247 | (int) target_obj_priv->gtt_offset, |
| 2248 | (int) reloc.presumed_offset, |
| 2249 | reloc.delta); |
| 2250 | #endif |
| 2251 | |
| 2252 | target_obj->pending_read_domains |= reloc.read_domains; |
| 2253 | target_obj->pending_write_domain |= reloc.write_domain; |
| 2254 | |
| 2255 | /* If the relocation already has the right value in it, no |
| 2256 | * more work needs to be done. |
| 2257 | */ |
| 2258 | if (target_obj_priv->gtt_offset == reloc.presumed_offset) { |
| 2259 | drm_gem_object_unreference(target_obj); |
| 2260 | continue; |
| 2261 | } |
| 2262 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2263 | ret = i915_gem_object_set_to_gtt_domain(obj, 1); |
| 2264 | if (ret != 0) { |
| 2265 | drm_gem_object_unreference(target_obj); |
| 2266 | i915_gem_object_unpin(obj); |
| 2267 | return -EINVAL; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2268 | } |
| 2269 | |
| 2270 | /* Map the page containing the relocation we're going to |
| 2271 | * perform. |
| 2272 | */ |
| 2273 | reloc_offset = obj_priv->gtt_offset + reloc.offset; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 2274 | reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping, |
| 2275 | (reloc_offset & |
| 2276 | ~(PAGE_SIZE - 1))); |
Eric Anholt | 3043c60 | 2008-10-02 12:24:47 -0700 | [diff] [blame] | 2277 | reloc_entry = (uint32_t __iomem *)(reloc_page + |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 2278 | (reloc_offset & (PAGE_SIZE - 1))); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2279 | reloc_val = target_obj_priv->gtt_offset + reloc.delta; |
| 2280 | |
| 2281 | #if WATCH_BUF |
| 2282 | DRM_INFO("Applied relocation: %p@0x%08x %08x -> %08x\n", |
| 2283 | obj, (unsigned int) reloc.offset, |
| 2284 | readl(reloc_entry), reloc_val); |
| 2285 | #endif |
| 2286 | writel(reloc_val, reloc_entry); |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 2287 | io_mapping_unmap_atomic(reloc_page); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2288 | |
| 2289 | /* Write the updated presumed offset for this entry back out |
| 2290 | * to the user. |
| 2291 | */ |
| 2292 | reloc.presumed_offset = target_obj_priv->gtt_offset; |
| 2293 | ret = copy_to_user(relocs + i, &reloc, sizeof(reloc)); |
| 2294 | if (ret != 0) { |
| 2295 | drm_gem_object_unreference(target_obj); |
| 2296 | i915_gem_object_unpin(obj); |
| 2297 | return ret; |
| 2298 | } |
| 2299 | |
| 2300 | drm_gem_object_unreference(target_obj); |
| 2301 | } |
| 2302 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2303 | #if WATCH_BUF |
| 2304 | if (0) |
| 2305 | i915_gem_dump_object(obj, 128, __func__, ~0); |
| 2306 | #endif |
| 2307 | return 0; |
| 2308 | } |
| 2309 | |
| 2310 | /** Dispatch a batchbuffer to the ring |
| 2311 | */ |
| 2312 | static int |
| 2313 | i915_dispatch_gem_execbuffer(struct drm_device *dev, |
| 2314 | struct drm_i915_gem_execbuffer *exec, |
| 2315 | uint64_t exec_offset) |
| 2316 | { |
| 2317 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 2318 | struct drm_clip_rect __user *boxes = (struct drm_clip_rect __user *) |
| 2319 | (uintptr_t) exec->cliprects_ptr; |
| 2320 | int nbox = exec->num_cliprects; |
| 2321 | int i = 0, count; |
| 2322 | uint32_t exec_start, exec_len; |
| 2323 | RING_LOCALS; |
| 2324 | |
| 2325 | exec_start = (uint32_t) exec_offset + exec->batch_start_offset; |
| 2326 | exec_len = (uint32_t) exec->batch_len; |
| 2327 | |
| 2328 | if ((exec_start | exec_len) & 0x7) { |
| 2329 | DRM_ERROR("alignment\n"); |
| 2330 | return -EINVAL; |
| 2331 | } |
| 2332 | |
| 2333 | if (!exec_start) |
| 2334 | return -EINVAL; |
| 2335 | |
| 2336 | count = nbox ? nbox : 1; |
| 2337 | |
| 2338 | for (i = 0; i < count; i++) { |
| 2339 | if (i < nbox) { |
| 2340 | int ret = i915_emit_box(dev, boxes, i, |
| 2341 | exec->DR1, exec->DR4); |
| 2342 | if (ret) |
| 2343 | return ret; |
| 2344 | } |
| 2345 | |
| 2346 | if (IS_I830(dev) || IS_845G(dev)) { |
| 2347 | BEGIN_LP_RING(4); |
| 2348 | OUT_RING(MI_BATCH_BUFFER); |
| 2349 | OUT_RING(exec_start | MI_BATCH_NON_SECURE); |
| 2350 | OUT_RING(exec_start + exec_len - 4); |
| 2351 | OUT_RING(0); |
| 2352 | ADVANCE_LP_RING(); |
| 2353 | } else { |
| 2354 | BEGIN_LP_RING(2); |
| 2355 | if (IS_I965G(dev)) { |
| 2356 | OUT_RING(MI_BATCH_BUFFER_START | |
| 2357 | (2 << 6) | |
| 2358 | MI_BATCH_NON_SECURE_I965); |
| 2359 | OUT_RING(exec_start); |
| 2360 | } else { |
| 2361 | OUT_RING(MI_BATCH_BUFFER_START | |
| 2362 | (2 << 6)); |
| 2363 | OUT_RING(exec_start | MI_BATCH_NON_SECURE); |
| 2364 | } |
| 2365 | ADVANCE_LP_RING(); |
| 2366 | } |
| 2367 | } |
| 2368 | |
| 2369 | /* XXX breadcrumb */ |
| 2370 | return 0; |
| 2371 | } |
| 2372 | |
| 2373 | /* Throttle our rendering by waiting until the ring has completed our requests |
| 2374 | * emitted over 20 msec ago. |
| 2375 | * |
| 2376 | * This should get us reasonable parallelism between CPU and GPU but also |
| 2377 | * relatively low latency when blocking on a particular request to finish. |
| 2378 | */ |
| 2379 | static int |
| 2380 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file_priv) |
| 2381 | { |
| 2382 | struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv; |
| 2383 | int ret = 0; |
| 2384 | uint32_t seqno; |
| 2385 | |
| 2386 | mutex_lock(&dev->struct_mutex); |
| 2387 | seqno = i915_file_priv->mm.last_gem_throttle_seqno; |
| 2388 | i915_file_priv->mm.last_gem_throttle_seqno = |
| 2389 | i915_file_priv->mm.last_gem_seqno; |
| 2390 | if (seqno) |
| 2391 | ret = i915_wait_request(dev, seqno); |
| 2392 | mutex_unlock(&dev->struct_mutex); |
| 2393 | return ret; |
| 2394 | } |
| 2395 | |
| 2396 | int |
| 2397 | i915_gem_execbuffer(struct drm_device *dev, void *data, |
| 2398 | struct drm_file *file_priv) |
| 2399 | { |
| 2400 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 2401 | struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv; |
| 2402 | struct drm_i915_gem_execbuffer *args = data; |
| 2403 | struct drm_i915_gem_exec_object *exec_list = NULL; |
| 2404 | struct drm_gem_object **object_list = NULL; |
| 2405 | struct drm_gem_object *batch_obj; |
| 2406 | int ret, i, pinned = 0; |
| 2407 | uint64_t exec_offset; |
| 2408 | uint32_t seqno, flush_domains; |
Keith Packard | ac94a96 | 2008-11-20 23:30:27 -0800 | [diff] [blame] | 2409 | int pin_tries; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2410 | |
| 2411 | #if WATCH_EXEC |
| 2412 | DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n", |
| 2413 | (int) args->buffers_ptr, args->buffer_count, args->batch_len); |
| 2414 | #endif |
| 2415 | |
Eric Anholt | 4f481ed | 2008-09-10 14:22:49 -0700 | [diff] [blame] | 2416 | if (args->buffer_count < 1) { |
| 2417 | DRM_ERROR("execbuf with %d buffers\n", args->buffer_count); |
| 2418 | return -EINVAL; |
| 2419 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2420 | /* Copy in the exec list from userland */ |
| 2421 | exec_list = drm_calloc(sizeof(*exec_list), args->buffer_count, |
| 2422 | DRM_MEM_DRIVER); |
| 2423 | object_list = drm_calloc(sizeof(*object_list), args->buffer_count, |
| 2424 | DRM_MEM_DRIVER); |
| 2425 | if (exec_list == NULL || object_list == NULL) { |
| 2426 | DRM_ERROR("Failed to allocate exec or object list " |
| 2427 | "for %d buffers\n", |
| 2428 | args->buffer_count); |
| 2429 | ret = -ENOMEM; |
| 2430 | goto pre_mutex_err; |
| 2431 | } |
| 2432 | ret = copy_from_user(exec_list, |
| 2433 | (struct drm_i915_relocation_entry __user *) |
| 2434 | (uintptr_t) args->buffers_ptr, |
| 2435 | sizeof(*exec_list) * args->buffer_count); |
| 2436 | if (ret != 0) { |
| 2437 | DRM_ERROR("copy %d exec entries failed %d\n", |
| 2438 | args->buffer_count, ret); |
| 2439 | goto pre_mutex_err; |
| 2440 | } |
| 2441 | |
| 2442 | mutex_lock(&dev->struct_mutex); |
| 2443 | |
| 2444 | i915_verify_inactive(dev, __FILE__, __LINE__); |
| 2445 | |
| 2446 | if (dev_priv->mm.wedged) { |
| 2447 | DRM_ERROR("Execbuf while wedged\n"); |
| 2448 | mutex_unlock(&dev->struct_mutex); |
| 2449 | return -EIO; |
| 2450 | } |
| 2451 | |
| 2452 | if (dev_priv->mm.suspended) { |
| 2453 | DRM_ERROR("Execbuf while VT-switched.\n"); |
| 2454 | mutex_unlock(&dev->struct_mutex); |
| 2455 | return -EBUSY; |
| 2456 | } |
| 2457 | |
Keith Packard | ac94a96 | 2008-11-20 23:30:27 -0800 | [diff] [blame] | 2458 | /* Look up object handles */ |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2459 | for (i = 0; i < args->buffer_count; i++) { |
| 2460 | object_list[i] = drm_gem_object_lookup(dev, file_priv, |
| 2461 | exec_list[i].handle); |
| 2462 | if (object_list[i] == NULL) { |
| 2463 | DRM_ERROR("Invalid object handle %d at index %d\n", |
| 2464 | exec_list[i].handle, i); |
| 2465 | ret = -EBADF; |
| 2466 | goto err; |
| 2467 | } |
Keith Packard | ac94a96 | 2008-11-20 23:30:27 -0800 | [diff] [blame] | 2468 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2469 | |
Keith Packard | ac94a96 | 2008-11-20 23:30:27 -0800 | [diff] [blame] | 2470 | /* Pin and relocate */ |
| 2471 | for (pin_tries = 0; ; pin_tries++) { |
| 2472 | ret = 0; |
| 2473 | for (i = 0; i < args->buffer_count; i++) { |
| 2474 | object_list[i]->pending_read_domains = 0; |
| 2475 | object_list[i]->pending_write_domain = 0; |
| 2476 | ret = i915_gem_object_pin_and_relocate(object_list[i], |
| 2477 | file_priv, |
| 2478 | &exec_list[i]); |
| 2479 | if (ret) |
| 2480 | break; |
| 2481 | pinned = i + 1; |
| 2482 | } |
| 2483 | /* success */ |
| 2484 | if (ret == 0) |
| 2485 | break; |
| 2486 | |
| 2487 | /* error other than GTT full, or we've already tried again */ |
| 2488 | if (ret != -ENOMEM || pin_tries >= 1) { |
| 2489 | DRM_ERROR("Failed to pin buffers %d\n", ret); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2490 | goto err; |
| 2491 | } |
Keith Packard | ac94a96 | 2008-11-20 23:30:27 -0800 | [diff] [blame] | 2492 | |
| 2493 | /* unpin all of our buffers */ |
| 2494 | for (i = 0; i < pinned; i++) |
| 2495 | i915_gem_object_unpin(object_list[i]); |
| 2496 | |
| 2497 | /* evict everyone we can from the aperture */ |
| 2498 | ret = i915_gem_evict_everything(dev); |
| 2499 | if (ret) |
| 2500 | goto err; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2501 | } |
| 2502 | |
| 2503 | /* Set the pending read domains for the batch buffer to COMMAND */ |
| 2504 | batch_obj = object_list[args->buffer_count-1]; |
| 2505 | batch_obj->pending_read_domains = I915_GEM_DOMAIN_COMMAND; |
| 2506 | batch_obj->pending_write_domain = 0; |
| 2507 | |
| 2508 | i915_verify_inactive(dev, __FILE__, __LINE__); |
| 2509 | |
Keith Packard | 646f0f6 | 2008-11-20 23:23:03 -0800 | [diff] [blame] | 2510 | /* Zero the global flush/invalidate flags. These |
| 2511 | * will be modified as new domains are computed |
| 2512 | * for each object |
| 2513 | */ |
| 2514 | dev->invalidate_domains = 0; |
| 2515 | dev->flush_domains = 0; |
| 2516 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2517 | for (i = 0; i < args->buffer_count; i++) { |
| 2518 | struct drm_gem_object *obj = object_list[i]; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2519 | |
Keith Packard | 646f0f6 | 2008-11-20 23:23:03 -0800 | [diff] [blame] | 2520 | /* Compute new gpu domains and update invalidate/flush */ |
Keith Packard | c0d9082 | 2008-11-20 23:11:08 -0800 | [diff] [blame] | 2521 | i915_gem_object_set_to_gpu_domain(obj, |
| 2522 | obj->pending_read_domains, |
| 2523 | obj->pending_write_domain); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2524 | } |
| 2525 | |
| 2526 | i915_verify_inactive(dev, __FILE__, __LINE__); |
| 2527 | |
Keith Packard | 646f0f6 | 2008-11-20 23:23:03 -0800 | [diff] [blame] | 2528 | if (dev->invalidate_domains | dev->flush_domains) { |
| 2529 | #if WATCH_EXEC |
| 2530 | DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n", |
| 2531 | __func__, |
| 2532 | dev->invalidate_domains, |
| 2533 | dev->flush_domains); |
| 2534 | #endif |
| 2535 | i915_gem_flush(dev, |
| 2536 | dev->invalidate_domains, |
| 2537 | dev->flush_domains); |
| 2538 | if (dev->flush_domains) |
| 2539 | (void)i915_add_request(dev, dev->flush_domains); |
| 2540 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2541 | |
| 2542 | i915_verify_inactive(dev, __FILE__, __LINE__); |
| 2543 | |
| 2544 | #if WATCH_COHERENCY |
| 2545 | for (i = 0; i < args->buffer_count; i++) { |
| 2546 | i915_gem_object_check_coherency(object_list[i], |
| 2547 | exec_list[i].handle); |
| 2548 | } |
| 2549 | #endif |
| 2550 | |
| 2551 | exec_offset = exec_list[args->buffer_count - 1].offset; |
| 2552 | |
| 2553 | #if WATCH_EXEC |
| 2554 | i915_gem_dump_object(object_list[args->buffer_count - 1], |
| 2555 | args->batch_len, |
| 2556 | __func__, |
| 2557 | ~0); |
| 2558 | #endif |
| 2559 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2560 | /* Exec the batchbuffer */ |
| 2561 | ret = i915_dispatch_gem_execbuffer(dev, args, exec_offset); |
| 2562 | if (ret) { |
| 2563 | DRM_ERROR("dispatch failed %d\n", ret); |
| 2564 | goto err; |
| 2565 | } |
| 2566 | |
| 2567 | /* |
| 2568 | * Ensure that the commands in the batch buffer are |
| 2569 | * finished before the interrupt fires |
| 2570 | */ |
| 2571 | flush_domains = i915_retire_commands(dev); |
| 2572 | |
| 2573 | i915_verify_inactive(dev, __FILE__, __LINE__); |
| 2574 | |
| 2575 | /* |
| 2576 | * Get a seqno representing the execution of the current buffer, |
| 2577 | * which we can wait on. We would like to mitigate these interrupts, |
| 2578 | * likely by only creating seqnos occasionally (so that we have |
| 2579 | * *some* interrupts representing completion of buffers that we can |
| 2580 | * wait on when trying to clear up gtt space). |
| 2581 | */ |
| 2582 | seqno = i915_add_request(dev, flush_domains); |
| 2583 | BUG_ON(seqno == 0); |
| 2584 | i915_file_priv->mm.last_gem_seqno = seqno; |
| 2585 | for (i = 0; i < args->buffer_count; i++) { |
| 2586 | struct drm_gem_object *obj = object_list[i]; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2587 | |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 2588 | i915_gem_object_move_to_active(obj, seqno); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2589 | #if WATCH_LRU |
| 2590 | DRM_INFO("%s: move to exec list %p\n", __func__, obj); |
| 2591 | #endif |
| 2592 | } |
| 2593 | #if WATCH_LRU |
| 2594 | i915_dump_lru(dev, __func__); |
| 2595 | #endif |
| 2596 | |
| 2597 | i915_verify_inactive(dev, __FILE__, __LINE__); |
| 2598 | |
| 2599 | /* Copy the new buffer offsets back to the user's exec list. */ |
| 2600 | ret = copy_to_user((struct drm_i915_relocation_entry __user *) |
| 2601 | (uintptr_t) args->buffers_ptr, |
| 2602 | exec_list, |
| 2603 | sizeof(*exec_list) * args->buffer_count); |
| 2604 | if (ret) |
| 2605 | DRM_ERROR("failed to copy %d exec entries " |
| 2606 | "back to user (%d)\n", |
| 2607 | args->buffer_count, ret); |
| 2608 | err: |
| 2609 | if (object_list != NULL) { |
| 2610 | for (i = 0; i < pinned; i++) |
| 2611 | i915_gem_object_unpin(object_list[i]); |
| 2612 | |
| 2613 | for (i = 0; i < args->buffer_count; i++) |
| 2614 | drm_gem_object_unreference(object_list[i]); |
| 2615 | } |
| 2616 | mutex_unlock(&dev->struct_mutex); |
| 2617 | |
| 2618 | pre_mutex_err: |
| 2619 | drm_free(object_list, sizeof(*object_list) * args->buffer_count, |
| 2620 | DRM_MEM_DRIVER); |
| 2621 | drm_free(exec_list, sizeof(*exec_list) * args->buffer_count, |
| 2622 | DRM_MEM_DRIVER); |
| 2623 | |
| 2624 | return ret; |
| 2625 | } |
| 2626 | |
| 2627 | int |
| 2628 | i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment) |
| 2629 | { |
| 2630 | struct drm_device *dev = obj->dev; |
| 2631 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 2632 | int ret; |
| 2633 | |
| 2634 | i915_verify_inactive(dev, __FILE__, __LINE__); |
| 2635 | if (obj_priv->gtt_space == NULL) { |
| 2636 | ret = i915_gem_object_bind_to_gtt(obj, alignment); |
| 2637 | if (ret != 0) { |
| 2638 | DRM_ERROR("Failure to bind: %d", ret); |
| 2639 | return ret; |
| 2640 | } |
| 2641 | } |
| 2642 | obj_priv->pin_count++; |
| 2643 | |
| 2644 | /* If the object is not active and not pending a flush, |
| 2645 | * remove it from the inactive list |
| 2646 | */ |
| 2647 | if (obj_priv->pin_count == 1) { |
| 2648 | atomic_inc(&dev->pin_count); |
| 2649 | atomic_add(obj->size, &dev->pin_memory); |
| 2650 | if (!obj_priv->active && |
| 2651 | (obj->write_domain & ~(I915_GEM_DOMAIN_CPU | |
| 2652 | I915_GEM_DOMAIN_GTT)) == 0 && |
| 2653 | !list_empty(&obj_priv->list)) |
| 2654 | list_del_init(&obj_priv->list); |
| 2655 | } |
| 2656 | i915_verify_inactive(dev, __FILE__, __LINE__); |
| 2657 | |
| 2658 | return 0; |
| 2659 | } |
| 2660 | |
| 2661 | void |
| 2662 | i915_gem_object_unpin(struct drm_gem_object *obj) |
| 2663 | { |
| 2664 | struct drm_device *dev = obj->dev; |
| 2665 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 2666 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 2667 | |
| 2668 | i915_verify_inactive(dev, __FILE__, __LINE__); |
| 2669 | obj_priv->pin_count--; |
| 2670 | BUG_ON(obj_priv->pin_count < 0); |
| 2671 | BUG_ON(obj_priv->gtt_space == NULL); |
| 2672 | |
| 2673 | /* If the object is no longer pinned, and is |
| 2674 | * neither active nor being flushed, then stick it on |
| 2675 | * the inactive list |
| 2676 | */ |
| 2677 | if (obj_priv->pin_count == 0) { |
| 2678 | if (!obj_priv->active && |
| 2679 | (obj->write_domain & ~(I915_GEM_DOMAIN_CPU | |
| 2680 | I915_GEM_DOMAIN_GTT)) == 0) |
| 2681 | list_move_tail(&obj_priv->list, |
| 2682 | &dev_priv->mm.inactive_list); |
| 2683 | atomic_dec(&dev->pin_count); |
| 2684 | atomic_sub(obj->size, &dev->pin_memory); |
| 2685 | } |
| 2686 | i915_verify_inactive(dev, __FILE__, __LINE__); |
| 2687 | } |
| 2688 | |
| 2689 | int |
| 2690 | i915_gem_pin_ioctl(struct drm_device *dev, void *data, |
| 2691 | struct drm_file *file_priv) |
| 2692 | { |
| 2693 | struct drm_i915_gem_pin *args = data; |
| 2694 | struct drm_gem_object *obj; |
| 2695 | struct drm_i915_gem_object *obj_priv; |
| 2696 | int ret; |
| 2697 | |
| 2698 | mutex_lock(&dev->struct_mutex); |
| 2699 | |
| 2700 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
| 2701 | if (obj == NULL) { |
| 2702 | DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n", |
| 2703 | args->handle); |
| 2704 | mutex_unlock(&dev->struct_mutex); |
| 2705 | return -EBADF; |
| 2706 | } |
| 2707 | obj_priv = obj->driver_private; |
| 2708 | |
| 2709 | ret = i915_gem_object_pin(obj, args->alignment); |
| 2710 | if (ret != 0) { |
| 2711 | drm_gem_object_unreference(obj); |
| 2712 | mutex_unlock(&dev->struct_mutex); |
| 2713 | return ret; |
| 2714 | } |
| 2715 | |
| 2716 | /* XXX - flush the CPU caches for pinned objects |
| 2717 | * as the X server doesn't manage domains yet |
| 2718 | */ |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2719 | i915_gem_object_flush_cpu_write_domain(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2720 | args->offset = obj_priv->gtt_offset; |
| 2721 | drm_gem_object_unreference(obj); |
| 2722 | mutex_unlock(&dev->struct_mutex); |
| 2723 | |
| 2724 | return 0; |
| 2725 | } |
| 2726 | |
| 2727 | int |
| 2728 | i915_gem_unpin_ioctl(struct drm_device *dev, void *data, |
| 2729 | struct drm_file *file_priv) |
| 2730 | { |
| 2731 | struct drm_i915_gem_pin *args = data; |
| 2732 | struct drm_gem_object *obj; |
| 2733 | |
| 2734 | mutex_lock(&dev->struct_mutex); |
| 2735 | |
| 2736 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
| 2737 | if (obj == NULL) { |
| 2738 | DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n", |
| 2739 | args->handle); |
| 2740 | mutex_unlock(&dev->struct_mutex); |
| 2741 | return -EBADF; |
| 2742 | } |
| 2743 | |
| 2744 | i915_gem_object_unpin(obj); |
| 2745 | |
| 2746 | drm_gem_object_unreference(obj); |
| 2747 | mutex_unlock(&dev->struct_mutex); |
| 2748 | return 0; |
| 2749 | } |
| 2750 | |
| 2751 | int |
| 2752 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, |
| 2753 | struct drm_file *file_priv) |
| 2754 | { |
| 2755 | struct drm_i915_gem_busy *args = data; |
| 2756 | struct drm_gem_object *obj; |
| 2757 | struct drm_i915_gem_object *obj_priv; |
| 2758 | |
| 2759 | mutex_lock(&dev->struct_mutex); |
| 2760 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
| 2761 | if (obj == NULL) { |
| 2762 | DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n", |
| 2763 | args->handle); |
| 2764 | mutex_unlock(&dev->struct_mutex); |
| 2765 | return -EBADF; |
| 2766 | } |
| 2767 | |
| 2768 | obj_priv = obj->driver_private; |
Eric Anholt | c4de0a5 | 2008-12-14 19:05:04 -0800 | [diff] [blame] | 2769 | /* Don't count being on the flushing list against the object being |
| 2770 | * done. Otherwise, a buffer left on the flushing list but not getting |
| 2771 | * flushed (because nobody's flushing that domain) won't ever return |
| 2772 | * unbusy and get reused by libdrm's bo cache. The other expected |
| 2773 | * consumer of this interface, OpenGL's occlusion queries, also specs |
| 2774 | * that the objects get unbusy "eventually" without any interference. |
| 2775 | */ |
| 2776 | args->busy = obj_priv->active && obj_priv->last_rendering_seqno != 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2777 | |
| 2778 | drm_gem_object_unreference(obj); |
| 2779 | mutex_unlock(&dev->struct_mutex); |
| 2780 | return 0; |
| 2781 | } |
| 2782 | |
| 2783 | int |
| 2784 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, |
| 2785 | struct drm_file *file_priv) |
| 2786 | { |
| 2787 | return i915_gem_ring_throttle(dev, file_priv); |
| 2788 | } |
| 2789 | |
| 2790 | int i915_gem_init_object(struct drm_gem_object *obj) |
| 2791 | { |
| 2792 | struct drm_i915_gem_object *obj_priv; |
| 2793 | |
| 2794 | obj_priv = drm_calloc(1, sizeof(*obj_priv), DRM_MEM_DRIVER); |
| 2795 | if (obj_priv == NULL) |
| 2796 | return -ENOMEM; |
| 2797 | |
| 2798 | /* |
| 2799 | * We've just allocated pages from the kernel, |
| 2800 | * so they've just been written by the CPU with |
| 2801 | * zeros. They'll need to be clflushed before we |
| 2802 | * use them with the GPU. |
| 2803 | */ |
| 2804 | obj->write_domain = I915_GEM_DOMAIN_CPU; |
| 2805 | obj->read_domains = I915_GEM_DOMAIN_CPU; |
| 2806 | |
Keith Packard | ba1eb1d | 2008-10-14 19:55:10 -0700 | [diff] [blame] | 2807 | obj_priv->agp_type = AGP_USER_MEMORY; |
| 2808 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2809 | obj->driver_private = obj_priv; |
| 2810 | obj_priv->obj = obj; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame^] | 2811 | obj_priv->fence_reg = I915_FENCE_REG_NONE; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2812 | INIT_LIST_HEAD(&obj_priv->list); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame^] | 2813 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2814 | return 0; |
| 2815 | } |
| 2816 | |
| 2817 | void i915_gem_free_object(struct drm_gem_object *obj) |
| 2818 | { |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame^] | 2819 | struct drm_device *dev = obj->dev; |
| 2820 | struct drm_gem_mm *mm = dev->mm_private; |
| 2821 | struct drm_map_list *list; |
| 2822 | struct drm_map *map; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2823 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 2824 | |
| 2825 | while (obj_priv->pin_count > 0) |
| 2826 | i915_gem_object_unpin(obj); |
| 2827 | |
| 2828 | i915_gem_object_unbind(obj); |
| 2829 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame^] | 2830 | list = &obj->map_list; |
| 2831 | drm_ht_remove_item(&mm->offset_hash, &list->hash); |
| 2832 | |
| 2833 | if (list->file_offset_node) { |
| 2834 | drm_mm_put_block(list->file_offset_node); |
| 2835 | list->file_offset_node = NULL; |
| 2836 | } |
| 2837 | |
| 2838 | map = list->map; |
| 2839 | if (map) { |
| 2840 | drm_free(map, sizeof(*map), DRM_MEM_DRIVER); |
| 2841 | list->map = NULL; |
| 2842 | } |
| 2843 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2844 | drm_free(obj_priv->page_cpu_valid, 1, DRM_MEM_DRIVER); |
| 2845 | drm_free(obj->driver_private, 1, DRM_MEM_DRIVER); |
| 2846 | } |
| 2847 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2848 | /** Unbinds all objects that are on the given buffer list. */ |
| 2849 | static int |
| 2850 | i915_gem_evict_from_list(struct drm_device *dev, struct list_head *head) |
| 2851 | { |
| 2852 | struct drm_gem_object *obj; |
| 2853 | struct drm_i915_gem_object *obj_priv; |
| 2854 | int ret; |
| 2855 | |
| 2856 | while (!list_empty(head)) { |
| 2857 | obj_priv = list_first_entry(head, |
| 2858 | struct drm_i915_gem_object, |
| 2859 | list); |
| 2860 | obj = obj_priv->obj; |
| 2861 | |
| 2862 | if (obj_priv->pin_count != 0) { |
| 2863 | DRM_ERROR("Pinned object in unbind list\n"); |
| 2864 | mutex_unlock(&dev->struct_mutex); |
| 2865 | return -EINVAL; |
| 2866 | } |
| 2867 | |
| 2868 | ret = i915_gem_object_unbind(obj); |
| 2869 | if (ret != 0) { |
| 2870 | DRM_ERROR("Error unbinding object in LeaveVT: %d\n", |
| 2871 | ret); |
| 2872 | mutex_unlock(&dev->struct_mutex); |
| 2873 | return ret; |
| 2874 | } |
| 2875 | } |
| 2876 | |
| 2877 | |
| 2878 | return 0; |
| 2879 | } |
| 2880 | |
| 2881 | static int |
| 2882 | i915_gem_idle(struct drm_device *dev) |
| 2883 | { |
| 2884 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 2885 | uint32_t seqno, cur_seqno, last_seqno; |
| 2886 | int stuck, ret; |
| 2887 | |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 2888 | mutex_lock(&dev->struct_mutex); |
| 2889 | |
| 2890 | if (dev_priv->mm.suspended || dev_priv->ring.ring_obj == NULL) { |
| 2891 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2892 | return 0; |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 2893 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2894 | |
| 2895 | /* Hack! Don't let anybody do execbuf while we don't control the chip. |
| 2896 | * We need to replace this with a semaphore, or something. |
| 2897 | */ |
| 2898 | dev_priv->mm.suspended = 1; |
| 2899 | |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 2900 | /* Cancel the retire work handler, wait for it to finish if running |
| 2901 | */ |
| 2902 | mutex_unlock(&dev->struct_mutex); |
| 2903 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); |
| 2904 | mutex_lock(&dev->struct_mutex); |
| 2905 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2906 | i915_kernel_lost_context(dev); |
| 2907 | |
| 2908 | /* Flush the GPU along with all non-CPU write domains |
| 2909 | */ |
| 2910 | i915_gem_flush(dev, ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT), |
| 2911 | ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT)); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame^] | 2912 | seqno = i915_add_request(dev, ~I915_GEM_DOMAIN_CPU); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2913 | |
| 2914 | if (seqno == 0) { |
| 2915 | mutex_unlock(&dev->struct_mutex); |
| 2916 | return -ENOMEM; |
| 2917 | } |
| 2918 | |
| 2919 | dev_priv->mm.waiting_gem_seqno = seqno; |
| 2920 | last_seqno = 0; |
| 2921 | stuck = 0; |
| 2922 | for (;;) { |
| 2923 | cur_seqno = i915_get_gem_seqno(dev); |
| 2924 | if (i915_seqno_passed(cur_seqno, seqno)) |
| 2925 | break; |
| 2926 | if (last_seqno == cur_seqno) { |
| 2927 | if (stuck++ > 100) { |
| 2928 | DRM_ERROR("hardware wedged\n"); |
| 2929 | dev_priv->mm.wedged = 1; |
| 2930 | DRM_WAKEUP(&dev_priv->irq_queue); |
| 2931 | break; |
| 2932 | } |
| 2933 | } |
| 2934 | msleep(10); |
| 2935 | last_seqno = cur_seqno; |
| 2936 | } |
| 2937 | dev_priv->mm.waiting_gem_seqno = 0; |
| 2938 | |
| 2939 | i915_gem_retire_requests(dev); |
| 2940 | |
Eric Anholt | 28dfe52 | 2008-11-13 15:00:55 -0800 | [diff] [blame] | 2941 | if (!dev_priv->mm.wedged) { |
| 2942 | /* Active and flushing should now be empty as we've |
| 2943 | * waited for a sequence higher than any pending execbuffer |
| 2944 | */ |
| 2945 | WARN_ON(!list_empty(&dev_priv->mm.active_list)); |
| 2946 | WARN_ON(!list_empty(&dev_priv->mm.flushing_list)); |
| 2947 | /* Request should now be empty as we've also waited |
| 2948 | * for the last request in the list |
| 2949 | */ |
| 2950 | WARN_ON(!list_empty(&dev_priv->mm.request_list)); |
| 2951 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2952 | |
Eric Anholt | 28dfe52 | 2008-11-13 15:00:55 -0800 | [diff] [blame] | 2953 | /* Empty the active and flushing lists to inactive. If there's |
| 2954 | * anything left at this point, it means that we're wedged and |
| 2955 | * nothing good's going to happen by leaving them there. So strip |
| 2956 | * the GPU domains and just stuff them onto inactive. |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2957 | */ |
Eric Anholt | 28dfe52 | 2008-11-13 15:00:55 -0800 | [diff] [blame] | 2958 | while (!list_empty(&dev_priv->mm.active_list)) { |
| 2959 | struct drm_i915_gem_object *obj_priv; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2960 | |
Eric Anholt | 28dfe52 | 2008-11-13 15:00:55 -0800 | [diff] [blame] | 2961 | obj_priv = list_first_entry(&dev_priv->mm.active_list, |
| 2962 | struct drm_i915_gem_object, |
| 2963 | list); |
| 2964 | obj_priv->obj->write_domain &= ~I915_GEM_GPU_DOMAINS; |
| 2965 | i915_gem_object_move_to_inactive(obj_priv->obj); |
| 2966 | } |
| 2967 | |
| 2968 | while (!list_empty(&dev_priv->mm.flushing_list)) { |
| 2969 | struct drm_i915_gem_object *obj_priv; |
| 2970 | |
Eric Anholt | 151903d | 2008-12-01 10:23:21 +1000 | [diff] [blame] | 2971 | obj_priv = list_first_entry(&dev_priv->mm.flushing_list, |
Eric Anholt | 28dfe52 | 2008-11-13 15:00:55 -0800 | [diff] [blame] | 2972 | struct drm_i915_gem_object, |
| 2973 | list); |
| 2974 | obj_priv->obj->write_domain &= ~I915_GEM_GPU_DOMAINS; |
| 2975 | i915_gem_object_move_to_inactive(obj_priv->obj); |
| 2976 | } |
| 2977 | |
| 2978 | |
| 2979 | /* Move all inactive buffers out of the GTT. */ |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2980 | ret = i915_gem_evict_from_list(dev, &dev_priv->mm.inactive_list); |
Eric Anholt | 28dfe52 | 2008-11-13 15:00:55 -0800 | [diff] [blame] | 2981 | WARN_ON(!list_empty(&dev_priv->mm.inactive_list)); |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 2982 | if (ret) { |
| 2983 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2984 | return ret; |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 2985 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2986 | |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 2987 | i915_gem_cleanup_ringbuffer(dev); |
| 2988 | mutex_unlock(&dev->struct_mutex); |
| 2989 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2990 | return 0; |
| 2991 | } |
| 2992 | |
| 2993 | static int |
| 2994 | i915_gem_init_hws(struct drm_device *dev) |
| 2995 | { |
| 2996 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 2997 | struct drm_gem_object *obj; |
| 2998 | struct drm_i915_gem_object *obj_priv; |
| 2999 | int ret; |
| 3000 | |
| 3001 | /* If we need a physical address for the status page, it's already |
| 3002 | * initialized at driver load time. |
| 3003 | */ |
| 3004 | if (!I915_NEED_GFX_HWS(dev)) |
| 3005 | return 0; |
| 3006 | |
| 3007 | obj = drm_gem_object_alloc(dev, 4096); |
| 3008 | if (obj == NULL) { |
| 3009 | DRM_ERROR("Failed to allocate status page\n"); |
| 3010 | return -ENOMEM; |
| 3011 | } |
| 3012 | obj_priv = obj->driver_private; |
Keith Packard | ba1eb1d | 2008-10-14 19:55:10 -0700 | [diff] [blame] | 3013 | obj_priv->agp_type = AGP_USER_CACHED_MEMORY; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3014 | |
| 3015 | ret = i915_gem_object_pin(obj, 4096); |
| 3016 | if (ret != 0) { |
| 3017 | drm_gem_object_unreference(obj); |
| 3018 | return ret; |
| 3019 | } |
| 3020 | |
| 3021 | dev_priv->status_gfx_addr = obj_priv->gtt_offset; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3022 | |
Keith Packard | ba1eb1d | 2008-10-14 19:55:10 -0700 | [diff] [blame] | 3023 | dev_priv->hw_status_page = kmap(obj_priv->page_list[0]); |
| 3024 | if (dev_priv->hw_status_page == NULL) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3025 | DRM_ERROR("Failed to map status page.\n"); |
| 3026 | memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map)); |
| 3027 | drm_gem_object_unreference(obj); |
| 3028 | return -EINVAL; |
| 3029 | } |
| 3030 | dev_priv->hws_obj = obj; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3031 | memset(dev_priv->hw_status_page, 0, PAGE_SIZE); |
| 3032 | I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr); |
Keith Packard | ba1eb1d | 2008-10-14 19:55:10 -0700 | [diff] [blame] | 3033 | I915_READ(HWS_PGA); /* posting read */ |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3034 | DRM_DEBUG("hws offset: 0x%08x\n", dev_priv->status_gfx_addr); |
| 3035 | |
| 3036 | return 0; |
| 3037 | } |
| 3038 | |
| 3039 | static int |
| 3040 | i915_gem_init_ringbuffer(struct drm_device *dev) |
| 3041 | { |
| 3042 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 3043 | struct drm_gem_object *obj; |
| 3044 | struct drm_i915_gem_object *obj_priv; |
| 3045 | int ret; |
Keith Packard | 50aa253 | 2008-10-14 17:20:35 -0700 | [diff] [blame] | 3046 | u32 head; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3047 | |
| 3048 | ret = i915_gem_init_hws(dev); |
| 3049 | if (ret != 0) |
| 3050 | return ret; |
| 3051 | |
| 3052 | obj = drm_gem_object_alloc(dev, 128 * 1024); |
| 3053 | if (obj == NULL) { |
| 3054 | DRM_ERROR("Failed to allocate ringbuffer\n"); |
| 3055 | return -ENOMEM; |
| 3056 | } |
| 3057 | obj_priv = obj->driver_private; |
| 3058 | |
| 3059 | ret = i915_gem_object_pin(obj, 4096); |
| 3060 | if (ret != 0) { |
| 3061 | drm_gem_object_unreference(obj); |
| 3062 | return ret; |
| 3063 | } |
| 3064 | |
| 3065 | /* Set up the kernel mapping for the ring. */ |
| 3066 | dev_priv->ring.Size = obj->size; |
| 3067 | dev_priv->ring.tail_mask = obj->size - 1; |
| 3068 | |
| 3069 | dev_priv->ring.map.offset = dev->agp->base + obj_priv->gtt_offset; |
| 3070 | dev_priv->ring.map.size = obj->size; |
| 3071 | dev_priv->ring.map.type = 0; |
| 3072 | dev_priv->ring.map.flags = 0; |
| 3073 | dev_priv->ring.map.mtrr = 0; |
| 3074 | |
Eric Anholt | bd88ee4 | 2008-09-23 14:50:57 -0700 | [diff] [blame] | 3075 | drm_core_ioremap_wc(&dev_priv->ring.map, dev); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3076 | if (dev_priv->ring.map.handle == NULL) { |
| 3077 | DRM_ERROR("Failed to map ringbuffer.\n"); |
| 3078 | memset(&dev_priv->ring, 0, sizeof(dev_priv->ring)); |
| 3079 | drm_gem_object_unreference(obj); |
| 3080 | return -EINVAL; |
| 3081 | } |
| 3082 | dev_priv->ring.ring_obj = obj; |
| 3083 | dev_priv->ring.virtual_start = dev_priv->ring.map.handle; |
| 3084 | |
| 3085 | /* Stop the ring if it's running. */ |
| 3086 | I915_WRITE(PRB0_CTL, 0); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3087 | I915_WRITE(PRB0_TAIL, 0); |
Keith Packard | 50aa253 | 2008-10-14 17:20:35 -0700 | [diff] [blame] | 3088 | I915_WRITE(PRB0_HEAD, 0); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3089 | |
| 3090 | /* Initialize the ring. */ |
| 3091 | I915_WRITE(PRB0_START, obj_priv->gtt_offset); |
Keith Packard | 50aa253 | 2008-10-14 17:20:35 -0700 | [diff] [blame] | 3092 | head = I915_READ(PRB0_HEAD) & HEAD_ADDR; |
| 3093 | |
| 3094 | /* G45 ring initialization fails to reset head to zero */ |
| 3095 | if (head != 0) { |
| 3096 | DRM_ERROR("Ring head not reset to zero " |
| 3097 | "ctl %08x head %08x tail %08x start %08x\n", |
| 3098 | I915_READ(PRB0_CTL), |
| 3099 | I915_READ(PRB0_HEAD), |
| 3100 | I915_READ(PRB0_TAIL), |
| 3101 | I915_READ(PRB0_START)); |
| 3102 | I915_WRITE(PRB0_HEAD, 0); |
| 3103 | |
| 3104 | DRM_ERROR("Ring head forced to zero " |
| 3105 | "ctl %08x head %08x tail %08x start %08x\n", |
| 3106 | I915_READ(PRB0_CTL), |
| 3107 | I915_READ(PRB0_HEAD), |
| 3108 | I915_READ(PRB0_TAIL), |
| 3109 | I915_READ(PRB0_START)); |
| 3110 | } |
| 3111 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3112 | I915_WRITE(PRB0_CTL, |
| 3113 | ((obj->size - 4096) & RING_NR_PAGES) | |
| 3114 | RING_NO_REPORT | |
| 3115 | RING_VALID); |
| 3116 | |
Keith Packard | 50aa253 | 2008-10-14 17:20:35 -0700 | [diff] [blame] | 3117 | head = I915_READ(PRB0_HEAD) & HEAD_ADDR; |
| 3118 | |
| 3119 | /* If the head is still not zero, the ring is dead */ |
| 3120 | if (head != 0) { |
| 3121 | DRM_ERROR("Ring initialization failed " |
| 3122 | "ctl %08x head %08x tail %08x start %08x\n", |
| 3123 | I915_READ(PRB0_CTL), |
| 3124 | I915_READ(PRB0_HEAD), |
| 3125 | I915_READ(PRB0_TAIL), |
| 3126 | I915_READ(PRB0_START)); |
| 3127 | return -EIO; |
| 3128 | } |
| 3129 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3130 | /* Update our cache of the ring state */ |
| 3131 | i915_kernel_lost_context(dev); |
| 3132 | |
| 3133 | return 0; |
| 3134 | } |
| 3135 | |
| 3136 | static void |
| 3137 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) |
| 3138 | { |
| 3139 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 3140 | |
| 3141 | if (dev_priv->ring.ring_obj == NULL) |
| 3142 | return; |
| 3143 | |
| 3144 | drm_core_ioremapfree(&dev_priv->ring.map, dev); |
| 3145 | |
| 3146 | i915_gem_object_unpin(dev_priv->ring.ring_obj); |
| 3147 | drm_gem_object_unreference(dev_priv->ring.ring_obj); |
| 3148 | dev_priv->ring.ring_obj = NULL; |
| 3149 | memset(&dev_priv->ring, 0, sizeof(dev_priv->ring)); |
| 3150 | |
| 3151 | if (dev_priv->hws_obj != NULL) { |
Keith Packard | ba1eb1d | 2008-10-14 19:55:10 -0700 | [diff] [blame] | 3152 | struct drm_gem_object *obj = dev_priv->hws_obj; |
| 3153 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 3154 | |
| 3155 | kunmap(obj_priv->page_list[0]); |
| 3156 | i915_gem_object_unpin(obj); |
| 3157 | drm_gem_object_unreference(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3158 | dev_priv->hws_obj = NULL; |
| 3159 | memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map)); |
Keith Packard | ba1eb1d | 2008-10-14 19:55:10 -0700 | [diff] [blame] | 3160 | dev_priv->hw_status_page = NULL; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3161 | |
| 3162 | /* Write high address into HWS_PGA when disabling. */ |
| 3163 | I915_WRITE(HWS_PGA, 0x1ffff000); |
| 3164 | } |
| 3165 | } |
| 3166 | |
| 3167 | int |
| 3168 | i915_gem_entervt_ioctl(struct drm_device *dev, void *data, |
| 3169 | struct drm_file *file_priv) |
| 3170 | { |
| 3171 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 3172 | int ret; |
| 3173 | |
| 3174 | if (dev_priv->mm.wedged) { |
| 3175 | DRM_ERROR("Reenabling wedged hardware, good luck\n"); |
| 3176 | dev_priv->mm.wedged = 0; |
| 3177 | } |
| 3178 | |
| 3179 | ret = i915_gem_init_ringbuffer(dev); |
| 3180 | if (ret != 0) |
| 3181 | return ret; |
| 3182 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 3183 | dev_priv->mm.gtt_mapping = io_mapping_create_wc(dev->agp->base, |
| 3184 | dev->agp->agp_info.aper_size |
| 3185 | * 1024 * 1024); |
| 3186 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3187 | mutex_lock(&dev->struct_mutex); |
| 3188 | BUG_ON(!list_empty(&dev_priv->mm.active_list)); |
| 3189 | BUG_ON(!list_empty(&dev_priv->mm.flushing_list)); |
| 3190 | BUG_ON(!list_empty(&dev_priv->mm.inactive_list)); |
| 3191 | BUG_ON(!list_empty(&dev_priv->mm.request_list)); |
| 3192 | dev_priv->mm.suspended = 0; |
| 3193 | mutex_unlock(&dev->struct_mutex); |
Kristian Høgsberg | dbb19d3 | 2008-08-20 11:04:27 -0400 | [diff] [blame] | 3194 | |
| 3195 | drm_irq_install(dev); |
| 3196 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3197 | return 0; |
| 3198 | } |
| 3199 | |
| 3200 | int |
| 3201 | i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, |
| 3202 | struct drm_file *file_priv) |
| 3203 | { |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 3204 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3205 | int ret; |
| 3206 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3207 | ret = i915_gem_idle(dev); |
Kristian Høgsberg | dbb19d3 | 2008-08-20 11:04:27 -0400 | [diff] [blame] | 3208 | drm_irq_uninstall(dev); |
| 3209 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 3210 | io_mapping_free(dev_priv->mm.gtt_mapping); |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 3211 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3212 | } |
| 3213 | |
| 3214 | void |
| 3215 | i915_gem_lastclose(struct drm_device *dev) |
| 3216 | { |
| 3217 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3218 | |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 3219 | ret = i915_gem_idle(dev); |
| 3220 | if (ret) |
| 3221 | DRM_ERROR("failed to idle hardware: %d\n", ret); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3222 | } |
| 3223 | |
| 3224 | void |
| 3225 | i915_gem_load(struct drm_device *dev) |
| 3226 | { |
| 3227 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 3228 | |
| 3229 | INIT_LIST_HEAD(&dev_priv->mm.active_list); |
| 3230 | INIT_LIST_HEAD(&dev_priv->mm.flushing_list); |
| 3231 | INIT_LIST_HEAD(&dev_priv->mm.inactive_list); |
| 3232 | INIT_LIST_HEAD(&dev_priv->mm.request_list); |
| 3233 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
| 3234 | i915_gem_retire_work_handler); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3235 | dev_priv->mm.next_gem_seqno = 1; |
| 3236 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame^] | 3237 | /* Old X drivers will take 0-2 for front, back, depth buffers */ |
| 3238 | dev_priv->fence_reg_start = 3; |
| 3239 | |
| 3240 | if (IS_I965G(dev)) |
| 3241 | dev_priv->num_fence_regs = 16; |
| 3242 | else |
| 3243 | dev_priv->num_fence_regs = 8; |
| 3244 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3245 | i915_gem_detect_bit_6_swizzle(dev); |
| 3246 | } |