Mark Brown | 1b340bd | 2008-07-30 19:12:04 +0100 | [diff] [blame] | 1 | #define DEBUG |
| 2 | /* |
| 3 | * pxa-ssp.c -- ALSA Soc Audio Layer |
| 4 | * |
| 5 | * Copyright 2005,2008 Wolfson Microelectronics PLC. |
| 6 | * Author: Liam Girdwood |
| 7 | * Mark Brown <broonie@opensource.wolfsonmicro.com> |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify it |
| 10 | * under the terms of the GNU General Public License as published by the |
| 11 | * Free Software Foundation; either version 2 of the License, or (at your |
| 12 | * option) any later version. |
| 13 | * |
| 14 | * TODO: |
| 15 | * o Test network mode for > 16bit sample size |
| 16 | */ |
| 17 | |
| 18 | #include <linux/init.h> |
| 19 | #include <linux/module.h> |
| 20 | #include <linux/platform_device.h> |
| 21 | #include <linux/clk.h> |
| 22 | #include <linux/io.h> |
| 23 | |
| 24 | #include <sound/core.h> |
| 25 | #include <sound/pcm.h> |
| 26 | #include <sound/initval.h> |
| 27 | #include <sound/pcm_params.h> |
| 28 | #include <sound/soc.h> |
| 29 | #include <sound/pxa2xx-lib.h> |
| 30 | |
| 31 | #include <mach/hardware.h> |
| 32 | #include <mach/pxa-regs.h> |
| 33 | #include <mach/regs-ssp.h> |
| 34 | #include <mach/audio.h> |
| 35 | #include <mach/ssp.h> |
| 36 | |
| 37 | #include "pxa2xx-pcm.h" |
| 38 | #include "pxa-ssp.h" |
| 39 | |
| 40 | /* |
| 41 | * SSP audio private data |
| 42 | */ |
| 43 | struct ssp_priv { |
| 44 | struct ssp_dev dev; |
| 45 | unsigned int sysclk; |
| 46 | int dai_fmt; |
| 47 | #ifdef CONFIG_PM |
| 48 | struct ssp_state state; |
| 49 | #endif |
| 50 | }; |
| 51 | |
| 52 | #define PXA2xx_SSP1_BASE 0x41000000 |
| 53 | #define PXA27x_SSP2_BASE 0x41700000 |
| 54 | #define PXA27x_SSP3_BASE 0x41900000 |
| 55 | #define PXA3xx_SSP4_BASE 0x41a00000 |
| 56 | |
| 57 | static struct pxa2xx_pcm_dma_params pxa_ssp1_pcm_mono_out = { |
| 58 | .name = "SSP1 PCM Mono out", |
| 59 | .dev_addr = PXA2xx_SSP1_BASE + SSDR, |
| 60 | .drcmr = &DRCMR(14), |
| 61 | .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG | |
| 62 | DCMD_BURST16 | DCMD_WIDTH2, |
| 63 | }; |
| 64 | |
| 65 | static struct pxa2xx_pcm_dma_params pxa_ssp1_pcm_mono_in = { |
| 66 | .name = "SSP1 PCM Mono in", |
| 67 | .dev_addr = PXA2xx_SSP1_BASE + SSDR, |
| 68 | .drcmr = &DRCMR(13), |
| 69 | .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC | |
| 70 | DCMD_BURST16 | DCMD_WIDTH2, |
| 71 | }; |
| 72 | |
| 73 | static struct pxa2xx_pcm_dma_params pxa_ssp1_pcm_stereo_out = { |
| 74 | .name = "SSP1 PCM Stereo out", |
| 75 | .dev_addr = PXA2xx_SSP1_BASE + SSDR, |
| 76 | .drcmr = &DRCMR(14), |
| 77 | .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG | |
| 78 | DCMD_BURST16 | DCMD_WIDTH4, |
| 79 | }; |
| 80 | |
| 81 | static struct pxa2xx_pcm_dma_params pxa_ssp1_pcm_stereo_in = { |
| 82 | .name = "SSP1 PCM Stereo in", |
| 83 | .dev_addr = PXA2xx_SSP1_BASE + SSDR, |
| 84 | .drcmr = &DRCMR(13), |
| 85 | .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC | |
| 86 | DCMD_BURST16 | DCMD_WIDTH4, |
| 87 | }; |
| 88 | |
| 89 | static struct pxa2xx_pcm_dma_params pxa_ssp2_pcm_mono_out = { |
| 90 | .name = "SSP2 PCM Mono out", |
| 91 | .dev_addr = PXA27x_SSP2_BASE + SSDR, |
| 92 | .drcmr = &DRCMR(16), |
| 93 | .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG | |
| 94 | DCMD_BURST16 | DCMD_WIDTH2, |
| 95 | }; |
| 96 | |
| 97 | static struct pxa2xx_pcm_dma_params pxa_ssp2_pcm_mono_in = { |
| 98 | .name = "SSP2 PCM Mono in", |
| 99 | .dev_addr = PXA27x_SSP2_BASE + SSDR, |
| 100 | .drcmr = &DRCMR(15), |
| 101 | .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC | |
| 102 | DCMD_BURST16 | DCMD_WIDTH2, |
| 103 | }; |
| 104 | |
| 105 | static struct pxa2xx_pcm_dma_params pxa_ssp2_pcm_stereo_out = { |
| 106 | .name = "SSP2 PCM Stereo out", |
| 107 | .dev_addr = PXA27x_SSP2_BASE + SSDR, |
| 108 | .drcmr = &DRCMR(16), |
| 109 | .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG | |
| 110 | DCMD_BURST16 | DCMD_WIDTH4, |
| 111 | }; |
| 112 | |
| 113 | static struct pxa2xx_pcm_dma_params pxa_ssp2_pcm_stereo_in = { |
| 114 | .name = "SSP2 PCM Stereo in", |
| 115 | .dev_addr = PXA27x_SSP2_BASE + SSDR, |
| 116 | .drcmr = &DRCMR(15), |
| 117 | .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC | |
| 118 | DCMD_BURST16 | DCMD_WIDTH4, |
| 119 | }; |
| 120 | |
| 121 | static struct pxa2xx_pcm_dma_params pxa_ssp3_pcm_mono_out = { |
| 122 | .name = "SSP3 PCM Mono out", |
| 123 | .dev_addr = PXA27x_SSP3_BASE + SSDR, |
| 124 | .drcmr = &DRCMR(67), |
| 125 | .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG | |
| 126 | DCMD_BURST16 | DCMD_WIDTH2, |
| 127 | }; |
| 128 | |
| 129 | static struct pxa2xx_pcm_dma_params pxa_ssp3_pcm_mono_in = { |
| 130 | .name = "SSP3 PCM Mono in", |
| 131 | .dev_addr = PXA27x_SSP3_BASE + SSDR, |
| 132 | .drcmr = &DRCMR(66), |
| 133 | .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC | |
| 134 | DCMD_BURST16 | DCMD_WIDTH2, |
| 135 | }; |
| 136 | |
| 137 | static struct pxa2xx_pcm_dma_params pxa_ssp3_pcm_stereo_out = { |
| 138 | .name = "SSP3 PCM Stereo out", |
| 139 | .dev_addr = PXA27x_SSP3_BASE + SSDR, |
| 140 | .drcmr = &DRCMR(67), |
| 141 | .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG | |
| 142 | DCMD_BURST16 | DCMD_WIDTH4, |
| 143 | }; |
| 144 | |
| 145 | static struct pxa2xx_pcm_dma_params pxa_ssp3_pcm_stereo_in = { |
| 146 | .name = "SSP3 PCM Stereo in", |
| 147 | .dev_addr = PXA27x_SSP3_BASE + SSDR, |
| 148 | .drcmr = &DRCMR(66), |
| 149 | .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC | |
| 150 | DCMD_BURST16 | DCMD_WIDTH4, |
| 151 | }; |
| 152 | |
| 153 | static struct pxa2xx_pcm_dma_params pxa_ssp4_pcm_mono_out = { |
| 154 | .name = "SSP4 PCM Mono out", |
| 155 | .dev_addr = PXA3xx_SSP4_BASE + SSDR, |
| 156 | .drcmr = &DRCMR(67), |
| 157 | .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG | |
| 158 | DCMD_BURST16 | DCMD_WIDTH2, |
| 159 | }; |
| 160 | |
| 161 | static struct pxa2xx_pcm_dma_params pxa_ssp4_pcm_mono_in = { |
| 162 | .name = "SSP4 PCM Mono in", |
| 163 | .dev_addr = PXA3xx_SSP4_BASE + SSDR, |
| 164 | .drcmr = &DRCMR(66), |
| 165 | .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC | |
| 166 | DCMD_BURST16 | DCMD_WIDTH2, |
| 167 | }; |
| 168 | |
| 169 | static struct pxa2xx_pcm_dma_params pxa_ssp4_pcm_stereo_out = { |
| 170 | .name = "SSP4 PCM Stereo out", |
| 171 | .dev_addr = PXA3xx_SSP4_BASE + SSDR, |
| 172 | .drcmr = &DRCMR(67), |
| 173 | .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG | |
| 174 | DCMD_BURST16 | DCMD_WIDTH4, |
| 175 | }; |
| 176 | |
| 177 | static struct pxa2xx_pcm_dma_params pxa_ssp4_pcm_stereo_in = { |
| 178 | .name = "SSP4 PCM Stereo in", |
| 179 | .dev_addr = PXA3xx_SSP4_BASE + SSDR, |
| 180 | .drcmr = &DRCMR(66), |
| 181 | .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC | |
| 182 | DCMD_BURST16 | DCMD_WIDTH4, |
| 183 | }; |
| 184 | |
| 185 | static void dump_registers(struct ssp_device *ssp) |
| 186 | { |
| 187 | dev_dbg(&ssp->pdev->dev, "SSCR0 0x%08x SSCR1 0x%08x SSTO 0x%08x\n", |
| 188 | ssp_read_reg(ssp, SSCR0), ssp_read_reg(ssp, SSCR1), |
| 189 | ssp_read_reg(ssp, SSTO)); |
| 190 | |
| 191 | dev_dbg(&ssp->pdev->dev, "SSPSP 0x%08x SSSR 0x%08x SSACD 0x%08x\n", |
| 192 | ssp_read_reg(ssp, SSPSP), ssp_read_reg(ssp, SSSR), |
| 193 | ssp_read_reg(ssp, SSACD)); |
| 194 | } |
| 195 | |
| 196 | static struct pxa2xx_pcm_dma_params *ssp_dma_params[4][4] = { |
| 197 | { |
| 198 | &pxa_ssp1_pcm_mono_out, &pxa_ssp1_pcm_mono_in, |
| 199 | &pxa_ssp1_pcm_stereo_out, &pxa_ssp1_pcm_stereo_in, |
| 200 | }, |
| 201 | { |
| 202 | &pxa_ssp2_pcm_mono_out, &pxa_ssp2_pcm_mono_in, |
| 203 | &pxa_ssp2_pcm_stereo_out, &pxa_ssp2_pcm_stereo_in, |
| 204 | }, |
| 205 | { |
| 206 | &pxa_ssp3_pcm_mono_out, &pxa_ssp3_pcm_mono_in, |
| 207 | &pxa_ssp3_pcm_stereo_out, &pxa_ssp3_pcm_stereo_in, |
| 208 | }, |
| 209 | { |
| 210 | &pxa_ssp4_pcm_mono_out, &pxa_ssp4_pcm_mono_in, |
| 211 | &pxa_ssp4_pcm_stereo_out, &pxa_ssp4_pcm_stereo_in, |
| 212 | }, |
| 213 | }; |
| 214 | |
Mark Brown | dee89c4 | 2008-11-18 22:11:38 +0000 | [diff] [blame^] | 215 | static int pxa_ssp_startup(struct snd_pcm_substream *substream, |
| 216 | struct snd_soc_dai *dai) |
Mark Brown | 1b340bd | 2008-07-30 19:12:04 +0100 | [diff] [blame] | 217 | { |
| 218 | struct snd_soc_pcm_runtime *rtd = substream->private_data; |
| 219 | struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai; |
| 220 | struct ssp_priv *priv = cpu_dai->private_data; |
| 221 | int ret = 0; |
| 222 | |
| 223 | if (!cpu_dai->active) { |
| 224 | ret = ssp_init(&priv->dev, cpu_dai->id + 1, SSP_NO_IRQ); |
| 225 | if (ret < 0) |
| 226 | return ret; |
| 227 | ssp_disable(&priv->dev); |
| 228 | } |
| 229 | return ret; |
| 230 | } |
| 231 | |
Mark Brown | dee89c4 | 2008-11-18 22:11:38 +0000 | [diff] [blame^] | 232 | static void pxa_ssp_shutdown(struct snd_pcm_substream *substream, |
| 233 | struct snd_soc_dai *dai) |
Mark Brown | 1b340bd | 2008-07-30 19:12:04 +0100 | [diff] [blame] | 234 | { |
| 235 | struct snd_soc_pcm_runtime *rtd = substream->private_data; |
| 236 | struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai; |
| 237 | struct ssp_priv *priv = cpu_dai->private_data; |
| 238 | |
| 239 | if (!cpu_dai->active) { |
| 240 | ssp_disable(&priv->dev); |
| 241 | ssp_exit(&priv->dev); |
| 242 | } |
| 243 | } |
| 244 | |
| 245 | #ifdef CONFIG_PM |
| 246 | |
| 247 | static int pxa_ssp_suspend(struct platform_device *pdev, |
| 248 | struct snd_soc_dai *cpu_dai) |
| 249 | { |
| 250 | struct ssp_priv *priv = cpu_dai->private_data; |
| 251 | |
| 252 | if (!cpu_dai->active) |
| 253 | return 0; |
| 254 | |
| 255 | ssp_save_state(&priv->dev, &priv->state); |
| 256 | clk_disable(priv->dev.ssp->clk); |
| 257 | return 0; |
| 258 | } |
| 259 | |
| 260 | static int pxa_ssp_resume(struct platform_device *pdev, |
| 261 | struct snd_soc_dai *cpu_dai) |
| 262 | { |
| 263 | struct ssp_priv *priv = cpu_dai->private_data; |
| 264 | |
| 265 | if (!cpu_dai->active) |
| 266 | return 0; |
| 267 | |
| 268 | clk_enable(priv->dev.ssp->clk); |
| 269 | ssp_restore_state(&priv->dev, &priv->state); |
| 270 | ssp_enable(&priv->dev); |
| 271 | |
| 272 | return 0; |
| 273 | } |
| 274 | |
| 275 | #else |
| 276 | #define pxa_ssp_suspend NULL |
| 277 | #define pxa_ssp_resume NULL |
| 278 | #endif |
| 279 | |
| 280 | /** |
| 281 | * ssp_set_clkdiv - set SSP clock divider |
| 282 | * @div: serial clock rate divider |
| 283 | */ |
| 284 | static void ssp_set_scr(struct ssp_dev *dev, u32 div) |
| 285 | { |
| 286 | struct ssp_device *ssp = dev->ssp; |
| 287 | u32 sscr0 = ssp_read_reg(dev->ssp, SSCR0) & ~SSCR0_SCR; |
| 288 | |
| 289 | ssp_write_reg(ssp, SSCR0, (sscr0 | SSCR0_SerClkDiv(div))); |
| 290 | } |
| 291 | |
| 292 | /* |
| 293 | * Set the SSP ports SYSCLK. |
| 294 | */ |
| 295 | static int pxa_ssp_set_dai_sysclk(struct snd_soc_dai *cpu_dai, |
| 296 | int clk_id, unsigned int freq, int dir) |
| 297 | { |
| 298 | struct ssp_priv *priv = cpu_dai->private_data; |
| 299 | struct ssp_device *ssp = priv->dev.ssp; |
| 300 | int val; |
| 301 | |
| 302 | u32 sscr0 = ssp_read_reg(ssp, SSCR0) & |
| 303 | ~(SSCR0_ECS | SSCR0_NCS | SSCR0_MOD | SSCR0_ADC); |
| 304 | |
| 305 | dev_dbg(&ssp->pdev->dev, |
| 306 | "pxa_ssp_set_dai_sysclk id: %d, clk_id %d, freq %d\n", |
| 307 | cpu_dai->id, clk_id, freq); |
| 308 | |
| 309 | switch (clk_id) { |
| 310 | case PXA_SSP_CLK_NET_PLL: |
| 311 | sscr0 |= SSCR0_MOD; |
| 312 | break; |
| 313 | case PXA_SSP_CLK_PLL: |
| 314 | /* Internal PLL is fixed */ |
| 315 | if (cpu_is_pxa25x()) |
| 316 | priv->sysclk = 1843200; |
| 317 | else |
| 318 | priv->sysclk = 13000000; |
| 319 | break; |
| 320 | case PXA_SSP_CLK_EXT: |
| 321 | priv->sysclk = freq; |
| 322 | sscr0 |= SSCR0_ECS; |
| 323 | break; |
| 324 | case PXA_SSP_CLK_NET: |
| 325 | priv->sysclk = freq; |
| 326 | sscr0 |= SSCR0_NCS | SSCR0_MOD; |
| 327 | break; |
| 328 | case PXA_SSP_CLK_AUDIO: |
| 329 | priv->sysclk = 0; |
| 330 | ssp_set_scr(&priv->dev, 1); |
| 331 | sscr0 |= SSCR0_ADC; |
| 332 | break; |
| 333 | default: |
| 334 | return -ENODEV; |
| 335 | } |
| 336 | |
| 337 | /* The SSP clock must be disabled when changing SSP clock mode |
| 338 | * on PXA2xx. On PXA3xx it must be enabled when doing so. */ |
| 339 | if (!cpu_is_pxa3xx()) |
| 340 | clk_disable(priv->dev.ssp->clk); |
| 341 | val = ssp_read_reg(ssp, SSCR0) | sscr0; |
| 342 | ssp_write_reg(ssp, SSCR0, val); |
| 343 | if (!cpu_is_pxa3xx()) |
| 344 | clk_enable(priv->dev.ssp->clk); |
| 345 | |
| 346 | return 0; |
| 347 | } |
| 348 | |
| 349 | /* |
| 350 | * Set the SSP clock dividers. |
| 351 | */ |
| 352 | static int pxa_ssp_set_dai_clkdiv(struct snd_soc_dai *cpu_dai, |
| 353 | int div_id, int div) |
| 354 | { |
| 355 | struct ssp_priv *priv = cpu_dai->private_data; |
| 356 | struct ssp_device *ssp = priv->dev.ssp; |
| 357 | int val; |
| 358 | |
| 359 | switch (div_id) { |
| 360 | case PXA_SSP_AUDIO_DIV_ACDS: |
| 361 | val = (ssp_read_reg(ssp, SSACD) & ~0x7) | SSACD_ACDS(div); |
| 362 | ssp_write_reg(ssp, SSACD, val); |
| 363 | break; |
| 364 | case PXA_SSP_AUDIO_DIV_SCDB: |
| 365 | val = ssp_read_reg(ssp, SSACD); |
| 366 | val &= ~SSACD_SCDB; |
| 367 | #if defined(CONFIG_PXA3xx) |
| 368 | if (cpu_is_pxa3xx()) |
| 369 | val &= ~SSACD_SCDX8; |
| 370 | #endif |
| 371 | switch (div) { |
| 372 | case PXA_SSP_CLK_SCDB_1: |
| 373 | val |= SSACD_SCDB; |
| 374 | break; |
| 375 | case PXA_SSP_CLK_SCDB_4: |
| 376 | break; |
| 377 | #if defined(CONFIG_PXA3xx) |
| 378 | case PXA_SSP_CLK_SCDB_8: |
| 379 | if (cpu_is_pxa3xx()) |
| 380 | val |= SSACD_SCDX8; |
| 381 | else |
| 382 | return -EINVAL; |
| 383 | break; |
| 384 | #endif |
| 385 | default: |
| 386 | return -EINVAL; |
| 387 | } |
| 388 | ssp_write_reg(ssp, SSACD, val); |
| 389 | break; |
| 390 | case PXA_SSP_DIV_SCR: |
| 391 | ssp_set_scr(&priv->dev, div); |
| 392 | break; |
| 393 | default: |
| 394 | return -ENODEV; |
| 395 | } |
| 396 | |
| 397 | return 0; |
| 398 | } |
| 399 | |
| 400 | /* |
| 401 | * Configure the PLL frequency pxa27x and (afaik - pxa320 only) |
| 402 | */ |
| 403 | static int pxa_ssp_set_dai_pll(struct snd_soc_dai *cpu_dai, |
| 404 | int pll_id, unsigned int freq_in, unsigned int freq_out) |
| 405 | { |
| 406 | struct ssp_priv *priv = cpu_dai->private_data; |
| 407 | struct ssp_device *ssp = priv->dev.ssp; |
| 408 | u32 ssacd = ssp_read_reg(ssp, SSACD) & ~0x70; |
| 409 | |
| 410 | #if defined(CONFIG_PXA3xx) |
| 411 | if (cpu_is_pxa3xx()) |
| 412 | ssp_write_reg(ssp, SSACDD, 0); |
| 413 | #endif |
| 414 | |
| 415 | switch (freq_out) { |
| 416 | case 5622000: |
| 417 | break; |
| 418 | case 11345000: |
| 419 | ssacd |= (0x1 << 4); |
| 420 | break; |
| 421 | case 12235000: |
| 422 | ssacd |= (0x2 << 4); |
| 423 | break; |
| 424 | case 14857000: |
| 425 | ssacd |= (0x3 << 4); |
| 426 | break; |
| 427 | case 32842000: |
| 428 | ssacd |= (0x4 << 4); |
| 429 | break; |
| 430 | case 48000000: |
| 431 | ssacd |= (0x5 << 4); |
| 432 | break; |
| 433 | case 0: |
| 434 | /* Disable */ |
| 435 | break; |
| 436 | |
| 437 | default: |
| 438 | #ifdef CONFIG_PXA3xx |
| 439 | /* PXA3xx has a clock ditherer which can be used to generate |
| 440 | * a wider range of frequencies - calculate a value for it. |
| 441 | */ |
| 442 | if (cpu_is_pxa3xx()) { |
| 443 | u32 val; |
| 444 | u64 tmp = 19968; |
| 445 | tmp *= 1000000; |
| 446 | do_div(tmp, freq_out); |
| 447 | val = tmp; |
| 448 | |
| 449 | val = (val << 16) | 64;; |
| 450 | ssp_write_reg(ssp, SSACDD, val); |
| 451 | |
| 452 | ssacd |= (0x6 << 4); |
| 453 | |
| 454 | dev_dbg(&ssp->pdev->dev, |
| 455 | "Using SSACDD %x to supply %dHz\n", |
| 456 | val, freq_out); |
| 457 | break; |
| 458 | } |
| 459 | #endif |
| 460 | |
| 461 | return -EINVAL; |
| 462 | } |
| 463 | |
| 464 | ssp_write_reg(ssp, SSACD, ssacd); |
| 465 | |
| 466 | return 0; |
| 467 | } |
| 468 | |
| 469 | /* |
| 470 | * Set the active slots in TDM/Network mode |
| 471 | */ |
| 472 | static int pxa_ssp_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, |
| 473 | unsigned int mask, int slots) |
| 474 | { |
| 475 | struct ssp_priv *priv = cpu_dai->private_data; |
| 476 | struct ssp_device *ssp = priv->dev.ssp; |
| 477 | u32 sscr0; |
| 478 | |
| 479 | sscr0 = ssp_read_reg(ssp, SSCR0) & ~SSCR0_SlotsPerFrm(7); |
| 480 | |
| 481 | /* set number of active slots */ |
| 482 | sscr0 |= SSCR0_SlotsPerFrm(slots); |
| 483 | ssp_write_reg(ssp, SSCR0, sscr0); |
| 484 | |
| 485 | /* set active slot mask */ |
| 486 | ssp_write_reg(ssp, SSTSA, mask); |
| 487 | ssp_write_reg(ssp, SSRSA, mask); |
| 488 | return 0; |
| 489 | } |
| 490 | |
| 491 | /* |
| 492 | * Tristate the SSP DAI lines |
| 493 | */ |
| 494 | static int pxa_ssp_set_dai_tristate(struct snd_soc_dai *cpu_dai, |
| 495 | int tristate) |
| 496 | { |
| 497 | struct ssp_priv *priv = cpu_dai->private_data; |
| 498 | struct ssp_device *ssp = priv->dev.ssp; |
| 499 | u32 sscr1; |
| 500 | |
| 501 | sscr1 = ssp_read_reg(ssp, SSCR1); |
| 502 | if (tristate) |
| 503 | sscr1 &= ~SSCR1_TTE; |
| 504 | else |
| 505 | sscr1 |= SSCR1_TTE; |
| 506 | ssp_write_reg(ssp, SSCR1, sscr1); |
| 507 | |
| 508 | return 0; |
| 509 | } |
| 510 | |
| 511 | /* |
| 512 | * Set up the SSP DAI format. |
| 513 | * The SSP Port must be inactive before calling this function as the |
| 514 | * physical interface format is changed. |
| 515 | */ |
| 516 | static int pxa_ssp_set_dai_fmt(struct snd_soc_dai *cpu_dai, |
| 517 | unsigned int fmt) |
| 518 | { |
| 519 | struct ssp_priv *priv = cpu_dai->private_data; |
| 520 | struct ssp_device *ssp = priv->dev.ssp; |
| 521 | u32 sscr0; |
| 522 | u32 sscr1; |
| 523 | u32 sspsp; |
| 524 | |
| 525 | /* reset port settings */ |
| 526 | sscr0 = ssp_read_reg(ssp, SSCR0) & |
| 527 | (SSCR0_ECS | SSCR0_NCS | SSCR0_MOD | SSCR0_ADC); |
| 528 | sscr1 = SSCR1_RxTresh(8) | SSCR1_TxTresh(7); |
| 529 | sspsp = 0; |
| 530 | |
| 531 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { |
| 532 | case SND_SOC_DAIFMT_CBM_CFM: |
| 533 | sscr1 |= SSCR1_SCLKDIR | SSCR1_SFRMDIR; |
| 534 | break; |
| 535 | case SND_SOC_DAIFMT_CBM_CFS: |
| 536 | sscr1 |= SSCR1_SCLKDIR; |
| 537 | break; |
| 538 | case SND_SOC_DAIFMT_CBS_CFS: |
| 539 | break; |
| 540 | default: |
| 541 | return -EINVAL; |
| 542 | } |
| 543 | |
| 544 | ssp_write_reg(ssp, SSCR0, sscr0); |
| 545 | ssp_write_reg(ssp, SSCR1, sscr1); |
| 546 | ssp_write_reg(ssp, SSPSP, sspsp); |
| 547 | |
| 548 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { |
| 549 | case SND_SOC_DAIFMT_I2S: |
| 550 | sscr0 |= SSCR0_MOD | SSCR0_PSP; |
| 551 | sscr1 |= SSCR1_RWOT | SSCR1_TRAIL; |
| 552 | |
| 553 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { |
| 554 | case SND_SOC_DAIFMT_NB_NF: |
| 555 | sspsp |= SSPSP_FSRT; |
| 556 | break; |
| 557 | case SND_SOC_DAIFMT_NB_IF: |
| 558 | sspsp |= SSPSP_SFRMP | SSPSP_FSRT; |
| 559 | break; |
| 560 | case SND_SOC_DAIFMT_IB_IF: |
| 561 | sspsp |= SSPSP_SFRMP; |
| 562 | break; |
| 563 | default: |
| 564 | return -EINVAL; |
| 565 | } |
| 566 | break; |
| 567 | |
| 568 | case SND_SOC_DAIFMT_DSP_A: |
| 569 | sspsp |= SSPSP_FSRT; |
| 570 | case SND_SOC_DAIFMT_DSP_B: |
| 571 | sscr0 |= SSCR0_MOD | SSCR0_PSP; |
| 572 | sscr1 |= SSCR1_TRAIL | SSCR1_RWOT; |
| 573 | |
| 574 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { |
| 575 | case SND_SOC_DAIFMT_NB_NF: |
| 576 | sspsp |= SSPSP_SFRMP; |
| 577 | break; |
| 578 | case SND_SOC_DAIFMT_IB_IF: |
| 579 | break; |
| 580 | default: |
| 581 | return -EINVAL; |
| 582 | } |
| 583 | break; |
| 584 | |
| 585 | default: |
| 586 | return -EINVAL; |
| 587 | } |
| 588 | |
| 589 | ssp_write_reg(ssp, SSCR0, sscr0); |
| 590 | ssp_write_reg(ssp, SSCR1, sscr1); |
| 591 | ssp_write_reg(ssp, SSPSP, sspsp); |
| 592 | |
| 593 | dump_registers(ssp); |
| 594 | |
| 595 | /* Since we are configuring the timings for the format by hand |
| 596 | * we have to defer some things until hw_params() where we |
| 597 | * know parameters like the sample size. |
| 598 | */ |
| 599 | priv->dai_fmt = fmt; |
| 600 | |
| 601 | return 0; |
| 602 | } |
| 603 | |
| 604 | /* |
| 605 | * Set the SSP audio DMA parameters and sample size. |
| 606 | * Can be called multiple times by oss emulation. |
| 607 | */ |
| 608 | static int pxa_ssp_hw_params(struct snd_pcm_substream *substream, |
Mark Brown | dee89c4 | 2008-11-18 22:11:38 +0000 | [diff] [blame^] | 609 | struct snd_pcm_hw_params *params, |
| 610 | struct snd_soc_dai *dai) |
Mark Brown | 1b340bd | 2008-07-30 19:12:04 +0100 | [diff] [blame] | 611 | { |
| 612 | struct snd_soc_pcm_runtime *rtd = substream->private_data; |
| 613 | struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai; |
| 614 | struct ssp_priv *priv = cpu_dai->private_data; |
| 615 | struct ssp_device *ssp = priv->dev.ssp; |
| 616 | int dma = 0, chn = params_channels(params); |
| 617 | u32 sscr0; |
| 618 | u32 sspsp; |
| 619 | int width = snd_pcm_format_physical_width(params_format(params)); |
| 620 | |
| 621 | /* select correct DMA params */ |
| 622 | if (substream->stream != SNDRV_PCM_STREAM_PLAYBACK) |
| 623 | dma = 1; /* capture DMA offset is 1,3 */ |
| 624 | if (chn == 2) |
| 625 | dma += 2; /* stereo DMA offset is 2, mono is 0 */ |
| 626 | cpu_dai->dma_data = ssp_dma_params[cpu_dai->id][dma]; |
| 627 | |
| 628 | dev_dbg(&ssp->pdev->dev, "pxa_ssp_hw_params: dma %d\n", dma); |
| 629 | |
| 630 | /* we can only change the settings if the port is not in use */ |
| 631 | if (ssp_read_reg(ssp, SSCR0) & SSCR0_SSE) |
| 632 | return 0; |
| 633 | |
| 634 | /* clear selected SSP bits */ |
| 635 | sscr0 = ssp_read_reg(ssp, SSCR0) & ~(SSCR0_DSS | SSCR0_EDSS); |
| 636 | ssp_write_reg(ssp, SSCR0, sscr0); |
| 637 | |
| 638 | /* bit size */ |
| 639 | sscr0 = ssp_read_reg(ssp, SSCR0); |
| 640 | switch (params_format(params)) { |
| 641 | case SNDRV_PCM_FORMAT_S16_LE: |
| 642 | #ifdef CONFIG_PXA3xx |
| 643 | if (cpu_is_pxa3xx()) |
| 644 | sscr0 |= SSCR0_FPCKE; |
| 645 | #endif |
| 646 | sscr0 |= SSCR0_DataSize(16); |
| 647 | if (params_channels(params) > 1) |
| 648 | sscr0 |= SSCR0_EDSS; |
| 649 | break; |
| 650 | case SNDRV_PCM_FORMAT_S24_LE: |
| 651 | sscr0 |= (SSCR0_EDSS | SSCR0_DataSize(8)); |
| 652 | /* we must be in network mode (2 slots) for 24 bit stereo */ |
| 653 | break; |
| 654 | case SNDRV_PCM_FORMAT_S32_LE: |
| 655 | sscr0 |= (SSCR0_EDSS | SSCR0_DataSize(16)); |
| 656 | /* we must be in network mode (2 slots) for 32 bit stereo */ |
| 657 | break; |
| 658 | } |
| 659 | ssp_write_reg(ssp, SSCR0, sscr0); |
| 660 | |
| 661 | switch (priv->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) { |
| 662 | case SND_SOC_DAIFMT_I2S: |
| 663 | /* Cleared when the DAI format is set */ |
| 664 | sspsp = ssp_read_reg(ssp, SSPSP) | SSPSP_SFRMWDTH(width); |
| 665 | ssp_write_reg(ssp, SSPSP, sspsp); |
| 666 | break; |
| 667 | default: |
| 668 | break; |
| 669 | } |
| 670 | |
| 671 | /* We always use a network mode so we always require TDM slots |
| 672 | * - complain loudly and fail if they've not been set up yet. |
| 673 | */ |
| 674 | if (!(ssp_read_reg(ssp, SSTSA) & 0xf)) { |
| 675 | dev_err(&ssp->pdev->dev, "No TDM timeslot configured\n"); |
| 676 | return -EINVAL; |
| 677 | } |
| 678 | |
| 679 | dump_registers(ssp); |
| 680 | |
| 681 | return 0; |
| 682 | } |
| 683 | |
Mark Brown | dee89c4 | 2008-11-18 22:11:38 +0000 | [diff] [blame^] | 684 | static int pxa_ssp_trigger(struct snd_pcm_substream *substream, int cmd, |
| 685 | struct snd_soc_dai *dai) |
Mark Brown | 1b340bd | 2008-07-30 19:12:04 +0100 | [diff] [blame] | 686 | { |
| 687 | struct snd_soc_pcm_runtime *rtd = substream->private_data; |
| 688 | struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai; |
| 689 | int ret = 0; |
| 690 | struct ssp_priv *priv = cpu_dai->private_data; |
| 691 | struct ssp_device *ssp = priv->dev.ssp; |
| 692 | int val; |
| 693 | |
| 694 | switch (cmd) { |
| 695 | case SNDRV_PCM_TRIGGER_RESUME: |
| 696 | ssp_enable(&priv->dev); |
| 697 | break; |
| 698 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: |
| 699 | val = ssp_read_reg(ssp, SSCR1); |
| 700 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) |
| 701 | val |= SSCR1_TSRE; |
| 702 | else |
| 703 | val |= SSCR1_RSRE; |
| 704 | ssp_write_reg(ssp, SSCR1, val); |
| 705 | val = ssp_read_reg(ssp, SSSR); |
| 706 | ssp_write_reg(ssp, SSSR, val); |
| 707 | break; |
| 708 | case SNDRV_PCM_TRIGGER_START: |
| 709 | val = ssp_read_reg(ssp, SSCR1); |
| 710 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) |
| 711 | val |= SSCR1_TSRE; |
| 712 | else |
| 713 | val |= SSCR1_RSRE; |
| 714 | ssp_write_reg(ssp, SSCR1, val); |
| 715 | ssp_enable(&priv->dev); |
| 716 | break; |
| 717 | case SNDRV_PCM_TRIGGER_STOP: |
| 718 | val = ssp_read_reg(ssp, SSCR1); |
| 719 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) |
| 720 | val &= ~SSCR1_TSRE; |
| 721 | else |
| 722 | val &= ~SSCR1_RSRE; |
| 723 | ssp_write_reg(ssp, SSCR1, val); |
| 724 | break; |
| 725 | case SNDRV_PCM_TRIGGER_SUSPEND: |
| 726 | ssp_disable(&priv->dev); |
| 727 | break; |
| 728 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: |
| 729 | val = ssp_read_reg(ssp, SSCR1); |
| 730 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) |
| 731 | val &= ~SSCR1_TSRE; |
| 732 | else |
| 733 | val &= ~SSCR1_RSRE; |
| 734 | ssp_write_reg(ssp, SSCR1, val); |
| 735 | break; |
| 736 | |
| 737 | default: |
| 738 | ret = -EINVAL; |
| 739 | } |
| 740 | |
| 741 | dump_registers(ssp); |
| 742 | |
| 743 | return ret; |
| 744 | } |
| 745 | |
| 746 | static int pxa_ssp_probe(struct platform_device *pdev, |
| 747 | struct snd_soc_dai *dai) |
| 748 | { |
| 749 | struct ssp_priv *priv; |
| 750 | int ret; |
| 751 | |
| 752 | priv = kzalloc(sizeof(struct ssp_priv), GFP_KERNEL); |
| 753 | if (!priv) |
| 754 | return -ENOMEM; |
| 755 | |
| 756 | priv->dev.ssp = ssp_request(dai->id, "SoC audio"); |
| 757 | if (priv->dev.ssp == NULL) { |
| 758 | ret = -ENODEV; |
| 759 | goto err_priv; |
| 760 | } |
| 761 | |
| 762 | dai->private_data = priv; |
| 763 | |
| 764 | return 0; |
| 765 | |
| 766 | err_priv: |
| 767 | kfree(priv); |
| 768 | return ret; |
| 769 | } |
| 770 | |
| 771 | static void pxa_ssp_remove(struct platform_device *pdev, |
| 772 | struct snd_soc_dai *dai) |
| 773 | { |
| 774 | struct ssp_priv *priv = dai->private_data; |
| 775 | ssp_free(priv->dev.ssp); |
| 776 | } |
| 777 | |
| 778 | #define PXA_SSP_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\ |
| 779 | SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | \ |
| 780 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 | \ |
| 781 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000) |
| 782 | |
| 783 | #define PXA_SSP_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ |
| 784 | SNDRV_PCM_FMTBIT_S24_LE | \ |
| 785 | SNDRV_PCM_FMTBIT_S32_LE) |
| 786 | |
| 787 | struct snd_soc_dai pxa_ssp_dai[] = { |
| 788 | { |
| 789 | .name = "pxa2xx-ssp1", |
| 790 | .id = 0, |
| 791 | .type = SND_SOC_DAI_PCM, |
| 792 | .probe = pxa_ssp_probe, |
| 793 | .remove = pxa_ssp_remove, |
| 794 | .suspend = pxa_ssp_suspend, |
| 795 | .resume = pxa_ssp_resume, |
| 796 | .playback = { |
| 797 | .channels_min = 1, |
| 798 | .channels_max = 2, |
| 799 | .rates = PXA_SSP_RATES, |
| 800 | .formats = PXA_SSP_FORMATS, |
| 801 | }, |
| 802 | .capture = { |
| 803 | .channels_min = 1, |
| 804 | .channels_max = 2, |
| 805 | .rates = PXA_SSP_RATES, |
| 806 | .formats = PXA_SSP_FORMATS, |
| 807 | }, |
| 808 | .ops = { |
| 809 | .startup = pxa_ssp_startup, |
| 810 | .shutdown = pxa_ssp_shutdown, |
| 811 | .trigger = pxa_ssp_trigger, |
| 812 | .hw_params = pxa_ssp_hw_params, |
Mark Brown | 1b340bd | 2008-07-30 19:12:04 +0100 | [diff] [blame] | 813 | .set_sysclk = pxa_ssp_set_dai_sysclk, |
| 814 | .set_clkdiv = pxa_ssp_set_dai_clkdiv, |
| 815 | .set_pll = pxa_ssp_set_dai_pll, |
| 816 | .set_fmt = pxa_ssp_set_dai_fmt, |
| 817 | .set_tdm_slot = pxa_ssp_set_dai_tdm_slot, |
| 818 | .set_tristate = pxa_ssp_set_dai_tristate, |
| 819 | }, |
| 820 | }, |
| 821 | { .name = "pxa2xx-ssp2", |
| 822 | .id = 1, |
| 823 | .type = SND_SOC_DAI_PCM, |
| 824 | .probe = pxa_ssp_probe, |
| 825 | .remove = pxa_ssp_remove, |
| 826 | .suspend = pxa_ssp_suspend, |
| 827 | .resume = pxa_ssp_resume, |
| 828 | .playback = { |
| 829 | .channels_min = 1, |
| 830 | .channels_max = 2, |
| 831 | .rates = PXA_SSP_RATES, |
| 832 | .formats = PXA_SSP_FORMATS, |
| 833 | }, |
| 834 | .capture = { |
| 835 | .channels_min = 1, |
| 836 | .channels_max = 2, |
| 837 | .rates = PXA_SSP_RATES, |
| 838 | .formats = PXA_SSP_FORMATS, |
| 839 | }, |
| 840 | .ops = { |
| 841 | .startup = pxa_ssp_startup, |
| 842 | .shutdown = pxa_ssp_shutdown, |
| 843 | .trigger = pxa_ssp_trigger, |
| 844 | .hw_params = pxa_ssp_hw_params, |
Mark Brown | 1b340bd | 2008-07-30 19:12:04 +0100 | [diff] [blame] | 845 | .set_sysclk = pxa_ssp_set_dai_sysclk, |
| 846 | .set_clkdiv = pxa_ssp_set_dai_clkdiv, |
| 847 | .set_pll = pxa_ssp_set_dai_pll, |
| 848 | .set_fmt = pxa_ssp_set_dai_fmt, |
| 849 | .set_tdm_slot = pxa_ssp_set_dai_tdm_slot, |
| 850 | .set_tristate = pxa_ssp_set_dai_tristate, |
| 851 | }, |
| 852 | }, |
| 853 | { |
| 854 | .name = "pxa2xx-ssp3", |
| 855 | .id = 2, |
| 856 | .type = SND_SOC_DAI_PCM, |
| 857 | .probe = pxa_ssp_probe, |
| 858 | .remove = pxa_ssp_remove, |
| 859 | .suspend = pxa_ssp_suspend, |
| 860 | .resume = pxa_ssp_resume, |
| 861 | .playback = { |
| 862 | .channels_min = 1, |
| 863 | .channels_max = 2, |
| 864 | .rates = PXA_SSP_RATES, |
| 865 | .formats = PXA_SSP_FORMATS, |
| 866 | }, |
| 867 | .capture = { |
| 868 | .channels_min = 1, |
| 869 | .channels_max = 2, |
| 870 | .rates = PXA_SSP_RATES, |
| 871 | .formats = PXA_SSP_FORMATS, |
| 872 | }, |
| 873 | .ops = { |
| 874 | .startup = pxa_ssp_startup, |
| 875 | .shutdown = pxa_ssp_shutdown, |
| 876 | .trigger = pxa_ssp_trigger, |
| 877 | .hw_params = pxa_ssp_hw_params, |
Mark Brown | 1b340bd | 2008-07-30 19:12:04 +0100 | [diff] [blame] | 878 | .set_sysclk = pxa_ssp_set_dai_sysclk, |
| 879 | .set_clkdiv = pxa_ssp_set_dai_clkdiv, |
| 880 | .set_pll = pxa_ssp_set_dai_pll, |
| 881 | .set_fmt = pxa_ssp_set_dai_fmt, |
| 882 | .set_tdm_slot = pxa_ssp_set_dai_tdm_slot, |
| 883 | .set_tristate = pxa_ssp_set_dai_tristate, |
| 884 | }, |
| 885 | }, |
| 886 | { |
| 887 | .name = "pxa2xx-ssp4", |
| 888 | .id = 3, |
| 889 | .type = SND_SOC_DAI_PCM, |
| 890 | .probe = pxa_ssp_probe, |
| 891 | .remove = pxa_ssp_remove, |
| 892 | .suspend = pxa_ssp_suspend, |
| 893 | .resume = pxa_ssp_resume, |
| 894 | .playback = { |
| 895 | .channels_min = 1, |
| 896 | .channels_max = 2, |
| 897 | .rates = PXA_SSP_RATES, |
| 898 | .formats = PXA_SSP_FORMATS, |
| 899 | }, |
| 900 | .capture = { |
| 901 | .channels_min = 1, |
| 902 | .channels_max = 2, |
| 903 | .rates = PXA_SSP_RATES, |
| 904 | .formats = PXA_SSP_FORMATS, |
| 905 | }, |
| 906 | .ops = { |
| 907 | .startup = pxa_ssp_startup, |
| 908 | .shutdown = pxa_ssp_shutdown, |
| 909 | .trigger = pxa_ssp_trigger, |
| 910 | .hw_params = pxa_ssp_hw_params, |
Mark Brown | 1b340bd | 2008-07-30 19:12:04 +0100 | [diff] [blame] | 911 | .set_sysclk = pxa_ssp_set_dai_sysclk, |
| 912 | .set_clkdiv = pxa_ssp_set_dai_clkdiv, |
| 913 | .set_pll = pxa_ssp_set_dai_pll, |
| 914 | .set_fmt = pxa_ssp_set_dai_fmt, |
| 915 | .set_tdm_slot = pxa_ssp_set_dai_tdm_slot, |
| 916 | .set_tristate = pxa_ssp_set_dai_tristate, |
| 917 | }, |
| 918 | }, |
| 919 | }; |
| 920 | EXPORT_SYMBOL_GPL(pxa_ssp_dai); |
| 921 | |
| 922 | /* Module information */ |
| 923 | MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>"); |
| 924 | MODULE_DESCRIPTION("PXA SSP/PCM SoC Interface"); |
| 925 | MODULE_LICENSE("GPL"); |