Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2 | * PCI Bus Services, see include/linux/pci.h for further explanation. |
| 3 | * |
| 4 | * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter, |
| 5 | * David Mosberger-Tang |
| 6 | * |
| 7 | * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz> |
| 8 | */ |
| 9 | |
| 10 | #include <linux/kernel.h> |
| 11 | #include <linux/delay.h> |
| 12 | #include <linux/init.h> |
| 13 | #include <linux/pci.h> |
David Brownell | 075c177 | 2007-04-26 00:12:06 -0700 | [diff] [blame] | 14 | #include <linux/pm.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 15 | #include <linux/module.h> |
| 16 | #include <linux/spinlock.h> |
Tim Schmielau | 4e57b68 | 2005-10-30 15:03:48 -0800 | [diff] [blame] | 17 | #include <linux/string.h> |
vignesh babu | 229f5af | 2007-08-13 18:23:14 +0530 | [diff] [blame] | 18 | #include <linux/log2.h> |
Shaohua Li | 7d715a6 | 2008-02-25 09:46:41 +0800 | [diff] [blame] | 19 | #include <linux/pci-aspm.h> |
Stephen Rothwell | c300bd2fb | 2008-07-10 02:16:44 +0200 | [diff] [blame] | 20 | #include <linux/pm_wakeup.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 21 | #include <asm/dma.h> /* isa_dma_bridge_buggy */ |
Greg KH | bc56b9e | 2005-04-08 14:53:31 +0900 | [diff] [blame] | 22 | #include "pci.h" |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 23 | |
Kristen Carlson Accardi | ffadcc2 | 2006-07-12 08:59:00 -0700 | [diff] [blame] | 24 | unsigned int pci_pm_d3_delay = 10; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 25 | |
Jeff Garzik | 32a2eea | 2007-10-11 16:57:27 -0400 | [diff] [blame] | 26 | #ifdef CONFIG_PCI_DOMAINS |
| 27 | int pci_domains_supported = 1; |
| 28 | #endif |
| 29 | |
Atsushi Nemoto | 4516a61 | 2007-02-05 16:36:06 -0800 | [diff] [blame] | 30 | #define DEFAULT_CARDBUS_IO_SIZE (256) |
| 31 | #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024) |
| 32 | /* pci=cbmemsize=nnM,cbiosize=nn can override this */ |
| 33 | unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE; |
| 34 | unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE; |
| 35 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 36 | /** |
| 37 | * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children |
| 38 | * @bus: pointer to PCI bus structure to search |
| 39 | * |
| 40 | * Given a PCI bus, returns the highest PCI bus number present in the set |
| 41 | * including the given PCI bus and its list of child PCI buses. |
| 42 | */ |
Sam Ravnborg | 96bde06 | 2007-03-26 21:53:30 -0800 | [diff] [blame] | 43 | unsigned char pci_bus_max_busnr(struct pci_bus* bus) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 44 | { |
| 45 | struct list_head *tmp; |
| 46 | unsigned char max, n; |
| 47 | |
Kristen Accardi | b82db5c | 2006-01-17 16:56:56 -0800 | [diff] [blame] | 48 | max = bus->subordinate; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 49 | list_for_each(tmp, &bus->children) { |
| 50 | n = pci_bus_max_busnr(pci_bus_b(tmp)); |
| 51 | if(n > max) |
| 52 | max = n; |
| 53 | } |
| 54 | return max; |
| 55 | } |
Kristen Accardi | b82db5c | 2006-01-17 16:56:56 -0800 | [diff] [blame] | 56 | EXPORT_SYMBOL_GPL(pci_bus_max_busnr); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 57 | |
Kristen Accardi | b82db5c | 2006-01-17 16:56:56 -0800 | [diff] [blame] | 58 | #if 0 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 59 | /** |
| 60 | * pci_max_busnr - returns maximum PCI bus number |
| 61 | * |
| 62 | * Returns the highest PCI bus number present in the system global list of |
| 63 | * PCI buses. |
| 64 | */ |
| 65 | unsigned char __devinit |
| 66 | pci_max_busnr(void) |
| 67 | { |
| 68 | struct pci_bus *bus = NULL; |
| 69 | unsigned char max, n; |
| 70 | |
| 71 | max = 0; |
| 72 | while ((bus = pci_find_next_bus(bus)) != NULL) { |
| 73 | n = pci_bus_max_busnr(bus); |
| 74 | if(n > max) |
| 75 | max = n; |
| 76 | } |
| 77 | return max; |
| 78 | } |
| 79 | |
Adrian Bunk | 54c762f | 2005-12-22 01:08:52 +0100 | [diff] [blame] | 80 | #endif /* 0 */ |
| 81 | |
Michael Ellerman | 687d5fe | 2006-11-22 18:26:18 +1100 | [diff] [blame] | 82 | #define PCI_FIND_CAP_TTL 48 |
| 83 | |
| 84 | static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn, |
| 85 | u8 pos, int cap, int *ttl) |
Roland Dreier | 24a4e37 | 2005-10-28 17:35:34 -0700 | [diff] [blame] | 86 | { |
| 87 | u8 id; |
Roland Dreier | 24a4e37 | 2005-10-28 17:35:34 -0700 | [diff] [blame] | 88 | |
Michael Ellerman | 687d5fe | 2006-11-22 18:26:18 +1100 | [diff] [blame] | 89 | while ((*ttl)--) { |
Roland Dreier | 24a4e37 | 2005-10-28 17:35:34 -0700 | [diff] [blame] | 90 | pci_bus_read_config_byte(bus, devfn, pos, &pos); |
| 91 | if (pos < 0x40) |
| 92 | break; |
| 93 | pos &= ~3; |
| 94 | pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID, |
| 95 | &id); |
| 96 | if (id == 0xff) |
| 97 | break; |
| 98 | if (id == cap) |
| 99 | return pos; |
| 100 | pos += PCI_CAP_LIST_NEXT; |
| 101 | } |
| 102 | return 0; |
| 103 | } |
| 104 | |
Michael Ellerman | 687d5fe | 2006-11-22 18:26:18 +1100 | [diff] [blame] | 105 | static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn, |
| 106 | u8 pos, int cap) |
| 107 | { |
| 108 | int ttl = PCI_FIND_CAP_TTL; |
| 109 | |
| 110 | return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl); |
| 111 | } |
| 112 | |
Roland Dreier | 24a4e37 | 2005-10-28 17:35:34 -0700 | [diff] [blame] | 113 | int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap) |
| 114 | { |
| 115 | return __pci_find_next_cap(dev->bus, dev->devfn, |
| 116 | pos + PCI_CAP_LIST_NEXT, cap); |
| 117 | } |
| 118 | EXPORT_SYMBOL_GPL(pci_find_next_capability); |
| 119 | |
Michael Ellerman | d3bac11 | 2006-11-22 18:26:16 +1100 | [diff] [blame] | 120 | static int __pci_bus_find_cap_start(struct pci_bus *bus, |
| 121 | unsigned int devfn, u8 hdr_type) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 122 | { |
| 123 | u16 status; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 124 | |
| 125 | pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status); |
| 126 | if (!(status & PCI_STATUS_CAP_LIST)) |
| 127 | return 0; |
| 128 | |
| 129 | switch (hdr_type) { |
| 130 | case PCI_HEADER_TYPE_NORMAL: |
| 131 | case PCI_HEADER_TYPE_BRIDGE: |
Michael Ellerman | d3bac11 | 2006-11-22 18:26:16 +1100 | [diff] [blame] | 132 | return PCI_CAPABILITY_LIST; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 133 | case PCI_HEADER_TYPE_CARDBUS: |
Michael Ellerman | d3bac11 | 2006-11-22 18:26:16 +1100 | [diff] [blame] | 134 | return PCI_CB_CAPABILITY_LIST; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 135 | default: |
| 136 | return 0; |
| 137 | } |
Michael Ellerman | d3bac11 | 2006-11-22 18:26:16 +1100 | [diff] [blame] | 138 | |
| 139 | return 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 140 | } |
| 141 | |
| 142 | /** |
| 143 | * pci_find_capability - query for devices' capabilities |
| 144 | * @dev: PCI device to query |
| 145 | * @cap: capability code |
| 146 | * |
| 147 | * Tell if a device supports a given PCI capability. |
| 148 | * Returns the address of the requested capability structure within the |
| 149 | * device's PCI configuration space or 0 in case the device does not |
| 150 | * support it. Possible values for @cap: |
| 151 | * |
| 152 | * %PCI_CAP_ID_PM Power Management |
| 153 | * %PCI_CAP_ID_AGP Accelerated Graphics Port |
| 154 | * %PCI_CAP_ID_VPD Vital Product Data |
| 155 | * %PCI_CAP_ID_SLOTID Slot Identification |
| 156 | * %PCI_CAP_ID_MSI Message Signalled Interrupts |
| 157 | * %PCI_CAP_ID_CHSWP CompactPCI HotSwap |
| 158 | * %PCI_CAP_ID_PCIX PCI-X |
| 159 | * %PCI_CAP_ID_EXP PCI Express |
| 160 | */ |
| 161 | int pci_find_capability(struct pci_dev *dev, int cap) |
| 162 | { |
Michael Ellerman | d3bac11 | 2006-11-22 18:26:16 +1100 | [diff] [blame] | 163 | int pos; |
| 164 | |
| 165 | pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type); |
| 166 | if (pos) |
| 167 | pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap); |
| 168 | |
| 169 | return pos; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 170 | } |
| 171 | |
| 172 | /** |
| 173 | * pci_bus_find_capability - query for devices' capabilities |
| 174 | * @bus: the PCI bus to query |
| 175 | * @devfn: PCI device to query |
| 176 | * @cap: capability code |
| 177 | * |
| 178 | * Like pci_find_capability() but works for pci devices that do not have a |
| 179 | * pci_dev structure set up yet. |
| 180 | * |
| 181 | * Returns the address of the requested capability structure within the |
| 182 | * device's PCI configuration space or 0 in case the device does not |
| 183 | * support it. |
| 184 | */ |
| 185 | int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap) |
| 186 | { |
Michael Ellerman | d3bac11 | 2006-11-22 18:26:16 +1100 | [diff] [blame] | 187 | int pos; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 188 | u8 hdr_type; |
| 189 | |
| 190 | pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type); |
| 191 | |
Michael Ellerman | d3bac11 | 2006-11-22 18:26:16 +1100 | [diff] [blame] | 192 | pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f); |
| 193 | if (pos) |
| 194 | pos = __pci_find_next_cap(bus, devfn, pos, cap); |
| 195 | |
| 196 | return pos; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 197 | } |
| 198 | |
| 199 | /** |
| 200 | * pci_find_ext_capability - Find an extended capability |
| 201 | * @dev: PCI device to query |
| 202 | * @cap: capability code |
| 203 | * |
| 204 | * Returns the address of the requested extended capability structure |
| 205 | * within the device's PCI configuration space or 0 if the device does |
| 206 | * not support it. Possible values for @cap: |
| 207 | * |
| 208 | * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting |
| 209 | * %PCI_EXT_CAP_ID_VC Virtual Channel |
| 210 | * %PCI_EXT_CAP_ID_DSN Device Serial Number |
| 211 | * %PCI_EXT_CAP_ID_PWR Power Budgeting |
| 212 | */ |
| 213 | int pci_find_ext_capability(struct pci_dev *dev, int cap) |
| 214 | { |
| 215 | u32 header; |
| 216 | int ttl = 480; /* 3840 bytes, minimum 8 bytes per capability */ |
| 217 | int pos = 0x100; |
| 218 | |
| 219 | if (dev->cfg_size <= 256) |
| 220 | return 0; |
| 221 | |
| 222 | if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL) |
| 223 | return 0; |
| 224 | |
| 225 | /* |
| 226 | * If we have no capabilities, this is indicated by cap ID, |
| 227 | * cap version and next pointer all being 0. |
| 228 | */ |
| 229 | if (header == 0) |
| 230 | return 0; |
| 231 | |
| 232 | while (ttl-- > 0) { |
| 233 | if (PCI_EXT_CAP_ID(header) == cap) |
| 234 | return pos; |
| 235 | |
| 236 | pos = PCI_EXT_CAP_NEXT(header); |
| 237 | if (pos < 0x100) |
| 238 | break; |
| 239 | |
| 240 | if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL) |
| 241 | break; |
| 242 | } |
| 243 | |
| 244 | return 0; |
| 245 | } |
Brice Goglin | 3a720d7 | 2006-05-23 06:10:01 -0400 | [diff] [blame] | 246 | EXPORT_SYMBOL_GPL(pci_find_ext_capability); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 247 | |
Michael Ellerman | 687d5fe | 2006-11-22 18:26:18 +1100 | [diff] [blame] | 248 | static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap) |
| 249 | { |
| 250 | int rc, ttl = PCI_FIND_CAP_TTL; |
| 251 | u8 cap, mask; |
| 252 | |
| 253 | if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST) |
| 254 | mask = HT_3BIT_CAP_MASK; |
| 255 | else |
| 256 | mask = HT_5BIT_CAP_MASK; |
| 257 | |
| 258 | pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos, |
| 259 | PCI_CAP_ID_HT, &ttl); |
| 260 | while (pos) { |
| 261 | rc = pci_read_config_byte(dev, pos + 3, &cap); |
| 262 | if (rc != PCIBIOS_SUCCESSFUL) |
| 263 | return 0; |
| 264 | |
| 265 | if ((cap & mask) == ht_cap) |
| 266 | return pos; |
| 267 | |
Brice Goglin | 47a4d5b | 2007-01-10 23:15:29 -0800 | [diff] [blame] | 268 | pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, |
| 269 | pos + PCI_CAP_LIST_NEXT, |
Michael Ellerman | 687d5fe | 2006-11-22 18:26:18 +1100 | [diff] [blame] | 270 | PCI_CAP_ID_HT, &ttl); |
| 271 | } |
| 272 | |
| 273 | return 0; |
| 274 | } |
| 275 | /** |
| 276 | * pci_find_next_ht_capability - query a device's Hypertransport capabilities |
| 277 | * @dev: PCI device to query |
| 278 | * @pos: Position from which to continue searching |
| 279 | * @ht_cap: Hypertransport capability code |
| 280 | * |
| 281 | * To be used in conjunction with pci_find_ht_capability() to search for |
| 282 | * all capabilities matching @ht_cap. @pos should always be a value returned |
| 283 | * from pci_find_ht_capability(). |
| 284 | * |
| 285 | * NB. To be 100% safe against broken PCI devices, the caller should take |
| 286 | * steps to avoid an infinite loop. |
| 287 | */ |
| 288 | int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap) |
| 289 | { |
| 290 | return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap); |
| 291 | } |
| 292 | EXPORT_SYMBOL_GPL(pci_find_next_ht_capability); |
| 293 | |
| 294 | /** |
| 295 | * pci_find_ht_capability - query a device's Hypertransport capabilities |
| 296 | * @dev: PCI device to query |
| 297 | * @ht_cap: Hypertransport capability code |
| 298 | * |
| 299 | * Tell if a device supports a given Hypertransport capability. |
| 300 | * Returns an address within the device's PCI configuration space |
| 301 | * or 0 in case the device does not support the request capability. |
| 302 | * The address points to the PCI capability, of type PCI_CAP_ID_HT, |
| 303 | * which has a Hypertransport capability matching @ht_cap. |
| 304 | */ |
| 305 | int pci_find_ht_capability(struct pci_dev *dev, int ht_cap) |
| 306 | { |
| 307 | int pos; |
| 308 | |
| 309 | pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type); |
| 310 | if (pos) |
| 311 | pos = __pci_find_next_ht_cap(dev, pos, ht_cap); |
| 312 | |
| 313 | return pos; |
| 314 | } |
| 315 | EXPORT_SYMBOL_GPL(pci_find_ht_capability); |
| 316 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 317 | /** |
| 318 | * pci_find_parent_resource - return resource region of parent bus of given region |
| 319 | * @dev: PCI device structure contains resources to be searched |
| 320 | * @res: child resource record for which parent is sought |
| 321 | * |
| 322 | * For given resource region of given device, return the resource |
| 323 | * region of parent bus the given region is contained in or where |
| 324 | * it should be allocated from. |
| 325 | */ |
| 326 | struct resource * |
| 327 | pci_find_parent_resource(const struct pci_dev *dev, struct resource *res) |
| 328 | { |
| 329 | const struct pci_bus *bus = dev->bus; |
| 330 | int i; |
| 331 | struct resource *best = NULL; |
| 332 | |
| 333 | for(i = 0; i < PCI_BUS_NUM_RESOURCES; i++) { |
| 334 | struct resource *r = bus->resource[i]; |
| 335 | if (!r) |
| 336 | continue; |
| 337 | if (res->start && !(res->start >= r->start && res->end <= r->end)) |
| 338 | continue; /* Not contained */ |
| 339 | if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM)) |
| 340 | continue; /* Wrong type */ |
| 341 | if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH)) |
| 342 | return r; /* Exact match */ |
| 343 | if ((res->flags & IORESOURCE_PREFETCH) && !(r->flags & IORESOURCE_PREFETCH)) |
| 344 | best = r; /* Approximating prefetchable by non-prefetchable */ |
| 345 | } |
| 346 | return best; |
| 347 | } |
| 348 | |
| 349 | /** |
John W. Linville | 064b53d | 2005-07-27 10:19:44 -0400 | [diff] [blame] | 350 | * pci_restore_bars - restore a devices BAR values (e.g. after wake-up) |
| 351 | * @dev: PCI device to have its BARs restored |
| 352 | * |
| 353 | * Restore the BAR values for a given device, so as to make it |
| 354 | * accessible by its driver. |
| 355 | */ |
Adrian Bunk | ad66859 | 2007-10-27 03:06:22 +0200 | [diff] [blame] | 356 | static void |
John W. Linville | 064b53d | 2005-07-27 10:19:44 -0400 | [diff] [blame] | 357 | pci_restore_bars(struct pci_dev *dev) |
| 358 | { |
| 359 | int i, numres; |
| 360 | |
| 361 | switch (dev->hdr_type) { |
| 362 | case PCI_HEADER_TYPE_NORMAL: |
| 363 | numres = 6; |
| 364 | break; |
| 365 | case PCI_HEADER_TYPE_BRIDGE: |
| 366 | numres = 2; |
| 367 | break; |
| 368 | case PCI_HEADER_TYPE_CARDBUS: |
| 369 | numres = 1; |
| 370 | break; |
| 371 | default: |
| 372 | /* Should never get here, but just in case... */ |
| 373 | return; |
| 374 | } |
| 375 | |
| 376 | for (i = 0; i < numres; i ++) |
| 377 | pci_update_resource(dev, &dev->resource[i], i); |
| 378 | } |
| 379 | |
Rafael J. Wysocki | 961d912 | 2008-07-07 03:32:02 +0200 | [diff] [blame] | 380 | static struct pci_platform_pm_ops *pci_platform_pm; |
| 381 | |
| 382 | int pci_set_platform_pm(struct pci_platform_pm_ops *ops) |
| 383 | { |
Rafael J. Wysocki | eb9d0fe | 2008-07-07 03:34:48 +0200 | [diff] [blame] | 384 | if (!ops->is_manageable || !ops->set_state || !ops->choose_state |
| 385 | || !ops->sleep_wake || !ops->can_wakeup) |
Rafael J. Wysocki | 961d912 | 2008-07-07 03:32:02 +0200 | [diff] [blame] | 386 | return -EINVAL; |
| 387 | pci_platform_pm = ops; |
| 388 | return 0; |
| 389 | } |
| 390 | |
| 391 | static inline bool platform_pci_power_manageable(struct pci_dev *dev) |
| 392 | { |
| 393 | return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false; |
| 394 | } |
| 395 | |
| 396 | static inline int platform_pci_set_power_state(struct pci_dev *dev, |
| 397 | pci_power_t t) |
| 398 | { |
| 399 | return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS; |
| 400 | } |
| 401 | |
| 402 | static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev) |
| 403 | { |
| 404 | return pci_platform_pm ? |
| 405 | pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR; |
| 406 | } |
Randy Dunlap | 8f7020d | 2005-10-23 11:57:38 -0700 | [diff] [blame] | 407 | |
Rafael J. Wysocki | eb9d0fe | 2008-07-07 03:34:48 +0200 | [diff] [blame] | 408 | static inline bool platform_pci_can_wakeup(struct pci_dev *dev) |
| 409 | { |
| 410 | return pci_platform_pm ? pci_platform_pm->can_wakeup(dev) : false; |
| 411 | } |
| 412 | |
| 413 | static inline int platform_pci_sleep_wake(struct pci_dev *dev, bool enable) |
| 414 | { |
| 415 | return pci_platform_pm ? |
| 416 | pci_platform_pm->sleep_wake(dev, enable) : -ENODEV; |
| 417 | } |
| 418 | |
John W. Linville | 064b53d | 2005-07-27 10:19:44 -0400 | [diff] [blame] | 419 | /** |
Rafael J. Wysocki | 44e4e66 | 2008-07-07 03:32:52 +0200 | [diff] [blame] | 420 | * pci_raw_set_power_state - Use PCI PM registers to set the power state of |
| 421 | * given PCI device |
| 422 | * @dev: PCI device to handle. |
Rafael J. Wysocki | 44e4e66 | 2008-07-07 03:32:52 +0200 | [diff] [blame] | 423 | * @state: PCI power state (D0, D1, D2, D3hot) to put the device into. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 424 | * |
Rafael J. Wysocki | 44e4e66 | 2008-07-07 03:32:52 +0200 | [diff] [blame] | 425 | * RETURN VALUE: |
| 426 | * -EINVAL if the requested state is invalid. |
| 427 | * -EIO if device does not support PCI PM or its PM capabilities register has a |
| 428 | * wrong version, or device doesn't support the requested state. |
| 429 | * 0 if device already is in the requested state. |
| 430 | * 0 if device's power state has been successfully changed. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 431 | */ |
Rafael J. Wysocki | 44e4e66 | 2008-07-07 03:32:52 +0200 | [diff] [blame] | 432 | static int |
Rafael J. Wysocki | 337001b | 2008-07-07 03:36:24 +0200 | [diff] [blame] | 433 | pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 434 | { |
Rafael J. Wysocki | 337001b | 2008-07-07 03:36:24 +0200 | [diff] [blame] | 435 | u16 pmcsr; |
Rafael J. Wysocki | 44e4e66 | 2008-07-07 03:32:52 +0200 | [diff] [blame] | 436 | bool need_restore = false; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 437 | |
Rafael J. Wysocki | 337001b | 2008-07-07 03:36:24 +0200 | [diff] [blame] | 438 | if (!dev->pm_cap) |
Andrew Lunn | cca03de | 2007-07-09 11:55:58 -0700 | [diff] [blame] | 439 | return -EIO; |
| 440 | |
Rafael J. Wysocki | 44e4e66 | 2008-07-07 03:32:52 +0200 | [diff] [blame] | 441 | if (state < PCI_D0 || state > PCI_D3hot) |
| 442 | return -EINVAL; |
| 443 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 444 | /* Validate current state: |
| 445 | * Can enter D0 from any state, but if we can only go deeper |
| 446 | * to sleep if we're already in a low power state |
| 447 | */ |
Rafael J. Wysocki | 44e4e66 | 2008-07-07 03:32:52 +0200 | [diff] [blame] | 448 | if (dev->current_state == state) { |
| 449 | /* we're already there */ |
| 450 | return 0; |
| 451 | } else if (state != PCI_D0 && dev->current_state <= PCI_D3cold |
| 452 | && dev->current_state > state) { |
Bjorn Helgaas | 80ccba1 | 2008-06-13 10:52:11 -0600 | [diff] [blame] | 453 | dev_err(&dev->dev, "invalid power transition " |
| 454 | "(from state %d to %d)\n", dev->current_state, state); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 455 | return -EINVAL; |
Rafael J. Wysocki | 44e4e66 | 2008-07-07 03:32:52 +0200 | [diff] [blame] | 456 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 457 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 458 | /* check if this device supports the desired state */ |
Rafael J. Wysocki | 337001b | 2008-07-07 03:36:24 +0200 | [diff] [blame] | 459 | if ((state == PCI_D1 && !dev->d1_support) |
| 460 | || (state == PCI_D2 && !dev->d2_support)) |
Daniel Ritz | 3fe9d19 | 2005-08-17 15:32:19 -0700 | [diff] [blame] | 461 | return -EIO; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 462 | |
Rafael J. Wysocki | 337001b | 2008-07-07 03:36:24 +0200 | [diff] [blame] | 463 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); |
John W. Linville | 064b53d | 2005-07-27 10:19:44 -0400 | [diff] [blame] | 464 | |
John W. Linville | 32a3658 | 2005-09-14 09:52:42 -0400 | [diff] [blame] | 465 | /* If we're (effectively) in D3, force entire word to 0. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 466 | * This doesn't affect PME_Status, disables PME_En, and |
| 467 | * sets PowerState to 0. |
| 468 | */ |
John W. Linville | 32a3658 | 2005-09-14 09:52:42 -0400 | [diff] [blame] | 469 | switch (dev->current_state) { |
John W. Linville | d3535fb | 2005-09-28 17:50:51 -0400 | [diff] [blame] | 470 | case PCI_D0: |
| 471 | case PCI_D1: |
| 472 | case PCI_D2: |
| 473 | pmcsr &= ~PCI_PM_CTRL_STATE_MASK; |
| 474 | pmcsr |= state; |
| 475 | break; |
John W. Linville | 32a3658 | 2005-09-14 09:52:42 -0400 | [diff] [blame] | 476 | case PCI_UNKNOWN: /* Boot-up */ |
| 477 | if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot |
| 478 | && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET)) |
Rafael J. Wysocki | 44e4e66 | 2008-07-07 03:32:52 +0200 | [diff] [blame] | 479 | need_restore = true; |
John W. Linville | 32a3658 | 2005-09-14 09:52:42 -0400 | [diff] [blame] | 480 | /* Fall-through: force to D0 */ |
John W. Linville | 32a3658 | 2005-09-14 09:52:42 -0400 | [diff] [blame] | 481 | default: |
John W. Linville | d3535fb | 2005-09-28 17:50:51 -0400 | [diff] [blame] | 482 | pmcsr = 0; |
John W. Linville | 32a3658 | 2005-09-14 09:52:42 -0400 | [diff] [blame] | 483 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 484 | } |
| 485 | |
| 486 | /* enter specified state */ |
Rafael J. Wysocki | 337001b | 2008-07-07 03:36:24 +0200 | [diff] [blame] | 487 | pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 488 | |
| 489 | /* Mandatory power management transition delays */ |
| 490 | /* see PCI PM 1.1 5.6.1 table 18 */ |
| 491 | if (state == PCI_D3hot || dev->current_state == PCI_D3hot) |
Kristen Carlson Accardi | ffadcc2 | 2006-07-12 08:59:00 -0700 | [diff] [blame] | 492 | msleep(pci_pm_d3_delay); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 493 | else if (state == PCI_D2 || dev->current_state == PCI_D2) |
| 494 | udelay(200); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 495 | |
David Shaohua Li | b913100 | 2005-03-19 00:16:18 -0500 | [diff] [blame] | 496 | dev->current_state = state; |
John W. Linville | 064b53d | 2005-07-27 10:19:44 -0400 | [diff] [blame] | 497 | |
| 498 | /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT |
| 499 | * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning |
| 500 | * from D3hot to D0 _may_ perform an internal reset, thereby |
| 501 | * going to "D0 Uninitialized" rather than "D0 Initialized". |
| 502 | * For example, at least some versions of the 3c905B and the |
| 503 | * 3c556B exhibit this behaviour. |
| 504 | * |
| 505 | * At least some laptop BIOSen (e.g. the Thinkpad T21) leave |
| 506 | * devices in a D3hot state at boot. Consequently, we need to |
| 507 | * restore at least the BARs so that the device will be |
| 508 | * accessible to its driver. |
| 509 | */ |
| 510 | if (need_restore) |
| 511 | pci_restore_bars(dev); |
| 512 | |
Shaohua Li | 7d715a6 | 2008-02-25 09:46:41 +0800 | [diff] [blame] | 513 | if (dev->bus->self) |
| 514 | pcie_aspm_pm_state_change(dev->bus->self); |
| 515 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 516 | return 0; |
| 517 | } |
| 518 | |
| 519 | /** |
Rafael J. Wysocki | 44e4e66 | 2008-07-07 03:32:52 +0200 | [diff] [blame] | 520 | * pci_update_current_state - Read PCI power state of given device from its |
| 521 | * PCI PM registers and cache it |
| 522 | * @dev: PCI device to handle. |
Rafael J. Wysocki | 44e4e66 | 2008-07-07 03:32:52 +0200 | [diff] [blame] | 523 | */ |
Rafael J. Wysocki | 337001b | 2008-07-07 03:36:24 +0200 | [diff] [blame] | 524 | static void pci_update_current_state(struct pci_dev *dev) |
Rafael J. Wysocki | 44e4e66 | 2008-07-07 03:32:52 +0200 | [diff] [blame] | 525 | { |
Rafael J. Wysocki | 337001b | 2008-07-07 03:36:24 +0200 | [diff] [blame] | 526 | if (dev->pm_cap) { |
Rafael J. Wysocki | 44e4e66 | 2008-07-07 03:32:52 +0200 | [diff] [blame] | 527 | u16 pmcsr; |
| 528 | |
Rafael J. Wysocki | 337001b | 2008-07-07 03:36:24 +0200 | [diff] [blame] | 529 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); |
Rafael J. Wysocki | 44e4e66 | 2008-07-07 03:32:52 +0200 | [diff] [blame] | 530 | dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK); |
| 531 | } |
| 532 | } |
| 533 | |
| 534 | /** |
| 535 | * pci_set_power_state - Set the power state of a PCI device |
| 536 | * @dev: PCI device to handle. |
| 537 | * @state: PCI power state (D0, D1, D2, D3hot) to put the device into. |
| 538 | * |
| 539 | * Transition a device to a new power state, using the platform formware and/or |
| 540 | * the device's PCI PM registers. |
| 541 | * |
| 542 | * RETURN VALUE: |
| 543 | * -EINVAL if the requested state is invalid. |
| 544 | * -EIO if device does not support PCI PM or its PM capabilities register has a |
| 545 | * wrong version, or device doesn't support the requested state. |
| 546 | * 0 if device already is in the requested state. |
| 547 | * 0 if device's power state has been successfully changed. |
| 548 | */ |
| 549 | int pci_set_power_state(struct pci_dev *dev, pci_power_t state) |
| 550 | { |
Rafael J. Wysocki | 337001b | 2008-07-07 03:36:24 +0200 | [diff] [blame] | 551 | int error; |
Rafael J. Wysocki | 44e4e66 | 2008-07-07 03:32:52 +0200 | [diff] [blame] | 552 | |
| 553 | /* bound the state we're entering */ |
| 554 | if (state > PCI_D3hot) |
| 555 | state = PCI_D3hot; |
| 556 | else if (state < PCI_D0) |
| 557 | state = PCI_D0; |
| 558 | else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev)) |
| 559 | /* |
| 560 | * If the device or the parent bridge do not support PCI PM, |
| 561 | * ignore the request if we're doing anything other than putting |
| 562 | * it into D0 (which would only happen on boot). |
| 563 | */ |
| 564 | return 0; |
| 565 | |
Rafael J. Wysocki | 44e4e66 | 2008-07-07 03:32:52 +0200 | [diff] [blame] | 566 | if (state == PCI_D0 && platform_pci_power_manageable(dev)) { |
| 567 | /* |
| 568 | * Allow the platform to change the state, for example via ACPI |
| 569 | * _PR0, _PS0 and some such, but do not trust it. |
| 570 | */ |
| 571 | int ret = platform_pci_set_power_state(dev, PCI_D0); |
| 572 | if (!ret) |
Rafael J. Wysocki | 337001b | 2008-07-07 03:36:24 +0200 | [diff] [blame] | 573 | pci_update_current_state(dev); |
Rafael J. Wysocki | 44e4e66 | 2008-07-07 03:32:52 +0200 | [diff] [blame] | 574 | } |
| 575 | |
Rafael J. Wysocki | 337001b | 2008-07-07 03:36:24 +0200 | [diff] [blame] | 576 | error = pci_raw_set_power_state(dev, state); |
Rafael J. Wysocki | 44e4e66 | 2008-07-07 03:32:52 +0200 | [diff] [blame] | 577 | |
| 578 | if (state > PCI_D0 && platform_pci_power_manageable(dev)) { |
| 579 | /* Allow the platform to finalize the transition */ |
| 580 | int ret = platform_pci_set_power_state(dev, state); |
| 581 | if (!ret) { |
Rafael J. Wysocki | 337001b | 2008-07-07 03:36:24 +0200 | [diff] [blame] | 582 | pci_update_current_state(dev); |
Rafael J. Wysocki | 44e4e66 | 2008-07-07 03:32:52 +0200 | [diff] [blame] | 583 | error = 0; |
| 584 | } |
| 585 | } |
| 586 | |
| 587 | return error; |
| 588 | } |
| 589 | |
| 590 | /** |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 591 | * pci_choose_state - Choose the power state of a PCI device |
| 592 | * @dev: PCI device to be suspended |
| 593 | * @state: target sleep state for the whole system. This is the value |
| 594 | * that is passed to suspend() function. |
| 595 | * |
| 596 | * Returns PCI power state suitable for given device and given system |
| 597 | * message. |
| 598 | */ |
| 599 | |
| 600 | pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state) |
| 601 | { |
Shaohua Li | ab826ca | 2007-07-20 10:03:22 +0800 | [diff] [blame] | 602 | pci_power_t ret; |
David Shaohua Li | 0f64474 | 2005-03-19 00:15:48 -0500 | [diff] [blame] | 603 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 604 | if (!pci_find_capability(dev, PCI_CAP_ID_PM)) |
| 605 | return PCI_D0; |
| 606 | |
Rafael J. Wysocki | 961d912 | 2008-07-07 03:32:02 +0200 | [diff] [blame] | 607 | ret = platform_pci_choose_state(dev); |
| 608 | if (ret != PCI_POWER_ERROR) |
| 609 | return ret; |
Pavel Machek | ca078ba | 2005-09-03 15:56:57 -0700 | [diff] [blame] | 610 | |
| 611 | switch (state.event) { |
| 612 | case PM_EVENT_ON: |
| 613 | return PCI_D0; |
| 614 | case PM_EVENT_FREEZE: |
David Brownell | b887d2e | 2006-08-14 23:11:05 -0700 | [diff] [blame] | 615 | case PM_EVENT_PRETHAW: |
| 616 | /* REVISIT both freeze and pre-thaw "should" use D0 */ |
Pavel Machek | ca078ba | 2005-09-03 15:56:57 -0700 | [diff] [blame] | 617 | case PM_EVENT_SUSPEND: |
Rafael J. Wysocki | 3a2d5b7 | 2008-02-23 19:13:25 +0100 | [diff] [blame] | 618 | case PM_EVENT_HIBERNATE: |
Pavel Machek | ca078ba | 2005-09-03 15:56:57 -0700 | [diff] [blame] | 619 | return PCI_D3hot; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 620 | default: |
Bjorn Helgaas | 80ccba1 | 2008-06-13 10:52:11 -0600 | [diff] [blame] | 621 | dev_info(&dev->dev, "unrecognized suspend event %d\n", |
| 622 | state.event); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 623 | BUG(); |
| 624 | } |
| 625 | return PCI_D0; |
| 626 | } |
| 627 | |
| 628 | EXPORT_SYMBOL(pci_choose_state); |
| 629 | |
Michael S. Tsirkin | b56a5a2 | 2006-08-21 16:22:22 +0300 | [diff] [blame] | 630 | static int pci_save_pcie_state(struct pci_dev *dev) |
| 631 | { |
| 632 | int pos, i = 0; |
| 633 | struct pci_cap_saved_state *save_state; |
| 634 | u16 *cap; |
Shaohua Li | 017fc48 | 2007-12-18 09:57:09 +0800 | [diff] [blame] | 635 | int found = 0; |
Michael S. Tsirkin | b56a5a2 | 2006-08-21 16:22:22 +0300 | [diff] [blame] | 636 | |
| 637 | pos = pci_find_capability(dev, PCI_CAP_ID_EXP); |
| 638 | if (pos <= 0) |
| 639 | return 0; |
| 640 | |
Eric W. Biederman | 9f35575 | 2007-03-08 13:06:13 -0700 | [diff] [blame] | 641 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP); |
| 642 | if (!save_state) |
| 643 | save_state = kzalloc(sizeof(*save_state) + sizeof(u16) * 4, GFP_KERNEL); |
Shaohua Li | 017fc48 | 2007-12-18 09:57:09 +0800 | [diff] [blame] | 644 | else |
| 645 | found = 1; |
Michael S. Tsirkin | b56a5a2 | 2006-08-21 16:22:22 +0300 | [diff] [blame] | 646 | if (!save_state) { |
Bjorn Helgaas | 80ccba1 | 2008-06-13 10:52:11 -0600 | [diff] [blame] | 647 | dev_err(&dev->dev, "out of memory in pci_save_pcie_state\n"); |
Michael S. Tsirkin | b56a5a2 | 2006-08-21 16:22:22 +0300 | [diff] [blame] | 648 | return -ENOMEM; |
| 649 | } |
| 650 | cap = (u16 *)&save_state->data[0]; |
| 651 | |
| 652 | pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &cap[i++]); |
| 653 | pci_read_config_word(dev, pos + PCI_EXP_LNKCTL, &cap[i++]); |
| 654 | pci_read_config_word(dev, pos + PCI_EXP_SLTCTL, &cap[i++]); |
| 655 | pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &cap[i++]); |
Shaohua Li | ec0a3a2 | 2007-12-18 09:56:56 +0800 | [diff] [blame] | 656 | save_state->cap_nr = PCI_CAP_ID_EXP; |
Shaohua Li | 017fc48 | 2007-12-18 09:57:09 +0800 | [diff] [blame] | 657 | if (!found) |
| 658 | pci_add_saved_cap(dev, save_state); |
Michael S. Tsirkin | b56a5a2 | 2006-08-21 16:22:22 +0300 | [diff] [blame] | 659 | return 0; |
| 660 | } |
| 661 | |
| 662 | static void pci_restore_pcie_state(struct pci_dev *dev) |
| 663 | { |
| 664 | int i = 0, pos; |
| 665 | struct pci_cap_saved_state *save_state; |
| 666 | u16 *cap; |
| 667 | |
| 668 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP); |
| 669 | pos = pci_find_capability(dev, PCI_CAP_ID_EXP); |
| 670 | if (!save_state || pos <= 0) |
| 671 | return; |
| 672 | cap = (u16 *)&save_state->data[0]; |
| 673 | |
| 674 | pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, cap[i++]); |
| 675 | pci_write_config_word(dev, pos + PCI_EXP_LNKCTL, cap[i++]); |
| 676 | pci_write_config_word(dev, pos + PCI_EXP_SLTCTL, cap[i++]); |
| 677 | pci_write_config_word(dev, pos + PCI_EXP_RTCTL, cap[i++]); |
Michael S. Tsirkin | b56a5a2 | 2006-08-21 16:22:22 +0300 | [diff] [blame] | 678 | } |
| 679 | |
Stephen Hemminger | cc692a5 | 2006-11-08 16:17:15 -0800 | [diff] [blame] | 680 | |
| 681 | static int pci_save_pcix_state(struct pci_dev *dev) |
| 682 | { |
| 683 | int pos, i = 0; |
| 684 | struct pci_cap_saved_state *save_state; |
| 685 | u16 *cap; |
Shaohua Li | 017fc48 | 2007-12-18 09:57:09 +0800 | [diff] [blame] | 686 | int found = 0; |
Stephen Hemminger | cc692a5 | 2006-11-08 16:17:15 -0800 | [diff] [blame] | 687 | |
| 688 | pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); |
| 689 | if (pos <= 0) |
| 690 | return 0; |
| 691 | |
Shaohua Li | f34303d | 2007-12-18 09:56:47 +0800 | [diff] [blame] | 692 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX); |
Eric W. Biederman | 9f35575 | 2007-03-08 13:06:13 -0700 | [diff] [blame] | 693 | if (!save_state) |
| 694 | save_state = kzalloc(sizeof(*save_state) + sizeof(u16), GFP_KERNEL); |
Shaohua Li | 017fc48 | 2007-12-18 09:57:09 +0800 | [diff] [blame] | 695 | else |
| 696 | found = 1; |
Stephen Hemminger | cc692a5 | 2006-11-08 16:17:15 -0800 | [diff] [blame] | 697 | if (!save_state) { |
Bjorn Helgaas | 80ccba1 | 2008-06-13 10:52:11 -0600 | [diff] [blame] | 698 | dev_err(&dev->dev, "out of memory in pci_save_pcie_state\n"); |
Stephen Hemminger | cc692a5 | 2006-11-08 16:17:15 -0800 | [diff] [blame] | 699 | return -ENOMEM; |
| 700 | } |
| 701 | cap = (u16 *)&save_state->data[0]; |
| 702 | |
| 703 | pci_read_config_word(dev, pos + PCI_X_CMD, &cap[i++]); |
Shaohua Li | ec0a3a2 | 2007-12-18 09:56:56 +0800 | [diff] [blame] | 704 | save_state->cap_nr = PCI_CAP_ID_PCIX; |
Shaohua Li | 017fc48 | 2007-12-18 09:57:09 +0800 | [diff] [blame] | 705 | if (!found) |
| 706 | pci_add_saved_cap(dev, save_state); |
Stephen Hemminger | cc692a5 | 2006-11-08 16:17:15 -0800 | [diff] [blame] | 707 | return 0; |
| 708 | } |
| 709 | |
| 710 | static void pci_restore_pcix_state(struct pci_dev *dev) |
| 711 | { |
| 712 | int i = 0, pos; |
| 713 | struct pci_cap_saved_state *save_state; |
| 714 | u16 *cap; |
| 715 | |
| 716 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX); |
| 717 | pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); |
| 718 | if (!save_state || pos <= 0) |
| 719 | return; |
| 720 | cap = (u16 *)&save_state->data[0]; |
| 721 | |
| 722 | pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]); |
Stephen Hemminger | cc692a5 | 2006-11-08 16:17:15 -0800 | [diff] [blame] | 723 | } |
| 724 | |
| 725 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 726 | /** |
| 727 | * pci_save_state - save the PCI configuration space of a device before suspending |
| 728 | * @dev: - PCI device that we're dealing with |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 729 | */ |
| 730 | int |
| 731 | pci_save_state(struct pci_dev *dev) |
| 732 | { |
| 733 | int i; |
| 734 | /* XXX: 100% dword access ok here? */ |
| 735 | for (i = 0; i < 16; i++) |
| 736 | pci_read_config_dword(dev, i * 4,&dev->saved_config_space[i]); |
Michael S. Tsirkin | b56a5a2 | 2006-08-21 16:22:22 +0300 | [diff] [blame] | 737 | if ((i = pci_save_pcie_state(dev)) != 0) |
| 738 | return i; |
Stephen Hemminger | cc692a5 | 2006-11-08 16:17:15 -0800 | [diff] [blame] | 739 | if ((i = pci_save_pcix_state(dev)) != 0) |
| 740 | return i; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 741 | return 0; |
| 742 | } |
| 743 | |
| 744 | /** |
| 745 | * pci_restore_state - Restore the saved state of a PCI device |
| 746 | * @dev: - PCI device that we're dealing with |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 747 | */ |
| 748 | int |
| 749 | pci_restore_state(struct pci_dev *dev) |
| 750 | { |
| 751 | int i; |
Al Viro | b4482a4 | 2007-10-14 19:35:40 +0100 | [diff] [blame] | 752 | u32 val; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 753 | |
Michael S. Tsirkin | b56a5a2 | 2006-08-21 16:22:22 +0300 | [diff] [blame] | 754 | /* PCI Express register must be restored first */ |
| 755 | pci_restore_pcie_state(dev); |
| 756 | |
Yu, Luming | 8b8c8d2 | 2006-04-25 00:00:34 -0700 | [diff] [blame] | 757 | /* |
| 758 | * The Base Address register should be programmed before the command |
| 759 | * register(s) |
| 760 | */ |
| 761 | for (i = 15; i >= 0; i--) { |
Dave Jones | 04d9c1a | 2006-04-18 21:06:51 -0700 | [diff] [blame] | 762 | pci_read_config_dword(dev, i * 4, &val); |
| 763 | if (val != dev->saved_config_space[i]) { |
Bjorn Helgaas | 80ccba1 | 2008-06-13 10:52:11 -0600 | [diff] [blame] | 764 | dev_printk(KERN_DEBUG, &dev->dev, "restoring config " |
| 765 | "space at offset %#x (was %#x, writing %#x)\n", |
| 766 | i, val, (int)dev->saved_config_space[i]); |
Dave Jones | 04d9c1a | 2006-04-18 21:06:51 -0700 | [diff] [blame] | 767 | pci_write_config_dword(dev,i * 4, |
| 768 | dev->saved_config_space[i]); |
| 769 | } |
| 770 | } |
Stephen Hemminger | cc692a5 | 2006-11-08 16:17:15 -0800 | [diff] [blame] | 771 | pci_restore_pcix_state(dev); |
Shaohua Li | 41017f0 | 2006-02-08 17:11:38 +0800 | [diff] [blame] | 772 | pci_restore_msi_state(dev); |
Michael Ellerman | 8fed4b6 | 2007-01-25 19:34:08 +1100 | [diff] [blame] | 773 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 774 | return 0; |
| 775 | } |
| 776 | |
Hidetoshi Seto | 38cc130 | 2006-12-18 10:30:00 +0900 | [diff] [blame] | 777 | static int do_pci_enable_device(struct pci_dev *dev, int bars) |
| 778 | { |
| 779 | int err; |
| 780 | |
| 781 | err = pci_set_power_state(dev, PCI_D0); |
| 782 | if (err < 0 && err != -EIO) |
| 783 | return err; |
| 784 | err = pcibios_enable_device(dev, bars); |
| 785 | if (err < 0) |
| 786 | return err; |
| 787 | pci_fixup_device(pci_fixup_enable, dev); |
| 788 | |
| 789 | return 0; |
| 790 | } |
| 791 | |
| 792 | /** |
Tejun Heo | 0b62e13 | 2007-07-27 14:43:35 +0900 | [diff] [blame] | 793 | * pci_reenable_device - Resume abandoned device |
Hidetoshi Seto | 38cc130 | 2006-12-18 10:30:00 +0900 | [diff] [blame] | 794 | * @dev: PCI device to be resumed |
| 795 | * |
| 796 | * Note this function is a backend of pci_default_resume and is not supposed |
| 797 | * to be called by normal code, write proper resume handler and use it instead. |
| 798 | */ |
Tejun Heo | 0b62e13 | 2007-07-27 14:43:35 +0900 | [diff] [blame] | 799 | int pci_reenable_device(struct pci_dev *dev) |
Hidetoshi Seto | 38cc130 | 2006-12-18 10:30:00 +0900 | [diff] [blame] | 800 | { |
| 801 | if (atomic_read(&dev->enable_cnt)) |
| 802 | return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1); |
| 803 | return 0; |
| 804 | } |
| 805 | |
Benjamin Herrenschmidt | b718989 | 2007-12-20 15:28:08 +1100 | [diff] [blame] | 806 | static int __pci_enable_device_flags(struct pci_dev *dev, |
| 807 | resource_size_t flags) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 808 | { |
| 809 | int err; |
Benjamin Herrenschmidt | b718989 | 2007-12-20 15:28:08 +1100 | [diff] [blame] | 810 | int i, bars = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 811 | |
Hidetoshi Seto | 9fb625c | 2006-12-18 10:28:43 +0900 | [diff] [blame] | 812 | if (atomic_add_return(1, &dev->enable_cnt) > 1) |
| 813 | return 0; /* already enabled */ |
| 814 | |
Benjamin Herrenschmidt | b718989 | 2007-12-20 15:28:08 +1100 | [diff] [blame] | 815 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) |
| 816 | if (dev->resource[i].flags & flags) |
| 817 | bars |= (1 << i); |
| 818 | |
Hidetoshi Seto | 38cc130 | 2006-12-18 10:30:00 +0900 | [diff] [blame] | 819 | err = do_pci_enable_device(dev, bars); |
Greg Kroah-Hartman | 95a6296 | 2005-07-28 11:37:33 -0700 | [diff] [blame] | 820 | if (err < 0) |
Hidetoshi Seto | 38cc130 | 2006-12-18 10:30:00 +0900 | [diff] [blame] | 821 | atomic_dec(&dev->enable_cnt); |
Hidetoshi Seto | 9fb625c | 2006-12-18 10:28:43 +0900 | [diff] [blame] | 822 | return err; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 823 | } |
| 824 | |
| 825 | /** |
Benjamin Herrenschmidt | b718989 | 2007-12-20 15:28:08 +1100 | [diff] [blame] | 826 | * pci_enable_device_io - Initialize a device for use with IO space |
| 827 | * @dev: PCI device to be initialized |
| 828 | * |
| 829 | * Initialize device before it's used by a driver. Ask low-level code |
| 830 | * to enable I/O resources. Wake up the device if it was suspended. |
| 831 | * Beware, this function can fail. |
| 832 | */ |
| 833 | int pci_enable_device_io(struct pci_dev *dev) |
| 834 | { |
| 835 | return __pci_enable_device_flags(dev, IORESOURCE_IO); |
| 836 | } |
| 837 | |
| 838 | /** |
| 839 | * pci_enable_device_mem - Initialize a device for use with Memory space |
| 840 | * @dev: PCI device to be initialized |
| 841 | * |
| 842 | * Initialize device before it's used by a driver. Ask low-level code |
| 843 | * to enable Memory resources. Wake up the device if it was suspended. |
| 844 | * Beware, this function can fail. |
| 845 | */ |
| 846 | int pci_enable_device_mem(struct pci_dev *dev) |
| 847 | { |
| 848 | return __pci_enable_device_flags(dev, IORESOURCE_MEM); |
| 849 | } |
| 850 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 851 | /** |
| 852 | * pci_enable_device - Initialize device before it's used by a driver. |
| 853 | * @dev: PCI device to be initialized |
| 854 | * |
| 855 | * Initialize device before it's used by a driver. Ask low-level code |
| 856 | * to enable I/O and memory. Wake up the device if it was suspended. |
| 857 | * Beware, this function can fail. |
Inaky Perez-Gonzalez | bae94d0 | 2006-11-22 12:40:31 -0800 | [diff] [blame] | 858 | * |
| 859 | * Note we don't actually enable the device many times if we call |
| 860 | * this function repeatedly (we just increment the count). |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 861 | */ |
Inaky Perez-Gonzalez | bae94d0 | 2006-11-22 12:40:31 -0800 | [diff] [blame] | 862 | int pci_enable_device(struct pci_dev *dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 863 | { |
Benjamin Herrenschmidt | b718989 | 2007-12-20 15:28:08 +1100 | [diff] [blame] | 864 | return __pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 865 | } |
| 866 | |
Tejun Heo | 9ac7849 | 2007-01-20 16:00:26 +0900 | [diff] [blame] | 867 | /* |
| 868 | * Managed PCI resources. This manages device on/off, intx/msi/msix |
| 869 | * on/off and BAR regions. pci_dev itself records msi/msix status, so |
| 870 | * there's no need to track it separately. pci_devres is initialized |
| 871 | * when a device is enabled using managed PCI device enable interface. |
| 872 | */ |
| 873 | struct pci_devres { |
Tejun Heo | 7f375f3 | 2007-02-25 04:36:01 -0800 | [diff] [blame] | 874 | unsigned int enabled:1; |
| 875 | unsigned int pinned:1; |
Tejun Heo | 9ac7849 | 2007-01-20 16:00:26 +0900 | [diff] [blame] | 876 | unsigned int orig_intx:1; |
| 877 | unsigned int restore_intx:1; |
| 878 | u32 region_mask; |
| 879 | }; |
| 880 | |
| 881 | static void pcim_release(struct device *gendev, void *res) |
| 882 | { |
| 883 | struct pci_dev *dev = container_of(gendev, struct pci_dev, dev); |
| 884 | struct pci_devres *this = res; |
| 885 | int i; |
| 886 | |
| 887 | if (dev->msi_enabled) |
| 888 | pci_disable_msi(dev); |
| 889 | if (dev->msix_enabled) |
| 890 | pci_disable_msix(dev); |
| 891 | |
| 892 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) |
| 893 | if (this->region_mask & (1 << i)) |
| 894 | pci_release_region(dev, i); |
| 895 | |
| 896 | if (this->restore_intx) |
| 897 | pci_intx(dev, this->orig_intx); |
| 898 | |
Tejun Heo | 7f375f3 | 2007-02-25 04:36:01 -0800 | [diff] [blame] | 899 | if (this->enabled && !this->pinned) |
Tejun Heo | 9ac7849 | 2007-01-20 16:00:26 +0900 | [diff] [blame] | 900 | pci_disable_device(dev); |
| 901 | } |
| 902 | |
| 903 | static struct pci_devres * get_pci_dr(struct pci_dev *pdev) |
| 904 | { |
| 905 | struct pci_devres *dr, *new_dr; |
| 906 | |
| 907 | dr = devres_find(&pdev->dev, pcim_release, NULL, NULL); |
| 908 | if (dr) |
| 909 | return dr; |
| 910 | |
| 911 | new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL); |
| 912 | if (!new_dr) |
| 913 | return NULL; |
| 914 | return devres_get(&pdev->dev, new_dr, NULL, NULL); |
| 915 | } |
| 916 | |
| 917 | static struct pci_devres * find_pci_dr(struct pci_dev *pdev) |
| 918 | { |
| 919 | if (pci_is_managed(pdev)) |
| 920 | return devres_find(&pdev->dev, pcim_release, NULL, NULL); |
| 921 | return NULL; |
| 922 | } |
| 923 | |
| 924 | /** |
| 925 | * pcim_enable_device - Managed pci_enable_device() |
| 926 | * @pdev: PCI device to be initialized |
| 927 | * |
| 928 | * Managed pci_enable_device(). |
| 929 | */ |
| 930 | int pcim_enable_device(struct pci_dev *pdev) |
| 931 | { |
| 932 | struct pci_devres *dr; |
| 933 | int rc; |
| 934 | |
| 935 | dr = get_pci_dr(pdev); |
| 936 | if (unlikely(!dr)) |
| 937 | return -ENOMEM; |
Tejun Heo | b95d58e | 2008-01-30 18:20:04 +0900 | [diff] [blame] | 938 | if (dr->enabled) |
| 939 | return 0; |
Tejun Heo | 9ac7849 | 2007-01-20 16:00:26 +0900 | [diff] [blame] | 940 | |
| 941 | rc = pci_enable_device(pdev); |
| 942 | if (!rc) { |
| 943 | pdev->is_managed = 1; |
Tejun Heo | 7f375f3 | 2007-02-25 04:36:01 -0800 | [diff] [blame] | 944 | dr->enabled = 1; |
Tejun Heo | 9ac7849 | 2007-01-20 16:00:26 +0900 | [diff] [blame] | 945 | } |
| 946 | return rc; |
| 947 | } |
| 948 | |
| 949 | /** |
| 950 | * pcim_pin_device - Pin managed PCI device |
| 951 | * @pdev: PCI device to pin |
| 952 | * |
| 953 | * Pin managed PCI device @pdev. Pinned device won't be disabled on |
| 954 | * driver detach. @pdev must have been enabled with |
| 955 | * pcim_enable_device(). |
| 956 | */ |
| 957 | void pcim_pin_device(struct pci_dev *pdev) |
| 958 | { |
| 959 | struct pci_devres *dr; |
| 960 | |
| 961 | dr = find_pci_dr(pdev); |
Tejun Heo | 7f375f3 | 2007-02-25 04:36:01 -0800 | [diff] [blame] | 962 | WARN_ON(!dr || !dr->enabled); |
Tejun Heo | 9ac7849 | 2007-01-20 16:00:26 +0900 | [diff] [blame] | 963 | if (dr) |
Tejun Heo | 7f375f3 | 2007-02-25 04:36:01 -0800 | [diff] [blame] | 964 | dr->pinned = 1; |
Tejun Heo | 9ac7849 | 2007-01-20 16:00:26 +0900 | [diff] [blame] | 965 | } |
| 966 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 967 | /** |
| 968 | * pcibios_disable_device - disable arch specific PCI resources for device dev |
| 969 | * @dev: the PCI device to disable |
| 970 | * |
| 971 | * Disables architecture specific PCI resources for the device. This |
| 972 | * is the default implementation. Architecture implementations can |
| 973 | * override this. |
| 974 | */ |
| 975 | void __attribute__ ((weak)) pcibios_disable_device (struct pci_dev *dev) {} |
| 976 | |
| 977 | /** |
| 978 | * pci_disable_device - Disable PCI device after use |
| 979 | * @dev: PCI device to be disabled |
| 980 | * |
| 981 | * Signal to the system that the PCI device is not in use by the system |
| 982 | * anymore. This only involves disabling PCI bus-mastering, if active. |
Inaky Perez-Gonzalez | bae94d0 | 2006-11-22 12:40:31 -0800 | [diff] [blame] | 983 | * |
| 984 | * Note we don't actually disable the device until all callers of |
| 985 | * pci_device_enable() have called pci_device_disable(). |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 986 | */ |
| 987 | void |
| 988 | pci_disable_device(struct pci_dev *dev) |
| 989 | { |
Tejun Heo | 9ac7849 | 2007-01-20 16:00:26 +0900 | [diff] [blame] | 990 | struct pci_devres *dr; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 991 | u16 pci_command; |
Shaohua Li | 99dc804 | 2006-05-26 10:58:27 +0800 | [diff] [blame] | 992 | |
Tejun Heo | 9ac7849 | 2007-01-20 16:00:26 +0900 | [diff] [blame] | 993 | dr = find_pci_dr(dev); |
| 994 | if (dr) |
Tejun Heo | 7f375f3 | 2007-02-25 04:36:01 -0800 | [diff] [blame] | 995 | dr->enabled = 0; |
Tejun Heo | 9ac7849 | 2007-01-20 16:00:26 +0900 | [diff] [blame] | 996 | |
Inaky Perez-Gonzalez | bae94d0 | 2006-11-22 12:40:31 -0800 | [diff] [blame] | 997 | if (atomic_sub_return(1, &dev->enable_cnt) != 0) |
| 998 | return; |
| 999 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1000 | pci_read_config_word(dev, PCI_COMMAND, &pci_command); |
| 1001 | if (pci_command & PCI_COMMAND_MASTER) { |
| 1002 | pci_command &= ~PCI_COMMAND_MASTER; |
| 1003 | pci_write_config_word(dev, PCI_COMMAND, pci_command); |
| 1004 | } |
Kenji Kaneshige | ceb4374 | 2005-04-08 14:53:31 +0900 | [diff] [blame] | 1005 | dev->is_busmaster = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1006 | |
| 1007 | pcibios_disable_device(dev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1008 | } |
| 1009 | |
| 1010 | /** |
Brian King | f7bdd12 | 2007-04-06 16:39:36 -0500 | [diff] [blame] | 1011 | * pcibios_set_pcie_reset_state - set reset state for device dev |
| 1012 | * @dev: the PCI-E device reset |
| 1013 | * @state: Reset state to enter into |
| 1014 | * |
| 1015 | * |
| 1016 | * Sets the PCI-E reset state for the device. This is the default |
| 1017 | * implementation. Architecture implementations can override this. |
| 1018 | */ |
| 1019 | int __attribute__ ((weak)) pcibios_set_pcie_reset_state(struct pci_dev *dev, |
| 1020 | enum pcie_reset_state state) |
| 1021 | { |
| 1022 | return -EINVAL; |
| 1023 | } |
| 1024 | |
| 1025 | /** |
| 1026 | * pci_set_pcie_reset_state - set reset state for device dev |
| 1027 | * @dev: the PCI-E device reset |
| 1028 | * @state: Reset state to enter into |
| 1029 | * |
| 1030 | * |
| 1031 | * Sets the PCI reset state for the device. |
| 1032 | */ |
| 1033 | int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state) |
| 1034 | { |
| 1035 | return pcibios_set_pcie_reset_state(dev, state); |
| 1036 | } |
| 1037 | |
| 1038 | /** |
Rafael J. Wysocki | eb9d0fe | 2008-07-07 03:34:48 +0200 | [diff] [blame] | 1039 | * pci_pme_capable - check the capability of PCI device to generate PME# |
| 1040 | * @dev: PCI device to handle. |
Rafael J. Wysocki | eb9d0fe | 2008-07-07 03:34:48 +0200 | [diff] [blame] | 1041 | * @state: PCI state from which device will issue PME#. |
| 1042 | */ |
Rafael J. Wysocki | 337001b | 2008-07-07 03:36:24 +0200 | [diff] [blame] | 1043 | static bool pci_pme_capable(struct pci_dev *dev, pci_power_t state) |
Rafael J. Wysocki | eb9d0fe | 2008-07-07 03:34:48 +0200 | [diff] [blame] | 1044 | { |
Rafael J. Wysocki | 337001b | 2008-07-07 03:36:24 +0200 | [diff] [blame] | 1045 | if (!dev->pm_cap) |
Rafael J. Wysocki | eb9d0fe | 2008-07-07 03:34:48 +0200 | [diff] [blame] | 1046 | return false; |
| 1047 | |
Rafael J. Wysocki | 337001b | 2008-07-07 03:36:24 +0200 | [diff] [blame] | 1048 | return !!(dev->pme_support & (1 << state)); |
Rafael J. Wysocki | eb9d0fe | 2008-07-07 03:34:48 +0200 | [diff] [blame] | 1049 | } |
| 1050 | |
| 1051 | /** |
| 1052 | * pci_pme_active - enable or disable PCI device's PME# function |
| 1053 | * @dev: PCI device to handle. |
Rafael J. Wysocki | eb9d0fe | 2008-07-07 03:34:48 +0200 | [diff] [blame] | 1054 | * @enable: 'true' to enable PME# generation; 'false' to disable it. |
| 1055 | * |
| 1056 | * The caller must verify that the device is capable of generating PME# before |
| 1057 | * calling this function with @enable equal to 'true'. |
| 1058 | */ |
Rafael J. Wysocki | 337001b | 2008-07-07 03:36:24 +0200 | [diff] [blame] | 1059 | static void pci_pme_active(struct pci_dev *dev, bool enable) |
Rafael J. Wysocki | eb9d0fe | 2008-07-07 03:34:48 +0200 | [diff] [blame] | 1060 | { |
| 1061 | u16 pmcsr; |
| 1062 | |
Rafael J. Wysocki | 337001b | 2008-07-07 03:36:24 +0200 | [diff] [blame] | 1063 | if (!dev->pm_cap) |
Rafael J. Wysocki | eb9d0fe | 2008-07-07 03:34:48 +0200 | [diff] [blame] | 1064 | return; |
| 1065 | |
Rafael J. Wysocki | 337001b | 2008-07-07 03:36:24 +0200 | [diff] [blame] | 1066 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); |
Rafael J. Wysocki | eb9d0fe | 2008-07-07 03:34:48 +0200 | [diff] [blame] | 1067 | /* Clear PME_Status by writing 1 to it and enable PME# */ |
| 1068 | pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE; |
| 1069 | if (!enable) |
| 1070 | pmcsr &= ~PCI_PM_CTRL_PME_ENABLE; |
| 1071 | |
Rafael J. Wysocki | 337001b | 2008-07-07 03:36:24 +0200 | [diff] [blame] | 1072 | pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr); |
Rafael J. Wysocki | eb9d0fe | 2008-07-07 03:34:48 +0200 | [diff] [blame] | 1073 | |
| 1074 | dev_printk(KERN_INFO, &dev->dev, "PME# %s\n", |
| 1075 | enable ? "enabled" : "disabled"); |
| 1076 | } |
| 1077 | |
| 1078 | /** |
David Brownell | 075c177 | 2007-04-26 00:12:06 -0700 | [diff] [blame] | 1079 | * pci_enable_wake - enable PCI device as wakeup event source |
| 1080 | * @dev: PCI device affected |
| 1081 | * @state: PCI state from which device will issue wakeup events |
| 1082 | * @enable: True to enable event generation; false to disable |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1083 | * |
David Brownell | 075c177 | 2007-04-26 00:12:06 -0700 | [diff] [blame] | 1084 | * This enables the device as a wakeup event source, or disables it. |
| 1085 | * When such events involves platform-specific hooks, those hooks are |
| 1086 | * called automatically by this routine. |
| 1087 | * |
| 1088 | * Devices with legacy power management (no standard PCI PM capabilities) |
Rafael J. Wysocki | eb9d0fe | 2008-07-07 03:34:48 +0200 | [diff] [blame] | 1089 | * always require such platform hooks. |
David Brownell | 075c177 | 2007-04-26 00:12:06 -0700 | [diff] [blame] | 1090 | * |
Rafael J. Wysocki | eb9d0fe | 2008-07-07 03:34:48 +0200 | [diff] [blame] | 1091 | * RETURN VALUE: |
| 1092 | * 0 is returned on success |
| 1093 | * -EINVAL is returned if device is not supposed to wake up the system |
| 1094 | * Error code depending on the platform is returned if both the platform and |
| 1095 | * the native mechanism fail to enable the generation of wake-up events |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1096 | */ |
| 1097 | int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable) |
| 1098 | { |
Rafael J. Wysocki | eb9d0fe | 2008-07-07 03:34:48 +0200 | [diff] [blame] | 1099 | int error = 0; |
| 1100 | bool pme_done = false; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1101 | |
Rafael J. Wysocki | eb9d0fe | 2008-07-07 03:34:48 +0200 | [diff] [blame] | 1102 | if (!device_may_wakeup(&dev->dev)) |
| 1103 | return -EINVAL; |
| 1104 | |
| 1105 | /* |
| 1106 | * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don |
| 1107 | * Anderson we should be doing PME# wake enable followed by ACPI wake |
| 1108 | * enable. To disable wake-up we call the platform first, for symmetry. |
David Brownell | 075c177 | 2007-04-26 00:12:06 -0700 | [diff] [blame] | 1109 | */ |
| 1110 | |
Rafael J. Wysocki | eb9d0fe | 2008-07-07 03:34:48 +0200 | [diff] [blame] | 1111 | if (!enable && platform_pci_can_wakeup(dev)) |
| 1112 | error = platform_pci_sleep_wake(dev, false); |
| 1113 | |
Rafael J. Wysocki | 337001b | 2008-07-07 03:36:24 +0200 | [diff] [blame] | 1114 | if (!enable || pci_pme_capable(dev, state)) { |
| 1115 | pci_pme_active(dev, enable); |
Rafael J. Wysocki | eb9d0fe | 2008-07-07 03:34:48 +0200 | [diff] [blame] | 1116 | pme_done = true; |
| 1117 | } |
| 1118 | |
| 1119 | if (enable && platform_pci_can_wakeup(dev)) |
| 1120 | error = platform_pci_sleep_wake(dev, true); |
| 1121 | |
| 1122 | return pme_done ? 0 : error; |
| 1123 | } |
| 1124 | |
| 1125 | /** |
Randy Dunlap | 443bd1c | 2008-07-21 09:27:18 -0700 | [diff] [blame] | 1126 | * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state |
Rafael J. Wysocki | 404cc2d | 2008-07-07 03:35:26 +0200 | [diff] [blame] | 1127 | * @dev: Device to handle. |
| 1128 | * |
| 1129 | * Choose the power state appropriate for the device depending on whether |
| 1130 | * it can wake up the system and/or is power manageable by the platform |
| 1131 | * (PCI_D3hot is the default) and put the device into that state. |
| 1132 | */ |
| 1133 | int pci_prepare_to_sleep(struct pci_dev *dev) |
| 1134 | { |
| 1135 | pci_power_t target_state = PCI_D3hot; |
Rafael J. Wysocki | 404cc2d | 2008-07-07 03:35:26 +0200 | [diff] [blame] | 1136 | int error; |
| 1137 | |
| 1138 | if (platform_pci_power_manageable(dev)) { |
| 1139 | /* |
| 1140 | * Call the platform to choose the target state of the device |
| 1141 | * and enable wake-up from this state if supported. |
| 1142 | */ |
| 1143 | pci_power_t state = platform_pci_choose_state(dev); |
| 1144 | |
| 1145 | switch (state) { |
| 1146 | case PCI_POWER_ERROR: |
| 1147 | case PCI_UNKNOWN: |
| 1148 | break; |
| 1149 | case PCI_D1: |
| 1150 | case PCI_D2: |
| 1151 | if (pci_no_d1d2(dev)) |
| 1152 | break; |
| 1153 | default: |
| 1154 | target_state = state; |
Rafael J. Wysocki | 404cc2d | 2008-07-07 03:35:26 +0200 | [diff] [blame] | 1155 | } |
| 1156 | } else if (device_may_wakeup(&dev->dev)) { |
| 1157 | /* |
| 1158 | * Find the deepest state from which the device can generate |
| 1159 | * wake-up events, make it the target state and enable device |
| 1160 | * to generate PME#. |
| 1161 | */ |
Rafael J. Wysocki | 337001b | 2008-07-07 03:36:24 +0200 | [diff] [blame] | 1162 | if (!dev->pm_cap) |
Rafael J. Wysocki | 404cc2d | 2008-07-07 03:35:26 +0200 | [diff] [blame] | 1163 | return -EIO; |
| 1164 | |
Rafael J. Wysocki | 337001b | 2008-07-07 03:36:24 +0200 | [diff] [blame] | 1165 | if (dev->pme_support) { |
| 1166 | while (target_state |
| 1167 | && !(dev->pme_support & (1 << target_state))) |
| 1168 | target_state--; |
Rafael J. Wysocki | 404cc2d | 2008-07-07 03:35:26 +0200 | [diff] [blame] | 1169 | } |
| 1170 | } |
| 1171 | |
Rafael J. Wysocki | c157dfa | 2008-07-13 22:45:06 +0200 | [diff] [blame] | 1172 | pci_enable_wake(dev, target_state, true); |
| 1173 | |
Rafael J. Wysocki | 404cc2d | 2008-07-07 03:35:26 +0200 | [diff] [blame] | 1174 | error = pci_set_power_state(dev, target_state); |
| 1175 | |
| 1176 | if (error) |
| 1177 | pci_enable_wake(dev, target_state, false); |
| 1178 | |
| 1179 | return error; |
| 1180 | } |
| 1181 | |
| 1182 | /** |
Randy Dunlap | 443bd1c | 2008-07-21 09:27:18 -0700 | [diff] [blame] | 1183 | * pci_back_from_sleep - turn PCI device on during system-wide transition into working state |
Rafael J. Wysocki | 404cc2d | 2008-07-07 03:35:26 +0200 | [diff] [blame] | 1184 | * @dev: Device to handle. |
| 1185 | * |
| 1186 | * Disable device's sytem wake-up capability and put it into D0. |
| 1187 | */ |
| 1188 | int pci_back_from_sleep(struct pci_dev *dev) |
| 1189 | { |
| 1190 | pci_enable_wake(dev, PCI_D0, false); |
| 1191 | return pci_set_power_state(dev, PCI_D0); |
| 1192 | } |
| 1193 | |
| 1194 | /** |
Rafael J. Wysocki | eb9d0fe | 2008-07-07 03:34:48 +0200 | [diff] [blame] | 1195 | * pci_pm_init - Initialize PM functions of given PCI device |
| 1196 | * @dev: PCI device to handle. |
| 1197 | */ |
| 1198 | void pci_pm_init(struct pci_dev *dev) |
| 1199 | { |
| 1200 | int pm; |
| 1201 | u16 pmc; |
David Brownell | 075c177 | 2007-04-26 00:12:06 -0700 | [diff] [blame] | 1202 | |
Rafael J. Wysocki | 337001b | 2008-07-07 03:36:24 +0200 | [diff] [blame] | 1203 | dev->pm_cap = 0; |
| 1204 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1205 | /* find PCI PM capability in list */ |
| 1206 | pm = pci_find_capability(dev, PCI_CAP_ID_PM); |
David Brownell | 075c177 | 2007-04-26 00:12:06 -0700 | [diff] [blame] | 1207 | if (!pm) |
Rafael J. Wysocki | eb9d0fe | 2008-07-07 03:34:48 +0200 | [diff] [blame] | 1208 | return; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1209 | /* Check device's ability to generate PME# */ |
Rafael J. Wysocki | eb9d0fe | 2008-07-07 03:34:48 +0200 | [diff] [blame] | 1210 | pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1211 | |
Rafael J. Wysocki | eb9d0fe | 2008-07-07 03:34:48 +0200 | [diff] [blame] | 1212 | if ((pmc & PCI_PM_CAP_VER_MASK) > 3) { |
| 1213 | dev_err(&dev->dev, "unsupported PM cap regs version (%u)\n", |
| 1214 | pmc & PCI_PM_CAP_VER_MASK); |
| 1215 | return; |
David Brownell | 075c177 | 2007-04-26 00:12:06 -0700 | [diff] [blame] | 1216 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1217 | |
Rafael J. Wysocki | 337001b | 2008-07-07 03:36:24 +0200 | [diff] [blame] | 1218 | dev->pm_cap = pm; |
| 1219 | |
| 1220 | dev->d1_support = false; |
| 1221 | dev->d2_support = false; |
| 1222 | if (!pci_no_d1d2(dev)) { |
| 1223 | if (pmc & PCI_PM_CAP_D1) { |
| 1224 | dev_printk(KERN_DEBUG, &dev->dev, "supports D1\n"); |
| 1225 | dev->d1_support = true; |
| 1226 | } |
| 1227 | if (pmc & PCI_PM_CAP_D2) { |
| 1228 | dev_printk(KERN_DEBUG, &dev->dev, "supports D2\n"); |
| 1229 | dev->d2_support = true; |
| 1230 | } |
| 1231 | } |
| 1232 | |
| 1233 | pmc &= PCI_PM_CAP_PME_MASK; |
| 1234 | if (pmc) { |
Rafael J. Wysocki | eb9d0fe | 2008-07-07 03:34:48 +0200 | [diff] [blame] | 1235 | dev_printk(KERN_INFO, &dev->dev, |
| 1236 | "PME# supported from%s%s%s%s%s\n", |
| 1237 | (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "", |
| 1238 | (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "", |
| 1239 | (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "", |
| 1240 | (pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "", |
| 1241 | (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : ""); |
Rafael J. Wysocki | 337001b | 2008-07-07 03:36:24 +0200 | [diff] [blame] | 1242 | dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT; |
Rafael J. Wysocki | eb9d0fe | 2008-07-07 03:34:48 +0200 | [diff] [blame] | 1243 | /* |
| 1244 | * Make device's PM flags reflect the wake-up capability, but |
| 1245 | * let the user space enable it to wake up the system as needed. |
| 1246 | */ |
| 1247 | device_set_wakeup_capable(&dev->dev, true); |
| 1248 | device_set_wakeup_enable(&dev->dev, false); |
| 1249 | /* Disable the PME# generation functionality */ |
Rafael J. Wysocki | 337001b | 2008-07-07 03:36:24 +0200 | [diff] [blame] | 1250 | pci_pme_active(dev, false); |
| 1251 | } else { |
| 1252 | dev->pme_support = 0; |
Rafael J. Wysocki | eb9d0fe | 2008-07-07 03:34:48 +0200 | [diff] [blame] | 1253 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1254 | } |
| 1255 | |
| 1256 | int |
| 1257 | pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge) |
| 1258 | { |
| 1259 | u8 pin; |
| 1260 | |
Kristen Accardi | 514d207 | 2005-11-02 16:24:39 -0800 | [diff] [blame] | 1261 | pin = dev->pin; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1262 | if (!pin) |
| 1263 | return -1; |
| 1264 | pin--; |
| 1265 | while (dev->bus->self) { |
| 1266 | pin = (pin + PCI_SLOT(dev->devfn)) % 4; |
| 1267 | dev = dev->bus->self; |
| 1268 | } |
| 1269 | *bridge = dev; |
| 1270 | return pin; |
| 1271 | } |
| 1272 | |
| 1273 | /** |
| 1274 | * pci_release_region - Release a PCI bar |
| 1275 | * @pdev: PCI device whose resources were previously reserved by pci_request_region |
| 1276 | * @bar: BAR to release |
| 1277 | * |
| 1278 | * Releases the PCI I/O and memory resources previously reserved by a |
| 1279 | * successful call to pci_request_region. Call this function only |
| 1280 | * after all use of the PCI regions has ceased. |
| 1281 | */ |
| 1282 | void pci_release_region(struct pci_dev *pdev, int bar) |
| 1283 | { |
Tejun Heo | 9ac7849 | 2007-01-20 16:00:26 +0900 | [diff] [blame] | 1284 | struct pci_devres *dr; |
| 1285 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1286 | if (pci_resource_len(pdev, bar) == 0) |
| 1287 | return; |
| 1288 | if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) |
| 1289 | release_region(pci_resource_start(pdev, bar), |
| 1290 | pci_resource_len(pdev, bar)); |
| 1291 | else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) |
| 1292 | release_mem_region(pci_resource_start(pdev, bar), |
| 1293 | pci_resource_len(pdev, bar)); |
Tejun Heo | 9ac7849 | 2007-01-20 16:00:26 +0900 | [diff] [blame] | 1294 | |
| 1295 | dr = find_pci_dr(pdev); |
| 1296 | if (dr) |
| 1297 | dr->region_mask &= ~(1 << bar); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1298 | } |
| 1299 | |
| 1300 | /** |
| 1301 | * pci_request_region - Reserved PCI I/O and memory resource |
| 1302 | * @pdev: PCI device whose resources are to be reserved |
| 1303 | * @bar: BAR to be reserved |
| 1304 | * @res_name: Name to be associated with resource. |
| 1305 | * |
| 1306 | * Mark the PCI region associated with PCI device @pdev BR @bar as |
| 1307 | * being reserved by owner @res_name. Do not access any |
| 1308 | * address inside the PCI regions unless this call returns |
| 1309 | * successfully. |
| 1310 | * |
| 1311 | * Returns 0 on success, or %EBUSY on error. A warning |
| 1312 | * message is also printed on failure. |
| 1313 | */ |
Jeff Garzik | 3c990e9 | 2006-03-04 21:52:42 -0500 | [diff] [blame] | 1314 | int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1315 | { |
Tejun Heo | 9ac7849 | 2007-01-20 16:00:26 +0900 | [diff] [blame] | 1316 | struct pci_devres *dr; |
| 1317 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1318 | if (pci_resource_len(pdev, bar) == 0) |
| 1319 | return 0; |
| 1320 | |
| 1321 | if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) { |
| 1322 | if (!request_region(pci_resource_start(pdev, bar), |
| 1323 | pci_resource_len(pdev, bar), res_name)) |
| 1324 | goto err_out; |
| 1325 | } |
| 1326 | else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) { |
| 1327 | if (!request_mem_region(pci_resource_start(pdev, bar), |
| 1328 | pci_resource_len(pdev, bar), res_name)) |
| 1329 | goto err_out; |
| 1330 | } |
Tejun Heo | 9ac7849 | 2007-01-20 16:00:26 +0900 | [diff] [blame] | 1331 | |
| 1332 | dr = find_pci_dr(pdev); |
| 1333 | if (dr) |
| 1334 | dr->region_mask |= 1 << bar; |
| 1335 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1336 | return 0; |
| 1337 | |
| 1338 | err_out: |
Bjorn Helgaas | 80ccba1 | 2008-06-13 10:52:11 -0600 | [diff] [blame] | 1339 | dev_warn(&pdev->dev, "BAR %d: can't reserve %s region [%#llx-%#llx]\n", |
Jesse Barnes | e4ec7a0 | 2008-06-25 16:12:25 -0700 | [diff] [blame] | 1340 | bar, |
| 1341 | pci_resource_flags(pdev, bar) & IORESOURCE_IO ? "I/O" : "mem", |
| 1342 | (unsigned long long)pci_resource_start(pdev, bar), |
| 1343 | (unsigned long long)pci_resource_end(pdev, bar)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1344 | return -EBUSY; |
| 1345 | } |
| 1346 | |
Hidetoshi Seto | c87deff | 2006-12-18 10:31:06 +0900 | [diff] [blame] | 1347 | /** |
| 1348 | * pci_release_selected_regions - Release selected PCI I/O and memory resources |
| 1349 | * @pdev: PCI device whose resources were previously reserved |
| 1350 | * @bars: Bitmask of BARs to be released |
| 1351 | * |
| 1352 | * Release selected PCI I/O and memory resources previously reserved. |
| 1353 | * Call this function only after all use of the PCI regions has ceased. |
| 1354 | */ |
| 1355 | void pci_release_selected_regions(struct pci_dev *pdev, int bars) |
| 1356 | { |
| 1357 | int i; |
| 1358 | |
| 1359 | for (i = 0; i < 6; i++) |
| 1360 | if (bars & (1 << i)) |
| 1361 | pci_release_region(pdev, i); |
| 1362 | } |
| 1363 | |
| 1364 | /** |
| 1365 | * pci_request_selected_regions - Reserve selected PCI I/O and memory resources |
| 1366 | * @pdev: PCI device whose resources are to be reserved |
| 1367 | * @bars: Bitmask of BARs to be requested |
| 1368 | * @res_name: Name to be associated with resource |
| 1369 | */ |
| 1370 | int pci_request_selected_regions(struct pci_dev *pdev, int bars, |
| 1371 | const char *res_name) |
| 1372 | { |
| 1373 | int i; |
| 1374 | |
| 1375 | for (i = 0; i < 6; i++) |
| 1376 | if (bars & (1 << i)) |
| 1377 | if(pci_request_region(pdev, i, res_name)) |
| 1378 | goto err_out; |
| 1379 | return 0; |
| 1380 | |
| 1381 | err_out: |
| 1382 | while(--i >= 0) |
| 1383 | if (bars & (1 << i)) |
| 1384 | pci_release_region(pdev, i); |
| 1385 | |
| 1386 | return -EBUSY; |
| 1387 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1388 | |
| 1389 | /** |
| 1390 | * pci_release_regions - Release reserved PCI I/O and memory resources |
| 1391 | * @pdev: PCI device whose resources were previously reserved by pci_request_regions |
| 1392 | * |
| 1393 | * Releases all PCI I/O and memory resources previously reserved by a |
| 1394 | * successful call to pci_request_regions. Call this function only |
| 1395 | * after all use of the PCI regions has ceased. |
| 1396 | */ |
| 1397 | |
| 1398 | void pci_release_regions(struct pci_dev *pdev) |
| 1399 | { |
Hidetoshi Seto | c87deff | 2006-12-18 10:31:06 +0900 | [diff] [blame] | 1400 | pci_release_selected_regions(pdev, (1 << 6) - 1); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1401 | } |
| 1402 | |
| 1403 | /** |
| 1404 | * pci_request_regions - Reserved PCI I/O and memory resources |
| 1405 | * @pdev: PCI device whose resources are to be reserved |
| 1406 | * @res_name: Name to be associated with resource. |
| 1407 | * |
| 1408 | * Mark all PCI regions associated with PCI device @pdev as |
| 1409 | * being reserved by owner @res_name. Do not access any |
| 1410 | * address inside the PCI regions unless this call returns |
| 1411 | * successfully. |
| 1412 | * |
| 1413 | * Returns 0 on success, or %EBUSY on error. A warning |
| 1414 | * message is also printed on failure. |
| 1415 | */ |
Jeff Garzik | 3c990e9 | 2006-03-04 21:52:42 -0500 | [diff] [blame] | 1416 | int pci_request_regions(struct pci_dev *pdev, const char *res_name) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1417 | { |
Hidetoshi Seto | c87deff | 2006-12-18 10:31:06 +0900 | [diff] [blame] | 1418 | return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1419 | } |
| 1420 | |
| 1421 | /** |
| 1422 | * pci_set_master - enables bus-mastering for device dev |
| 1423 | * @dev: the PCI device to enable |
| 1424 | * |
| 1425 | * Enables bus-mastering on the device and calls pcibios_set_master() |
| 1426 | * to do the needed arch specific settings. |
| 1427 | */ |
| 1428 | void |
| 1429 | pci_set_master(struct pci_dev *dev) |
| 1430 | { |
| 1431 | u16 cmd; |
| 1432 | |
| 1433 | pci_read_config_word(dev, PCI_COMMAND, &cmd); |
| 1434 | if (! (cmd & PCI_COMMAND_MASTER)) { |
Bjorn Helgaas | 80ccba1 | 2008-06-13 10:52:11 -0600 | [diff] [blame] | 1435 | dev_dbg(&dev->dev, "enabling bus mastering\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1436 | cmd |= PCI_COMMAND_MASTER; |
| 1437 | pci_write_config_word(dev, PCI_COMMAND, cmd); |
| 1438 | } |
| 1439 | dev->is_busmaster = 1; |
| 1440 | pcibios_set_master(dev); |
| 1441 | } |
| 1442 | |
Matthew Wilcox | edb2d97 | 2006-10-10 08:01:21 -0600 | [diff] [blame] | 1443 | #ifdef PCI_DISABLE_MWI |
| 1444 | int pci_set_mwi(struct pci_dev *dev) |
| 1445 | { |
| 1446 | return 0; |
| 1447 | } |
| 1448 | |
Randy Dunlap | 694625c | 2007-07-09 11:55:54 -0700 | [diff] [blame] | 1449 | int pci_try_set_mwi(struct pci_dev *dev) |
| 1450 | { |
| 1451 | return 0; |
| 1452 | } |
| 1453 | |
Matthew Wilcox | edb2d97 | 2006-10-10 08:01:21 -0600 | [diff] [blame] | 1454 | void pci_clear_mwi(struct pci_dev *dev) |
| 1455 | { |
| 1456 | } |
| 1457 | |
| 1458 | #else |
Matthew Wilcox | ebf5a24 | 2006-10-10 08:01:20 -0600 | [diff] [blame] | 1459 | |
| 1460 | #ifndef PCI_CACHE_LINE_BYTES |
| 1461 | #define PCI_CACHE_LINE_BYTES L1_CACHE_BYTES |
| 1462 | #endif |
| 1463 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1464 | /* This can be overridden by arch code. */ |
Matthew Wilcox | ebf5a24 | 2006-10-10 08:01:20 -0600 | [diff] [blame] | 1465 | /* Don't forget this is measured in 32-bit words, not bytes */ |
| 1466 | u8 pci_cache_line_size = PCI_CACHE_LINE_BYTES / 4; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1467 | |
| 1468 | /** |
Matthew Wilcox | edb2d97 | 2006-10-10 08:01:21 -0600 | [diff] [blame] | 1469 | * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed |
| 1470 | * @dev: the PCI device for which MWI is to be enabled |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1471 | * |
Matthew Wilcox | edb2d97 | 2006-10-10 08:01:21 -0600 | [diff] [blame] | 1472 | * Helper function for pci_set_mwi. |
| 1473 | * Originally copied from drivers/net/acenic.c. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1474 | * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>. |
| 1475 | * |
| 1476 | * RETURNS: An appropriate -ERRNO error value on error, or zero for success. |
| 1477 | */ |
| 1478 | static int |
Matthew Wilcox | edb2d97 | 2006-10-10 08:01:21 -0600 | [diff] [blame] | 1479 | pci_set_cacheline_size(struct pci_dev *dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1480 | { |
| 1481 | u8 cacheline_size; |
| 1482 | |
| 1483 | if (!pci_cache_line_size) |
| 1484 | return -EINVAL; /* The system doesn't support MWI. */ |
| 1485 | |
| 1486 | /* Validate current setting: the PCI_CACHE_LINE_SIZE must be |
| 1487 | equal to or multiple of the right value. */ |
| 1488 | pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); |
| 1489 | if (cacheline_size >= pci_cache_line_size && |
| 1490 | (cacheline_size % pci_cache_line_size) == 0) |
| 1491 | return 0; |
| 1492 | |
| 1493 | /* Write the correct value. */ |
| 1494 | pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size); |
| 1495 | /* Read it back. */ |
| 1496 | pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); |
| 1497 | if (cacheline_size == pci_cache_line_size) |
| 1498 | return 0; |
| 1499 | |
Bjorn Helgaas | 80ccba1 | 2008-06-13 10:52:11 -0600 | [diff] [blame] | 1500 | dev_printk(KERN_DEBUG, &dev->dev, "cache line size of %d is not " |
| 1501 | "supported\n", pci_cache_line_size << 2); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1502 | |
| 1503 | return -EINVAL; |
| 1504 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1505 | |
| 1506 | /** |
| 1507 | * pci_set_mwi - enables memory-write-invalidate PCI transaction |
| 1508 | * @dev: the PCI device for which MWI is enabled |
| 1509 | * |
Randy Dunlap | 694625c | 2007-07-09 11:55:54 -0700 | [diff] [blame] | 1510 | * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1511 | * |
| 1512 | * RETURNS: An appropriate -ERRNO error value on error, or zero for success. |
| 1513 | */ |
| 1514 | int |
| 1515 | pci_set_mwi(struct pci_dev *dev) |
| 1516 | { |
| 1517 | int rc; |
| 1518 | u16 cmd; |
| 1519 | |
Matthew Wilcox | edb2d97 | 2006-10-10 08:01:21 -0600 | [diff] [blame] | 1520 | rc = pci_set_cacheline_size(dev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1521 | if (rc) |
| 1522 | return rc; |
| 1523 | |
| 1524 | pci_read_config_word(dev, PCI_COMMAND, &cmd); |
| 1525 | if (! (cmd & PCI_COMMAND_INVALIDATE)) { |
Bjorn Helgaas | 80ccba1 | 2008-06-13 10:52:11 -0600 | [diff] [blame] | 1526 | dev_dbg(&dev->dev, "enabling Mem-Wr-Inval\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1527 | cmd |= PCI_COMMAND_INVALIDATE; |
| 1528 | pci_write_config_word(dev, PCI_COMMAND, cmd); |
| 1529 | } |
| 1530 | |
| 1531 | return 0; |
| 1532 | } |
| 1533 | |
| 1534 | /** |
Randy Dunlap | 694625c | 2007-07-09 11:55:54 -0700 | [diff] [blame] | 1535 | * pci_try_set_mwi - enables memory-write-invalidate PCI transaction |
| 1536 | * @dev: the PCI device for which MWI is enabled |
| 1537 | * |
| 1538 | * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND. |
| 1539 | * Callers are not required to check the return value. |
| 1540 | * |
| 1541 | * RETURNS: An appropriate -ERRNO error value on error, or zero for success. |
| 1542 | */ |
| 1543 | int pci_try_set_mwi(struct pci_dev *dev) |
| 1544 | { |
| 1545 | int rc = pci_set_mwi(dev); |
| 1546 | return rc; |
| 1547 | } |
| 1548 | |
| 1549 | /** |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1550 | * pci_clear_mwi - disables Memory-Write-Invalidate for device dev |
| 1551 | * @dev: the PCI device to disable |
| 1552 | * |
| 1553 | * Disables PCI Memory-Write-Invalidate transaction on the device |
| 1554 | */ |
| 1555 | void |
| 1556 | pci_clear_mwi(struct pci_dev *dev) |
| 1557 | { |
| 1558 | u16 cmd; |
| 1559 | |
| 1560 | pci_read_config_word(dev, PCI_COMMAND, &cmd); |
| 1561 | if (cmd & PCI_COMMAND_INVALIDATE) { |
| 1562 | cmd &= ~PCI_COMMAND_INVALIDATE; |
| 1563 | pci_write_config_word(dev, PCI_COMMAND, cmd); |
| 1564 | } |
| 1565 | } |
Matthew Wilcox | edb2d97 | 2006-10-10 08:01:21 -0600 | [diff] [blame] | 1566 | #endif /* ! PCI_DISABLE_MWI */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1567 | |
Brett M Russ | a04ce0f | 2005-08-15 15:23:41 -0400 | [diff] [blame] | 1568 | /** |
| 1569 | * pci_intx - enables/disables PCI INTx for device dev |
Randy Dunlap | 8f7020d | 2005-10-23 11:57:38 -0700 | [diff] [blame] | 1570 | * @pdev: the PCI device to operate on |
| 1571 | * @enable: boolean: whether to enable or disable PCI INTx |
Brett M Russ | a04ce0f | 2005-08-15 15:23:41 -0400 | [diff] [blame] | 1572 | * |
| 1573 | * Enables/disables PCI INTx for device dev |
| 1574 | */ |
| 1575 | void |
| 1576 | pci_intx(struct pci_dev *pdev, int enable) |
| 1577 | { |
| 1578 | u16 pci_command, new; |
| 1579 | |
| 1580 | pci_read_config_word(pdev, PCI_COMMAND, &pci_command); |
| 1581 | |
| 1582 | if (enable) { |
| 1583 | new = pci_command & ~PCI_COMMAND_INTX_DISABLE; |
| 1584 | } else { |
| 1585 | new = pci_command | PCI_COMMAND_INTX_DISABLE; |
| 1586 | } |
| 1587 | |
| 1588 | if (new != pci_command) { |
Tejun Heo | 9ac7849 | 2007-01-20 16:00:26 +0900 | [diff] [blame] | 1589 | struct pci_devres *dr; |
| 1590 | |
Brett M Russ | 2fd9d74 | 2005-09-09 10:02:22 -0700 | [diff] [blame] | 1591 | pci_write_config_word(pdev, PCI_COMMAND, new); |
Tejun Heo | 9ac7849 | 2007-01-20 16:00:26 +0900 | [diff] [blame] | 1592 | |
| 1593 | dr = find_pci_dr(pdev); |
| 1594 | if (dr && !dr->restore_intx) { |
| 1595 | dr->restore_intx = 1; |
| 1596 | dr->orig_intx = !enable; |
| 1597 | } |
Brett M Russ | a04ce0f | 2005-08-15 15:23:41 -0400 | [diff] [blame] | 1598 | } |
| 1599 | } |
| 1600 | |
Eric W. Biederman | f5f2b13 | 2007-03-05 00:30:07 -0800 | [diff] [blame] | 1601 | /** |
| 1602 | * pci_msi_off - disables any msi or msix capabilities |
Randy Dunlap | 8d7d86e | 2007-03-16 19:55:52 -0700 | [diff] [blame] | 1603 | * @dev: the PCI device to operate on |
Eric W. Biederman | f5f2b13 | 2007-03-05 00:30:07 -0800 | [diff] [blame] | 1604 | * |
| 1605 | * If you want to use msi see pci_enable_msi and friends. |
| 1606 | * This is a lower level primitive that allows us to disable |
| 1607 | * msi operation at the device level. |
| 1608 | */ |
| 1609 | void pci_msi_off(struct pci_dev *dev) |
| 1610 | { |
| 1611 | int pos; |
| 1612 | u16 control; |
| 1613 | |
| 1614 | pos = pci_find_capability(dev, PCI_CAP_ID_MSI); |
| 1615 | if (pos) { |
| 1616 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control); |
| 1617 | control &= ~PCI_MSI_FLAGS_ENABLE; |
| 1618 | pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control); |
| 1619 | } |
| 1620 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); |
| 1621 | if (pos) { |
| 1622 | pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control); |
| 1623 | control &= ~PCI_MSIX_FLAGS_ENABLE; |
| 1624 | pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); |
| 1625 | } |
| 1626 | } |
| 1627 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1628 | #ifndef HAVE_ARCH_PCI_SET_DMA_MASK |
| 1629 | /* |
| 1630 | * These can be overridden by arch-specific implementations |
| 1631 | */ |
| 1632 | int |
| 1633 | pci_set_dma_mask(struct pci_dev *dev, u64 mask) |
| 1634 | { |
| 1635 | if (!pci_dma_supported(dev, mask)) |
| 1636 | return -EIO; |
| 1637 | |
| 1638 | dev->dma_mask = mask; |
| 1639 | |
| 1640 | return 0; |
| 1641 | } |
| 1642 | |
| 1643 | int |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1644 | pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask) |
| 1645 | { |
| 1646 | if (!pci_dma_supported(dev, mask)) |
| 1647 | return -EIO; |
| 1648 | |
| 1649 | dev->dev.coherent_dma_mask = mask; |
| 1650 | |
| 1651 | return 0; |
| 1652 | } |
| 1653 | #endif |
Hidetoshi Seto | c87deff | 2006-12-18 10:31:06 +0900 | [diff] [blame] | 1654 | |
FUJITA Tomonori | 4d57cdf | 2008-02-04 22:27:55 -0800 | [diff] [blame] | 1655 | #ifndef HAVE_ARCH_PCI_SET_DMA_MAX_SEGMENT_SIZE |
| 1656 | int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size) |
| 1657 | { |
| 1658 | return dma_set_max_seg_size(&dev->dev, size); |
| 1659 | } |
| 1660 | EXPORT_SYMBOL(pci_set_dma_max_seg_size); |
| 1661 | #endif |
| 1662 | |
FUJITA Tomonori | 59fc67d | 2008-02-04 22:28:14 -0800 | [diff] [blame] | 1663 | #ifndef HAVE_ARCH_PCI_SET_DMA_SEGMENT_BOUNDARY |
| 1664 | int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask) |
| 1665 | { |
| 1666 | return dma_set_seg_boundary(&dev->dev, mask); |
| 1667 | } |
| 1668 | EXPORT_SYMBOL(pci_set_dma_seg_boundary); |
| 1669 | #endif |
| 1670 | |
Hidetoshi Seto | c87deff | 2006-12-18 10:31:06 +0900 | [diff] [blame] | 1671 | /** |
Peter Oruba | d556ad4 | 2007-05-15 13:59:13 +0200 | [diff] [blame] | 1672 | * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count |
| 1673 | * @dev: PCI device to query |
| 1674 | * |
| 1675 | * Returns mmrbc: maximum designed memory read count in bytes |
| 1676 | * or appropriate error value. |
| 1677 | */ |
| 1678 | int pcix_get_max_mmrbc(struct pci_dev *dev) |
| 1679 | { |
Andrew Morton | b7b095c | 2007-07-09 11:55:50 -0700 | [diff] [blame] | 1680 | int err, cap; |
Peter Oruba | d556ad4 | 2007-05-15 13:59:13 +0200 | [diff] [blame] | 1681 | u32 stat; |
| 1682 | |
| 1683 | cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); |
| 1684 | if (!cap) |
| 1685 | return -EINVAL; |
| 1686 | |
| 1687 | err = pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat); |
| 1688 | if (err) |
| 1689 | return -EINVAL; |
| 1690 | |
Andrew Morton | b7b095c | 2007-07-09 11:55:50 -0700 | [diff] [blame] | 1691 | return (stat & PCI_X_STATUS_MAX_READ) >> 12; |
Peter Oruba | d556ad4 | 2007-05-15 13:59:13 +0200 | [diff] [blame] | 1692 | } |
| 1693 | EXPORT_SYMBOL(pcix_get_max_mmrbc); |
| 1694 | |
| 1695 | /** |
| 1696 | * pcix_get_mmrbc - get PCI-X maximum memory read byte count |
| 1697 | * @dev: PCI device to query |
| 1698 | * |
| 1699 | * Returns mmrbc: maximum memory read count in bytes |
| 1700 | * or appropriate error value. |
| 1701 | */ |
| 1702 | int pcix_get_mmrbc(struct pci_dev *dev) |
| 1703 | { |
| 1704 | int ret, cap; |
| 1705 | u32 cmd; |
| 1706 | |
| 1707 | cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); |
| 1708 | if (!cap) |
| 1709 | return -EINVAL; |
| 1710 | |
| 1711 | ret = pci_read_config_dword(dev, cap + PCI_X_CMD, &cmd); |
| 1712 | if (!ret) |
| 1713 | ret = 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2); |
| 1714 | |
| 1715 | return ret; |
| 1716 | } |
| 1717 | EXPORT_SYMBOL(pcix_get_mmrbc); |
| 1718 | |
| 1719 | /** |
| 1720 | * pcix_set_mmrbc - set PCI-X maximum memory read byte count |
| 1721 | * @dev: PCI device to query |
| 1722 | * @mmrbc: maximum memory read count in bytes |
| 1723 | * valid values are 512, 1024, 2048, 4096 |
| 1724 | * |
| 1725 | * If possible sets maximum memory read byte count, some bridges have erratas |
| 1726 | * that prevent this. |
| 1727 | */ |
| 1728 | int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc) |
| 1729 | { |
| 1730 | int cap, err = -EINVAL; |
| 1731 | u32 stat, cmd, v, o; |
| 1732 | |
vignesh babu | 229f5af | 2007-08-13 18:23:14 +0530 | [diff] [blame] | 1733 | if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc)) |
Peter Oruba | d556ad4 | 2007-05-15 13:59:13 +0200 | [diff] [blame] | 1734 | goto out; |
| 1735 | |
| 1736 | v = ffs(mmrbc) - 10; |
| 1737 | |
| 1738 | cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); |
| 1739 | if (!cap) |
| 1740 | goto out; |
| 1741 | |
| 1742 | err = pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat); |
| 1743 | if (err) |
| 1744 | goto out; |
| 1745 | |
| 1746 | if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21) |
| 1747 | return -E2BIG; |
| 1748 | |
| 1749 | err = pci_read_config_dword(dev, cap + PCI_X_CMD, &cmd); |
| 1750 | if (err) |
| 1751 | goto out; |
| 1752 | |
| 1753 | o = (cmd & PCI_X_CMD_MAX_READ) >> 2; |
| 1754 | if (o != v) { |
| 1755 | if (v > o && dev->bus && |
| 1756 | (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC)) |
| 1757 | return -EIO; |
| 1758 | |
| 1759 | cmd &= ~PCI_X_CMD_MAX_READ; |
| 1760 | cmd |= v << 2; |
| 1761 | err = pci_write_config_dword(dev, cap + PCI_X_CMD, cmd); |
| 1762 | } |
| 1763 | out: |
| 1764 | return err; |
| 1765 | } |
| 1766 | EXPORT_SYMBOL(pcix_set_mmrbc); |
| 1767 | |
| 1768 | /** |
| 1769 | * pcie_get_readrq - get PCI Express read request size |
| 1770 | * @dev: PCI device to query |
| 1771 | * |
| 1772 | * Returns maximum memory read request in bytes |
| 1773 | * or appropriate error value. |
| 1774 | */ |
| 1775 | int pcie_get_readrq(struct pci_dev *dev) |
| 1776 | { |
| 1777 | int ret, cap; |
| 1778 | u16 ctl; |
| 1779 | |
| 1780 | cap = pci_find_capability(dev, PCI_CAP_ID_EXP); |
| 1781 | if (!cap) |
| 1782 | return -EINVAL; |
| 1783 | |
| 1784 | ret = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl); |
| 1785 | if (!ret) |
| 1786 | ret = 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12); |
| 1787 | |
| 1788 | return ret; |
| 1789 | } |
| 1790 | EXPORT_SYMBOL(pcie_get_readrq); |
| 1791 | |
| 1792 | /** |
| 1793 | * pcie_set_readrq - set PCI Express maximum memory read request |
| 1794 | * @dev: PCI device to query |
Randy Dunlap | 42e61f4 | 2007-07-23 21:42:11 -0700 | [diff] [blame] | 1795 | * @rq: maximum memory read count in bytes |
Peter Oruba | d556ad4 | 2007-05-15 13:59:13 +0200 | [diff] [blame] | 1796 | * valid values are 128, 256, 512, 1024, 2048, 4096 |
| 1797 | * |
| 1798 | * If possible sets maximum read byte count |
| 1799 | */ |
| 1800 | int pcie_set_readrq(struct pci_dev *dev, int rq) |
| 1801 | { |
| 1802 | int cap, err = -EINVAL; |
| 1803 | u16 ctl, v; |
| 1804 | |
vignesh babu | 229f5af | 2007-08-13 18:23:14 +0530 | [diff] [blame] | 1805 | if (rq < 128 || rq > 4096 || !is_power_of_2(rq)) |
Peter Oruba | d556ad4 | 2007-05-15 13:59:13 +0200 | [diff] [blame] | 1806 | goto out; |
| 1807 | |
| 1808 | v = (ffs(rq) - 8) << 12; |
| 1809 | |
| 1810 | cap = pci_find_capability(dev, PCI_CAP_ID_EXP); |
| 1811 | if (!cap) |
| 1812 | goto out; |
| 1813 | |
| 1814 | err = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl); |
| 1815 | if (err) |
| 1816 | goto out; |
| 1817 | |
| 1818 | if ((ctl & PCI_EXP_DEVCTL_READRQ) != v) { |
| 1819 | ctl &= ~PCI_EXP_DEVCTL_READRQ; |
| 1820 | ctl |= v; |
| 1821 | err = pci_write_config_dword(dev, cap + PCI_EXP_DEVCTL, ctl); |
| 1822 | } |
| 1823 | |
| 1824 | out: |
| 1825 | return err; |
| 1826 | } |
| 1827 | EXPORT_SYMBOL(pcie_set_readrq); |
| 1828 | |
| 1829 | /** |
Hidetoshi Seto | c87deff | 2006-12-18 10:31:06 +0900 | [diff] [blame] | 1830 | * pci_select_bars - Make BAR mask from the type of resource |
Randy Dunlap | f95d882 | 2007-02-10 14:41:56 -0800 | [diff] [blame] | 1831 | * @dev: the PCI device for which BAR mask is made |
Hidetoshi Seto | c87deff | 2006-12-18 10:31:06 +0900 | [diff] [blame] | 1832 | * @flags: resource type mask to be selected |
| 1833 | * |
| 1834 | * This helper routine makes bar mask from the type of resource. |
| 1835 | */ |
| 1836 | int pci_select_bars(struct pci_dev *dev, unsigned long flags) |
| 1837 | { |
| 1838 | int i, bars = 0; |
| 1839 | for (i = 0; i < PCI_NUM_RESOURCES; i++) |
| 1840 | if (pci_resource_flags(dev, i) & flags) |
| 1841 | bars |= (1 << i); |
| 1842 | return bars; |
| 1843 | } |
| 1844 | |
Jeff Garzik | 32a2eea | 2007-10-11 16:57:27 -0400 | [diff] [blame] | 1845 | static void __devinit pci_no_domains(void) |
| 1846 | { |
| 1847 | #ifdef CONFIG_PCI_DOMAINS |
| 1848 | pci_domains_supported = 0; |
| 1849 | #endif |
| 1850 | } |
| 1851 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1852 | static int __devinit pci_init(void) |
| 1853 | { |
| 1854 | struct pci_dev *dev = NULL; |
| 1855 | |
| 1856 | while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { |
| 1857 | pci_fixup_device(pci_fixup_final, dev); |
| 1858 | } |
| 1859 | return 0; |
| 1860 | } |
| 1861 | |
| 1862 | static int __devinit pci_setup(char *str) |
| 1863 | { |
| 1864 | while (str) { |
| 1865 | char *k = strchr(str, ','); |
| 1866 | if (k) |
| 1867 | *k++ = 0; |
| 1868 | if (*str && (str = pcibios_setup(str)) && *str) { |
Matthew Wilcox | 309e57d | 2006-03-05 22:33:34 -0700 | [diff] [blame] | 1869 | if (!strcmp(str, "nomsi")) { |
| 1870 | pci_no_msi(); |
Randy Dunlap | 7f78576 | 2007-10-05 13:17:58 -0700 | [diff] [blame] | 1871 | } else if (!strcmp(str, "noaer")) { |
| 1872 | pci_no_aer(); |
Jeff Garzik | 32a2eea | 2007-10-11 16:57:27 -0400 | [diff] [blame] | 1873 | } else if (!strcmp(str, "nodomains")) { |
| 1874 | pci_no_domains(); |
Atsushi Nemoto | 4516a61 | 2007-02-05 16:36:06 -0800 | [diff] [blame] | 1875 | } else if (!strncmp(str, "cbiosize=", 9)) { |
| 1876 | pci_cardbus_io_size = memparse(str + 9, &str); |
| 1877 | } else if (!strncmp(str, "cbmemsize=", 10)) { |
| 1878 | pci_cardbus_mem_size = memparse(str + 10, &str); |
Matthew Wilcox | 309e57d | 2006-03-05 22:33:34 -0700 | [diff] [blame] | 1879 | } else { |
| 1880 | printk(KERN_ERR "PCI: Unknown option `%s'\n", |
| 1881 | str); |
| 1882 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1883 | } |
| 1884 | str = k; |
| 1885 | } |
Andi Kleen | 0637a70 | 2006-09-26 10:52:41 +0200 | [diff] [blame] | 1886 | return 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1887 | } |
Andi Kleen | 0637a70 | 2006-09-26 10:52:41 +0200 | [diff] [blame] | 1888 | early_param("pci", pci_setup); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1889 | |
| 1890 | device_initcall(pci_init); |
| 1891 | |
Tejun Heo | 0b62e13 | 2007-07-27 14:43:35 +0900 | [diff] [blame] | 1892 | EXPORT_SYMBOL(pci_reenable_device); |
Benjamin Herrenschmidt | b718989 | 2007-12-20 15:28:08 +1100 | [diff] [blame] | 1893 | EXPORT_SYMBOL(pci_enable_device_io); |
| 1894 | EXPORT_SYMBOL(pci_enable_device_mem); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1895 | EXPORT_SYMBOL(pci_enable_device); |
Tejun Heo | 9ac7849 | 2007-01-20 16:00:26 +0900 | [diff] [blame] | 1896 | EXPORT_SYMBOL(pcim_enable_device); |
| 1897 | EXPORT_SYMBOL(pcim_pin_device); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1898 | EXPORT_SYMBOL(pci_disable_device); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1899 | EXPORT_SYMBOL(pci_find_capability); |
| 1900 | EXPORT_SYMBOL(pci_bus_find_capability); |
| 1901 | EXPORT_SYMBOL(pci_release_regions); |
| 1902 | EXPORT_SYMBOL(pci_request_regions); |
| 1903 | EXPORT_SYMBOL(pci_release_region); |
| 1904 | EXPORT_SYMBOL(pci_request_region); |
Hidetoshi Seto | c87deff | 2006-12-18 10:31:06 +0900 | [diff] [blame] | 1905 | EXPORT_SYMBOL(pci_release_selected_regions); |
| 1906 | EXPORT_SYMBOL(pci_request_selected_regions); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1907 | EXPORT_SYMBOL(pci_set_master); |
| 1908 | EXPORT_SYMBOL(pci_set_mwi); |
Randy Dunlap | 694625c | 2007-07-09 11:55:54 -0700 | [diff] [blame] | 1909 | EXPORT_SYMBOL(pci_try_set_mwi); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1910 | EXPORT_SYMBOL(pci_clear_mwi); |
Brett M Russ | a04ce0f | 2005-08-15 15:23:41 -0400 | [diff] [blame] | 1911 | EXPORT_SYMBOL_GPL(pci_intx); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1912 | EXPORT_SYMBOL(pci_set_dma_mask); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1913 | EXPORT_SYMBOL(pci_set_consistent_dma_mask); |
| 1914 | EXPORT_SYMBOL(pci_assign_resource); |
| 1915 | EXPORT_SYMBOL(pci_find_parent_resource); |
Hidetoshi Seto | c87deff | 2006-12-18 10:31:06 +0900 | [diff] [blame] | 1916 | EXPORT_SYMBOL(pci_select_bars); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1917 | |
| 1918 | EXPORT_SYMBOL(pci_set_power_state); |
| 1919 | EXPORT_SYMBOL(pci_save_state); |
| 1920 | EXPORT_SYMBOL(pci_restore_state); |
| 1921 | EXPORT_SYMBOL(pci_enable_wake); |
Rafael J. Wysocki | 404cc2d | 2008-07-07 03:35:26 +0200 | [diff] [blame] | 1922 | EXPORT_SYMBOL(pci_prepare_to_sleep); |
| 1923 | EXPORT_SYMBOL(pci_back_from_sleep); |
Brian King | f7bdd12 | 2007-04-06 16:39:36 -0500 | [diff] [blame] | 1924 | EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1925 | |