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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07002 * PCI Bus Services, see include/linux/pci.h for further explanation.
3 *
4 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
5 * David Mosberger-Tang
6 *
7 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
8 */
9
10#include <linux/kernel.h>
11#include <linux/delay.h>
12#include <linux/init.h>
13#include <linux/pci.h>
David Brownell075c1772007-04-26 00:12:06 -070014#include <linux/pm.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070015#include <linux/module.h>
16#include <linux/spinlock.h>
Tim Schmielau4e57b682005-10-30 15:03:48 -080017#include <linux/string.h>
vignesh babu229f5af2007-08-13 18:23:14 +053018#include <linux/log2.h>
Shaohua Li7d715a62008-02-25 09:46:41 +080019#include <linux/pci-aspm.h>
Stephen Rothwellc300bd2fb2008-07-10 02:16:44 +020020#include <linux/pm_wakeup.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070021#include <asm/dma.h> /* isa_dma_bridge_buggy */
Greg KHbc56b9e2005-04-08 14:53:31 +090022#include "pci.h"
Linus Torvalds1da177e2005-04-16 15:20:36 -070023
Kristen Carlson Accardiffadcc22006-07-12 08:59:00 -070024unsigned int pci_pm_d3_delay = 10;
Linus Torvalds1da177e2005-04-16 15:20:36 -070025
Jeff Garzik32a2eea2007-10-11 16:57:27 -040026#ifdef CONFIG_PCI_DOMAINS
27int pci_domains_supported = 1;
28#endif
29
Atsushi Nemoto4516a612007-02-05 16:36:06 -080030#define DEFAULT_CARDBUS_IO_SIZE (256)
31#define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
32/* pci=cbmemsize=nnM,cbiosize=nn can override this */
33unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE;
34unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE;
35
Linus Torvalds1da177e2005-04-16 15:20:36 -070036/**
37 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
38 * @bus: pointer to PCI bus structure to search
39 *
40 * Given a PCI bus, returns the highest PCI bus number present in the set
41 * including the given PCI bus and its list of child PCI buses.
42 */
Sam Ravnborg96bde062007-03-26 21:53:30 -080043unsigned char pci_bus_max_busnr(struct pci_bus* bus)
Linus Torvalds1da177e2005-04-16 15:20:36 -070044{
45 struct list_head *tmp;
46 unsigned char max, n;
47
Kristen Accardib82db5c2006-01-17 16:56:56 -080048 max = bus->subordinate;
Linus Torvalds1da177e2005-04-16 15:20:36 -070049 list_for_each(tmp, &bus->children) {
50 n = pci_bus_max_busnr(pci_bus_b(tmp));
51 if(n > max)
52 max = n;
53 }
54 return max;
55}
Kristen Accardib82db5c2006-01-17 16:56:56 -080056EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
Linus Torvalds1da177e2005-04-16 15:20:36 -070057
Kristen Accardib82db5c2006-01-17 16:56:56 -080058#if 0
Linus Torvalds1da177e2005-04-16 15:20:36 -070059/**
60 * pci_max_busnr - returns maximum PCI bus number
61 *
62 * Returns the highest PCI bus number present in the system global list of
63 * PCI buses.
64 */
65unsigned char __devinit
66pci_max_busnr(void)
67{
68 struct pci_bus *bus = NULL;
69 unsigned char max, n;
70
71 max = 0;
72 while ((bus = pci_find_next_bus(bus)) != NULL) {
73 n = pci_bus_max_busnr(bus);
74 if(n > max)
75 max = n;
76 }
77 return max;
78}
79
Adrian Bunk54c762f2005-12-22 01:08:52 +010080#endif /* 0 */
81
Michael Ellerman687d5fe2006-11-22 18:26:18 +110082#define PCI_FIND_CAP_TTL 48
83
84static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
85 u8 pos, int cap, int *ttl)
Roland Dreier24a4e372005-10-28 17:35:34 -070086{
87 u8 id;
Roland Dreier24a4e372005-10-28 17:35:34 -070088
Michael Ellerman687d5fe2006-11-22 18:26:18 +110089 while ((*ttl)--) {
Roland Dreier24a4e372005-10-28 17:35:34 -070090 pci_bus_read_config_byte(bus, devfn, pos, &pos);
91 if (pos < 0x40)
92 break;
93 pos &= ~3;
94 pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID,
95 &id);
96 if (id == 0xff)
97 break;
98 if (id == cap)
99 return pos;
100 pos += PCI_CAP_LIST_NEXT;
101 }
102 return 0;
103}
104
Michael Ellerman687d5fe2006-11-22 18:26:18 +1100105static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn,
106 u8 pos, int cap)
107{
108 int ttl = PCI_FIND_CAP_TTL;
109
110 return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
111}
112
Roland Dreier24a4e372005-10-28 17:35:34 -0700113int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
114{
115 return __pci_find_next_cap(dev->bus, dev->devfn,
116 pos + PCI_CAP_LIST_NEXT, cap);
117}
118EXPORT_SYMBOL_GPL(pci_find_next_capability);
119
Michael Ellermand3bac112006-11-22 18:26:16 +1100120static int __pci_bus_find_cap_start(struct pci_bus *bus,
121 unsigned int devfn, u8 hdr_type)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700122{
123 u16 status;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700124
125 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
126 if (!(status & PCI_STATUS_CAP_LIST))
127 return 0;
128
129 switch (hdr_type) {
130 case PCI_HEADER_TYPE_NORMAL:
131 case PCI_HEADER_TYPE_BRIDGE:
Michael Ellermand3bac112006-11-22 18:26:16 +1100132 return PCI_CAPABILITY_LIST;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700133 case PCI_HEADER_TYPE_CARDBUS:
Michael Ellermand3bac112006-11-22 18:26:16 +1100134 return PCI_CB_CAPABILITY_LIST;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700135 default:
136 return 0;
137 }
Michael Ellermand3bac112006-11-22 18:26:16 +1100138
139 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700140}
141
142/**
143 * pci_find_capability - query for devices' capabilities
144 * @dev: PCI device to query
145 * @cap: capability code
146 *
147 * Tell if a device supports a given PCI capability.
148 * Returns the address of the requested capability structure within the
149 * device's PCI configuration space or 0 in case the device does not
150 * support it. Possible values for @cap:
151 *
152 * %PCI_CAP_ID_PM Power Management
153 * %PCI_CAP_ID_AGP Accelerated Graphics Port
154 * %PCI_CAP_ID_VPD Vital Product Data
155 * %PCI_CAP_ID_SLOTID Slot Identification
156 * %PCI_CAP_ID_MSI Message Signalled Interrupts
157 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
158 * %PCI_CAP_ID_PCIX PCI-X
159 * %PCI_CAP_ID_EXP PCI Express
160 */
161int pci_find_capability(struct pci_dev *dev, int cap)
162{
Michael Ellermand3bac112006-11-22 18:26:16 +1100163 int pos;
164
165 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
166 if (pos)
167 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);
168
169 return pos;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700170}
171
172/**
173 * pci_bus_find_capability - query for devices' capabilities
174 * @bus: the PCI bus to query
175 * @devfn: PCI device to query
176 * @cap: capability code
177 *
178 * Like pci_find_capability() but works for pci devices that do not have a
179 * pci_dev structure set up yet.
180 *
181 * Returns the address of the requested capability structure within the
182 * device's PCI configuration space or 0 in case the device does not
183 * support it.
184 */
185int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
186{
Michael Ellermand3bac112006-11-22 18:26:16 +1100187 int pos;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700188 u8 hdr_type;
189
190 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
191
Michael Ellermand3bac112006-11-22 18:26:16 +1100192 pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f);
193 if (pos)
194 pos = __pci_find_next_cap(bus, devfn, pos, cap);
195
196 return pos;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700197}
198
199/**
200 * pci_find_ext_capability - Find an extended capability
201 * @dev: PCI device to query
202 * @cap: capability code
203 *
204 * Returns the address of the requested extended capability structure
205 * within the device's PCI configuration space or 0 if the device does
206 * not support it. Possible values for @cap:
207 *
208 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
209 * %PCI_EXT_CAP_ID_VC Virtual Channel
210 * %PCI_EXT_CAP_ID_DSN Device Serial Number
211 * %PCI_EXT_CAP_ID_PWR Power Budgeting
212 */
213int pci_find_ext_capability(struct pci_dev *dev, int cap)
214{
215 u32 header;
216 int ttl = 480; /* 3840 bytes, minimum 8 bytes per capability */
217 int pos = 0x100;
218
219 if (dev->cfg_size <= 256)
220 return 0;
221
222 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
223 return 0;
224
225 /*
226 * If we have no capabilities, this is indicated by cap ID,
227 * cap version and next pointer all being 0.
228 */
229 if (header == 0)
230 return 0;
231
232 while (ttl-- > 0) {
233 if (PCI_EXT_CAP_ID(header) == cap)
234 return pos;
235
236 pos = PCI_EXT_CAP_NEXT(header);
237 if (pos < 0x100)
238 break;
239
240 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
241 break;
242 }
243
244 return 0;
245}
Brice Goglin3a720d72006-05-23 06:10:01 -0400246EXPORT_SYMBOL_GPL(pci_find_ext_capability);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700247
Michael Ellerman687d5fe2006-11-22 18:26:18 +1100248static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap)
249{
250 int rc, ttl = PCI_FIND_CAP_TTL;
251 u8 cap, mask;
252
253 if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST)
254 mask = HT_3BIT_CAP_MASK;
255 else
256 mask = HT_5BIT_CAP_MASK;
257
258 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
259 PCI_CAP_ID_HT, &ttl);
260 while (pos) {
261 rc = pci_read_config_byte(dev, pos + 3, &cap);
262 if (rc != PCIBIOS_SUCCESSFUL)
263 return 0;
264
265 if ((cap & mask) == ht_cap)
266 return pos;
267
Brice Goglin47a4d5b2007-01-10 23:15:29 -0800268 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn,
269 pos + PCI_CAP_LIST_NEXT,
Michael Ellerman687d5fe2006-11-22 18:26:18 +1100270 PCI_CAP_ID_HT, &ttl);
271 }
272
273 return 0;
274}
275/**
276 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
277 * @dev: PCI device to query
278 * @pos: Position from which to continue searching
279 * @ht_cap: Hypertransport capability code
280 *
281 * To be used in conjunction with pci_find_ht_capability() to search for
282 * all capabilities matching @ht_cap. @pos should always be a value returned
283 * from pci_find_ht_capability().
284 *
285 * NB. To be 100% safe against broken PCI devices, the caller should take
286 * steps to avoid an infinite loop.
287 */
288int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap)
289{
290 return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap);
291}
292EXPORT_SYMBOL_GPL(pci_find_next_ht_capability);
293
294/**
295 * pci_find_ht_capability - query a device's Hypertransport capabilities
296 * @dev: PCI device to query
297 * @ht_cap: Hypertransport capability code
298 *
299 * Tell if a device supports a given Hypertransport capability.
300 * Returns an address within the device's PCI configuration space
301 * or 0 in case the device does not support the request capability.
302 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
303 * which has a Hypertransport capability matching @ht_cap.
304 */
305int pci_find_ht_capability(struct pci_dev *dev, int ht_cap)
306{
307 int pos;
308
309 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
310 if (pos)
311 pos = __pci_find_next_ht_cap(dev, pos, ht_cap);
312
313 return pos;
314}
315EXPORT_SYMBOL_GPL(pci_find_ht_capability);
316
Linus Torvalds1da177e2005-04-16 15:20:36 -0700317/**
318 * pci_find_parent_resource - return resource region of parent bus of given region
319 * @dev: PCI device structure contains resources to be searched
320 * @res: child resource record for which parent is sought
321 *
322 * For given resource region of given device, return the resource
323 * region of parent bus the given region is contained in or where
324 * it should be allocated from.
325 */
326struct resource *
327pci_find_parent_resource(const struct pci_dev *dev, struct resource *res)
328{
329 const struct pci_bus *bus = dev->bus;
330 int i;
331 struct resource *best = NULL;
332
333 for(i = 0; i < PCI_BUS_NUM_RESOURCES; i++) {
334 struct resource *r = bus->resource[i];
335 if (!r)
336 continue;
337 if (res->start && !(res->start >= r->start && res->end <= r->end))
338 continue; /* Not contained */
339 if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM))
340 continue; /* Wrong type */
341 if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH))
342 return r; /* Exact match */
343 if ((res->flags & IORESOURCE_PREFETCH) && !(r->flags & IORESOURCE_PREFETCH))
344 best = r; /* Approximating prefetchable by non-prefetchable */
345 }
346 return best;
347}
348
349/**
John W. Linville064b53d2005-07-27 10:19:44 -0400350 * pci_restore_bars - restore a devices BAR values (e.g. after wake-up)
351 * @dev: PCI device to have its BARs restored
352 *
353 * Restore the BAR values for a given device, so as to make it
354 * accessible by its driver.
355 */
Adrian Bunkad668592007-10-27 03:06:22 +0200356static void
John W. Linville064b53d2005-07-27 10:19:44 -0400357pci_restore_bars(struct pci_dev *dev)
358{
359 int i, numres;
360
361 switch (dev->hdr_type) {
362 case PCI_HEADER_TYPE_NORMAL:
363 numres = 6;
364 break;
365 case PCI_HEADER_TYPE_BRIDGE:
366 numres = 2;
367 break;
368 case PCI_HEADER_TYPE_CARDBUS:
369 numres = 1;
370 break;
371 default:
372 /* Should never get here, but just in case... */
373 return;
374 }
375
376 for (i = 0; i < numres; i ++)
377 pci_update_resource(dev, &dev->resource[i], i);
378}
379
Rafael J. Wysocki961d9122008-07-07 03:32:02 +0200380static struct pci_platform_pm_ops *pci_platform_pm;
381
382int pci_set_platform_pm(struct pci_platform_pm_ops *ops)
383{
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +0200384 if (!ops->is_manageable || !ops->set_state || !ops->choose_state
385 || !ops->sleep_wake || !ops->can_wakeup)
Rafael J. Wysocki961d9122008-07-07 03:32:02 +0200386 return -EINVAL;
387 pci_platform_pm = ops;
388 return 0;
389}
390
391static inline bool platform_pci_power_manageable(struct pci_dev *dev)
392{
393 return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false;
394}
395
396static inline int platform_pci_set_power_state(struct pci_dev *dev,
397 pci_power_t t)
398{
399 return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS;
400}
401
402static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev)
403{
404 return pci_platform_pm ?
405 pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR;
406}
Randy Dunlap8f7020d2005-10-23 11:57:38 -0700407
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +0200408static inline bool platform_pci_can_wakeup(struct pci_dev *dev)
409{
410 return pci_platform_pm ? pci_platform_pm->can_wakeup(dev) : false;
411}
412
413static inline int platform_pci_sleep_wake(struct pci_dev *dev, bool enable)
414{
415 return pci_platform_pm ?
416 pci_platform_pm->sleep_wake(dev, enable) : -ENODEV;
417}
418
John W. Linville064b53d2005-07-27 10:19:44 -0400419/**
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200420 * pci_raw_set_power_state - Use PCI PM registers to set the power state of
421 * given PCI device
422 * @dev: PCI device to handle.
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200423 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700424 *
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200425 * RETURN VALUE:
426 * -EINVAL if the requested state is invalid.
427 * -EIO if device does not support PCI PM or its PM capabilities register has a
428 * wrong version, or device doesn't support the requested state.
429 * 0 if device already is in the requested state.
430 * 0 if device's power state has been successfully changed.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700431 */
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200432static int
Rafael J. Wysocki337001b2008-07-07 03:36:24 +0200433pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700434{
Rafael J. Wysocki337001b2008-07-07 03:36:24 +0200435 u16 pmcsr;
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200436 bool need_restore = false;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700437
Rafael J. Wysocki337001b2008-07-07 03:36:24 +0200438 if (!dev->pm_cap)
Andrew Lunncca03de2007-07-09 11:55:58 -0700439 return -EIO;
440
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200441 if (state < PCI_D0 || state > PCI_D3hot)
442 return -EINVAL;
443
Linus Torvalds1da177e2005-04-16 15:20:36 -0700444 /* Validate current state:
445 * Can enter D0 from any state, but if we can only go deeper
446 * to sleep if we're already in a low power state
447 */
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200448 if (dev->current_state == state) {
449 /* we're already there */
450 return 0;
451 } else if (state != PCI_D0 && dev->current_state <= PCI_D3cold
452 && dev->current_state > state) {
Bjorn Helgaas80ccba12008-06-13 10:52:11 -0600453 dev_err(&dev->dev, "invalid power transition "
454 "(from state %d to %d)\n", dev->current_state, state);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700455 return -EINVAL;
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200456 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700457
Linus Torvalds1da177e2005-04-16 15:20:36 -0700458 /* check if this device supports the desired state */
Rafael J. Wysocki337001b2008-07-07 03:36:24 +0200459 if ((state == PCI_D1 && !dev->d1_support)
460 || (state == PCI_D2 && !dev->d2_support))
Daniel Ritz3fe9d192005-08-17 15:32:19 -0700461 return -EIO;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700462
Rafael J. Wysocki337001b2008-07-07 03:36:24 +0200463 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
John W. Linville064b53d2005-07-27 10:19:44 -0400464
John W. Linville32a36582005-09-14 09:52:42 -0400465 /* If we're (effectively) in D3, force entire word to 0.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700466 * This doesn't affect PME_Status, disables PME_En, and
467 * sets PowerState to 0.
468 */
John W. Linville32a36582005-09-14 09:52:42 -0400469 switch (dev->current_state) {
John W. Linvilled3535fb2005-09-28 17:50:51 -0400470 case PCI_D0:
471 case PCI_D1:
472 case PCI_D2:
473 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
474 pmcsr |= state;
475 break;
John W. Linville32a36582005-09-14 09:52:42 -0400476 case PCI_UNKNOWN: /* Boot-up */
477 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
478 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200479 need_restore = true;
John W. Linville32a36582005-09-14 09:52:42 -0400480 /* Fall-through: force to D0 */
John W. Linville32a36582005-09-14 09:52:42 -0400481 default:
John W. Linvilled3535fb2005-09-28 17:50:51 -0400482 pmcsr = 0;
John W. Linville32a36582005-09-14 09:52:42 -0400483 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700484 }
485
486 /* enter specified state */
Rafael J. Wysocki337001b2008-07-07 03:36:24 +0200487 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700488
489 /* Mandatory power management transition delays */
490 /* see PCI PM 1.1 5.6.1 table 18 */
491 if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
Kristen Carlson Accardiffadcc22006-07-12 08:59:00 -0700492 msleep(pci_pm_d3_delay);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700493 else if (state == PCI_D2 || dev->current_state == PCI_D2)
494 udelay(200);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700495
David Shaohua Lib9131002005-03-19 00:16:18 -0500496 dev->current_state = state;
John W. Linville064b53d2005-07-27 10:19:44 -0400497
498 /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
499 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
500 * from D3hot to D0 _may_ perform an internal reset, thereby
501 * going to "D0 Uninitialized" rather than "D0 Initialized".
502 * For example, at least some versions of the 3c905B and the
503 * 3c556B exhibit this behaviour.
504 *
505 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
506 * devices in a D3hot state at boot. Consequently, we need to
507 * restore at least the BARs so that the device will be
508 * accessible to its driver.
509 */
510 if (need_restore)
511 pci_restore_bars(dev);
512
Shaohua Li7d715a62008-02-25 09:46:41 +0800513 if (dev->bus->self)
514 pcie_aspm_pm_state_change(dev->bus->self);
515
Linus Torvalds1da177e2005-04-16 15:20:36 -0700516 return 0;
517}
518
519/**
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200520 * pci_update_current_state - Read PCI power state of given device from its
521 * PCI PM registers and cache it
522 * @dev: PCI device to handle.
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200523 */
Rafael J. Wysocki337001b2008-07-07 03:36:24 +0200524static void pci_update_current_state(struct pci_dev *dev)
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200525{
Rafael J. Wysocki337001b2008-07-07 03:36:24 +0200526 if (dev->pm_cap) {
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200527 u16 pmcsr;
528
Rafael J. Wysocki337001b2008-07-07 03:36:24 +0200529 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200530 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
531 }
532}
533
534/**
535 * pci_set_power_state - Set the power state of a PCI device
536 * @dev: PCI device to handle.
537 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
538 *
539 * Transition a device to a new power state, using the platform formware and/or
540 * the device's PCI PM registers.
541 *
542 * RETURN VALUE:
543 * -EINVAL if the requested state is invalid.
544 * -EIO if device does not support PCI PM or its PM capabilities register has a
545 * wrong version, or device doesn't support the requested state.
546 * 0 if device already is in the requested state.
547 * 0 if device's power state has been successfully changed.
548 */
549int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
550{
Rafael J. Wysocki337001b2008-07-07 03:36:24 +0200551 int error;
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200552
553 /* bound the state we're entering */
554 if (state > PCI_D3hot)
555 state = PCI_D3hot;
556 else if (state < PCI_D0)
557 state = PCI_D0;
558 else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
559 /*
560 * If the device or the parent bridge do not support PCI PM,
561 * ignore the request if we're doing anything other than putting
562 * it into D0 (which would only happen on boot).
563 */
564 return 0;
565
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200566 if (state == PCI_D0 && platform_pci_power_manageable(dev)) {
567 /*
568 * Allow the platform to change the state, for example via ACPI
569 * _PR0, _PS0 and some such, but do not trust it.
570 */
571 int ret = platform_pci_set_power_state(dev, PCI_D0);
572 if (!ret)
Rafael J. Wysocki337001b2008-07-07 03:36:24 +0200573 pci_update_current_state(dev);
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200574 }
575
Rafael J. Wysocki337001b2008-07-07 03:36:24 +0200576 error = pci_raw_set_power_state(dev, state);
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200577
578 if (state > PCI_D0 && platform_pci_power_manageable(dev)) {
579 /* Allow the platform to finalize the transition */
580 int ret = platform_pci_set_power_state(dev, state);
581 if (!ret) {
Rafael J. Wysocki337001b2008-07-07 03:36:24 +0200582 pci_update_current_state(dev);
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200583 error = 0;
584 }
585 }
586
587 return error;
588}
589
590/**
Linus Torvalds1da177e2005-04-16 15:20:36 -0700591 * pci_choose_state - Choose the power state of a PCI device
592 * @dev: PCI device to be suspended
593 * @state: target sleep state for the whole system. This is the value
594 * that is passed to suspend() function.
595 *
596 * Returns PCI power state suitable for given device and given system
597 * message.
598 */
599
600pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
601{
Shaohua Liab826ca2007-07-20 10:03:22 +0800602 pci_power_t ret;
David Shaohua Li0f644742005-03-19 00:15:48 -0500603
Linus Torvalds1da177e2005-04-16 15:20:36 -0700604 if (!pci_find_capability(dev, PCI_CAP_ID_PM))
605 return PCI_D0;
606
Rafael J. Wysocki961d9122008-07-07 03:32:02 +0200607 ret = platform_pci_choose_state(dev);
608 if (ret != PCI_POWER_ERROR)
609 return ret;
Pavel Machekca078ba2005-09-03 15:56:57 -0700610
611 switch (state.event) {
612 case PM_EVENT_ON:
613 return PCI_D0;
614 case PM_EVENT_FREEZE:
David Brownellb887d2e2006-08-14 23:11:05 -0700615 case PM_EVENT_PRETHAW:
616 /* REVISIT both freeze and pre-thaw "should" use D0 */
Pavel Machekca078ba2005-09-03 15:56:57 -0700617 case PM_EVENT_SUSPEND:
Rafael J. Wysocki3a2d5b72008-02-23 19:13:25 +0100618 case PM_EVENT_HIBERNATE:
Pavel Machekca078ba2005-09-03 15:56:57 -0700619 return PCI_D3hot;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700620 default:
Bjorn Helgaas80ccba12008-06-13 10:52:11 -0600621 dev_info(&dev->dev, "unrecognized suspend event %d\n",
622 state.event);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700623 BUG();
624 }
625 return PCI_D0;
626}
627
628EXPORT_SYMBOL(pci_choose_state);
629
Michael S. Tsirkinb56a5a22006-08-21 16:22:22 +0300630static int pci_save_pcie_state(struct pci_dev *dev)
631{
632 int pos, i = 0;
633 struct pci_cap_saved_state *save_state;
634 u16 *cap;
Shaohua Li017fc482007-12-18 09:57:09 +0800635 int found = 0;
Michael S. Tsirkinb56a5a22006-08-21 16:22:22 +0300636
637 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
638 if (pos <= 0)
639 return 0;
640
Eric W. Biederman9f355752007-03-08 13:06:13 -0700641 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
642 if (!save_state)
643 save_state = kzalloc(sizeof(*save_state) + sizeof(u16) * 4, GFP_KERNEL);
Shaohua Li017fc482007-12-18 09:57:09 +0800644 else
645 found = 1;
Michael S. Tsirkinb56a5a22006-08-21 16:22:22 +0300646 if (!save_state) {
Bjorn Helgaas80ccba12008-06-13 10:52:11 -0600647 dev_err(&dev->dev, "out of memory in pci_save_pcie_state\n");
Michael S. Tsirkinb56a5a22006-08-21 16:22:22 +0300648 return -ENOMEM;
649 }
650 cap = (u16 *)&save_state->data[0];
651
652 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &cap[i++]);
653 pci_read_config_word(dev, pos + PCI_EXP_LNKCTL, &cap[i++]);
654 pci_read_config_word(dev, pos + PCI_EXP_SLTCTL, &cap[i++]);
655 pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &cap[i++]);
Shaohua Liec0a3a22007-12-18 09:56:56 +0800656 save_state->cap_nr = PCI_CAP_ID_EXP;
Shaohua Li017fc482007-12-18 09:57:09 +0800657 if (!found)
658 pci_add_saved_cap(dev, save_state);
Michael S. Tsirkinb56a5a22006-08-21 16:22:22 +0300659 return 0;
660}
661
662static void pci_restore_pcie_state(struct pci_dev *dev)
663{
664 int i = 0, pos;
665 struct pci_cap_saved_state *save_state;
666 u16 *cap;
667
668 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
669 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
670 if (!save_state || pos <= 0)
671 return;
672 cap = (u16 *)&save_state->data[0];
673
674 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, cap[i++]);
675 pci_write_config_word(dev, pos + PCI_EXP_LNKCTL, cap[i++]);
676 pci_write_config_word(dev, pos + PCI_EXP_SLTCTL, cap[i++]);
677 pci_write_config_word(dev, pos + PCI_EXP_RTCTL, cap[i++]);
Michael S. Tsirkinb56a5a22006-08-21 16:22:22 +0300678}
679
Stephen Hemmingercc692a52006-11-08 16:17:15 -0800680
681static int pci_save_pcix_state(struct pci_dev *dev)
682{
683 int pos, i = 0;
684 struct pci_cap_saved_state *save_state;
685 u16 *cap;
Shaohua Li017fc482007-12-18 09:57:09 +0800686 int found = 0;
Stephen Hemmingercc692a52006-11-08 16:17:15 -0800687
688 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
689 if (pos <= 0)
690 return 0;
691
Shaohua Lif34303d2007-12-18 09:56:47 +0800692 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
Eric W. Biederman9f355752007-03-08 13:06:13 -0700693 if (!save_state)
694 save_state = kzalloc(sizeof(*save_state) + sizeof(u16), GFP_KERNEL);
Shaohua Li017fc482007-12-18 09:57:09 +0800695 else
696 found = 1;
Stephen Hemmingercc692a52006-11-08 16:17:15 -0800697 if (!save_state) {
Bjorn Helgaas80ccba12008-06-13 10:52:11 -0600698 dev_err(&dev->dev, "out of memory in pci_save_pcie_state\n");
Stephen Hemmingercc692a52006-11-08 16:17:15 -0800699 return -ENOMEM;
700 }
701 cap = (u16 *)&save_state->data[0];
702
703 pci_read_config_word(dev, pos + PCI_X_CMD, &cap[i++]);
Shaohua Liec0a3a22007-12-18 09:56:56 +0800704 save_state->cap_nr = PCI_CAP_ID_PCIX;
Shaohua Li017fc482007-12-18 09:57:09 +0800705 if (!found)
706 pci_add_saved_cap(dev, save_state);
Stephen Hemmingercc692a52006-11-08 16:17:15 -0800707 return 0;
708}
709
710static void pci_restore_pcix_state(struct pci_dev *dev)
711{
712 int i = 0, pos;
713 struct pci_cap_saved_state *save_state;
714 u16 *cap;
715
716 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
717 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
718 if (!save_state || pos <= 0)
719 return;
720 cap = (u16 *)&save_state->data[0];
721
722 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
Stephen Hemmingercc692a52006-11-08 16:17:15 -0800723}
724
725
Linus Torvalds1da177e2005-04-16 15:20:36 -0700726/**
727 * pci_save_state - save the PCI configuration space of a device before suspending
728 * @dev: - PCI device that we're dealing with
Linus Torvalds1da177e2005-04-16 15:20:36 -0700729 */
730int
731pci_save_state(struct pci_dev *dev)
732{
733 int i;
734 /* XXX: 100% dword access ok here? */
735 for (i = 0; i < 16; i++)
736 pci_read_config_dword(dev, i * 4,&dev->saved_config_space[i]);
Michael S. Tsirkinb56a5a22006-08-21 16:22:22 +0300737 if ((i = pci_save_pcie_state(dev)) != 0)
738 return i;
Stephen Hemmingercc692a52006-11-08 16:17:15 -0800739 if ((i = pci_save_pcix_state(dev)) != 0)
740 return i;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700741 return 0;
742}
743
744/**
745 * pci_restore_state - Restore the saved state of a PCI device
746 * @dev: - PCI device that we're dealing with
Linus Torvalds1da177e2005-04-16 15:20:36 -0700747 */
748int
749pci_restore_state(struct pci_dev *dev)
750{
751 int i;
Al Virob4482a42007-10-14 19:35:40 +0100752 u32 val;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700753
Michael S. Tsirkinb56a5a22006-08-21 16:22:22 +0300754 /* PCI Express register must be restored first */
755 pci_restore_pcie_state(dev);
756
Yu, Luming8b8c8d22006-04-25 00:00:34 -0700757 /*
758 * The Base Address register should be programmed before the command
759 * register(s)
760 */
761 for (i = 15; i >= 0; i--) {
Dave Jones04d9c1a2006-04-18 21:06:51 -0700762 pci_read_config_dword(dev, i * 4, &val);
763 if (val != dev->saved_config_space[i]) {
Bjorn Helgaas80ccba12008-06-13 10:52:11 -0600764 dev_printk(KERN_DEBUG, &dev->dev, "restoring config "
765 "space at offset %#x (was %#x, writing %#x)\n",
766 i, val, (int)dev->saved_config_space[i]);
Dave Jones04d9c1a2006-04-18 21:06:51 -0700767 pci_write_config_dword(dev,i * 4,
768 dev->saved_config_space[i]);
769 }
770 }
Stephen Hemmingercc692a52006-11-08 16:17:15 -0800771 pci_restore_pcix_state(dev);
Shaohua Li41017f02006-02-08 17:11:38 +0800772 pci_restore_msi_state(dev);
Michael Ellerman8fed4b62007-01-25 19:34:08 +1100773
Linus Torvalds1da177e2005-04-16 15:20:36 -0700774 return 0;
775}
776
Hidetoshi Seto38cc1302006-12-18 10:30:00 +0900777static int do_pci_enable_device(struct pci_dev *dev, int bars)
778{
779 int err;
780
781 err = pci_set_power_state(dev, PCI_D0);
782 if (err < 0 && err != -EIO)
783 return err;
784 err = pcibios_enable_device(dev, bars);
785 if (err < 0)
786 return err;
787 pci_fixup_device(pci_fixup_enable, dev);
788
789 return 0;
790}
791
792/**
Tejun Heo0b62e132007-07-27 14:43:35 +0900793 * pci_reenable_device - Resume abandoned device
Hidetoshi Seto38cc1302006-12-18 10:30:00 +0900794 * @dev: PCI device to be resumed
795 *
796 * Note this function is a backend of pci_default_resume and is not supposed
797 * to be called by normal code, write proper resume handler and use it instead.
798 */
Tejun Heo0b62e132007-07-27 14:43:35 +0900799int pci_reenable_device(struct pci_dev *dev)
Hidetoshi Seto38cc1302006-12-18 10:30:00 +0900800{
801 if (atomic_read(&dev->enable_cnt))
802 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1);
803 return 0;
804}
805
Benjamin Herrenschmidtb7189892007-12-20 15:28:08 +1100806static int __pci_enable_device_flags(struct pci_dev *dev,
807 resource_size_t flags)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700808{
809 int err;
Benjamin Herrenschmidtb7189892007-12-20 15:28:08 +1100810 int i, bars = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700811
Hidetoshi Seto9fb625c2006-12-18 10:28:43 +0900812 if (atomic_add_return(1, &dev->enable_cnt) > 1)
813 return 0; /* already enabled */
814
Benjamin Herrenschmidtb7189892007-12-20 15:28:08 +1100815 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
816 if (dev->resource[i].flags & flags)
817 bars |= (1 << i);
818
Hidetoshi Seto38cc1302006-12-18 10:30:00 +0900819 err = do_pci_enable_device(dev, bars);
Greg Kroah-Hartman95a62962005-07-28 11:37:33 -0700820 if (err < 0)
Hidetoshi Seto38cc1302006-12-18 10:30:00 +0900821 atomic_dec(&dev->enable_cnt);
Hidetoshi Seto9fb625c2006-12-18 10:28:43 +0900822 return err;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700823}
824
825/**
Benjamin Herrenschmidtb7189892007-12-20 15:28:08 +1100826 * pci_enable_device_io - Initialize a device for use with IO space
827 * @dev: PCI device to be initialized
828 *
829 * Initialize device before it's used by a driver. Ask low-level code
830 * to enable I/O resources. Wake up the device if it was suspended.
831 * Beware, this function can fail.
832 */
833int pci_enable_device_io(struct pci_dev *dev)
834{
835 return __pci_enable_device_flags(dev, IORESOURCE_IO);
836}
837
838/**
839 * pci_enable_device_mem - Initialize a device for use with Memory space
840 * @dev: PCI device to be initialized
841 *
842 * Initialize device before it's used by a driver. Ask low-level code
843 * to enable Memory resources. Wake up the device if it was suspended.
844 * Beware, this function can fail.
845 */
846int pci_enable_device_mem(struct pci_dev *dev)
847{
848 return __pci_enable_device_flags(dev, IORESOURCE_MEM);
849}
850
Linus Torvalds1da177e2005-04-16 15:20:36 -0700851/**
852 * pci_enable_device - Initialize device before it's used by a driver.
853 * @dev: PCI device to be initialized
854 *
855 * Initialize device before it's used by a driver. Ask low-level code
856 * to enable I/O and memory. Wake up the device if it was suspended.
857 * Beware, this function can fail.
Inaky Perez-Gonzalezbae94d02006-11-22 12:40:31 -0800858 *
859 * Note we don't actually enable the device many times if we call
860 * this function repeatedly (we just increment the count).
Linus Torvalds1da177e2005-04-16 15:20:36 -0700861 */
Inaky Perez-Gonzalezbae94d02006-11-22 12:40:31 -0800862int pci_enable_device(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700863{
Benjamin Herrenschmidtb7189892007-12-20 15:28:08 +1100864 return __pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700865}
866
Tejun Heo9ac78492007-01-20 16:00:26 +0900867/*
868 * Managed PCI resources. This manages device on/off, intx/msi/msix
869 * on/off and BAR regions. pci_dev itself records msi/msix status, so
870 * there's no need to track it separately. pci_devres is initialized
871 * when a device is enabled using managed PCI device enable interface.
872 */
873struct pci_devres {
Tejun Heo7f375f32007-02-25 04:36:01 -0800874 unsigned int enabled:1;
875 unsigned int pinned:1;
Tejun Heo9ac78492007-01-20 16:00:26 +0900876 unsigned int orig_intx:1;
877 unsigned int restore_intx:1;
878 u32 region_mask;
879};
880
881static void pcim_release(struct device *gendev, void *res)
882{
883 struct pci_dev *dev = container_of(gendev, struct pci_dev, dev);
884 struct pci_devres *this = res;
885 int i;
886
887 if (dev->msi_enabled)
888 pci_disable_msi(dev);
889 if (dev->msix_enabled)
890 pci_disable_msix(dev);
891
892 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
893 if (this->region_mask & (1 << i))
894 pci_release_region(dev, i);
895
896 if (this->restore_intx)
897 pci_intx(dev, this->orig_intx);
898
Tejun Heo7f375f32007-02-25 04:36:01 -0800899 if (this->enabled && !this->pinned)
Tejun Heo9ac78492007-01-20 16:00:26 +0900900 pci_disable_device(dev);
901}
902
903static struct pci_devres * get_pci_dr(struct pci_dev *pdev)
904{
905 struct pci_devres *dr, *new_dr;
906
907 dr = devres_find(&pdev->dev, pcim_release, NULL, NULL);
908 if (dr)
909 return dr;
910
911 new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL);
912 if (!new_dr)
913 return NULL;
914 return devres_get(&pdev->dev, new_dr, NULL, NULL);
915}
916
917static struct pci_devres * find_pci_dr(struct pci_dev *pdev)
918{
919 if (pci_is_managed(pdev))
920 return devres_find(&pdev->dev, pcim_release, NULL, NULL);
921 return NULL;
922}
923
924/**
925 * pcim_enable_device - Managed pci_enable_device()
926 * @pdev: PCI device to be initialized
927 *
928 * Managed pci_enable_device().
929 */
930int pcim_enable_device(struct pci_dev *pdev)
931{
932 struct pci_devres *dr;
933 int rc;
934
935 dr = get_pci_dr(pdev);
936 if (unlikely(!dr))
937 return -ENOMEM;
Tejun Heob95d58e2008-01-30 18:20:04 +0900938 if (dr->enabled)
939 return 0;
Tejun Heo9ac78492007-01-20 16:00:26 +0900940
941 rc = pci_enable_device(pdev);
942 if (!rc) {
943 pdev->is_managed = 1;
Tejun Heo7f375f32007-02-25 04:36:01 -0800944 dr->enabled = 1;
Tejun Heo9ac78492007-01-20 16:00:26 +0900945 }
946 return rc;
947}
948
949/**
950 * pcim_pin_device - Pin managed PCI device
951 * @pdev: PCI device to pin
952 *
953 * Pin managed PCI device @pdev. Pinned device won't be disabled on
954 * driver detach. @pdev must have been enabled with
955 * pcim_enable_device().
956 */
957void pcim_pin_device(struct pci_dev *pdev)
958{
959 struct pci_devres *dr;
960
961 dr = find_pci_dr(pdev);
Tejun Heo7f375f32007-02-25 04:36:01 -0800962 WARN_ON(!dr || !dr->enabled);
Tejun Heo9ac78492007-01-20 16:00:26 +0900963 if (dr)
Tejun Heo7f375f32007-02-25 04:36:01 -0800964 dr->pinned = 1;
Tejun Heo9ac78492007-01-20 16:00:26 +0900965}
966
Linus Torvalds1da177e2005-04-16 15:20:36 -0700967/**
968 * pcibios_disable_device - disable arch specific PCI resources for device dev
969 * @dev: the PCI device to disable
970 *
971 * Disables architecture specific PCI resources for the device. This
972 * is the default implementation. Architecture implementations can
973 * override this.
974 */
975void __attribute__ ((weak)) pcibios_disable_device (struct pci_dev *dev) {}
976
977/**
978 * pci_disable_device - Disable PCI device after use
979 * @dev: PCI device to be disabled
980 *
981 * Signal to the system that the PCI device is not in use by the system
982 * anymore. This only involves disabling PCI bus-mastering, if active.
Inaky Perez-Gonzalezbae94d02006-11-22 12:40:31 -0800983 *
984 * Note we don't actually disable the device until all callers of
985 * pci_device_enable() have called pci_device_disable().
Linus Torvalds1da177e2005-04-16 15:20:36 -0700986 */
987void
988pci_disable_device(struct pci_dev *dev)
989{
Tejun Heo9ac78492007-01-20 16:00:26 +0900990 struct pci_devres *dr;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700991 u16 pci_command;
Shaohua Li99dc8042006-05-26 10:58:27 +0800992
Tejun Heo9ac78492007-01-20 16:00:26 +0900993 dr = find_pci_dr(dev);
994 if (dr)
Tejun Heo7f375f32007-02-25 04:36:01 -0800995 dr->enabled = 0;
Tejun Heo9ac78492007-01-20 16:00:26 +0900996
Inaky Perez-Gonzalezbae94d02006-11-22 12:40:31 -0800997 if (atomic_sub_return(1, &dev->enable_cnt) != 0)
998 return;
999
Linus Torvalds1da177e2005-04-16 15:20:36 -07001000 pci_read_config_word(dev, PCI_COMMAND, &pci_command);
1001 if (pci_command & PCI_COMMAND_MASTER) {
1002 pci_command &= ~PCI_COMMAND_MASTER;
1003 pci_write_config_word(dev, PCI_COMMAND, pci_command);
1004 }
Kenji Kaneshigeceb43742005-04-08 14:53:31 +09001005 dev->is_busmaster = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001006
1007 pcibios_disable_device(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001008}
1009
1010/**
Brian Kingf7bdd122007-04-06 16:39:36 -05001011 * pcibios_set_pcie_reset_state - set reset state for device dev
1012 * @dev: the PCI-E device reset
1013 * @state: Reset state to enter into
1014 *
1015 *
1016 * Sets the PCI-E reset state for the device. This is the default
1017 * implementation. Architecture implementations can override this.
1018 */
1019int __attribute__ ((weak)) pcibios_set_pcie_reset_state(struct pci_dev *dev,
1020 enum pcie_reset_state state)
1021{
1022 return -EINVAL;
1023}
1024
1025/**
1026 * pci_set_pcie_reset_state - set reset state for device dev
1027 * @dev: the PCI-E device reset
1028 * @state: Reset state to enter into
1029 *
1030 *
1031 * Sets the PCI reset state for the device.
1032 */
1033int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
1034{
1035 return pcibios_set_pcie_reset_state(dev, state);
1036}
1037
1038/**
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001039 * pci_pme_capable - check the capability of PCI device to generate PME#
1040 * @dev: PCI device to handle.
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001041 * @state: PCI state from which device will issue PME#.
1042 */
Rafael J. Wysocki337001b2008-07-07 03:36:24 +02001043static bool pci_pme_capable(struct pci_dev *dev, pci_power_t state)
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001044{
Rafael J. Wysocki337001b2008-07-07 03:36:24 +02001045 if (!dev->pm_cap)
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001046 return false;
1047
Rafael J. Wysocki337001b2008-07-07 03:36:24 +02001048 return !!(dev->pme_support & (1 << state));
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001049}
1050
1051/**
1052 * pci_pme_active - enable or disable PCI device's PME# function
1053 * @dev: PCI device to handle.
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001054 * @enable: 'true' to enable PME# generation; 'false' to disable it.
1055 *
1056 * The caller must verify that the device is capable of generating PME# before
1057 * calling this function with @enable equal to 'true'.
1058 */
Rafael J. Wysocki337001b2008-07-07 03:36:24 +02001059static void pci_pme_active(struct pci_dev *dev, bool enable)
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001060{
1061 u16 pmcsr;
1062
Rafael J. Wysocki337001b2008-07-07 03:36:24 +02001063 if (!dev->pm_cap)
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001064 return;
1065
Rafael J. Wysocki337001b2008-07-07 03:36:24 +02001066 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001067 /* Clear PME_Status by writing 1 to it and enable PME# */
1068 pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
1069 if (!enable)
1070 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1071
Rafael J. Wysocki337001b2008-07-07 03:36:24 +02001072 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001073
1074 dev_printk(KERN_INFO, &dev->dev, "PME# %s\n",
1075 enable ? "enabled" : "disabled");
1076}
1077
1078/**
David Brownell075c1772007-04-26 00:12:06 -07001079 * pci_enable_wake - enable PCI device as wakeup event source
1080 * @dev: PCI device affected
1081 * @state: PCI state from which device will issue wakeup events
1082 * @enable: True to enable event generation; false to disable
Linus Torvalds1da177e2005-04-16 15:20:36 -07001083 *
David Brownell075c1772007-04-26 00:12:06 -07001084 * This enables the device as a wakeup event source, or disables it.
1085 * When such events involves platform-specific hooks, those hooks are
1086 * called automatically by this routine.
1087 *
1088 * Devices with legacy power management (no standard PCI PM capabilities)
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001089 * always require such platform hooks.
David Brownell075c1772007-04-26 00:12:06 -07001090 *
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001091 * RETURN VALUE:
1092 * 0 is returned on success
1093 * -EINVAL is returned if device is not supposed to wake up the system
1094 * Error code depending on the platform is returned if both the platform and
1095 * the native mechanism fail to enable the generation of wake-up events
Linus Torvalds1da177e2005-04-16 15:20:36 -07001096 */
1097int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable)
1098{
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001099 int error = 0;
1100 bool pme_done = false;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001101
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001102 if (!device_may_wakeup(&dev->dev))
1103 return -EINVAL;
1104
1105 /*
1106 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
1107 * Anderson we should be doing PME# wake enable followed by ACPI wake
1108 * enable. To disable wake-up we call the platform first, for symmetry.
David Brownell075c1772007-04-26 00:12:06 -07001109 */
1110
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001111 if (!enable && platform_pci_can_wakeup(dev))
1112 error = platform_pci_sleep_wake(dev, false);
1113
Rafael J. Wysocki337001b2008-07-07 03:36:24 +02001114 if (!enable || pci_pme_capable(dev, state)) {
1115 pci_pme_active(dev, enable);
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001116 pme_done = true;
1117 }
1118
1119 if (enable && platform_pci_can_wakeup(dev))
1120 error = platform_pci_sleep_wake(dev, true);
1121
1122 return pme_done ? 0 : error;
1123}
1124
1125/**
Randy Dunlap443bd1c2008-07-21 09:27:18 -07001126 * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state
Rafael J. Wysocki404cc2d2008-07-07 03:35:26 +02001127 * @dev: Device to handle.
1128 *
1129 * Choose the power state appropriate for the device depending on whether
1130 * it can wake up the system and/or is power manageable by the platform
1131 * (PCI_D3hot is the default) and put the device into that state.
1132 */
1133int pci_prepare_to_sleep(struct pci_dev *dev)
1134{
1135 pci_power_t target_state = PCI_D3hot;
Rafael J. Wysocki404cc2d2008-07-07 03:35:26 +02001136 int error;
1137
1138 if (platform_pci_power_manageable(dev)) {
1139 /*
1140 * Call the platform to choose the target state of the device
1141 * and enable wake-up from this state if supported.
1142 */
1143 pci_power_t state = platform_pci_choose_state(dev);
1144
1145 switch (state) {
1146 case PCI_POWER_ERROR:
1147 case PCI_UNKNOWN:
1148 break;
1149 case PCI_D1:
1150 case PCI_D2:
1151 if (pci_no_d1d2(dev))
1152 break;
1153 default:
1154 target_state = state;
Rafael J. Wysocki404cc2d2008-07-07 03:35:26 +02001155 }
1156 } else if (device_may_wakeup(&dev->dev)) {
1157 /*
1158 * Find the deepest state from which the device can generate
1159 * wake-up events, make it the target state and enable device
1160 * to generate PME#.
1161 */
Rafael J. Wysocki337001b2008-07-07 03:36:24 +02001162 if (!dev->pm_cap)
Rafael J. Wysocki404cc2d2008-07-07 03:35:26 +02001163 return -EIO;
1164
Rafael J. Wysocki337001b2008-07-07 03:36:24 +02001165 if (dev->pme_support) {
1166 while (target_state
1167 && !(dev->pme_support & (1 << target_state)))
1168 target_state--;
Rafael J. Wysocki404cc2d2008-07-07 03:35:26 +02001169 }
1170 }
1171
Rafael J. Wysockic157dfa2008-07-13 22:45:06 +02001172 pci_enable_wake(dev, target_state, true);
1173
Rafael J. Wysocki404cc2d2008-07-07 03:35:26 +02001174 error = pci_set_power_state(dev, target_state);
1175
1176 if (error)
1177 pci_enable_wake(dev, target_state, false);
1178
1179 return error;
1180}
1181
1182/**
Randy Dunlap443bd1c2008-07-21 09:27:18 -07001183 * pci_back_from_sleep - turn PCI device on during system-wide transition into working state
Rafael J. Wysocki404cc2d2008-07-07 03:35:26 +02001184 * @dev: Device to handle.
1185 *
1186 * Disable device's sytem wake-up capability and put it into D0.
1187 */
1188int pci_back_from_sleep(struct pci_dev *dev)
1189{
1190 pci_enable_wake(dev, PCI_D0, false);
1191 return pci_set_power_state(dev, PCI_D0);
1192}
1193
1194/**
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001195 * pci_pm_init - Initialize PM functions of given PCI device
1196 * @dev: PCI device to handle.
1197 */
1198void pci_pm_init(struct pci_dev *dev)
1199{
1200 int pm;
1201 u16 pmc;
David Brownell075c1772007-04-26 00:12:06 -07001202
Rafael J. Wysocki337001b2008-07-07 03:36:24 +02001203 dev->pm_cap = 0;
1204
Linus Torvalds1da177e2005-04-16 15:20:36 -07001205 /* find PCI PM capability in list */
1206 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
David Brownell075c1772007-04-26 00:12:06 -07001207 if (!pm)
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001208 return;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001209 /* Check device's ability to generate PME# */
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001210 pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001211
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001212 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
1213 dev_err(&dev->dev, "unsupported PM cap regs version (%u)\n",
1214 pmc & PCI_PM_CAP_VER_MASK);
1215 return;
David Brownell075c1772007-04-26 00:12:06 -07001216 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001217
Rafael J. Wysocki337001b2008-07-07 03:36:24 +02001218 dev->pm_cap = pm;
1219
1220 dev->d1_support = false;
1221 dev->d2_support = false;
1222 if (!pci_no_d1d2(dev)) {
1223 if (pmc & PCI_PM_CAP_D1) {
1224 dev_printk(KERN_DEBUG, &dev->dev, "supports D1\n");
1225 dev->d1_support = true;
1226 }
1227 if (pmc & PCI_PM_CAP_D2) {
1228 dev_printk(KERN_DEBUG, &dev->dev, "supports D2\n");
1229 dev->d2_support = true;
1230 }
1231 }
1232
1233 pmc &= PCI_PM_CAP_PME_MASK;
1234 if (pmc) {
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001235 dev_printk(KERN_INFO, &dev->dev,
1236 "PME# supported from%s%s%s%s%s\n",
1237 (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "",
1238 (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "",
1239 (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "",
1240 (pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "",
1241 (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : "");
Rafael J. Wysocki337001b2008-07-07 03:36:24 +02001242 dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT;
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001243 /*
1244 * Make device's PM flags reflect the wake-up capability, but
1245 * let the user space enable it to wake up the system as needed.
1246 */
1247 device_set_wakeup_capable(&dev->dev, true);
1248 device_set_wakeup_enable(&dev->dev, false);
1249 /* Disable the PME# generation functionality */
Rafael J. Wysocki337001b2008-07-07 03:36:24 +02001250 pci_pme_active(dev, false);
1251 } else {
1252 dev->pme_support = 0;
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001253 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001254}
1255
1256int
1257pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
1258{
1259 u8 pin;
1260
Kristen Accardi514d2072005-11-02 16:24:39 -08001261 pin = dev->pin;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001262 if (!pin)
1263 return -1;
1264 pin--;
1265 while (dev->bus->self) {
1266 pin = (pin + PCI_SLOT(dev->devfn)) % 4;
1267 dev = dev->bus->self;
1268 }
1269 *bridge = dev;
1270 return pin;
1271}
1272
1273/**
1274 * pci_release_region - Release a PCI bar
1275 * @pdev: PCI device whose resources were previously reserved by pci_request_region
1276 * @bar: BAR to release
1277 *
1278 * Releases the PCI I/O and memory resources previously reserved by a
1279 * successful call to pci_request_region. Call this function only
1280 * after all use of the PCI regions has ceased.
1281 */
1282void pci_release_region(struct pci_dev *pdev, int bar)
1283{
Tejun Heo9ac78492007-01-20 16:00:26 +09001284 struct pci_devres *dr;
1285
Linus Torvalds1da177e2005-04-16 15:20:36 -07001286 if (pci_resource_len(pdev, bar) == 0)
1287 return;
1288 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
1289 release_region(pci_resource_start(pdev, bar),
1290 pci_resource_len(pdev, bar));
1291 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
1292 release_mem_region(pci_resource_start(pdev, bar),
1293 pci_resource_len(pdev, bar));
Tejun Heo9ac78492007-01-20 16:00:26 +09001294
1295 dr = find_pci_dr(pdev);
1296 if (dr)
1297 dr->region_mask &= ~(1 << bar);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001298}
1299
1300/**
1301 * pci_request_region - Reserved PCI I/O and memory resource
1302 * @pdev: PCI device whose resources are to be reserved
1303 * @bar: BAR to be reserved
1304 * @res_name: Name to be associated with resource.
1305 *
1306 * Mark the PCI region associated with PCI device @pdev BR @bar as
1307 * being reserved by owner @res_name. Do not access any
1308 * address inside the PCI regions unless this call returns
1309 * successfully.
1310 *
1311 * Returns 0 on success, or %EBUSY on error. A warning
1312 * message is also printed on failure.
1313 */
Jeff Garzik3c990e92006-03-04 21:52:42 -05001314int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001315{
Tejun Heo9ac78492007-01-20 16:00:26 +09001316 struct pci_devres *dr;
1317
Linus Torvalds1da177e2005-04-16 15:20:36 -07001318 if (pci_resource_len(pdev, bar) == 0)
1319 return 0;
1320
1321 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
1322 if (!request_region(pci_resource_start(pdev, bar),
1323 pci_resource_len(pdev, bar), res_name))
1324 goto err_out;
1325 }
1326 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
1327 if (!request_mem_region(pci_resource_start(pdev, bar),
1328 pci_resource_len(pdev, bar), res_name))
1329 goto err_out;
1330 }
Tejun Heo9ac78492007-01-20 16:00:26 +09001331
1332 dr = find_pci_dr(pdev);
1333 if (dr)
1334 dr->region_mask |= 1 << bar;
1335
Linus Torvalds1da177e2005-04-16 15:20:36 -07001336 return 0;
1337
1338err_out:
Bjorn Helgaas80ccba12008-06-13 10:52:11 -06001339 dev_warn(&pdev->dev, "BAR %d: can't reserve %s region [%#llx-%#llx]\n",
Jesse Barnese4ec7a02008-06-25 16:12:25 -07001340 bar,
1341 pci_resource_flags(pdev, bar) & IORESOURCE_IO ? "I/O" : "mem",
1342 (unsigned long long)pci_resource_start(pdev, bar),
1343 (unsigned long long)pci_resource_end(pdev, bar));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001344 return -EBUSY;
1345}
1346
Hidetoshi Setoc87deff2006-12-18 10:31:06 +09001347/**
1348 * pci_release_selected_regions - Release selected PCI I/O and memory resources
1349 * @pdev: PCI device whose resources were previously reserved
1350 * @bars: Bitmask of BARs to be released
1351 *
1352 * Release selected PCI I/O and memory resources previously reserved.
1353 * Call this function only after all use of the PCI regions has ceased.
1354 */
1355void pci_release_selected_regions(struct pci_dev *pdev, int bars)
1356{
1357 int i;
1358
1359 for (i = 0; i < 6; i++)
1360 if (bars & (1 << i))
1361 pci_release_region(pdev, i);
1362}
1363
1364/**
1365 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
1366 * @pdev: PCI device whose resources are to be reserved
1367 * @bars: Bitmask of BARs to be requested
1368 * @res_name: Name to be associated with resource
1369 */
1370int pci_request_selected_regions(struct pci_dev *pdev, int bars,
1371 const char *res_name)
1372{
1373 int i;
1374
1375 for (i = 0; i < 6; i++)
1376 if (bars & (1 << i))
1377 if(pci_request_region(pdev, i, res_name))
1378 goto err_out;
1379 return 0;
1380
1381err_out:
1382 while(--i >= 0)
1383 if (bars & (1 << i))
1384 pci_release_region(pdev, i);
1385
1386 return -EBUSY;
1387}
Linus Torvalds1da177e2005-04-16 15:20:36 -07001388
1389/**
1390 * pci_release_regions - Release reserved PCI I/O and memory resources
1391 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
1392 *
1393 * Releases all PCI I/O and memory resources previously reserved by a
1394 * successful call to pci_request_regions. Call this function only
1395 * after all use of the PCI regions has ceased.
1396 */
1397
1398void pci_release_regions(struct pci_dev *pdev)
1399{
Hidetoshi Setoc87deff2006-12-18 10:31:06 +09001400 pci_release_selected_regions(pdev, (1 << 6) - 1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001401}
1402
1403/**
1404 * pci_request_regions - Reserved PCI I/O and memory resources
1405 * @pdev: PCI device whose resources are to be reserved
1406 * @res_name: Name to be associated with resource.
1407 *
1408 * Mark all PCI regions associated with PCI device @pdev as
1409 * being reserved by owner @res_name. Do not access any
1410 * address inside the PCI regions unless this call returns
1411 * successfully.
1412 *
1413 * Returns 0 on success, or %EBUSY on error. A warning
1414 * message is also printed on failure.
1415 */
Jeff Garzik3c990e92006-03-04 21:52:42 -05001416int pci_request_regions(struct pci_dev *pdev, const char *res_name)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001417{
Hidetoshi Setoc87deff2006-12-18 10:31:06 +09001418 return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001419}
1420
1421/**
1422 * pci_set_master - enables bus-mastering for device dev
1423 * @dev: the PCI device to enable
1424 *
1425 * Enables bus-mastering on the device and calls pcibios_set_master()
1426 * to do the needed arch specific settings.
1427 */
1428void
1429pci_set_master(struct pci_dev *dev)
1430{
1431 u16 cmd;
1432
1433 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1434 if (! (cmd & PCI_COMMAND_MASTER)) {
Bjorn Helgaas80ccba12008-06-13 10:52:11 -06001435 dev_dbg(&dev->dev, "enabling bus mastering\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001436 cmd |= PCI_COMMAND_MASTER;
1437 pci_write_config_word(dev, PCI_COMMAND, cmd);
1438 }
1439 dev->is_busmaster = 1;
1440 pcibios_set_master(dev);
1441}
1442
Matthew Wilcoxedb2d972006-10-10 08:01:21 -06001443#ifdef PCI_DISABLE_MWI
1444int pci_set_mwi(struct pci_dev *dev)
1445{
1446 return 0;
1447}
1448
Randy Dunlap694625c2007-07-09 11:55:54 -07001449int pci_try_set_mwi(struct pci_dev *dev)
1450{
1451 return 0;
1452}
1453
Matthew Wilcoxedb2d972006-10-10 08:01:21 -06001454void pci_clear_mwi(struct pci_dev *dev)
1455{
1456}
1457
1458#else
Matthew Wilcoxebf5a242006-10-10 08:01:20 -06001459
1460#ifndef PCI_CACHE_LINE_BYTES
1461#define PCI_CACHE_LINE_BYTES L1_CACHE_BYTES
1462#endif
1463
Linus Torvalds1da177e2005-04-16 15:20:36 -07001464/* This can be overridden by arch code. */
Matthew Wilcoxebf5a242006-10-10 08:01:20 -06001465/* Don't forget this is measured in 32-bit words, not bytes */
1466u8 pci_cache_line_size = PCI_CACHE_LINE_BYTES / 4;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001467
1468/**
Matthew Wilcoxedb2d972006-10-10 08:01:21 -06001469 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
1470 * @dev: the PCI device for which MWI is to be enabled
Linus Torvalds1da177e2005-04-16 15:20:36 -07001471 *
Matthew Wilcoxedb2d972006-10-10 08:01:21 -06001472 * Helper function for pci_set_mwi.
1473 * Originally copied from drivers/net/acenic.c.
Linus Torvalds1da177e2005-04-16 15:20:36 -07001474 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
1475 *
1476 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
1477 */
1478static int
Matthew Wilcoxedb2d972006-10-10 08:01:21 -06001479pci_set_cacheline_size(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001480{
1481 u8 cacheline_size;
1482
1483 if (!pci_cache_line_size)
1484 return -EINVAL; /* The system doesn't support MWI. */
1485
1486 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
1487 equal to or multiple of the right value. */
1488 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
1489 if (cacheline_size >= pci_cache_line_size &&
1490 (cacheline_size % pci_cache_line_size) == 0)
1491 return 0;
1492
1493 /* Write the correct value. */
1494 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
1495 /* Read it back. */
1496 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
1497 if (cacheline_size == pci_cache_line_size)
1498 return 0;
1499
Bjorn Helgaas80ccba12008-06-13 10:52:11 -06001500 dev_printk(KERN_DEBUG, &dev->dev, "cache line size of %d is not "
1501 "supported\n", pci_cache_line_size << 2);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001502
1503 return -EINVAL;
1504}
Linus Torvalds1da177e2005-04-16 15:20:36 -07001505
1506/**
1507 * pci_set_mwi - enables memory-write-invalidate PCI transaction
1508 * @dev: the PCI device for which MWI is enabled
1509 *
Randy Dunlap694625c2007-07-09 11:55:54 -07001510 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
Linus Torvalds1da177e2005-04-16 15:20:36 -07001511 *
1512 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
1513 */
1514int
1515pci_set_mwi(struct pci_dev *dev)
1516{
1517 int rc;
1518 u16 cmd;
1519
Matthew Wilcoxedb2d972006-10-10 08:01:21 -06001520 rc = pci_set_cacheline_size(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001521 if (rc)
1522 return rc;
1523
1524 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1525 if (! (cmd & PCI_COMMAND_INVALIDATE)) {
Bjorn Helgaas80ccba12008-06-13 10:52:11 -06001526 dev_dbg(&dev->dev, "enabling Mem-Wr-Inval\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001527 cmd |= PCI_COMMAND_INVALIDATE;
1528 pci_write_config_word(dev, PCI_COMMAND, cmd);
1529 }
1530
1531 return 0;
1532}
1533
1534/**
Randy Dunlap694625c2007-07-09 11:55:54 -07001535 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
1536 * @dev: the PCI device for which MWI is enabled
1537 *
1538 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
1539 * Callers are not required to check the return value.
1540 *
1541 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
1542 */
1543int pci_try_set_mwi(struct pci_dev *dev)
1544{
1545 int rc = pci_set_mwi(dev);
1546 return rc;
1547}
1548
1549/**
Linus Torvalds1da177e2005-04-16 15:20:36 -07001550 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
1551 * @dev: the PCI device to disable
1552 *
1553 * Disables PCI Memory-Write-Invalidate transaction on the device
1554 */
1555void
1556pci_clear_mwi(struct pci_dev *dev)
1557{
1558 u16 cmd;
1559
1560 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1561 if (cmd & PCI_COMMAND_INVALIDATE) {
1562 cmd &= ~PCI_COMMAND_INVALIDATE;
1563 pci_write_config_word(dev, PCI_COMMAND, cmd);
1564 }
1565}
Matthew Wilcoxedb2d972006-10-10 08:01:21 -06001566#endif /* ! PCI_DISABLE_MWI */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001567
Brett M Russa04ce0f2005-08-15 15:23:41 -04001568/**
1569 * pci_intx - enables/disables PCI INTx for device dev
Randy Dunlap8f7020d2005-10-23 11:57:38 -07001570 * @pdev: the PCI device to operate on
1571 * @enable: boolean: whether to enable or disable PCI INTx
Brett M Russa04ce0f2005-08-15 15:23:41 -04001572 *
1573 * Enables/disables PCI INTx for device dev
1574 */
1575void
1576pci_intx(struct pci_dev *pdev, int enable)
1577{
1578 u16 pci_command, new;
1579
1580 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
1581
1582 if (enable) {
1583 new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
1584 } else {
1585 new = pci_command | PCI_COMMAND_INTX_DISABLE;
1586 }
1587
1588 if (new != pci_command) {
Tejun Heo9ac78492007-01-20 16:00:26 +09001589 struct pci_devres *dr;
1590
Brett M Russ2fd9d742005-09-09 10:02:22 -07001591 pci_write_config_word(pdev, PCI_COMMAND, new);
Tejun Heo9ac78492007-01-20 16:00:26 +09001592
1593 dr = find_pci_dr(pdev);
1594 if (dr && !dr->restore_intx) {
1595 dr->restore_intx = 1;
1596 dr->orig_intx = !enable;
1597 }
Brett M Russa04ce0f2005-08-15 15:23:41 -04001598 }
1599}
1600
Eric W. Biedermanf5f2b132007-03-05 00:30:07 -08001601/**
1602 * pci_msi_off - disables any msi or msix capabilities
Randy Dunlap8d7d86e2007-03-16 19:55:52 -07001603 * @dev: the PCI device to operate on
Eric W. Biedermanf5f2b132007-03-05 00:30:07 -08001604 *
1605 * If you want to use msi see pci_enable_msi and friends.
1606 * This is a lower level primitive that allows us to disable
1607 * msi operation at the device level.
1608 */
1609void pci_msi_off(struct pci_dev *dev)
1610{
1611 int pos;
1612 u16 control;
1613
1614 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
1615 if (pos) {
1616 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control);
1617 control &= ~PCI_MSI_FLAGS_ENABLE;
1618 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);
1619 }
1620 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
1621 if (pos) {
1622 pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control);
1623 control &= ~PCI_MSIX_FLAGS_ENABLE;
1624 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
1625 }
1626}
1627
Linus Torvalds1da177e2005-04-16 15:20:36 -07001628#ifndef HAVE_ARCH_PCI_SET_DMA_MASK
1629/*
1630 * These can be overridden by arch-specific implementations
1631 */
1632int
1633pci_set_dma_mask(struct pci_dev *dev, u64 mask)
1634{
1635 if (!pci_dma_supported(dev, mask))
1636 return -EIO;
1637
1638 dev->dma_mask = mask;
1639
1640 return 0;
1641}
1642
1643int
Linus Torvalds1da177e2005-04-16 15:20:36 -07001644pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
1645{
1646 if (!pci_dma_supported(dev, mask))
1647 return -EIO;
1648
1649 dev->dev.coherent_dma_mask = mask;
1650
1651 return 0;
1652}
1653#endif
Hidetoshi Setoc87deff2006-12-18 10:31:06 +09001654
FUJITA Tomonori4d57cdf2008-02-04 22:27:55 -08001655#ifndef HAVE_ARCH_PCI_SET_DMA_MAX_SEGMENT_SIZE
1656int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size)
1657{
1658 return dma_set_max_seg_size(&dev->dev, size);
1659}
1660EXPORT_SYMBOL(pci_set_dma_max_seg_size);
1661#endif
1662
FUJITA Tomonori59fc67d2008-02-04 22:28:14 -08001663#ifndef HAVE_ARCH_PCI_SET_DMA_SEGMENT_BOUNDARY
1664int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask)
1665{
1666 return dma_set_seg_boundary(&dev->dev, mask);
1667}
1668EXPORT_SYMBOL(pci_set_dma_seg_boundary);
1669#endif
1670
Hidetoshi Setoc87deff2006-12-18 10:31:06 +09001671/**
Peter Orubad556ad42007-05-15 13:59:13 +02001672 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
1673 * @dev: PCI device to query
1674 *
1675 * Returns mmrbc: maximum designed memory read count in bytes
1676 * or appropriate error value.
1677 */
1678int pcix_get_max_mmrbc(struct pci_dev *dev)
1679{
Andrew Mortonb7b095c2007-07-09 11:55:50 -07001680 int err, cap;
Peter Orubad556ad42007-05-15 13:59:13 +02001681 u32 stat;
1682
1683 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1684 if (!cap)
1685 return -EINVAL;
1686
1687 err = pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat);
1688 if (err)
1689 return -EINVAL;
1690
Andrew Mortonb7b095c2007-07-09 11:55:50 -07001691 return (stat & PCI_X_STATUS_MAX_READ) >> 12;
Peter Orubad556ad42007-05-15 13:59:13 +02001692}
1693EXPORT_SYMBOL(pcix_get_max_mmrbc);
1694
1695/**
1696 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
1697 * @dev: PCI device to query
1698 *
1699 * Returns mmrbc: maximum memory read count in bytes
1700 * or appropriate error value.
1701 */
1702int pcix_get_mmrbc(struct pci_dev *dev)
1703{
1704 int ret, cap;
1705 u32 cmd;
1706
1707 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1708 if (!cap)
1709 return -EINVAL;
1710
1711 ret = pci_read_config_dword(dev, cap + PCI_X_CMD, &cmd);
1712 if (!ret)
1713 ret = 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2);
1714
1715 return ret;
1716}
1717EXPORT_SYMBOL(pcix_get_mmrbc);
1718
1719/**
1720 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
1721 * @dev: PCI device to query
1722 * @mmrbc: maximum memory read count in bytes
1723 * valid values are 512, 1024, 2048, 4096
1724 *
1725 * If possible sets maximum memory read byte count, some bridges have erratas
1726 * that prevent this.
1727 */
1728int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
1729{
1730 int cap, err = -EINVAL;
1731 u32 stat, cmd, v, o;
1732
vignesh babu229f5af2007-08-13 18:23:14 +05301733 if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc))
Peter Orubad556ad42007-05-15 13:59:13 +02001734 goto out;
1735
1736 v = ffs(mmrbc) - 10;
1737
1738 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1739 if (!cap)
1740 goto out;
1741
1742 err = pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat);
1743 if (err)
1744 goto out;
1745
1746 if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21)
1747 return -E2BIG;
1748
1749 err = pci_read_config_dword(dev, cap + PCI_X_CMD, &cmd);
1750 if (err)
1751 goto out;
1752
1753 o = (cmd & PCI_X_CMD_MAX_READ) >> 2;
1754 if (o != v) {
1755 if (v > o && dev->bus &&
1756 (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
1757 return -EIO;
1758
1759 cmd &= ~PCI_X_CMD_MAX_READ;
1760 cmd |= v << 2;
1761 err = pci_write_config_dword(dev, cap + PCI_X_CMD, cmd);
1762 }
1763out:
1764 return err;
1765}
1766EXPORT_SYMBOL(pcix_set_mmrbc);
1767
1768/**
1769 * pcie_get_readrq - get PCI Express read request size
1770 * @dev: PCI device to query
1771 *
1772 * Returns maximum memory read request in bytes
1773 * or appropriate error value.
1774 */
1775int pcie_get_readrq(struct pci_dev *dev)
1776{
1777 int ret, cap;
1778 u16 ctl;
1779
1780 cap = pci_find_capability(dev, PCI_CAP_ID_EXP);
1781 if (!cap)
1782 return -EINVAL;
1783
1784 ret = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
1785 if (!ret)
1786 ret = 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
1787
1788 return ret;
1789}
1790EXPORT_SYMBOL(pcie_get_readrq);
1791
1792/**
1793 * pcie_set_readrq - set PCI Express maximum memory read request
1794 * @dev: PCI device to query
Randy Dunlap42e61f42007-07-23 21:42:11 -07001795 * @rq: maximum memory read count in bytes
Peter Orubad556ad42007-05-15 13:59:13 +02001796 * valid values are 128, 256, 512, 1024, 2048, 4096
1797 *
1798 * If possible sets maximum read byte count
1799 */
1800int pcie_set_readrq(struct pci_dev *dev, int rq)
1801{
1802 int cap, err = -EINVAL;
1803 u16 ctl, v;
1804
vignesh babu229f5af2007-08-13 18:23:14 +05301805 if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
Peter Orubad556ad42007-05-15 13:59:13 +02001806 goto out;
1807
1808 v = (ffs(rq) - 8) << 12;
1809
1810 cap = pci_find_capability(dev, PCI_CAP_ID_EXP);
1811 if (!cap)
1812 goto out;
1813
1814 err = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
1815 if (err)
1816 goto out;
1817
1818 if ((ctl & PCI_EXP_DEVCTL_READRQ) != v) {
1819 ctl &= ~PCI_EXP_DEVCTL_READRQ;
1820 ctl |= v;
1821 err = pci_write_config_dword(dev, cap + PCI_EXP_DEVCTL, ctl);
1822 }
1823
1824out:
1825 return err;
1826}
1827EXPORT_SYMBOL(pcie_set_readrq);
1828
1829/**
Hidetoshi Setoc87deff2006-12-18 10:31:06 +09001830 * pci_select_bars - Make BAR mask from the type of resource
Randy Dunlapf95d8822007-02-10 14:41:56 -08001831 * @dev: the PCI device for which BAR mask is made
Hidetoshi Setoc87deff2006-12-18 10:31:06 +09001832 * @flags: resource type mask to be selected
1833 *
1834 * This helper routine makes bar mask from the type of resource.
1835 */
1836int pci_select_bars(struct pci_dev *dev, unsigned long flags)
1837{
1838 int i, bars = 0;
1839 for (i = 0; i < PCI_NUM_RESOURCES; i++)
1840 if (pci_resource_flags(dev, i) & flags)
1841 bars |= (1 << i);
1842 return bars;
1843}
1844
Jeff Garzik32a2eea2007-10-11 16:57:27 -04001845static void __devinit pci_no_domains(void)
1846{
1847#ifdef CONFIG_PCI_DOMAINS
1848 pci_domains_supported = 0;
1849#endif
1850}
1851
Linus Torvalds1da177e2005-04-16 15:20:36 -07001852static int __devinit pci_init(void)
1853{
1854 struct pci_dev *dev = NULL;
1855
1856 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
1857 pci_fixup_device(pci_fixup_final, dev);
1858 }
1859 return 0;
1860}
1861
1862static int __devinit pci_setup(char *str)
1863{
1864 while (str) {
1865 char *k = strchr(str, ',');
1866 if (k)
1867 *k++ = 0;
1868 if (*str && (str = pcibios_setup(str)) && *str) {
Matthew Wilcox309e57d2006-03-05 22:33:34 -07001869 if (!strcmp(str, "nomsi")) {
1870 pci_no_msi();
Randy Dunlap7f785762007-10-05 13:17:58 -07001871 } else if (!strcmp(str, "noaer")) {
1872 pci_no_aer();
Jeff Garzik32a2eea2007-10-11 16:57:27 -04001873 } else if (!strcmp(str, "nodomains")) {
1874 pci_no_domains();
Atsushi Nemoto4516a612007-02-05 16:36:06 -08001875 } else if (!strncmp(str, "cbiosize=", 9)) {
1876 pci_cardbus_io_size = memparse(str + 9, &str);
1877 } else if (!strncmp(str, "cbmemsize=", 10)) {
1878 pci_cardbus_mem_size = memparse(str + 10, &str);
Matthew Wilcox309e57d2006-03-05 22:33:34 -07001879 } else {
1880 printk(KERN_ERR "PCI: Unknown option `%s'\n",
1881 str);
1882 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001883 }
1884 str = k;
1885 }
Andi Kleen0637a702006-09-26 10:52:41 +02001886 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001887}
Andi Kleen0637a702006-09-26 10:52:41 +02001888early_param("pci", pci_setup);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001889
1890device_initcall(pci_init);
1891
Tejun Heo0b62e132007-07-27 14:43:35 +09001892EXPORT_SYMBOL(pci_reenable_device);
Benjamin Herrenschmidtb7189892007-12-20 15:28:08 +11001893EXPORT_SYMBOL(pci_enable_device_io);
1894EXPORT_SYMBOL(pci_enable_device_mem);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001895EXPORT_SYMBOL(pci_enable_device);
Tejun Heo9ac78492007-01-20 16:00:26 +09001896EXPORT_SYMBOL(pcim_enable_device);
1897EXPORT_SYMBOL(pcim_pin_device);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001898EXPORT_SYMBOL(pci_disable_device);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001899EXPORT_SYMBOL(pci_find_capability);
1900EXPORT_SYMBOL(pci_bus_find_capability);
1901EXPORT_SYMBOL(pci_release_regions);
1902EXPORT_SYMBOL(pci_request_regions);
1903EXPORT_SYMBOL(pci_release_region);
1904EXPORT_SYMBOL(pci_request_region);
Hidetoshi Setoc87deff2006-12-18 10:31:06 +09001905EXPORT_SYMBOL(pci_release_selected_regions);
1906EXPORT_SYMBOL(pci_request_selected_regions);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001907EXPORT_SYMBOL(pci_set_master);
1908EXPORT_SYMBOL(pci_set_mwi);
Randy Dunlap694625c2007-07-09 11:55:54 -07001909EXPORT_SYMBOL(pci_try_set_mwi);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001910EXPORT_SYMBOL(pci_clear_mwi);
Brett M Russa04ce0f2005-08-15 15:23:41 -04001911EXPORT_SYMBOL_GPL(pci_intx);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001912EXPORT_SYMBOL(pci_set_dma_mask);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001913EXPORT_SYMBOL(pci_set_consistent_dma_mask);
1914EXPORT_SYMBOL(pci_assign_resource);
1915EXPORT_SYMBOL(pci_find_parent_resource);
Hidetoshi Setoc87deff2006-12-18 10:31:06 +09001916EXPORT_SYMBOL(pci_select_bars);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001917
1918EXPORT_SYMBOL(pci_set_power_state);
1919EXPORT_SYMBOL(pci_save_state);
1920EXPORT_SYMBOL(pci_restore_state);
1921EXPORT_SYMBOL(pci_enable_wake);
Rafael J. Wysocki404cc2d2008-07-07 03:35:26 +02001922EXPORT_SYMBOL(pci_prepare_to_sleep);
1923EXPORT_SYMBOL(pci_back_from_sleep);
Brian Kingf7bdd122007-04-06 16:39:36 -05001924EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001925