blob: 4b8d0b3f7d2b1f38fb30fd1b9118916b23123b62 [file] [log] [blame]
Ben Skeggs4b223ee2010-08-03 10:00:56 +10001/*
2 * Copyright 2010 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
Ben Skeggs966a5b72010-11-24 10:49:02 +100025#include <linux/firmware.h>
26
Ben Skeggs4b223ee2010-08-03 10:00:56 +100027#include "drmP.h"
28
29#include "nouveau_drv.h"
Ben Skeggs966a5b72010-11-24 10:49:02 +100030#include "nouveau_mm.h"
Ben Skeggs0411de82011-05-25 18:32:44 +100031
Ben Skeggs966a5b72010-11-24 10:49:02 +100032#include "nvc0_graph.h"
Ben Skeggs0411de82011-05-25 18:32:44 +100033#include "nvc0_grhub.fuc.h"
34#include "nvc0_grgpc.fuc.h"
35
36static void
37nvc0_graph_ctxctl_debug_unit(struct drm_device *dev, u32 base)
38{
39 NV_INFO(dev, "PGRAPH: %06x - done 0x%08x\n", base,
40 nv_rd32(dev, base + 0x400));
41 NV_INFO(dev, "PGRAPH: %06x - stat 0x%08x 0x%08x 0x%08x 0x%08x\n", base,
42 nv_rd32(dev, base + 0x800), nv_rd32(dev, base + 0x804),
43 nv_rd32(dev, base + 0x808), nv_rd32(dev, base + 0x80c));
44 NV_INFO(dev, "PGRAPH: %06x - stat 0x%08x 0x%08x 0x%08x 0x%08x\n", base,
45 nv_rd32(dev, base + 0x810), nv_rd32(dev, base + 0x814),
46 nv_rd32(dev, base + 0x818), nv_rd32(dev, base + 0x81c));
47}
48
49static void
50nvc0_graph_ctxctl_debug(struct drm_device *dev)
51{
52 u32 gpcnr = nv_rd32(dev, 0x409604) & 0xffff;
53 u32 gpc;
54
55 nvc0_graph_ctxctl_debug_unit(dev, 0x409000);
56 for (gpc = 0; gpc < gpcnr; gpc++)
57 nvc0_graph_ctxctl_debug_unit(dev, 0x502000 + (gpc * 0x8000));
58}
Ben Skeggs966a5b72010-11-24 10:49:02 +100059
Ben Skeggs966a5b72010-11-24 10:49:02 +100060static int
Ben Skeggs7a45cd12011-04-01 10:59:53 +100061nvc0_graph_load_context(struct nouveau_channel *chan)
62{
63 struct drm_device *dev = chan->dev;
64
65 nv_wr32(dev, 0x409840, 0x00000030);
66 nv_wr32(dev, 0x409500, 0x80000000 | chan->ramin->vinst >> 12);
67 nv_wr32(dev, 0x409504, 0x00000003);
68 if (!nv_wait(dev, 0x409800, 0x00000010, 0x00000010))
69 NV_ERROR(dev, "PGRAPH: load_ctx timeout\n");
70
71 return 0;
72}
73
74static int
75nvc0_graph_unload_context_to(struct drm_device *dev, u64 chan)
76{
77 nv_wr32(dev, 0x409840, 0x00000003);
78 nv_wr32(dev, 0x409500, 0x80000000 | chan >> 12);
79 nv_wr32(dev, 0x409504, 0x00000009);
80 if (!nv_wait(dev, 0x409800, 0x00000001, 0x00000000)) {
81 NV_ERROR(dev, "PGRAPH: unload_ctx timeout\n");
82 return -EBUSY;
83 }
84
85 return 0;
86}
87
88static int
Ben Skeggs966a5b72010-11-24 10:49:02 +100089nvc0_graph_construct_context(struct nouveau_channel *chan)
90{
91 struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
Ben Skeggs7a45cd12011-04-01 10:59:53 +100092 struct nvc0_graph_priv *priv = nv_engine(chan->dev, NVOBJ_ENGINE_GR);
93 struct nvc0_graph_chan *grch = chan->engctx[NVOBJ_ENGINE_GR];
Ben Skeggs966a5b72010-11-24 10:49:02 +100094 struct drm_device *dev = chan->dev;
95 int ret, i;
96 u32 *ctx;
97
98 ctx = kmalloc(priv->grctx_size, GFP_KERNEL);
99 if (!ctx)
100 return -ENOMEM;
101
Ben Skeggs0411de82011-05-25 18:32:44 +1000102 if (!nouveau_ctxfw) {
103 nv_wr32(dev, 0x409840, 0x80000000);
104 nv_wr32(dev, 0x409500, 0x80000000 | chan->ramin->vinst >> 12);
105 nv_wr32(dev, 0x409504, 0x00000001);
106 if (!nv_wait(dev, 0x409800, 0x80000000, 0x80000000)) {
107 NV_ERROR(dev, "PGRAPH: HUB_SET_CHAN timeout\n");
108 nvc0_graph_ctxctl_debug(dev);
Dan Carpenter60f7ab02011-06-25 08:54:46 +0300109 ret = -EBUSY;
110 goto err;
Ben Skeggs0411de82011-05-25 18:32:44 +1000111 }
112 } else {
113 nvc0_graph_load_context(chan);
Ben Skeggs966a5b72010-11-24 10:49:02 +1000114
Ben Skeggs0411de82011-05-25 18:32:44 +1000115 nv_wo32(grch->grctx, 0x1c, 1);
116 nv_wo32(grch->grctx, 0x20, 0);
117 nv_wo32(grch->grctx, 0x28, 0);
118 nv_wo32(grch->grctx, 0x2c, 0);
119 dev_priv->engine.instmem.flush(dev);
120 }
Ben Skeggs966a5b72010-11-24 10:49:02 +1000121
122 ret = nvc0_grctx_generate(chan);
Dan Carpenter60f7ab02011-06-25 08:54:46 +0300123 if (ret)
124 goto err;
Ben Skeggs966a5b72010-11-24 10:49:02 +1000125
Ben Skeggs0411de82011-05-25 18:32:44 +1000126 if (!nouveau_ctxfw) {
127 nv_wr32(dev, 0x409840, 0x80000000);
128 nv_wr32(dev, 0x409500, 0x80000000 | chan->ramin->vinst >> 12);
129 nv_wr32(dev, 0x409504, 0x00000002);
130 if (!nv_wait(dev, 0x409800, 0x80000000, 0x80000000)) {
131 NV_ERROR(dev, "PGRAPH: HUB_CTX_SAVE timeout\n");
132 nvc0_graph_ctxctl_debug(dev);
Dan Carpenter60f7ab02011-06-25 08:54:46 +0300133 ret = -EBUSY;
134 goto err;
Ben Skeggs0411de82011-05-25 18:32:44 +1000135 }
136 } else {
137 ret = nvc0_graph_unload_context_to(dev, chan->ramin->vinst);
Dan Carpenter60f7ab02011-06-25 08:54:46 +0300138 if (ret)
139 goto err;
Ben Skeggs966a5b72010-11-24 10:49:02 +1000140 }
141
142 for (i = 0; i < priv->grctx_size; i += 4)
143 ctx[i / 4] = nv_ro32(grch->grctx, i);
144
145 priv->grctx_vals = ctx;
146 return 0;
Dan Carpenter60f7ab02011-06-25 08:54:46 +0300147
148err:
149 kfree(ctx);
150 return ret;
Ben Skeggs966a5b72010-11-24 10:49:02 +1000151}
152
153static int
154nvc0_graph_create_context_mmio_list(struct nouveau_channel *chan)
155{
Ben Skeggs7a45cd12011-04-01 10:59:53 +1000156 struct nvc0_graph_priv *priv = nv_engine(chan->dev, NVOBJ_ENGINE_GR);
157 struct nvc0_graph_chan *grch = chan->engctx[NVOBJ_ENGINE_GR];
Ben Skeggs966a5b72010-11-24 10:49:02 +1000158 struct drm_device *dev = chan->dev;
159 int i = 0, gpc, tp, ret;
160 u32 magic;
161
Ben Skeggs6e32fed2011-06-03 14:23:30 +1000162 ret = nouveau_gpuobj_new(dev, chan, 0x2000, 256, NVOBJ_FLAG_VM,
Ben Skeggs966a5b72010-11-24 10:49:02 +1000163 &grch->unk408004);
164 if (ret)
165 return ret;
166
Ben Skeggs6e32fed2011-06-03 14:23:30 +1000167 ret = nouveau_gpuobj_new(dev, chan, 0x8000, 256, NVOBJ_FLAG_VM,
Ben Skeggs966a5b72010-11-24 10:49:02 +1000168 &grch->unk40800c);
169 if (ret)
170 return ret;
171
Ben Skeggs6e32fed2011-06-03 14:23:30 +1000172 ret = nouveau_gpuobj_new(dev, chan, 384 * 1024, 4096,
Ben Skeggsc906ca02011-01-14 10:27:02 +1000173 NVOBJ_FLAG_VM | NVOBJ_FLAG_VM_USER,
Ben Skeggs966a5b72010-11-24 10:49:02 +1000174 &grch->unk418810);
175 if (ret)
176 return ret;
177
Ben Skeggs6e32fed2011-06-03 14:23:30 +1000178 ret = nouveau_gpuobj_new(dev, chan, 0x1000, 0, NVOBJ_FLAG_VM,
Ben Skeggs966a5b72010-11-24 10:49:02 +1000179 &grch->mmio);
180 if (ret)
181 return ret;
182
183
184 nv_wo32(grch->mmio, i++ * 4, 0x00408004);
Ben Skeggsf8522fc2011-05-25 17:22:43 +1000185 nv_wo32(grch->mmio, i++ * 4, grch->unk408004->linst >> 8);
Ben Skeggs966a5b72010-11-24 10:49:02 +1000186 nv_wo32(grch->mmio, i++ * 4, 0x00408008);
187 nv_wo32(grch->mmio, i++ * 4, 0x80000018);
188
189 nv_wo32(grch->mmio, i++ * 4, 0x0040800c);
Ben Skeggsf8522fc2011-05-25 17:22:43 +1000190 nv_wo32(grch->mmio, i++ * 4, grch->unk40800c->linst >> 8);
Ben Skeggs966a5b72010-11-24 10:49:02 +1000191 nv_wo32(grch->mmio, i++ * 4, 0x00408010);
192 nv_wo32(grch->mmio, i++ * 4, 0x80000000);
193
194 nv_wo32(grch->mmio, i++ * 4, 0x00418810);
Ben Skeggsf8522fc2011-05-25 17:22:43 +1000195 nv_wo32(grch->mmio, i++ * 4, 0x80000000 | grch->unk418810->linst >> 12);
Ben Skeggs966a5b72010-11-24 10:49:02 +1000196 nv_wo32(grch->mmio, i++ * 4, 0x00419848);
Ben Skeggsf8522fc2011-05-25 17:22:43 +1000197 nv_wo32(grch->mmio, i++ * 4, 0x10000000 | grch->unk418810->linst >> 12);
Ben Skeggs966a5b72010-11-24 10:49:02 +1000198
199 nv_wo32(grch->mmio, i++ * 4, 0x00419004);
Ben Skeggsf8522fc2011-05-25 17:22:43 +1000200 nv_wo32(grch->mmio, i++ * 4, grch->unk40800c->linst >> 8);
Ben Skeggs966a5b72010-11-24 10:49:02 +1000201 nv_wo32(grch->mmio, i++ * 4, 0x00419008);
202 nv_wo32(grch->mmio, i++ * 4, 0x00000000);
203
204 nv_wo32(grch->mmio, i++ * 4, 0x00418808);
Ben Skeggsf8522fc2011-05-25 17:22:43 +1000205 nv_wo32(grch->mmio, i++ * 4, grch->unk408004->linst >> 8);
Ben Skeggs966a5b72010-11-24 10:49:02 +1000206 nv_wo32(grch->mmio, i++ * 4, 0x0041880c);
207 nv_wo32(grch->mmio, i++ * 4, 0x80000018);
208
209 magic = 0x02180000;
210 nv_wo32(grch->mmio, i++ * 4, 0x00405830);
211 nv_wo32(grch->mmio, i++ * 4, magic);
212 for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
Ben Skeggse1b89b12011-05-24 14:57:53 +1000213 for (tp = 0; tp < priv->tp_nr[gpc]; tp++, magic += 0x0324) {
Ben Skeggs966a5b72010-11-24 10:49:02 +1000214 u32 reg = 0x504520 + (gpc * 0x8000) + (tp * 0x0800);
215 nv_wo32(grch->mmio, i++ * 4, reg);
216 nv_wo32(grch->mmio, i++ * 4, magic);
217 }
218 }
219
220 grch->mmio_nr = i / 2;
221 return 0;
222}
223
Ben Skeggs7a45cd12011-04-01 10:59:53 +1000224static int
225nvc0_graph_context_new(struct nouveau_channel *chan, int engine)
Ben Skeggs4b223ee2010-08-03 10:00:56 +1000226{
Ben Skeggs966a5b72010-11-24 10:49:02 +1000227 struct drm_device *dev = chan->dev;
Ben Skeggs7a45cd12011-04-01 10:59:53 +1000228 struct drm_nouveau_private *dev_priv = dev->dev_private;
229 struct nouveau_instmem_engine *pinstmem = &dev_priv->engine.instmem;
230 struct nvc0_graph_priv *priv = nv_engine(dev, engine);
231 struct nvc0_graph_chan *grch;
Ben Skeggs966a5b72010-11-24 10:49:02 +1000232 struct nouveau_gpuobj *grctx;
233 int ret, i;
234
Ben Skeggs7a45cd12011-04-01 10:59:53 +1000235 grch = kzalloc(sizeof(*grch), GFP_KERNEL);
236 if (!grch)
Ben Skeggs966a5b72010-11-24 10:49:02 +1000237 return -ENOMEM;
Ben Skeggs7a45cd12011-04-01 10:59:53 +1000238 chan->engctx[NVOBJ_ENGINE_GR] = grch;
Ben Skeggs966a5b72010-11-24 10:49:02 +1000239
Ben Skeggs6e32fed2011-06-03 14:23:30 +1000240 ret = nouveau_gpuobj_new(dev, chan, priv->grctx_size, 256,
Ben Skeggs966a5b72010-11-24 10:49:02 +1000241 NVOBJ_FLAG_VM | NVOBJ_FLAG_ZERO_ALLOC,
242 &grch->grctx);
243 if (ret)
244 goto error;
Ben Skeggs966a5b72010-11-24 10:49:02 +1000245 grctx = grch->grctx;
246
247 ret = nvc0_graph_create_context_mmio_list(chan);
248 if (ret)
249 goto error;
250
Ben Skeggsf8522fc2011-05-25 17:22:43 +1000251 nv_wo32(chan->ramin, 0x0210, lower_32_bits(grctx->linst) | 4);
252 nv_wo32(chan->ramin, 0x0214, upper_32_bits(grctx->linst));
Ben Skeggs966a5b72010-11-24 10:49:02 +1000253 pinstmem->flush(dev);
254
255 if (!priv->grctx_vals) {
256 ret = nvc0_graph_construct_context(chan);
257 if (ret)
258 goto error;
259 }
260
261 for (i = 0; i < priv->grctx_size; i += 4)
262 nv_wo32(grctx, i, priv->grctx_vals[i / 4]);
263
Ben Skeggs0411de82011-05-25 18:32:44 +1000264 if (!nouveau_ctxfw) {
265 nv_wo32(grctx, 0x00, grch->mmio_nr);
266 nv_wo32(grctx, 0x04, grch->mmio->linst >> 8);
267 } else {
268 nv_wo32(grctx, 0xf4, 0);
269 nv_wo32(grctx, 0xf8, 0);
270 nv_wo32(grctx, 0x10, grch->mmio_nr);
271 nv_wo32(grctx, 0x14, lower_32_bits(grch->mmio->linst));
272 nv_wo32(grctx, 0x18, upper_32_bits(grch->mmio->linst));
273 nv_wo32(grctx, 0x1c, 1);
274 nv_wo32(grctx, 0x20, 0);
275 nv_wo32(grctx, 0x28, 0);
276 nv_wo32(grctx, 0x2c, 0);
277 }
Ben Skeggs966a5b72010-11-24 10:49:02 +1000278 pinstmem->flush(dev);
Ben Skeggs4b223ee2010-08-03 10:00:56 +1000279 return 0;
Ben Skeggs966a5b72010-11-24 10:49:02 +1000280
281error:
Ben Skeggs7a45cd12011-04-01 10:59:53 +1000282 priv->base.context_del(chan, engine);
Ben Skeggs966a5b72010-11-24 10:49:02 +1000283 return ret;
Ben Skeggs4b223ee2010-08-03 10:00:56 +1000284}
285
Ben Skeggs7a45cd12011-04-01 10:59:53 +1000286static void
287nvc0_graph_context_del(struct nouveau_channel *chan, int engine)
Ben Skeggs4b223ee2010-08-03 10:00:56 +1000288{
Ben Skeggs7a45cd12011-04-01 10:59:53 +1000289 struct nvc0_graph_chan *grch = chan->engctx[engine];
Ben Skeggs966a5b72010-11-24 10:49:02 +1000290
291 nouveau_gpuobj_ref(NULL, &grch->mmio);
292 nouveau_gpuobj_ref(NULL, &grch->unk418810);
293 nouveau_gpuobj_ref(NULL, &grch->unk40800c);
294 nouveau_gpuobj_ref(NULL, &grch->unk408004);
295 nouveau_gpuobj_ref(NULL, &grch->grctx);
Ben Skeggs7a45cd12011-04-01 10:59:53 +1000296 chan->engctx[engine] = NULL;
Ben Skeggs4b223ee2010-08-03 10:00:56 +1000297}
298
Ben Skeggs7a45cd12011-04-01 10:59:53 +1000299static int
300nvc0_graph_object_new(struct nouveau_channel *chan, int engine,
301 u32 handle, u16 class)
Ben Skeggs4b223ee2010-08-03 10:00:56 +1000302{
Ben Skeggs966a5b72010-11-24 10:49:02 +1000303 return 0;
304}
305
306static int
Ben Skeggs6c320fe2011-07-20 11:22:33 +1000307nvc0_graph_fini(struct drm_device *dev, int engine, bool suspend)
Ben Skeggs966a5b72010-11-24 10:49:02 +1000308{
Ben Skeggs4b223ee2010-08-03 10:00:56 +1000309 return 0;
310}
311
Ben Skeggs966a5b72010-11-24 10:49:02 +1000312static int
Ben Skeggsbd2f2032011-02-08 15:16:23 +1000313nvc0_graph_mthd_page_flip(struct nouveau_channel *chan,
314 u32 class, u32 mthd, u32 data)
315{
316 nouveau_finish_page_flip(chan, NULL);
317 return 0;
318}
319
Ben Skeggs966a5b72010-11-24 10:49:02 +1000320static void
321nvc0_graph_init_obj418880(struct drm_device *dev)
322{
Ben Skeggs7a45cd12011-04-01 10:59:53 +1000323 struct nvc0_graph_priv *priv = nv_engine(dev, NVOBJ_ENGINE_GR);
Ben Skeggs966a5b72010-11-24 10:49:02 +1000324 int i;
325
326 nv_wr32(dev, GPC_BCAST(0x0880), 0x00000000);
327 nv_wr32(dev, GPC_BCAST(0x08a4), 0x00000000);
328 for (i = 0; i < 4; i++)
329 nv_wr32(dev, GPC_BCAST(0x0888) + (i * 4), 0x00000000);
330 nv_wr32(dev, GPC_BCAST(0x08b4), priv->unk4188b4->vinst >> 8);
331 nv_wr32(dev, GPC_BCAST(0x08b8), priv->unk4188b8->vinst >> 8);
332}
333
334static void
335nvc0_graph_init_regs(struct drm_device *dev)
336{
337 nv_wr32(dev, 0x400080, 0x003083c2);
338 nv_wr32(dev, 0x400088, 0x00006fe7);
339 nv_wr32(dev, 0x40008c, 0x00000000);
340 nv_wr32(dev, 0x400090, 0x00000030);
341 nv_wr32(dev, 0x40013c, 0x013901f7);
342 nv_wr32(dev, 0x400140, 0x00000100);
343 nv_wr32(dev, 0x400144, 0x00000000);
344 nv_wr32(dev, 0x400148, 0x00000110);
345 nv_wr32(dev, 0x400138, 0x00000000);
346 nv_wr32(dev, 0x400130, 0x00000000);
347 nv_wr32(dev, 0x400134, 0x00000000);
348 nv_wr32(dev, 0x400124, 0x00000002);
349}
350
351static void
352nvc0_graph_init_gpc_0(struct drm_device *dev)
353{
Ben Skeggs7a45cd12011-04-01 10:59:53 +1000354 struct nvc0_graph_priv *priv = nv_engine(dev, NVOBJ_ENGINE_GR);
Ben Skeggs066d65d2011-05-26 12:12:43 +1000355 const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, priv->tp_total);
Ben Skeggsaa58c402011-04-18 12:52:47 +1000356 u32 data[TP_MAX / 8];
357 u8 tpnr[GPC_MAX];
358 int i, gpc, tpc;
Ben Skeggs966a5b72010-11-24 10:49:02 +1000359
Emil Velikovf2129492011-03-19 23:31:52 +0000360 /*
361 * TP ROP UNKVAL(magic_not_rop_nr)
362 * 450: 4/0/0/0 2 3
363 * 460: 3/4/0/0 4 1
364 * 465: 3/4/4/0 4 7
365 * 470: 3/3/4/4 5 5
366 * 480: 3/4/4/4 6 6
Emil Velikovf2129492011-03-19 23:31:52 +0000367 */
368
Ben Skeggsaa58c402011-04-18 12:52:47 +1000369 memset(data, 0x00, sizeof(data));
370 memcpy(tpnr, priv->tp_nr, sizeof(priv->tp_nr));
371 for (i = 0, gpc = -1; i < priv->tp_total; i++) {
372 do {
373 gpc = (gpc + 1) % priv->gpc_nr;
374 } while (!tpnr[gpc]);
375 tpc = priv->tp_nr[gpc] - tpnr[gpc]--;
376
377 data[i / 8] |= tpc << ((i % 8) * 4);
378 }
379
380 nv_wr32(dev, GPC_BCAST(0x0980), data[0]);
381 nv_wr32(dev, GPC_BCAST(0x0984), data[1]);
382 nv_wr32(dev, GPC_BCAST(0x0988), data[2]);
383 nv_wr32(dev, GPC_BCAST(0x098c), data[3]);
Ben Skeggs966a5b72010-11-24 10:49:02 +1000384
385 for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
386 nv_wr32(dev, GPC_UNIT(gpc, 0x0914), priv->magic_not_rop_nr << 8 |
387 priv->tp_nr[gpc]);
388 nv_wr32(dev, GPC_UNIT(gpc, 0x0910), 0x00040000 | priv->tp_total);
Ben Skeggs066d65d2011-05-26 12:12:43 +1000389 nv_wr32(dev, GPC_UNIT(gpc, 0x0918), magicgpc918);
Ben Skeggs966a5b72010-11-24 10:49:02 +1000390 }
391
Ben Skeggs066d65d2011-05-26 12:12:43 +1000392 nv_wr32(dev, GPC_BCAST(0x1bd4), magicgpc918);
Ben Skeggse425e0b2011-06-29 10:42:14 +1000393 nv_wr32(dev, GPC_BCAST(0x08ac), nv_rd32(dev, 0x100800));
Ben Skeggs966a5b72010-11-24 10:49:02 +1000394}
395
396static void
397nvc0_graph_init_units(struct drm_device *dev)
398{
399 nv_wr32(dev, 0x409c24, 0x000f0000);
400 nv_wr32(dev, 0x404000, 0xc0000000); /* DISPATCH */
401 nv_wr32(dev, 0x404600, 0xc0000000); /* M2MF */
402 nv_wr32(dev, 0x408030, 0xc0000000);
403 nv_wr32(dev, 0x40601c, 0xc0000000);
404 nv_wr32(dev, 0x404490, 0xc0000000); /* MACRO */
405 nv_wr32(dev, 0x406018, 0xc0000000);
406 nv_wr32(dev, 0x405840, 0xc0000000);
407 nv_wr32(dev, 0x405844, 0x00ffffff);
408 nv_mask(dev, 0x419cc0, 0x00000008, 0x00000008);
409 nv_mask(dev, 0x419eb4, 0x00001000, 0x00001000);
410}
411
412static void
413nvc0_graph_init_gpc_1(struct drm_device *dev)
414{
Ben Skeggs7a45cd12011-04-01 10:59:53 +1000415 struct nvc0_graph_priv *priv = nv_engine(dev, NVOBJ_ENGINE_GR);
Ben Skeggs966a5b72010-11-24 10:49:02 +1000416 int gpc, tp;
417
418 for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
419 nv_wr32(dev, GPC_UNIT(gpc, 0x0420), 0xc0000000);
420 nv_wr32(dev, GPC_UNIT(gpc, 0x0900), 0xc0000000);
421 nv_wr32(dev, GPC_UNIT(gpc, 0x1028), 0xc0000000);
422 nv_wr32(dev, GPC_UNIT(gpc, 0x0824), 0xc0000000);
423 for (tp = 0; tp < priv->tp_nr[gpc]; tp++) {
424 nv_wr32(dev, TP_UNIT(gpc, tp, 0x508), 0xffffffff);
425 nv_wr32(dev, TP_UNIT(gpc, tp, 0x50c), 0xffffffff);
426 nv_wr32(dev, TP_UNIT(gpc, tp, 0x224), 0xc0000000);
427 nv_wr32(dev, TP_UNIT(gpc, tp, 0x48c), 0xc0000000);
428 nv_wr32(dev, TP_UNIT(gpc, tp, 0x084), 0xc0000000);
Ben Skeggs0f1cb202011-01-21 11:15:16 +1000429 nv_wr32(dev, TP_UNIT(gpc, tp, 0x644), 0x001ffffe);
430 nv_wr32(dev, TP_UNIT(gpc, tp, 0x64c), 0x0000000f);
Ben Skeggs966a5b72010-11-24 10:49:02 +1000431 }
432 nv_wr32(dev, GPC_UNIT(gpc, 0x2c90), 0xffffffff);
433 nv_wr32(dev, GPC_UNIT(gpc, 0x2c94), 0xffffffff);
434 }
435}
436
437static void
438nvc0_graph_init_rop(struct drm_device *dev)
439{
Ben Skeggs7a45cd12011-04-01 10:59:53 +1000440 struct nvc0_graph_priv *priv = nv_engine(dev, NVOBJ_ENGINE_GR);
Ben Skeggs966a5b72010-11-24 10:49:02 +1000441 int rop;
442
443 for (rop = 0; rop < priv->rop_nr; rop++) {
444 nv_wr32(dev, ROP_UNIT(rop, 0x144), 0xc0000000);
445 nv_wr32(dev, ROP_UNIT(rop, 0x070), 0xc0000000);
446 nv_wr32(dev, ROP_UNIT(rop, 0x204), 0xffffffff);
447 nv_wr32(dev, ROP_UNIT(rop, 0x208), 0xffffffff);
448 }
449}
450
Ben Skeggsfe799112011-04-12 18:50:36 +1000451static void
452nvc0_graph_init_fuc(struct drm_device *dev, u32 fuc_base,
453 struct nvc0_graph_fuc *code, struct nvc0_graph_fuc *data)
Ben Skeggs966a5b72010-11-24 10:49:02 +1000454{
Ben Skeggsfe799112011-04-12 18:50:36 +1000455 int i;
Ben Skeggs966a5b72010-11-24 10:49:02 +1000456
457 nv_wr32(dev, fuc_base + 0x01c0, 0x01000000);
Ben Skeggsfe799112011-04-12 18:50:36 +1000458 for (i = 0; i < data->size / 4; i++)
459 nv_wr32(dev, fuc_base + 0x01c4, data->data[i]);
Ben Skeggs966a5b72010-11-24 10:49:02 +1000460
461 nv_wr32(dev, fuc_base + 0x0180, 0x01000000);
Ben Skeggsfe799112011-04-12 18:50:36 +1000462 for (i = 0; i < code->size / 4; i++) {
Ben Skeggs966a5b72010-11-24 10:49:02 +1000463 if ((i & 0x3f) == 0)
464 nv_wr32(dev, fuc_base + 0x0188, i >> 6);
Ben Skeggsfe799112011-04-12 18:50:36 +1000465 nv_wr32(dev, fuc_base + 0x0184, code->data[i]);
Ben Skeggs966a5b72010-11-24 10:49:02 +1000466 }
Ben Skeggs966a5b72010-11-24 10:49:02 +1000467}
468
469static int
470nvc0_graph_init_ctxctl(struct drm_device *dev)
471{
Ben Skeggs0411de82011-05-25 18:32:44 +1000472 struct drm_nouveau_private *dev_priv = dev->dev_private;
Ben Skeggs7a45cd12011-04-01 10:59:53 +1000473 struct nvc0_graph_priv *priv = nv_engine(dev, NVOBJ_ENGINE_GR);
Ben Skeggs966a5b72010-11-24 10:49:02 +1000474 u32 r000260;
Ben Skeggs0411de82011-05-25 18:32:44 +1000475 int i;
476
477 if (!nouveau_ctxfw) {
478 /* load HUB microcode */
479 r000260 = nv_mask(dev, 0x000260, 0x00000001, 0x00000000);
480 nv_wr32(dev, 0x4091c0, 0x01000000);
481 for (i = 0; i < sizeof(nvc0_grhub_data) / 4; i++)
482 nv_wr32(dev, 0x4091c4, nvc0_grhub_data[i]);
483
484 nv_wr32(dev, 0x409180, 0x01000000);
485 for (i = 0; i < sizeof(nvc0_grhub_code) / 4; i++) {
486 if ((i & 0x3f) == 0)
487 nv_wr32(dev, 0x409188, i >> 6);
488 nv_wr32(dev, 0x409184, nvc0_grhub_code[i]);
489 }
490
491 /* load GPC microcode */
492 nv_wr32(dev, 0x41a1c0, 0x01000000);
493 for (i = 0; i < sizeof(nvc0_grgpc_data) / 4; i++)
494 nv_wr32(dev, 0x41a1c4, nvc0_grgpc_data[i]);
495
496 nv_wr32(dev, 0x41a180, 0x01000000);
497 for (i = 0; i < sizeof(nvc0_grgpc_code) / 4; i++) {
498 if ((i & 0x3f) == 0)
499 nv_wr32(dev, 0x41a188, i >> 6);
500 nv_wr32(dev, 0x41a184, nvc0_grgpc_code[i]);
501 }
502 nv_wr32(dev, 0x000260, r000260);
503
504 /* start HUB ucode running, it'll init the GPCs */
505 nv_wr32(dev, 0x409800, dev_priv->chipset);
506 nv_wr32(dev, 0x40910c, 0x00000000);
507 nv_wr32(dev, 0x409100, 0x00000002);
508 if (!nv_wait(dev, 0x409800, 0x80000000, 0x80000000)) {
509 NV_ERROR(dev, "PGRAPH: HUB_INIT timed out\n");
510 nvc0_graph_ctxctl_debug(dev);
511 return -EBUSY;
512 }
513
514 priv->grctx_size = nv_rd32(dev, 0x409804);
515 return 0;
516 }
Ben Skeggs966a5b72010-11-24 10:49:02 +1000517
518 /* load fuc microcode */
519 r000260 = nv_mask(dev, 0x000260, 0x00000001, 0x00000000);
Ben Skeggsfe799112011-04-12 18:50:36 +1000520 nvc0_graph_init_fuc(dev, 0x409000, &priv->fuc409c, &priv->fuc409d);
521 nvc0_graph_init_fuc(dev, 0x41a000, &priv->fuc41ac, &priv->fuc41ad);
Ben Skeggs966a5b72010-11-24 10:49:02 +1000522 nv_wr32(dev, 0x000260, r000260);
523
Ben Skeggs966a5b72010-11-24 10:49:02 +1000524 /* start both of them running */
525 nv_wr32(dev, 0x409840, 0xffffffff);
526 nv_wr32(dev, 0x41a10c, 0x00000000);
527 nv_wr32(dev, 0x40910c, 0x00000000);
528 nv_wr32(dev, 0x41a100, 0x00000002);
529 nv_wr32(dev, 0x409100, 0x00000002);
530 if (!nv_wait(dev, 0x409800, 0x00000001, 0x00000001))
531 NV_INFO(dev, "0x409800 wait failed\n");
532
533 nv_wr32(dev, 0x409840, 0xffffffff);
534 nv_wr32(dev, 0x409500, 0x7fffffff);
535 nv_wr32(dev, 0x409504, 0x00000021);
536
537 nv_wr32(dev, 0x409840, 0xffffffff);
538 nv_wr32(dev, 0x409500, 0x00000000);
539 nv_wr32(dev, 0x409504, 0x00000010);
540 if (!nv_wait_ne(dev, 0x409800, 0xffffffff, 0x00000000)) {
541 NV_ERROR(dev, "fuc09 req 0x10 timeout\n");
542 return -EBUSY;
543 }
544 priv->grctx_size = nv_rd32(dev, 0x409800);
545
546 nv_wr32(dev, 0x409840, 0xffffffff);
547 nv_wr32(dev, 0x409500, 0x00000000);
548 nv_wr32(dev, 0x409504, 0x00000016);
549 if (!nv_wait_ne(dev, 0x409800, 0xffffffff, 0x00000000)) {
550 NV_ERROR(dev, "fuc09 req 0x16 timeout\n");
551 return -EBUSY;
552 }
553
554 nv_wr32(dev, 0x409840, 0xffffffff);
555 nv_wr32(dev, 0x409500, 0x00000000);
556 nv_wr32(dev, 0x409504, 0x00000025);
557 if (!nv_wait_ne(dev, 0x409800, 0xffffffff, 0x00000000)) {
558 NV_ERROR(dev, "fuc09 req 0x25 timeout\n");
559 return -EBUSY;
560 }
561
562 return 0;
Ben Skeggs4b223ee2010-08-03 10:00:56 +1000563}
564
Ben Skeggs7a45cd12011-04-01 10:59:53 +1000565static int
566nvc0_graph_init(struct drm_device *dev, int engine)
Ben Skeggs4b223ee2010-08-03 10:00:56 +1000567{
Ben Skeggs966a5b72010-11-24 10:49:02 +1000568 int ret;
569
Ben Skeggs966a5b72010-11-24 10:49:02 +1000570 nv_mask(dev, 0x000200, 0x18001000, 0x00000000);
571 nv_mask(dev, 0x000200, 0x18001000, 0x18001000);
572
Ben Skeggs966a5b72010-11-24 10:49:02 +1000573 nvc0_graph_init_obj418880(dev);
574 nvc0_graph_init_regs(dev);
Emil Velikovf2129492011-03-19 23:31:52 +0000575 /*nvc0_graph_init_unitplemented_magics(dev);*/
Ben Skeggs966a5b72010-11-24 10:49:02 +1000576 nvc0_graph_init_gpc_0(dev);
Emil Velikovf2129492011-03-19 23:31:52 +0000577 /*nvc0_graph_init_unitplemented_c242(dev);*/
Ben Skeggs966a5b72010-11-24 10:49:02 +1000578
579 nv_wr32(dev, 0x400500, 0x00010001);
580 nv_wr32(dev, 0x400100, 0xffffffff);
581 nv_wr32(dev, 0x40013c, 0xffffffff);
582
583 nvc0_graph_init_units(dev);
584 nvc0_graph_init_gpc_1(dev);
585 nvc0_graph_init_rop(dev);
586
587 nv_wr32(dev, 0x400108, 0xffffffff);
588 nv_wr32(dev, 0x400138, 0xffffffff);
589 nv_wr32(dev, 0x400118, 0xffffffff);
590 nv_wr32(dev, 0x400130, 0xffffffff);
591 nv_wr32(dev, 0x40011c, 0xffffffff);
592 nv_wr32(dev, 0x400134, 0xffffffff);
593 nv_wr32(dev, 0x400054, 0x34ce3464);
594
595 ret = nvc0_graph_init_ctxctl(dev);
Ben Skeggsa82dd492011-04-01 13:56:05 +1000596 if (ret)
597 return ret;
598
Ben Skeggs4b223ee2010-08-03 10:00:56 +1000599 return 0;
600}
601
Ben Skeggsd5a27372011-04-01 16:10:08 +1000602int
Ben Skeggs966a5b72010-11-24 10:49:02 +1000603nvc0_graph_isr_chid(struct drm_device *dev, u64 inst)
604{
605 struct drm_nouveau_private *dev_priv = dev->dev_private;
606 struct nouveau_channel *chan;
607 unsigned long flags;
608 int i;
609
610 spin_lock_irqsave(&dev_priv->channels.lock, flags);
611 for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
612 chan = dev_priv->channels.ptr[i];
613 if (!chan || !chan->ramin)
614 continue;
615
616 if (inst == chan->ramin->vinst)
617 break;
618 }
619 spin_unlock_irqrestore(&dev_priv->channels.lock, flags);
620 return i;
621}
622
623static void
Ben Skeggs0411de82011-05-25 18:32:44 +1000624nvc0_graph_ctxctl_isr(struct drm_device *dev)
625{
626 u32 ustat = nv_rd32(dev, 0x409c18);
627
628 if (ustat & 0x00000001)
629 NV_INFO(dev, "PGRAPH: CTXCTRL ucode error\n");
630 if (ustat & 0x00080000)
631 NV_INFO(dev, "PGRAPH: CTXCTRL watchdog timeout\n");
632 if (ustat & ~0x00080001)
633 NV_INFO(dev, "PGRAPH: CTXCTRL 0x%08x\n", ustat);
634
635 nvc0_graph_ctxctl_debug(dev);
636 nv_wr32(dev, 0x409c20, ustat);
637}
638
639static void
Ben Skeggs966a5b72010-11-24 10:49:02 +1000640nvc0_graph_isr(struct drm_device *dev)
641{
642 u64 inst = (u64)(nv_rd32(dev, 0x409b00) & 0x0fffffff) << 12;
643 u32 chid = nvc0_graph_isr_chid(dev, inst);
644 u32 stat = nv_rd32(dev, 0x400100);
645 u32 addr = nv_rd32(dev, 0x400704);
646 u32 mthd = (addr & 0x00003ffc);
647 u32 subc = (addr & 0x00070000) >> 16;
648 u32 data = nv_rd32(dev, 0x400708);
649 u32 code = nv_rd32(dev, 0x400110);
650 u32 class = nv_rd32(dev, 0x404200 + (subc * 4));
651
652 if (stat & 0x00000010) {
Ben Skeggsbd2f2032011-02-08 15:16:23 +1000653 if (nouveau_gpuobj_mthd_call2(dev, chid, class, mthd, data)) {
654 NV_INFO(dev, "PGRAPH: ILLEGAL_MTHD ch %d [0x%010llx] "
655 "subc %d class 0x%04x mthd 0x%04x "
656 "data 0x%08x\n",
657 chid, inst, subc, class, mthd, data);
658 }
Ben Skeggs966a5b72010-11-24 10:49:02 +1000659 nv_wr32(dev, 0x400100, 0x00000010);
660 stat &= ~0x00000010;
661 }
662
Ben Skeggseae5e7f2010-12-30 11:40:07 +1000663 if (stat & 0x00000020) {
664 NV_INFO(dev, "PGRAPH: ILLEGAL_CLASS ch %d [0x%010llx] subc %d "
665 "class 0x%04x mthd 0x%04x data 0x%08x\n",
666 chid, inst, subc, class, mthd, data);
667 nv_wr32(dev, 0x400100, 0x00000020);
668 stat &= ~0x00000020;
669 }
670
Ben Skeggs966a5b72010-11-24 10:49:02 +1000671 if (stat & 0x00100000) {
672 NV_INFO(dev, "PGRAPH: DATA_ERROR [");
Ben Skeggs6effe392010-12-30 11:48:03 +1000673 nouveau_enum_print(nv50_data_error_names, code);
Ben Skeggs966a5b72010-11-24 10:49:02 +1000674 printk("] ch %d [0x%010llx] subc %d class 0x%04x "
675 "mthd 0x%04x data 0x%08x\n",
676 chid, inst, subc, class, mthd, data);
677 nv_wr32(dev, 0x400100, 0x00100000);
678 stat &= ~0x00100000;
679 }
680
Ben Skeggseae5e7f2010-12-30 11:40:07 +1000681 if (stat & 0x00200000) {
682 u32 trap = nv_rd32(dev, 0x400108);
683 NV_INFO(dev, "PGRAPH: TRAP ch %d status 0x%08x\n", chid, trap);
684 nv_wr32(dev, 0x400108, trap);
685 nv_wr32(dev, 0x400100, 0x00200000);
686 stat &= ~0x00200000;
687 }
688
Ben Skeggs966a5b72010-11-24 10:49:02 +1000689 if (stat & 0x00080000) {
Ben Skeggs0411de82011-05-25 18:32:44 +1000690 nvc0_graph_ctxctl_isr(dev);
Ben Skeggs966a5b72010-11-24 10:49:02 +1000691 nv_wr32(dev, 0x400100, 0x00080000);
692 stat &= ~0x00080000;
693 }
694
695 if (stat) {
696 NV_INFO(dev, "PGRAPH: unknown stat 0x%08x\n", stat);
697 nv_wr32(dev, 0x400100, stat);
698 }
699
700 nv_wr32(dev, 0x400500, 0x00010001);
701}
Ben Skeggs51f73d62011-01-21 13:53:21 +1000702
Ben Skeggsfe799112011-04-12 18:50:36 +1000703static int
704nvc0_graph_create_fw(struct drm_device *dev, const char *fwname,
705 struct nvc0_graph_fuc *fuc)
706{
707 struct drm_nouveau_private *dev_priv = dev->dev_private;
708 const struct firmware *fw;
709 char f[32];
710 int ret;
711
712 snprintf(f, sizeof(f), "nouveau/nv%02x_%s", dev_priv->chipset, fwname);
713 ret = request_firmware(&fw, f, &dev->pdev->dev);
714 if (ret) {
715 snprintf(f, sizeof(f), "nouveau/%s", fwname);
716 ret = request_firmware(&fw, f, &dev->pdev->dev);
717 if (ret) {
718 NV_ERROR(dev, "failed to load %s\n", fwname);
719 return ret;
720 }
721 }
722
723 fuc->size = fw->size;
724 fuc->data = kmemdup(fw->data, fuc->size, GFP_KERNEL);
725 release_firmware(fw);
726 return (fuc->data != NULL) ? 0 : -ENOMEM;
727}
728
729static void
730nvc0_graph_destroy_fw(struct nvc0_graph_fuc *fuc)
731{
732 if (fuc->data) {
733 kfree(fuc->data);
734 fuc->data = NULL;
735 }
736}
737
Ben Skeggs7a45cd12011-04-01 10:59:53 +1000738static void
739nvc0_graph_destroy(struct drm_device *dev, int engine)
740{
741 struct nvc0_graph_priv *priv = nv_engine(dev, engine);
742
Ben Skeggs0411de82011-05-25 18:32:44 +1000743 if (nouveau_ctxfw) {
744 nvc0_graph_destroy_fw(&priv->fuc409c);
745 nvc0_graph_destroy_fw(&priv->fuc409d);
746 nvc0_graph_destroy_fw(&priv->fuc41ac);
747 nvc0_graph_destroy_fw(&priv->fuc41ad);
748 }
Ben Skeggsfe799112011-04-12 18:50:36 +1000749
Ben Skeggs7a45cd12011-04-01 10:59:53 +1000750 nouveau_irq_unregister(dev, 12);
Ben Skeggs7a45cd12011-04-01 10:59:53 +1000751
752 nouveau_gpuobj_ref(NULL, &priv->unk4188b8);
753 nouveau_gpuobj_ref(NULL, &priv->unk4188b4);
754
755 if (priv->grctx_vals)
756 kfree(priv->grctx_vals);
757
758 NVOBJ_ENGINE_DEL(dev, GR);
759 kfree(priv);
760}
761
762int
763nvc0_graph_create(struct drm_device *dev)
764{
765 struct drm_nouveau_private *dev_priv = dev->dev_private;
766 struct nvc0_graph_priv *priv;
767 int ret, gpc, i;
Ben Skeggs847adea2011-05-24 14:37:41 +1000768 u32 fermi;
Ben Skeggs7a45cd12011-04-01 10:59:53 +1000769
Ben Skeggs847adea2011-05-24 14:37:41 +1000770 fermi = nvc0_graph_class(dev);
771 if (!fermi) {
Ben Skeggsa82dd492011-04-01 13:56:05 +1000772 NV_ERROR(dev, "PGRAPH: unsupported chipset, please report!\n");
773 return 0;
774 }
775
Ben Skeggs7a45cd12011-04-01 10:59:53 +1000776 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
777 if (!priv)
778 return -ENOMEM;
779
780 priv->base.destroy = nvc0_graph_destroy;
781 priv->base.init = nvc0_graph_init;
782 priv->base.fini = nvc0_graph_fini;
783 priv->base.context_new = nvc0_graph_context_new;
784 priv->base.context_del = nvc0_graph_context_del;
785 priv->base.object_new = nvc0_graph_object_new;
786
787 NVOBJ_ENGINE_ADD(dev, GR, &priv->base);
788 nouveau_irq_register(dev, 12, nvc0_graph_isr);
Ben Skeggs7a45cd12011-04-01 10:59:53 +1000789
Ben Skeggs0411de82011-05-25 18:32:44 +1000790 if (nouveau_ctxfw) {
791 NV_INFO(dev, "PGRAPH: using external firmware\n");
792 if (nvc0_graph_create_fw(dev, "fuc409c", &priv->fuc409c) ||
793 nvc0_graph_create_fw(dev, "fuc409d", &priv->fuc409d) ||
794 nvc0_graph_create_fw(dev, "fuc41ac", &priv->fuc41ac) ||
795 nvc0_graph_create_fw(dev, "fuc41ad", &priv->fuc41ad)) {
796 ret = 0;
797 goto error;
798 }
Ben Skeggsfe799112011-04-12 18:50:36 +1000799 }
800
Ben Skeggs7a45cd12011-04-01 10:59:53 +1000801 ret = nouveau_gpuobj_new(dev, NULL, 0x1000, 256, 0, &priv->unk4188b4);
802 if (ret)
803 goto error;
804
805 ret = nouveau_gpuobj_new(dev, NULL, 0x1000, 256, 0, &priv->unk4188b8);
806 if (ret)
807 goto error;
808
809 for (i = 0; i < 0x1000; i += 4) {
810 nv_wo32(priv->unk4188b4, i, 0x00000010);
811 nv_wo32(priv->unk4188b8, i, 0x00000010);
812 }
813
814 priv->gpc_nr = nv_rd32(dev, 0x409604) & 0x0000001f;
815 priv->rop_nr = (nv_rd32(dev, 0x409604) & 0x001f0000) >> 16;
816 for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
817 priv->tp_nr[gpc] = nv_rd32(dev, GPC_UNIT(gpc, 0x2608));
818 priv->tp_total += priv->tp_nr[gpc];
819 }
820
821 /*XXX: these need figuring out... */
822 switch (dev_priv->chipset) {
823 case 0xc0:
824 if (priv->tp_total == 11) { /* 465, 3/4/4/0, 4 */
825 priv->magic_not_rop_nr = 0x07;
Ben Skeggs7a45cd12011-04-01 10:59:53 +1000826 } else
827 if (priv->tp_total == 14) { /* 470, 3/3/4/4, 5 */
828 priv->magic_not_rop_nr = 0x05;
Ben Skeggs7a45cd12011-04-01 10:59:53 +1000829 } else
830 if (priv->tp_total == 15) { /* 480, 3/4/4/4, 6 */
831 priv->magic_not_rop_nr = 0x06;
Ben Skeggs7a45cd12011-04-01 10:59:53 +1000832 }
833 break;
834 case 0xc3: /* 450, 4/0/0/0, 2 */
835 priv->magic_not_rop_nr = 0x03;
Ben Skeggs7a45cd12011-04-01 10:59:53 +1000836 break;
837 case 0xc4: /* 460, 3/4/0/0, 4 */
838 priv->magic_not_rop_nr = 0x01;
Ben Skeggs7a45cd12011-04-01 10:59:53 +1000839 break;
Ben Skeggsa2199972011-05-26 10:54:05 +1000840 case 0xc1: /* 2/0/0/0, 1 */
841 priv->magic_not_rop_nr = 0x01;
Ben Skeggsa2199972011-05-26 10:54:05 +1000842 break;
843 case 0xc8: /* 4/4/3/4, 5 */
844 priv->magic_not_rop_nr = 0x06;
Ben Skeggsa2199972011-05-26 10:54:05 +1000845 break;
846 case 0xce: /* 4/4/0/0, 4 */
847 priv->magic_not_rop_nr = 0x03;
Ben Skeggsa2199972011-05-26 10:54:05 +1000848 break;
Ben Skeggs3c23a7b2011-06-24 11:14:00 +1000849 case 0xcf: /* 4/0/0/0, 3 */
850 priv->magic_not_rop_nr = 0x03;
851 break;
Ben Skeggs7a45cd12011-04-01 10:59:53 +1000852 }
853
854 if (!priv->magic_not_rop_nr) {
855 NV_ERROR(dev, "PGRAPH: unknown config: %d/%d/%d/%d, %d\n",
856 priv->tp_nr[0], priv->tp_nr[1], priv->tp_nr[2],
857 priv->tp_nr[3], priv->rop_nr);
858 /* use 0xc3's values... */
859 priv->magic_not_rop_nr = 0x03;
Ben Skeggs7a45cd12011-04-01 10:59:53 +1000860 }
861
862 NVOBJ_CLASS(dev, 0x902d, GR); /* 2D */
863 NVOBJ_CLASS(dev, 0x9039, GR); /* M2MF */
864 NVOBJ_MTHD (dev, 0x9039, 0x0500, nvc0_graph_mthd_page_flip);
865 NVOBJ_CLASS(dev, 0x9097, GR); /* 3D */
Ben Skeggs847adea2011-05-24 14:37:41 +1000866 if (fermi >= 0x9197)
867 NVOBJ_CLASS(dev, 0x9197, GR); /* 3D (NVC1-) */
868 if (fermi >= 0x9297)
869 NVOBJ_CLASS(dev, 0x9297, GR); /* 3D (NVC8-) */
Ben Skeggs7a45cd12011-04-01 10:59:53 +1000870 NVOBJ_CLASS(dev, 0x90c0, GR); /* COMPUTE */
871 return 0;
872
873error:
874 nvc0_graph_destroy(dev, NVOBJ_ENGINE_GR);
875 return ret;
876}