| Duy Truong | 790f06d | 2013-02-13 16:38:12 -0800 | [diff] [blame] | 1 | /* Copyright (c) 2012, The Linux Foundation. All rights reserved. |
| Taniya Das | 43bcdd6 | 2011-12-02 17:33:27 +0530 | [diff] [blame] | 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | */ |
| 12 | |
| 13 | #ifndef __ASM_ARCH_MSM_IRQS_8625_H |
| 14 | #define __ASM_ARCH_MSM_IRQS_8625_H |
| 15 | |
| Taniya Das | ea4263f9 | 2012-08-22 18:52:51 +0530 | [diff] [blame] | 16 | #ifdef CONFIG_MSM_FIQ |
| 17 | #define FIQ_START 0 |
| 18 | #endif |
| 19 | |
| Taniya Das | 43bcdd6 | 2011-12-02 17:33:27 +0530 | [diff] [blame] | 20 | /* As per QGIC2 PPI 16 aka 0 is reserved */ |
| Ashwin Chaugule | d82ed3a | 2012-11-05 10:35:30 -0500 | [diff] [blame] | 21 | #define MSM8625_INT_ARMQC_PERFMON (GIC_PPI_START + 1) |
| Taniya Das | 43bcdd6 | 2011-12-02 17:33:27 +0530 | [diff] [blame] | 22 | #define MSM8625_INT_DEBUG_TIMER_EXP (GIC_PPI_START + 2) |
| 23 | #define MSM8625_INT_GP_TIMER_EXP (GIC_PPI_START + 3) |
| 24 | #define MSM8625_INT_COMMRX (GIC_PPI_START + 4) |
| 25 | #define MSM8625_INT_COMMTX (GIC_PPI_START + 5) |
| 26 | |
| 27 | /* rest of the PPI's not used |
| 28 | */ |
| 29 | |
| 30 | #define MSM8625_INT_A9_M2A_0 (GIC_SPI_START + 0) |
| 31 | #define MSM8625_INT_A9_M2A_1 (GIC_SPI_START + 1) |
| 32 | #define MSM8625_INT_A9_M2A_2 (GIC_SPI_START + 2) |
| 33 | #define MSM8625_INT_A9_M2A_3 (GIC_SPI_START + 3) |
| 34 | #define MSM8625_INT_A9_M2A_4 (GIC_SPI_START + 4) |
| 35 | #define MSM8625_INT_A9_M2A_5 (GIC_SPI_START + 5) |
| 36 | #define MSM8625_INT_A9_M2A_6 (GIC_SPI_START + 6) |
| 37 | #define MSM8625_INT_ACSR_MP_CORE_IPC0 (GIC_SPI_START + 7) |
| 38 | #define MSM8625_INT_ACSR_MP_CORE_IPC1 (GIC_SPI_START + 8) |
| 39 | #define MSM8625_INT_UART1 (GIC_SPI_START + 9) |
| 40 | #define MSM8625_INT_UART2 (GIC_SPI_START + 10) |
| 41 | #define MSM8625_INT_UART3 (GIC_SPI_START + 11) |
| 42 | #define MSM8625_INT_UART1_RX (GIC_SPI_START + 12) |
| 43 | #define MSM8625_INT_UART2_RX (GIC_SPI_START + 13) |
| 44 | #define MSM8625_INT_UART3_RX (GIC_SPI_START + 14) |
| 45 | #define MSM8625_INT_USB_OTG (GIC_SPI_START + 15) |
| 46 | #define MSM8625_INT_DSI_IRQ (GIC_SPI_START + 16) |
| 47 | #define MSM8625_INT_CSI_IRQ_1 (GIC_SPI_START + 17) |
| 48 | #define MSM8625_INT_CSI_IRQ_0 (GIC_SPI_START + 18) |
| 49 | #define MSM8625_INT_MDP (GIC_SPI_START + 19) |
| 50 | #define MSM8625_INT_GRAPHICS (GIC_SPI_START + 20) |
| 51 | #define MSM8625_INT_ADM_AARM (GIC_SPI_START + 21) |
| 52 | #define MSM8625_INT_ADSP_A11 (GIC_SPI_START + 22) |
| 53 | #define MSM8625_INT_ADSP_A9_A11 (GIC_SPI_START + 23) |
| 54 | #define MSM8625_INT_SDC1_0 (GIC_SPI_START + 24) |
| 55 | #define MSM8625_INT_SDC1_1 (GIC_SPI_START + 25) |
| 56 | #define MSM8625_INT_SDC2_0 (GIC_SPI_START + 26) |
| 57 | #define MSM8625_INT_SDC2_1 (GIC_SPI_START + 27) |
| 58 | #define MSM8625_INT_KEYSENSE (GIC_SPI_START + 28) |
| 59 | #define MSM8625_INT_TCHSCRN_SSBI (GIC_SPI_START + 29) |
| 60 | #define MSM8625_INT_TCHSCRN1 (GIC_SPI_START + 30) |
| 61 | #define MSM8625_INT_TCHSCRN2 (GIC_SPI_START + 31) |
| 62 | |
| 63 | #define MSM8625_INT_GPIO_GROUP1 (GIC_SPI_START + 32 + 0) |
| 64 | #define MSM8625_INT_GPIO_GROUP2 (GIC_SPI_START + 32 + 1) |
| 65 | #define MSM8625_INT_PWB_I2C (GIC_SPI_START + 32 + 2) |
| 66 | #define MSM8625_INT_SOFTRESET (GIC_SPI_START + 32 + 3) |
| 67 | #define MSM8625_INT_NAND_WR_ER_DONE (GIC_SPI_START + 32 + 4) |
| 68 | #define MSM8625_INT_NAND_OP_DONE (GIC_SPI_START + 32 + 5) |
| 69 | #define MSM8625_INT_PBUS_ARM11 (GIC_SPI_START + 32 + 6) |
| 70 | #define MSM8625_INT_AXI_MPU_SMI (GIC_SPI_START + 32 + 7) |
| 71 | #define MSM8625_INT_AXI_MPU_EBI1 (GIC_SPI_START + 32 + 8) |
| 72 | #define MSM8625_INT_AD_HSSD (GIC_SPI_START + 32 + 9) |
| 73 | #define MSM8625_INT_NOTUSED (GIC_SPI_START + 32 + 10) |
| 74 | #define MSM8625_INT_ARM11_DMA (GIC_SPI_START + 32 + 11) |
| 75 | #define MSM8625_INT_TSIF_IRQ (GIC_SPI_START + 32 + 12) |
| 76 | #define MSM8625_INT_UART1DM_IRQ (GIC_SPI_START + 32 + 13) |
| 77 | #define MSM8625_INT_UART1DM_RX (GIC_SPI_START + 32 + 14) |
| 78 | #define MSM8625_INT_USB_HS (GIC_SPI_START + 32 + 15) |
| 79 | #define MSM8625_INT_SDC3_0 (GIC_SPI_START + 32 + 16) |
| 80 | #define MSM8625_INT_SDC3_1 (GIC_SPI_START + 32 + 17) |
| 81 | #define MSM8625_INT_SDC4_0 (GIC_SPI_START + 32 + 18) |
| 82 | #define MSM8625_INT_SDC4_1 (GIC_SPI_START + 32 + 19) |
| 83 | #define MSM8625_INT_UART2DM_IRQ (GIC_SPI_START + 32 + 20) |
| 84 | #define MSM8625_INT_UART2DM_RX (GIC_SPI_START + 32 + 21) |
| 85 | #define MSM8625_INT_L2CC_EM (GIC_SPI_START + 32 + 22) |
| Ashwin Chaugule | 3deb6b8 | 2012-12-21 13:09:48 -0500 | [diff] [blame] | 86 | #define MSM8625_INT_SC_SICL2PERFMONIRPTREQ (GIC_SPI_START + 32 + 23) |
| Taniya Das | 43bcdd6 | 2011-12-02 17:33:27 +0530 | [diff] [blame] | 87 | #define MSM8625_INT_CE_IRQ (GIC_SPI_START + 32 + 24) |
| Kaushal Kumar | c0e5d67 | 2012-07-31 16:07:49 +0530 | [diff] [blame] | 88 | #define MSM8625_INT_CPR_IRQ0 (GIC_SPI_START + 32 + 25) |
| 89 | #define MSM8625_INT_CPR_IRQ1 (GIC_SPI_START + 32 + 26) |
| 90 | #define MSM8625_INT_CPR_IRQ2 (GIC_SPI_START + 32 + 27) |
| tirupathireddy | 1c543eb | 2012-09-20 16:37:01 +0530 | [diff] [blame] | 91 | #define MSM8625_INT_ACSR_MP_CORE_IPC2 (GIC_SPI_START + 32 + 28) |
| 92 | #define MSM8625_INT_ACSR_MP_CORE_IPC3 (GIC_SPI_START + 32 + 29) |
| Taniya Das | 43bcdd6 | 2011-12-02 17:33:27 +0530 | [diff] [blame] | 93 | |
| 94 | #define MSM8625_INT_ADSP_A11_SMSM MSM8625_INT_ADSP_A11 |
| 95 | #endif |