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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * sata_qstor.c - Pacific Digital Corporation QStor SATA
3 *
4 * Maintained by: Mark Lord <mlord@pobox.com>
5 *
6 * Copyright 2005 Pacific Digital Corporation.
7 * (OSL/GPL code release authorized by Jalil Fadavi).
8 *
Linus Torvalds1da177e2005-04-16 15:20:36 -07009 *
Jeff Garzikaf36d7f2005-08-28 20:18:39 -040010 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2, or (at your option)
13 * any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; see the file COPYING. If not, write to
22 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
23 *
24 *
25 * libata documentation is available via 'make {ps|pdf}docs',
26 * as Documentation/DocBook/libata.*
Linus Torvalds1da177e2005-04-16 15:20:36 -070027 *
28 */
29
30#include <linux/kernel.h>
31#include <linux/module.h>
32#include <linux/pci.h>
33#include <linux/init.h>
34#include <linux/blkdev.h>
35#include <linux/delay.h>
36#include <linux/interrupt.h>
Jeff Garzika9524a72005-10-30 14:39:11 -050037#include <linux/device.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070038#include <scsi/scsi_host.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070039#include <linux/libata.h>
40
41#define DRV_NAME "sata_qstor"
Jeff Garzik2a3103c2007-08-31 04:54:06 -040042#define DRV_VERSION "0.09"
Linus Torvalds1da177e2005-04-16 15:20:36 -070043
44enum {
Tejun Heo0d5ff562007-02-01 15:06:36 +090045 QS_MMIO_BAR = 4,
46
Linus Torvalds1da177e2005-04-16 15:20:36 -070047 QS_PORTS = 4,
48 QS_MAX_PRD = LIBATA_MAX_PRD,
49 QS_CPB_ORDER = 6,
50 QS_CPB_BYTES = (1 << QS_CPB_ORDER),
51 QS_PRD_BYTES = QS_MAX_PRD * 16,
52 QS_PKT_BYTES = QS_CPB_BYTES + QS_PRD_BYTES,
53
Linus Torvalds1da177e2005-04-16 15:20:36 -070054 /* global register offsets */
55 QS_HCF_CNFG3 = 0x0003, /* host configuration offset */
56 QS_HID_HPHY = 0x0004, /* host physical interface info */
57 QS_HCT_CTRL = 0x00e4, /* global interrupt mask offset */
58 QS_HST_SFF = 0x0100, /* host status fifo offset */
59 QS_HVS_SERD3 = 0x0393, /* PHY enable offset */
60
61 /* global control bits */
62 QS_HPHY_64BIT = (1 << 1), /* 64-bit bus detected */
63 QS_CNFG3_GSRST = 0x01, /* global chip reset */
64 QS_SERD3_PHY_ENA = 0xf0, /* PHY detection ENAble*/
65
66 /* per-channel register offsets */
67 QS_CCF_CPBA = 0x0710, /* chan CPB base address */
68 QS_CCF_CSEP = 0x0718, /* chan CPB separation factor */
69 QS_CFC_HUFT = 0x0800, /* host upstream fifo threshold */
70 QS_CFC_HDFT = 0x0804, /* host downstream fifo threshold */
71 QS_CFC_DUFT = 0x0808, /* dev upstream fifo threshold */
72 QS_CFC_DDFT = 0x080c, /* dev downstream fifo threshold */
73 QS_CCT_CTR0 = 0x0900, /* chan control-0 offset */
74 QS_CCT_CTR1 = 0x0901, /* chan control-1 offset */
75 QS_CCT_CFF = 0x0a00, /* chan command fifo offset */
76
77 /* channel control bits */
78 QS_CTR0_REG = (1 << 1), /* register mode (vs. pkt mode) */
79 QS_CTR0_CLER = (1 << 2), /* clear channel errors */
80 QS_CTR1_RDEV = (1 << 1), /* sata phy/comms reset */
81 QS_CTR1_RCHN = (1 << 4), /* reset channel logic */
82 QS_CCF_RUN_PKT = 0x107, /* RUN a new dma PKT */
83
84 /* pkt sub-field headers */
85 QS_HCB_HDR = 0x01, /* Host Control Block header */
86 QS_DCB_HDR = 0x02, /* Device Control Block header */
87
88 /* pkt HCB flag bits */
89 QS_HF_DIRO = (1 << 0), /* data DIRection Out */
90 QS_HF_DAT = (1 << 3), /* DATa pkt */
91 QS_HF_IEN = (1 << 4), /* Interrupt ENable */
92 QS_HF_VLD = (1 << 5), /* VaLiD pkt */
93
94 /* pkt DCB flag bits */
95 QS_DF_PORD = (1 << 2), /* Pio OR Dma */
96 QS_DF_ELBA = (1 << 3), /* Extended LBA (lba48) */
97
98 /* PCI device IDs */
99 board_2068_idx = 0, /* QStor 4-port SATA/RAID */
100};
101
Al Viro0420dd12005-10-21 06:46:02 +0100102enum {
103 QS_DMA_BOUNDARY = ~0UL
104};
105
Mark Lord12ee7d32007-11-07 10:52:55 -0500106typedef enum { qs_state_mmio, qs_state_pkt } qs_state_t;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700107
108struct qs_port_priv {
109 u8 *pkt;
110 dma_addr_t pkt_dma;
111 qs_state_t state;
112};
113
Tejun Heo82ef04f2008-07-31 17:02:40 +0900114static int qs_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
115static int qs_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
Jeff Garzik5796d1c2007-10-26 00:03:37 -0400116static int qs_ata_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700117static int qs_port_start(struct ata_port *ap);
Jeff Garzikcca39742006-08-24 03:19:22 -0400118static void qs_host_stop(struct ata_host *host);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700119static void qs_qc_prep(struct ata_queued_cmd *qc);
Tejun Heo9a3d9eb2006-01-23 13:09:36 +0900120static unsigned int qs_qc_issue(struct ata_queued_cmd *qc);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700121static int qs_check_atapi_dma(struct ata_queued_cmd *qc);
Alan Coxb73fc892005-08-26 16:03:19 +0100122static void qs_bmdma_stop(struct ata_queued_cmd *qc);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700123static u8 qs_bmdma_status(struct ata_port *ap);
Mark Lord6004bda2007-11-07 10:54:15 -0500124static void qs_freeze(struct ata_port *ap);
125static void qs_thaw(struct ata_port *ap);
Tejun Heoa1efdab2008-03-25 12:22:50 +0900126static int qs_prereset(struct ata_link *link, unsigned long deadline);
Mark Lord6004bda2007-11-07 10:54:15 -0500127static void qs_error_handler(struct ata_port *ap);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700128
Jeff Garzik193515d2005-11-07 00:59:37 -0500129static struct scsi_host_template qs_ata_sht = {
Tejun Heo68d1d072008-03-25 12:22:49 +0900130 ATA_BASE_SHT(DRV_NAME),
Linus Torvalds1da177e2005-04-16 15:20:36 -0700131 .sg_tablesize = QS_MAX_PRD,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700132 .dma_boundary = QS_DMA_BOUNDARY,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700133};
134
Tejun Heo029cfd62008-03-25 12:22:49 +0900135static struct ata_port_operations qs_ata_ops = {
136 .inherits = &ata_sff_port_ops,
137
Linus Torvalds1da177e2005-04-16 15:20:36 -0700138 .check_atapi_dma = qs_check_atapi_dma,
Tejun Heo029cfd62008-03-25 12:22:49 +0900139 .bmdma_stop = qs_bmdma_stop,
140 .bmdma_status = qs_bmdma_status,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700141 .qc_prep = qs_qc_prep,
142 .qc_issue = qs_qc_issue,
Tejun Heo029cfd62008-03-25 12:22:49 +0900143
Mark Lord6004bda2007-11-07 10:54:15 -0500144 .freeze = qs_freeze,
145 .thaw = qs_thaw,
Tejun Heoa1efdab2008-03-25 12:22:50 +0900146 .prereset = qs_prereset,
147 .softreset = ATA_OP_NULL,
Mark Lord6004bda2007-11-07 10:54:15 -0500148 .error_handler = qs_error_handler,
Tejun Heo029cfd62008-03-25 12:22:49 +0900149 .post_internal_cmd = ATA_OP_NULL,
Alan Coxc96f1732009-03-24 10:23:46 +0000150 .lost_interrupt = ATA_OP_NULL,
Tejun Heo029cfd62008-03-25 12:22:49 +0900151
Linus Torvalds1da177e2005-04-16 15:20:36 -0700152 .scr_read = qs_scr_read,
153 .scr_write = qs_scr_write,
Tejun Heo029cfd62008-03-25 12:22:49 +0900154
Linus Torvalds1da177e2005-04-16 15:20:36 -0700155 .port_start = qs_port_start,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700156 .host_stop = qs_host_stop,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700157};
158
Arjan van de Ven98ac62d2005-11-28 10:06:23 +0100159static const struct ata_port_info qs_port_info[] = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700160 /* board_2068_idx */
161 {
Jeff Garzikcca39742006-08-24 03:19:22 -0400162 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
Albert Leee50362e2005-09-27 17:39:50 +0800163 ATA_FLAG_MMIO | ATA_FLAG_PIO_POLLING,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100164 .pio_mask = ATA_PIO4_ONLY,
Jeff Garzikbf6263a2007-07-09 12:16:50 -0400165 .udma_mask = ATA_UDMA6,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700166 .port_ops = &qs_ata_ops,
167 },
168};
169
Jeff Garzik3b7d6972005-11-10 11:04:11 -0500170static const struct pci_device_id qs_ata_pci_tbl[] = {
Jeff Garzik2d2744f2006-09-28 20:21:59 -0400171 { PCI_VDEVICE(PDC, 0x2068), board_2068_idx },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700172
173 { } /* terminate list */
174};
175
176static struct pci_driver qs_ata_pci_driver = {
177 .name = DRV_NAME,
178 .id_table = qs_ata_pci_tbl,
179 .probe = qs_ata_init_one,
180 .remove = ata_pci_remove_one,
181};
182
Tejun Heo0d5ff562007-02-01 15:06:36 +0900183static void __iomem *qs_mmio_base(struct ata_host *host)
184{
185 return host->iomap[QS_MMIO_BAR];
186}
187
Linus Torvalds1da177e2005-04-16 15:20:36 -0700188static int qs_check_atapi_dma(struct ata_queued_cmd *qc)
189{
190 return 1; /* ATAPI DMA not supported */
191}
192
Jeff Garzikd18d36b2005-08-27 04:13:52 -0400193static void qs_bmdma_stop(struct ata_queued_cmd *qc)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700194{
195 /* nothing */
196}
197
198static u8 qs_bmdma_status(struct ata_port *ap)
199{
200 return 0;
201}
202
Linus Torvalds1da177e2005-04-16 15:20:36 -0700203static inline void qs_enter_reg_mode(struct ata_port *ap)
204{
Tejun Heo0d5ff562007-02-01 15:06:36 +0900205 u8 __iomem *chan = qs_mmio_base(ap->host) + (ap->port_no * 0x4000);
Mark Lord12ee7d32007-11-07 10:52:55 -0500206 struct qs_port_priv *pp = ap->private_data;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700207
Mark Lord12ee7d32007-11-07 10:52:55 -0500208 pp->state = qs_state_mmio;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700209 writeb(QS_CTR0_REG, chan + QS_CCT_CTR0);
210 readb(chan + QS_CCT_CTR0); /* flush */
211}
212
213static inline void qs_reset_channel_logic(struct ata_port *ap)
214{
Tejun Heo0d5ff562007-02-01 15:06:36 +0900215 u8 __iomem *chan = qs_mmio_base(ap->host) + (ap->port_no * 0x4000);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700216
217 writeb(QS_CTR1_RCHN, chan + QS_CCT_CTR1);
218 readb(chan + QS_CCT_CTR0); /* flush */
219 qs_enter_reg_mode(ap);
220}
221
Mark Lord6004bda2007-11-07 10:54:15 -0500222static void qs_freeze(struct ata_port *ap)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700223{
Mark Lord6004bda2007-11-07 10:54:15 -0500224 u8 __iomem *mmio_base = qs_mmio_base(ap->host);
225
226 writeb(0, mmio_base + QS_HCT_CTRL); /* disable host interrupts */
227 qs_enter_reg_mode(ap);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700228}
229
Mark Lord6004bda2007-11-07 10:54:15 -0500230static void qs_thaw(struct ata_port *ap)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700231{
Mark Lord6004bda2007-11-07 10:54:15 -0500232 u8 __iomem *mmio_base = qs_mmio_base(ap->host);
233
234 qs_enter_reg_mode(ap);
235 writeb(1, mmio_base + QS_HCT_CTRL); /* enable host interrupts */
236}
237
238static int qs_prereset(struct ata_link *link, unsigned long deadline)
239{
240 struct ata_port *ap = link->ap;
241
Linus Torvalds1da177e2005-04-16 15:20:36 -0700242 qs_reset_channel_logic(ap);
Tejun Heo9363c382008-04-07 22:47:16 +0900243 return ata_sff_prereset(link, deadline);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700244}
245
Tejun Heo82ef04f2008-07-31 17:02:40 +0900246static int qs_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700247{
248 if (sc_reg > SCR_CONTROL)
Tejun Heoda3dbb12007-07-16 14:29:40 +0900249 return -EINVAL;
Tejun Heo82ef04f2008-07-31 17:02:40 +0900250 *val = readl(link->ap->ioaddr.scr_addr + (sc_reg * 8));
Tejun Heoda3dbb12007-07-16 14:29:40 +0900251 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700252}
253
Mark Lord6004bda2007-11-07 10:54:15 -0500254static void qs_error_handler(struct ata_port *ap)
255{
256 qs_enter_reg_mode(ap);
Tejun Heoa1efdab2008-03-25 12:22:50 +0900257 ata_std_error_handler(ap);
Mark Lord6004bda2007-11-07 10:54:15 -0500258}
259
Tejun Heo82ef04f2008-07-31 17:02:40 +0900260static int qs_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700261{
262 if (sc_reg > SCR_CONTROL)
Tejun Heoda3dbb12007-07-16 14:29:40 +0900263 return -EINVAL;
Tejun Heo82ef04f2008-07-31 17:02:40 +0900264 writel(val, link->ap->ioaddr.scr_addr + (sc_reg * 8));
Tejun Heoda3dbb12007-07-16 14:29:40 +0900265 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700266}
267
Jeff Garzik828d09d2005-11-12 01:27:07 -0500268static unsigned int qs_fill_sg(struct ata_queued_cmd *qc)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700269{
Jeff Garzikcedc9a42005-10-05 07:13:30 -0400270 struct scatterlist *sg;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700271 struct ata_port *ap = qc->ap;
272 struct qs_port_priv *pp = ap->private_data;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700273 u8 *prd = pp->pkt + QS_CPB_BYTES;
Tejun Heoff2aeb12007-12-05 16:43:11 +0900274 unsigned int si;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700275
Tejun Heoff2aeb12007-12-05 16:43:11 +0900276 for_each_sg(qc->sg, sg, qc->n_elem, si) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700277 u64 addr;
278 u32 len;
279
280 addr = sg_dma_address(sg);
281 *(__le64 *)prd = cpu_to_le64(addr);
282 prd += sizeof(u64);
283
284 len = sg_dma_len(sg);
285 *(__le32 *)prd = cpu_to_le32(len);
286 prd += sizeof(u64);
287
Tejun Heoff2aeb12007-12-05 16:43:11 +0900288 VPRINTK("PRD[%u] = (0x%llX, 0x%X)\n", si,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700289 (unsigned long long)addr, len);
290 }
Jeff Garzik828d09d2005-11-12 01:27:07 -0500291
Tejun Heoff2aeb12007-12-05 16:43:11 +0900292 return si;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700293}
294
295static void qs_qc_prep(struct ata_queued_cmd *qc)
296{
297 struct qs_port_priv *pp = qc->ap->private_data;
298 u8 dflags = QS_DF_PORD, *buf = pp->pkt;
299 u8 hflags = QS_HF_DAT | QS_HF_IEN | QS_HF_VLD;
300 u64 addr;
Jeff Garzik828d09d2005-11-12 01:27:07 -0500301 unsigned int nelem;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700302
303 VPRINTK("ENTER\n");
304
305 qs_enter_reg_mode(qc->ap);
306 if (qc->tf.protocol != ATA_PROT_DMA) {
Tejun Heo9363c382008-04-07 22:47:16 +0900307 ata_sff_qc_prep(qc);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700308 return;
309 }
310
Jeff Garzik828d09d2005-11-12 01:27:07 -0500311 nelem = qs_fill_sg(qc);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700312
313 if ((qc->tf.flags & ATA_TFLAG_WRITE))
314 hflags |= QS_HF_DIRO;
315 if ((qc->tf.flags & ATA_TFLAG_LBA48))
316 dflags |= QS_DF_ELBA;
317
318 /* host control block (HCB) */
319 buf[ 0] = QS_HCB_HDR;
320 buf[ 1] = hflags;
Tejun Heo726f0782007-01-03 17:30:39 +0900321 *(__le32 *)(&buf[ 4]) = cpu_to_le32(qc->nbytes);
Jeff Garzik828d09d2005-11-12 01:27:07 -0500322 *(__le32 *)(&buf[ 8]) = cpu_to_le32(nelem);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700323 addr = ((u64)pp->pkt_dma) + QS_CPB_BYTES;
324 *(__le64 *)(&buf[16]) = cpu_to_le64(addr);
325
326 /* device control block (DCB) */
327 buf[24] = QS_DCB_HDR;
328 buf[28] = dflags;
329
330 /* frame information structure (FIS) */
Tejun Heo99771262007-07-16 14:29:38 +0900331 ata_tf_to_fis(&qc->tf, 0, 1, &buf[32]);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700332}
333
334static inline void qs_packet_start(struct ata_queued_cmd *qc)
335{
336 struct ata_port *ap = qc->ap;
Tejun Heo0d5ff562007-02-01 15:06:36 +0900337 u8 __iomem *chan = qs_mmio_base(ap->host) + (ap->port_no * 0x4000);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700338
339 VPRINTK("ENTER, ap %p\n", ap);
340
341 writeb(QS_CTR0_CLER, chan + QS_CCT_CTR0);
342 wmb(); /* flush PRDs and pkt to memory */
343 writel(QS_CCF_RUN_PKT, chan + QS_CCT_CFF);
344 readl(chan + QS_CCT_CFF); /* flush */
345}
346
Tejun Heo9a3d9eb2006-01-23 13:09:36 +0900347static unsigned int qs_qc_issue(struct ata_queued_cmd *qc)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700348{
349 struct qs_port_priv *pp = qc->ap->private_data;
350
351 switch (qc->tf.protocol) {
352 case ATA_PROT_DMA:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700353 pp->state = qs_state_pkt;
354 qs_packet_start(qc);
355 return 0;
356
Tejun Heo0dc36882007-12-18 16:34:43 -0500357 case ATAPI_PROT_DMA:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700358 BUG();
359 break;
360
361 default:
362 break;
363 }
364
365 pp->state = qs_state_mmio;
Tejun Heo9363c382008-04-07 22:47:16 +0900366 return ata_sff_qc_issue(qc);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700367}
368
Mark Lord6004bda2007-11-07 10:54:15 -0500369static void qs_do_or_die(struct ata_queued_cmd *qc, u8 status)
370{
371 qc->err_mask |= ac_err_mask(status);
372
373 if (!qc->err_mask) {
374 ata_qc_complete(qc);
375 } else {
376 struct ata_port *ap = qc->ap;
377 struct ata_eh_info *ehi = &ap->link.eh_info;
378
379 ata_ehi_clear_desc(ehi);
380 ata_ehi_push_desc(ehi, "status 0x%02X", status);
381
382 if (qc->err_mask == AC_ERR_DEV)
383 ata_port_abort(ap);
384 else
385 ata_port_freeze(ap);
386 }
387}
388
Jeff Garzikcca39742006-08-24 03:19:22 -0400389static inline unsigned int qs_intr_pkt(struct ata_host *host)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700390{
391 unsigned int handled = 0;
392 u8 sFFE;
Tejun Heo0d5ff562007-02-01 15:06:36 +0900393 u8 __iomem *mmio_base = qs_mmio_base(host);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700394
395 do {
396 u32 sff0 = readl(mmio_base + QS_HST_SFF);
397 u32 sff1 = readl(mmio_base + QS_HST_SFF + 4);
398 u8 sEVLD = (sff1 >> 30) & 0x01; /* valid flag */
399 sFFE = sff1 >> 31; /* empty flag */
400
401 if (sEVLD) {
402 u8 sDST = sff0 >> 16; /* dev status */
403 u8 sHST = sff1 & 0x3f; /* host status */
404 unsigned int port_no = (sff1 >> 8) & 0x03;
Jeff Garzikcca39742006-08-24 03:19:22 -0400405 struct ata_port *ap = host->ports[port_no];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700406
407 DPRINTK("SFF=%08x%08x: sCHAN=%u sHST=%d sDST=%02x\n",
408 sff1, sff0, port_no, sHST, sDST);
409 handled = 1;
Jeff Garzik029f5462006-04-02 10:30:40 -0400410 if (ap && !(ap->flags & ATA_FLAG_DISABLED)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700411 struct ata_queued_cmd *qc;
412 struct qs_port_priv *pp = ap->private_data;
413 if (!pp || pp->state != qs_state_pkt)
414 continue;
Tejun Heo9af5c9c2007-08-06 18:36:22 +0900415 qc = ata_qc_from_tag(ap, ap->link.active_tag);
Albert Leee50362e2005-09-27 17:39:50 +0800416 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700417 switch (sHST) {
Jeff Garzika7dac442005-10-30 04:44:42 -0500418 case 0: /* successful CPB */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700419 case 3: /* device error */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700420 qs_enter_reg_mode(qc->ap);
Mark Lord6004bda2007-11-07 10:54:15 -0500421 qs_do_or_die(qc, sDST);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700422 break;
423 default:
424 break;
425 }
426 }
427 }
428 }
429 } while (!sFFE);
430 return handled;
431}
432
Jeff Garzikcca39742006-08-24 03:19:22 -0400433static inline unsigned int qs_intr_mmio(struct ata_host *host)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700434{
435 unsigned int handled = 0, port_no;
436
Jeff Garzikcca39742006-08-24 03:19:22 -0400437 for (port_no = 0; port_no < host->n_ports; ++port_no) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700438 struct ata_port *ap;
Jeff Garzikcca39742006-08-24 03:19:22 -0400439 ap = host->ports[port_no];
Tejun Heoc1389502005-08-22 14:59:24 +0900440 if (ap &&
Jeff Garzik029f5462006-04-02 10:30:40 -0400441 !(ap->flags & ATA_FLAG_DISABLED)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700442 struct ata_queued_cmd *qc;
Mark Lord904c7ba2007-11-07 10:53:41 -0500443 struct qs_port_priv *pp;
444 qc = ata_qc_from_tag(ap, ap->link.active_tag);
445 if (!qc || !(qc->flags & ATA_QCFLAG_ACTIVE)) {
446 /*
447 * The qstor hardware generates spurious
448 * interrupts from time to time when switching
449 * in and out of packet mode.
450 * There's no obvious way to know if we're
451 * here now due to that, so just ack the irq
452 * and pretend we knew it was ours.. (ugh).
453 * This does not affect packet mode.
454 */
Tejun Heo9363c382008-04-07 22:47:16 +0900455 ata_sff_check_status(ap);
Mark Lord904c7ba2007-11-07 10:53:41 -0500456 handled = 1;
457 continue;
458 }
459 pp = ap->private_data;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700460 if (!pp || pp->state != qs_state_mmio)
461 continue;
Mark Lord904c7ba2007-11-07 10:53:41 -0500462 if (!(qc->tf.flags & ATA_TFLAG_POLLING))
Tejun Heo9363c382008-04-07 22:47:16 +0900463 handled |= ata_sff_host_intr(ap, qc);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700464 }
465 }
466 return handled;
467}
468
David Howells7d12e782006-10-05 14:55:46 +0100469static irqreturn_t qs_intr(int irq, void *dev_instance)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700470{
Jeff Garzikcca39742006-08-24 03:19:22 -0400471 struct ata_host *host = dev_instance;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700472 unsigned int handled = 0;
Mark Lord904c7ba2007-11-07 10:53:41 -0500473 unsigned long flags;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700474
475 VPRINTK("ENTER\n");
476
Mark Lord904c7ba2007-11-07 10:53:41 -0500477 spin_lock_irqsave(&host->lock, flags);
Jeff Garzikcca39742006-08-24 03:19:22 -0400478 handled = qs_intr_pkt(host) | qs_intr_mmio(host);
Mark Lord904c7ba2007-11-07 10:53:41 -0500479 spin_unlock_irqrestore(&host->lock, flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700480
481 VPRINTK("EXIT\n");
482
483 return IRQ_RETVAL(handled);
484}
485
Tejun Heo0d5ff562007-02-01 15:06:36 +0900486static void qs_ata_setup_port(struct ata_ioports *port, void __iomem *base)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700487{
488 port->cmd_addr =
489 port->data_addr = base + 0x400;
490 port->error_addr =
491 port->feature_addr = base + 0x408; /* hob_feature = 0x409 */
492 port->nsect_addr = base + 0x410; /* hob_nsect = 0x411 */
493 port->lbal_addr = base + 0x418; /* hob_lbal = 0x419 */
494 port->lbam_addr = base + 0x420; /* hob_lbam = 0x421 */
495 port->lbah_addr = base + 0x428; /* hob_lbah = 0x429 */
496 port->device_addr = base + 0x430;
497 port->status_addr =
498 port->command_addr = base + 0x438;
499 port->altstatus_addr =
500 port->ctl_addr = base + 0x440;
501 port->scr_addr = base + 0xc00;
502}
503
504static int qs_port_start(struct ata_port *ap)
505{
Jeff Garzikcca39742006-08-24 03:19:22 -0400506 struct device *dev = ap->host->dev;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700507 struct qs_port_priv *pp;
Tejun Heo0d5ff562007-02-01 15:06:36 +0900508 void __iomem *mmio_base = qs_mmio_base(ap->host);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700509 void __iomem *chan = mmio_base + (ap->port_no * 0x4000);
510 u64 addr;
511 int rc;
512
513 rc = ata_port_start(ap);
514 if (rc)
515 return rc;
Tejun Heo24dc5f32007-01-20 16:00:28 +0900516 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
517 if (!pp)
518 return -ENOMEM;
519 pp->pkt = dmam_alloc_coherent(dev, QS_PKT_BYTES, &pp->pkt_dma,
520 GFP_KERNEL);
521 if (!pp->pkt)
522 return -ENOMEM;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700523 memset(pp->pkt, 0, QS_PKT_BYTES);
524 ap->private_data = pp;
525
Mark Lord12ee7d32007-11-07 10:52:55 -0500526 qs_enter_reg_mode(ap);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700527 addr = (u64)pp->pkt_dma;
528 writel((u32) addr, chan + QS_CCF_CPBA);
529 writel((u32)(addr >> 32), chan + QS_CCF_CPBA + 4);
530 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700531}
532
Jeff Garzikcca39742006-08-24 03:19:22 -0400533static void qs_host_stop(struct ata_host *host)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700534{
Tejun Heo0d5ff562007-02-01 15:06:36 +0900535 void __iomem *mmio_base = qs_mmio_base(host);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700536
537 writeb(0, mmio_base + QS_HCT_CTRL); /* disable host interrupts */
538 writeb(QS_CNFG3_GSRST, mmio_base + QS_HCF_CNFG3); /* global reset */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700539}
540
Tejun Heo4447d352007-04-17 23:44:08 +0900541static void qs_host_init(struct ata_host *host, unsigned int chip_id)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700542{
Tejun Heo4447d352007-04-17 23:44:08 +0900543 void __iomem *mmio_base = host->iomap[QS_MMIO_BAR];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700544 unsigned int port_no;
545
546 writeb(0, mmio_base + QS_HCT_CTRL); /* disable host interrupts */
547 writeb(QS_CNFG3_GSRST, mmio_base + QS_HCF_CNFG3); /* global reset */
548
549 /* reset each channel in turn */
Tejun Heo4447d352007-04-17 23:44:08 +0900550 for (port_no = 0; port_no < host->n_ports; ++port_no) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700551 u8 __iomem *chan = mmio_base + (port_no * 0x4000);
552 writeb(QS_CTR1_RDEV|QS_CTR1_RCHN, chan + QS_CCT_CTR1);
553 writeb(QS_CTR0_REG, chan + QS_CCT_CTR0);
554 readb(chan + QS_CCT_CTR0); /* flush */
555 }
556 writeb(QS_SERD3_PHY_ENA, mmio_base + QS_HVS_SERD3); /* enable phy */
557
Tejun Heo4447d352007-04-17 23:44:08 +0900558 for (port_no = 0; port_no < host->n_ports; ++port_no) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700559 u8 __iomem *chan = mmio_base + (port_no * 0x4000);
560 /* set FIFO depths to same settings as Windows driver */
561 writew(32, chan + QS_CFC_HUFT);
562 writew(32, chan + QS_CFC_HDFT);
563 writew(10, chan + QS_CFC_DUFT);
564 writew( 8, chan + QS_CFC_DDFT);
565 /* set CPB size in bytes, as a power of two */
566 writeb(QS_CPB_ORDER, chan + QS_CCF_CSEP);
567 }
568 writeb(1, mmio_base + QS_HCT_CTRL); /* enable host interrupts */
569}
570
571/*
572 * The QStor understands 64-bit buses, and uses 64-bit fields
573 * for DMA pointers regardless of bus width. We just have to
574 * make sure our DMA masks are set appropriately for whatever
575 * bridge lies between us and the QStor, and then the DMA mapping
576 * code will ensure we only ever "see" appropriate buffer addresses.
577 * If we're 32-bit limited somewhere, then our 64-bit fields will
578 * just end up with zeros in the upper 32-bits, without any special
579 * logic required outside of this routine (below).
580 */
581static int qs_set_dma_masks(struct pci_dev *pdev, void __iomem *mmio_base)
582{
583 u32 bus_info = readl(mmio_base + QS_HID_HPHY);
584 int rc, have_64bit_bus = (bus_info & QS_HPHY_64BIT);
585
586 if (have_64bit_bus &&
Yang Hongyang6a355282009-04-06 19:01:13 -0700587 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
588 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700589 if (rc) {
Yang Hongyang284901a2009-04-06 19:01:15 -0700590 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700591 if (rc) {
Jeff Garzika9524a72005-10-30 14:39:11 -0500592 dev_printk(KERN_ERR, &pdev->dev,
593 "64-bit DMA enable failed\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700594 return rc;
595 }
596 }
597 } else {
Yang Hongyang284901a2009-04-06 19:01:15 -0700598 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700599 if (rc) {
Jeff Garzika9524a72005-10-30 14:39:11 -0500600 dev_printk(KERN_ERR, &pdev->dev,
601 "32-bit DMA enable failed\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700602 return rc;
603 }
Yang Hongyang284901a2009-04-06 19:01:15 -0700604 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700605 if (rc) {
Jeff Garzika9524a72005-10-30 14:39:11 -0500606 dev_printk(KERN_ERR, &pdev->dev,
607 "32-bit consistent DMA enable failed\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700608 return rc;
609 }
610 }
611 return 0;
612}
613
614static int qs_ata_init_one(struct pci_dev *pdev,
615 const struct pci_device_id *ent)
616{
617 static int printed_version;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700618 unsigned int board_idx = (unsigned int) ent->driver_data;
Tejun Heo4447d352007-04-17 23:44:08 +0900619 const struct ata_port_info *ppi[] = { &qs_port_info[board_idx], NULL };
620 struct ata_host *host;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700621 int rc, port_no;
622
623 if (!printed_version++)
Jeff Garzika9524a72005-10-30 14:39:11 -0500624 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700625
Tejun Heo4447d352007-04-17 23:44:08 +0900626 /* alloc host */
627 host = ata_host_alloc_pinfo(&pdev->dev, ppi, QS_PORTS);
628 if (!host)
629 return -ENOMEM;
630
631 /* acquire resources and fill host */
Tejun Heo24dc5f32007-01-20 16:00:28 +0900632 rc = pcim_enable_device(pdev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700633 if (rc)
634 return rc;
635
Tejun Heo0d5ff562007-02-01 15:06:36 +0900636 if ((pci_resource_flags(pdev, QS_MMIO_BAR) & IORESOURCE_MEM) == 0)
Tejun Heo24dc5f32007-01-20 16:00:28 +0900637 return -ENODEV;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700638
Tejun Heo0d5ff562007-02-01 15:06:36 +0900639 rc = pcim_iomap_regions(pdev, 1 << QS_MMIO_BAR, DRV_NAME);
640 if (rc)
641 return rc;
Tejun Heo4447d352007-04-17 23:44:08 +0900642 host->iomap = pcim_iomap_table(pdev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700643
Tejun Heo4447d352007-04-17 23:44:08 +0900644 rc = qs_set_dma_masks(pdev, host->iomap[QS_MMIO_BAR]);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700645 if (rc)
Tejun Heo24dc5f32007-01-20 16:00:28 +0900646 return rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700647
Tejun Heo4447d352007-04-17 23:44:08 +0900648 for (port_no = 0; port_no < host->n_ports; ++port_no) {
Tejun Heocbcdd872007-08-18 13:14:55 +0900649 struct ata_port *ap = host->ports[port_no];
650 unsigned int offset = port_no * 0x4000;
651 void __iomem *chan = host->iomap[QS_MMIO_BAR] + offset;
652
653 qs_ata_setup_port(&ap->ioaddr, chan);
654
655 ata_port_pbar_desc(ap, QS_MMIO_BAR, -1, "mmio");
656 ata_port_pbar_desc(ap, QS_MMIO_BAR, offset, "port");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700657 }
658
Linus Torvalds1da177e2005-04-16 15:20:36 -0700659 /* initialize adapter */
Tejun Heo4447d352007-04-17 23:44:08 +0900660 qs_host_init(host, board_idx);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700661
Tejun Heo4447d352007-04-17 23:44:08 +0900662 pci_set_master(pdev);
663 return ata_host_activate(host, pdev->irq, qs_intr, IRQF_SHARED,
664 &qs_ata_sht);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700665}
666
667static int __init qs_ata_init(void)
668{
Pavel Roskinb7887192006-08-10 18:13:18 +0900669 return pci_register_driver(&qs_ata_pci_driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700670}
671
672static void __exit qs_ata_exit(void)
673{
674 pci_unregister_driver(&qs_ata_pci_driver);
675}
676
677MODULE_AUTHOR("Mark Lord");
678MODULE_DESCRIPTION("Pacific Digital Corporation QStor SATA low-level driver");
679MODULE_LICENSE("GPL");
680MODULE_DEVICE_TABLE(pci, qs_ata_pci_tbl);
681MODULE_VERSION(DRV_VERSION);
682
683module_init(qs_ata_init);
684module_exit(qs_ata_exit);