| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | #ifndef __MATROXFB_DAC1064_H__ |
| 2 | #define __MATROXFB_DAC1064_H__ |
| 3 | |
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4 | |
| 5 | #include "matroxfb_base.h" |
| 6 | |
| 7 | #ifdef CONFIG_FB_MATROX_MYSTIQUE |
| 8 | extern struct matrox_switch matrox_mystique; |
| 9 | #endif |
| 10 | #ifdef CONFIG_FB_MATROX_G |
| 11 | extern struct matrox_switch matrox_G100; |
| 12 | #endif |
| 13 | #ifdef NEED_DAC1064 |
| 14 | void DAC1064_global_init(WPMINFO2); |
| 15 | void DAC1064_global_restore(WPMINFO2); |
| 16 | #endif |
| 17 | |
| 18 | #define M1064_INDEX 0x00 |
| 19 | #define M1064_PALWRADD 0x00 |
| 20 | #define M1064_PALDATA 0x01 |
| 21 | #define M1064_PIXRDMSK 0x02 |
| 22 | #define M1064_PALRDADD 0x03 |
| 23 | #define M1064_X_DATAREG 0x0A |
| 24 | #define M1064_CURPOSXL 0x0C /* can be accessed as DWORD */ |
| 25 | #define M1064_CURPOSXH 0x0D |
| 26 | #define M1064_CURPOSYL 0x0E |
| 27 | #define M1064_CURPOSYH 0x0F |
| 28 | |
| 29 | #define M1064_XCURADDL 0x04 |
| 30 | #define M1064_XCURADDH 0x05 |
| 31 | #define M1064_XCURCTRL 0x06 |
| 32 | #define M1064_XCURCTRL_DIS 0x00 /* transparent, transparent, transparent, transparent */ |
| 33 | #define M1064_XCURCTRL_3COLOR 0x01 /* transparent, 0, 1, 2 */ |
| 34 | #define M1064_XCURCTRL_XGA 0x02 /* 0, 1, transparent, complement */ |
| 35 | #define M1064_XCURCTRL_XWIN 0x03 /* transparent, transparent, 0, 1 */ |
| 36 | #define M1064_XCURCOL0RED 0x08 |
| 37 | #define M1064_XCURCOL0GREEN 0x09 |
| 38 | #define M1064_XCURCOL0BLUE 0x0A |
| 39 | #define M1064_XCURCOL1RED 0x0C |
| 40 | #define M1064_XCURCOL1GREEN 0x0D |
| 41 | #define M1064_XCURCOL1BLUE 0x0E |
| Paul A. Clarke | 6d39bed | 2006-05-20 14:59:51 -0700 | [diff] [blame] | 42 | #define M1064_XDVICLKCTRL 0x0F |
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 43 | #define M1064_XCURCOL2RED 0x10 |
| 44 | #define M1064_XCURCOL2GREEN 0x11 |
| 45 | #define M1064_XCURCOL2BLUE 0x12 |
| 46 | #define DAC1064_XVREFCTRL 0x18 |
| 47 | #define DAC1064_XVREFCTRL_INTERNAL 0x3F |
| 48 | #define DAC1064_XVREFCTRL_EXTERNAL 0x00 |
| 49 | #define DAC1064_XVREFCTRL_G100_DEFAULT 0x03 |
| 50 | #define M1064_XMULCTRL 0x19 |
| 51 | #define M1064_XMULCTRL_DEPTH_8BPP 0x00 /* 8 bpp paletized */ |
| 52 | #define M1064_XMULCTRL_DEPTH_15BPP_1BPP 0x01 /* 15 bpp paletized + 1 bpp overlay */ |
| 53 | #define M1064_XMULCTRL_DEPTH_16BPP 0x02 /* 16 bpp paletized */ |
| 54 | #define M1064_XMULCTRL_DEPTH_24BPP 0x03 /* 24 bpp paletized */ |
| 55 | #define M1064_XMULCTRL_DEPTH_24BPP_8BPP 0x04 /* 24 bpp direct + 8 bpp overlay paletized */ |
| 56 | #define M1064_XMULCTRL_2G8V16 0x05 /* 15 bpp video direct, half xres, 8bpp paletized */ |
| 57 | #define M1064_XMULCTRL_G16V16 0x06 /* 15 bpp video, 15bpp graphics, one of them paletized */ |
| 58 | #define M1064_XMULCTRL_DEPTH_32BPP 0x07 /* 24 bpp paletized + 8 bpp unused */ |
| 59 | #define M1064_XMULCTRL_GRAPHICS_PALETIZED 0x00 |
| 60 | #define M1064_XMULCTRL_VIDEO_PALETIZED 0x08 |
| 61 | #define M1064_XPIXCLKCTRL 0x1A |
| 62 | #define M1064_XPIXCLKCTRL_SRC_PCI 0x00 |
| 63 | #define M1064_XPIXCLKCTRL_SRC_PLL 0x01 |
| 64 | #define M1064_XPIXCLKCTRL_SRC_EXT 0x02 |
| 65 | #define M1064_XPIXCLKCTRL_SRC_SYS 0x03 /* G200/G400 */ |
| 66 | #define M1064_XPIXCLKCTRL_SRC_PLL2 0x03 /* G450 */ |
| 67 | #define M1064_XPIXCLKCTRL_SRC_MASK 0x03 |
| 68 | #define M1064_XPIXCLKCTRL_EN 0x00 |
| 69 | #define M1064_XPIXCLKCTRL_DIS 0x04 |
| 70 | #define M1064_XPIXCLKCTRL_PLL_DOWN 0x00 |
| 71 | #define M1064_XPIXCLKCTRL_PLL_UP 0x08 |
| 72 | #define M1064_XGENCTRL 0x1D |
| 73 | #define M1064_XGENCTRL_VS_0 0x00 |
| 74 | #define M1064_XGENCTRL_VS_1 0x01 |
| 75 | #define M1064_XGENCTRL_ALPHA_DIS 0x00 |
| 76 | #define M1064_XGENCTRL_ALPHA_EN 0x02 |
| 77 | #define M1064_XGENCTRL_BLACK_0IRE 0x00 |
| 78 | #define M1064_XGENCTRL_BLACK_75IRE 0x10 |
| 79 | #define M1064_XGENCTRL_SYNC_ON_GREEN 0x00 |
| 80 | #define M1064_XGENCTRL_NO_SYNC_ON_GREEN 0x20 |
| 81 | #define M1064_XGENCTRL_SYNC_ON_GREEN_MASK 0x20 |
| 82 | #define M1064_XMISCCTRL 0x1E |
| 83 | #define M1064_XMISCCTRL_DAC_DIS 0x00 |
| 84 | #define M1064_XMISCCTRL_DAC_EN 0x01 |
| 85 | #define M1064_XMISCCTRL_MFC_VGA 0x00 |
| 86 | #define M1064_XMISCCTRL_MFC_MAFC 0x02 |
| 87 | #define M1064_XMISCCTRL_MFC_DIS 0x06 |
| 88 | #define GX00_XMISCCTRL_MFC_MAFC 0x02 |
| 89 | #define GX00_XMISCCTRL_MFC_PANELLINK 0x04 |
| 90 | #define GX00_XMISCCTRL_MFC_DIS 0x06 |
| 91 | #define GX00_XMISCCTRL_MFC_MASK 0x06 |
| 92 | #define M1064_XMISCCTRL_DAC_6BIT 0x00 |
| 93 | #define M1064_XMISCCTRL_DAC_8BIT 0x08 |
| 94 | #define M1064_XMISCCTRL_DAC_WIDTHMASK 0x08 |
| 95 | #define M1064_XMISCCTRL_LUT_DIS 0x00 |
| 96 | #define M1064_XMISCCTRL_LUT_EN 0x10 |
| 97 | #define G400_XMISCCTRL_VDO_MAFC12 0x00 |
| 98 | #define G400_XMISCCTRL_VDO_BYPASS656 0x40 |
| 99 | #define G400_XMISCCTRL_VDO_C2_MAFC12 0x80 |
| 100 | #define G400_XMISCCTRL_VDO_C2_BYPASS656 0xC0 |
| 101 | #define G400_XMISCCTRL_VDO_MASK 0xE0 |
| 102 | #define M1064_XGENIOCTRL 0x2A |
| 103 | #define M1064_XGENIODATA 0x2B |
| 104 | #define DAC1064_XSYSPLLM 0x2C |
| 105 | #define DAC1064_XSYSPLLN 0x2D |
| 106 | #define DAC1064_XSYSPLLP 0x2E |
| 107 | #define DAC1064_XSYSPLLSTAT 0x2F |
| 108 | #define M1064_XZOOMCTRL 0x38 |
| 109 | #define M1064_XZOOMCTRL_1 0x00 |
| 110 | #define M1064_XZOOMCTRL_2 0x01 |
| 111 | #define M1064_XZOOMCTRL_4 0x03 |
| 112 | #define M1064_XSENSETEST 0x3A |
| 113 | #define M1064_XSENSETEST_BCOMP 0x01 |
| 114 | #define M1064_XSENSETEST_GCOMP 0x02 |
| 115 | #define M1064_XSENSETEST_RCOMP 0x04 |
| 116 | #define M1064_XSENSETEST_PDOWN 0x00 |
| 117 | #define M1064_XSENSETEST_PUP 0x80 |
| 118 | #define M1064_XCRCREML 0x3C |
| 119 | #define M1064_XCRCREMH 0x3D |
| 120 | #define M1064_XCRCBITSEL 0x3E |
| 121 | #define M1064_XCOLKEYMASKL 0x40 |
| 122 | #define M1064_XCOLKEYMASKH 0x41 |
| 123 | #define M1064_XCOLKEYL 0x42 |
| 124 | #define M1064_XCOLKEYH 0x43 |
| 125 | #define M1064_XPIXPLLAM 0x44 |
| 126 | #define M1064_XPIXPLLAN 0x45 |
| 127 | #define M1064_XPIXPLLAP 0x46 |
| 128 | #define M1064_XPIXPLLBM 0x48 |
| 129 | #define M1064_XPIXPLLBN 0x49 |
| 130 | #define M1064_XPIXPLLBP 0x4A |
| 131 | #define M1064_XPIXPLLCM 0x4C |
| 132 | #define M1064_XPIXPLLCN 0x4D |
| 133 | #define M1064_XPIXPLLCP 0x4E |
| 134 | #define M1064_XPIXPLLSTAT 0x4F |
| 135 | |
| 136 | #define M1064_XTVO_IDX 0x87 |
| 137 | #define M1064_XTVO_DATA 0x88 |
| 138 | |
| 139 | #define M1064_XOUTPUTCONN 0x8A |
| 140 | #define M1064_XSYNCCTRL 0x8B |
| 141 | #define M1064_XVIDPLLSTAT 0x8C |
| 142 | #define M1064_XVIDPLLP 0x8D |
| 143 | #define M1064_XVIDPLLM 0x8E |
| 144 | #define M1064_XVIDPLLN 0x8F |
| 145 | |
| 146 | #define M1064_XPWRCTRL 0xA0 |
| Paul A. Clarke | 6d39bed | 2006-05-20 14:59:51 -0700 | [diff] [blame] | 147 | #define M1064_XPWRCTRL_PANELPDN 0x04 |
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 148 | |
| 149 | #define M1064_XPANMODE 0xA2 |
| 150 | |
| 151 | enum POS1064 { |
| 152 | POS1064_XCURADDL=0, POS1064_XCURADDH, POS1064_XCURCTRL, |
| 153 | POS1064_XCURCOL0RED, POS1064_XCURCOL0GREEN, POS1064_XCURCOL0BLUE, |
| 154 | POS1064_XCURCOL1RED, POS1064_XCURCOL1GREEN, POS1064_XCURCOL1BLUE, |
| 155 | POS1064_XCURCOL2RED, POS1064_XCURCOL2GREEN, POS1064_XCURCOL2BLUE, |
| 156 | POS1064_XVREFCTRL, POS1064_XMULCTRL, POS1064_XPIXCLKCTRL, POS1064_XGENCTRL, |
| 157 | POS1064_XMISCCTRL, |
| 158 | POS1064_XGENIOCTRL, POS1064_XGENIODATA, POS1064_XZOOMCTRL, POS1064_XSENSETEST, |
| 159 | POS1064_XCRCBITSEL, |
| 160 | POS1064_XCOLKEYMASKL, POS1064_XCOLKEYMASKH, POS1064_XCOLKEYL, POS1064_XCOLKEYH, |
| 161 | POS1064_XOUTPUTCONN, POS1064_XPANMODE, POS1064_XPWRCTRL }; |
| 162 | |
| 163 | |
| 164 | #endif /* __MATROXFB_DAC1064_H__ */ |