Gitiles
Code Review Sign In
gerrit-public.fairphone.software / kernel / msm / 056cb48a2fb6fb31debf665695a9f97b45cfb8ec / . / drivers / net / tulip / de4x5.c
blob: ee48bfd6734938a0e241170e320b1335ee6dac7c [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1/* de4x5.c: A DIGITAL DC21x4x DECchip and DE425/DE434/DE435/DE450/DE500
2 ethernet driver for Linux.
3
4 Copyright 1994, 1995 Digital Equipment Corporation.
5
6 Testing resources for this driver have been made available
7 in part by NASA Ames Research Center (mjacob@nas.nasa.gov).
8
9 The author may be reached at davies@maniac.ultranet.com.
10
11 This program is free software; you can redistribute it and/or modify it
12 under the terms of the GNU General Public License as published by the
13 Free Software Foundation; either version 2 of the License, or (at your
14 option) any later version.
15
16 THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
17 WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
19 NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
22 USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
23 ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25 THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26
27 You should have received a copy of the GNU General Public License along
28 with this program; if not, write to the Free Software Foundation, Inc.,
29 675 Mass Ave, Cambridge, MA 02139, USA.
30
31 Originally, this driver was written for the Digital Equipment
32 Corporation series of EtherWORKS ethernet cards:
33
34 DE425 TP/COAX EISA
35 DE434 TP PCI
36 DE435 TP/COAX/AUI PCI
37 DE450 TP/COAX/AUI PCI
38 DE500 10/100 PCI Fasternet
39
40 but it will now attempt to support all cards which conform to the
41 Digital Semiconductor SROM Specification. The driver currently
42 recognises the following chips:
43
44 DC21040 (no SROM)
45 DC21041[A]
46 DC21140[A]
47 DC21142
48 DC21143
49
50 So far the driver is known to work with the following cards:
51
52 KINGSTON
53 Linksys
54 ZNYX342
55 SMC8432
56 SMC9332 (w/new SROM)
57 ZNYX31[45]
58 ZNYX346 10/100 4 port (can act as a 10/100 bridge!)
59
60 The driver has been tested on a relatively busy network using the DE425,
61 DE434, DE435 and DE500 cards and benchmarked with 'ttcp': it transferred
62 16M of data to a DECstation 5000/200 as follows:
63
64 TCP UDP
65 TX RX TX RX
66 DE425 1030k 997k 1170k 1128k
67 DE434 1063k 995k 1170k 1125k
68 DE435 1063k 995k 1170k 1125k
69 DE500 1063k 998k 1170k 1125k in 10Mb/s mode
70
71 All values are typical (in kBytes/sec) from a sample of 4 for each
72 measurement. Their error is +/-20k on a quiet (private) network and also
73 depend on what load the CPU has.
74
75 =========================================================================
76 This driver has been written substantially from scratch, although its
77 inheritance of style and stack interface from 'ewrk3.c' and in turn from
78 Donald Becker's 'lance.c' should be obvious. With the module autoload of
79 every usable DECchip board, I pinched Donald's 'next_module' field to
80 link my modules together.
81
82 Upto 15 EISA cards can be supported under this driver, limited primarily
83 by the available IRQ lines. I have checked different configurations of
84 multiple depca, EtherWORKS 3 cards and de4x5 cards and have not found a
85 problem yet (provided you have at least depca.c v0.38) ...
86
87 PCI support has been added to allow the driver to work with the DE434,
88 DE435, DE450 and DE500 cards. The I/O accesses are a bit of a kludge due
89 to the differences in the EISA and PCI CSR address offsets from the base
90 address.
91
92 The ability to load this driver as a loadable module has been included
93 and used extensively during the driver development (to save those long
94 reboot sequences). Loadable module support under PCI and EISA has been
95 achieved by letting the driver autoprobe as if it were compiled into the
96 kernel. Do make sure you're not sharing interrupts with anything that
97 cannot accommodate interrupt sharing!
98
99 To utilise this ability, you have to do 8 things:
100
101 0) have a copy of the loadable modules code installed on your system.
102 1) copy de4x5.c from the /linux/drivers/net directory to your favourite
103 temporary directory.
104 2) for fixed autoprobes (not recommended), edit the source code near
105 line 5594 to reflect the I/O address you're using, or assign these when
106 loading by:
107
108 insmod de4x5 io=0xghh where g = bus number
109 hh = device number
110
111 NB: autoprobing for modules is now supported by default. You may just
112 use:
113
114 insmod de4x5
115
116 to load all available boards. For a specific board, still use
117 the 'io=?' above.
118 3) compile de4x5.c, but include -DMODULE in the command line to ensure
119 that the correct bits are compiled (see end of source code).
120 4) if you are wanting to add a new card, goto 5. Otherwise, recompile a
121 kernel with the de4x5 configuration turned off and reboot.
122 5) insmod de4x5 [io=0xghh]
123 6) run the net startup bits for your new eth?? interface(s) manually
124 (usually /etc/rc.inet[12] at boot time).
125 7) enjoy!
126
127 To unload a module, turn off the associated interface(s)
128 'ifconfig eth?? down' then 'rmmod de4x5'.
129
130 Automedia detection is included so that in principal you can disconnect
131 from, e.g. TP, reconnect to BNC and things will still work (after a
132 pause whilst the driver figures out where its media went). My tests
133 using ping showed that it appears to work....
134
135 By default, the driver will now autodetect any DECchip based card.
136 Should you have a need to restrict the driver to DIGITAL only cards, you
137 can compile with a DEC_ONLY define, or if loading as a module, use the
138 'dec_only=1' parameter.
139
140 I've changed the timing routines to use the kernel timer and scheduling
141 functions so that the hangs and other assorted problems that occurred
142 while autosensing the media should be gone. A bonus for the DC21040
143 auto media sense algorithm is that it can now use one that is more in
144 line with the rest (the DC21040 chip doesn't have a hardware timer).
145 The downside is the 1 'jiffies' (10ms) resolution.
146
147 IEEE 802.3u MII interface code has been added in anticipation that some
148 products may use it in the future.
149
150 The SMC9332 card has a non-compliant SROM which needs fixing - I have
151 patched this driver to detect it because the SROM format used complies
152 to a previous DEC-STD format.
153
154 I have removed the buffer copies needed for receive on Intels. I cannot
155 remove them for Alphas since the Tulip hardware only does longword
156 aligned DMA transfers and the Alphas get alignment traps with non
157 longword aligned data copies (which makes them really slow). No comment.
158
159 I have added SROM decoding routines to make this driver work with any
160 card that supports the Digital Semiconductor SROM spec. This will help
161 all cards running the dc2114x series chips in particular. Cards using
162 the dc2104x chips should run correctly with the basic driver. I'm in
163 debt to <mjacob@feral.com> for the testing and feedback that helped get
164 this feature working. So far we have tested KINGSTON, SMC8432, SMC9332
165 (with the latest SROM complying with the SROM spec V3: their first was
166 broken), ZNYX342 and LinkSys. ZYNX314 (dual 21041 MAC) and ZNYX 315
167 (quad 21041 MAC) cards also appear to work despite their incorrectly
168 wired IRQs.
169
170 I have added a temporary fix for interrupt problems when some SCSI cards
171 share the same interrupt as the DECchip based cards. The problem occurs
172 because the SCSI card wants to grab the interrupt as a fast interrupt
173 (runs the service routine with interrupts turned off) vs. this card
174 which really needs to run the service routine with interrupts turned on.
175 This driver will now add the interrupt service routine as a fast
176 interrupt if it is bounced from the slow interrupt. THIS IS NOT A
177 RECOMMENDED WAY TO RUN THE DRIVER and has been done for a limited time
178 until people sort out their compatibility issues and the kernel
179 interrupt service code is fixed. YOU SHOULD SEPARATE OUT THE FAST
180 INTERRUPT CARDS FROM THE SLOW INTERRUPT CARDS to ensure that they do not
181 run on the same interrupt. PCMCIA/CardBus is another can of worms...
182
183 Finally, I think I have really fixed the module loading problem with
184 more than one DECchip based card. As a side effect, I don't mess with
185 the device structure any more which means that if more than 1 card in
186 2.0.x is installed (4 in 2.1.x), the user will have to edit
187 linux/drivers/net/Space.c to make room for them. Hence, module loading
188 is the preferred way to use this driver, since it doesn't have this
189 limitation.
190
191 Where SROM media detection is used and full duplex is specified in the
192 SROM, the feature is ignored unless lp->params.fdx is set at compile
193 time OR during a module load (insmod de4x5 args='eth??:fdx' [see
194 below]). This is because there is no way to automatically detect full
195 duplex links except through autonegotiation. When I include the
196 autonegotiation feature in the SROM autoconf code, this detection will
197 occur automatically for that case.
198
199 Command line arguments are now allowed, similar to passing arguments
200 through LILO. This will allow a per adapter board set up of full duplex
201 and media. The only lexical constraints are: the board name (dev->name)
202 appears in the list before its parameters. The list of parameters ends
203 either at the end of the parameter list or with another board name. The
204 following parameters are allowed:
205
206 fdx for full duplex
207 autosense to set the media/speed; with the following
208 sub-parameters:
209 TP, TP_NW, BNC, AUI, BNC_AUI, 100Mb, 10Mb, AUTO
210
211 Case sensitivity is important for the sub-parameters. They *must* be
212 upper case. Examples:
213
214 insmod de4x5 args='eth1:fdx autosense=BNC eth0:autosense=100Mb'.
215
216 For a compiled in driver, at or above line 548, place e.g.
217 #define DE4X5_PARM "eth0:fdx autosense=AUI eth2:autosense=TP"
218
219 Yes, I know full duplex isn't permissible on BNC or AUI; they're just
220 examples. By default, full duplex is turned off and AUTO is the default
221 autosense setting. In reality, I expect only the full duplex option to
222 be used. Note the use of single quotes in the two examples above and the
223 lack of commas to separate items. ALSO, you must get the requested media
224 correct in relation to what the adapter SROM says it has. There's no way
225 to determine this in advance other than by trial and error and common
226 sense, e.g. call a BNC connectored port 'BNC', not '10Mb'.
227
228 Changed the bus probing. EISA used to be done first, followed by PCI.
229 Most people probably don't even know what a de425 is today and the EISA
230 probe has messed up some SCSI cards in the past, so now PCI is always
231 probed first followed by EISA if a) the architecture allows EISA and
232 either b) there have been no PCI cards detected or c) an EISA probe is
233 forced by the user. To force a probe include "force_eisa" in your
234 insmod "args" line; for built-in kernels either change the driver to do
235 this automatically or include #define DE4X5_FORCE_EISA on or before
236 line 1040 in the driver.
237
238 TO DO:
239 ------
240
241 Revision History
242 ----------------
243
244 Version Date Description
245
246 0.1 17-Nov-94 Initial writing. ALPHA code release.
247 0.2 13-Jan-95 Added PCI support for DE435's.
248 0.21 19-Jan-95 Added auto media detection.
249 0.22 10-Feb-95 Fix interrupt handler call <chris@cosy.sbg.ac.at>.
250 Fix recognition bug reported by <bkm@star.rl.ac.uk>.
251 Add request/release_region code.
252 Add loadable modules support for PCI.
253 Clean up loadable modules support.
254 0.23 28-Feb-95 Added DC21041 and DC21140 support.
255 Fix missed frame counter value and initialisation.
256 Fixed EISA probe.
257 0.24 11-Apr-95 Change delay routine to use <linux/udelay>.
258 Change TX_BUFFS_AVAIL macro.
259 Change media autodetection to allow manual setting.
260 Completed DE500 (DC21140) support.
261 0.241 18-Apr-95 Interim release without DE500 Autosense Algorithm.
262 0.242 10-May-95 Minor changes.
263 0.30 12-Jun-95 Timer fix for DC21140.
264 Portability changes.
265 Add ALPHA changes from <jestabro@ant.tay1.dec.com>.
266 Add DE500 semi automatic autosense.
267 Add Link Fail interrupt TP failure detection.
268 Add timer based link change detection.
269 Plugged a memory leak in de4x5_queue_pkt().
270 0.31 13-Jun-95 Fixed PCI stuff for 1.3.1.
271 0.32 26-Jun-95 Added verify_area() calls in de4x5_ioctl() from a
272 suggestion by <heiko@colossus.escape.de>.
273 0.33 8-Aug-95 Add shared interrupt support (not released yet).
274 0.331 21-Aug-95 Fix de4x5_open() with fast CPUs.
275 Fix de4x5_interrupt().
276 Fix dc21140_autoconf() mess.
277 No shared interrupt support.
278 0.332 11-Sep-95 Added MII management interface routines.
279 0.40 5-Mar-96 Fix setup frame timeout <maartenb@hpkuipc.cern.ch>.
280 Add kernel timer code (h/w is too flaky).
281 Add MII based PHY autosense.
282 Add new multicasting code.
283 Add new autosense algorithms for media/mode
284 selection using kernel scheduling/timing.
285 Re-formatted.
286 Made changes suggested by <jeff@router.patch.net>:
287 Change driver to detect all DECchip based cards
288 with DEC_ONLY restriction a special case.
289 Changed driver to autoprobe as a module. No irq
290 checking is done now - assume BIOS is good!
291 Added SMC9332 detection <manabe@Roy.dsl.tutics.ac.jp>
292 0.41 21-Mar-96 Don't check for get_hw_addr checksum unless DEC card
293 only <niles@axp745gsfc.nasa.gov>
294 Fix for multiple PCI cards reported by <jos@xos.nl>
295 Duh, put the SA_SHIRQ flag into request_interrupt().
296 Fix SMC ethernet address in enet_det[].
297 Print chip name instead of "UNKNOWN" during boot.
298 0.42 26-Apr-96 Fix MII write TA bit error.
299 Fix bug in dc21040 and dc21041 autosense code.
300 Remove buffer copies on receive for Intels.
301 Change sk_buff handling during media disconnects to
302 eliminate DUP packets.
303 Add dynamic TX thresholding.
304 Change all chips to use perfect multicast filtering.
305 Fix alloc_device() bug <jari@markkus2.fimr.fi>
306 0.43 21-Jun-96 Fix unconnected media TX retry bug.
307 Add Accton to the list of broken cards.
308 Fix TX under-run bug for non DC21140 chips.
309 Fix boot command probe bug in alloc_device() as
310 reported by <koen.gadeyne@barco.com> and
311 <orava@nether.tky.hut.fi>.
312 Add cache locks to prevent a race condition as
313 reported by <csd@microplex.com> and
314 <baba@beckman.uiuc.edu>.
315 Upgraded alloc_device() code.
316 0.431 28-Jun-96 Fix potential bug in queue_pkt() from discussion
317 with <csd@microplex.com>
318 0.44 13-Aug-96 Fix RX overflow bug in 2114[023] chips.
319 Fix EISA probe bugs reported by <os2@kpi.kharkov.ua>
320 and <michael@compurex.com>.
321 0.441 9-Sep-96 Change dc21041_autoconf() to probe quiet BNC media
322 with a loopback packet.
323 0.442 9-Sep-96 Include AUI in dc21041 media printout. Bug reported
324 by <bhat@mundook.cs.mu.OZ.AU>
325 0.45 8-Dec-96 Include endian functions for PPC use, from work
326 by <cort@cs.nmt.edu> and <g.thomas@opengroup.org>.
327 0.451 28-Dec-96 Added fix to allow autoprobe for modules after
328 suggestion from <mjacob@feral.com>.
329 0.5 30-Jan-97 Added SROM decoding functions.
330 Updated debug flags.
331 Fix sleep/wakeup calls for PCI cards, bug reported
332 by <cross@gweep.lkg.dec.com>.
333 Added multi-MAC, one SROM feature from discussion
334 with <mjacob@feral.com>.
335 Added full module autoprobe capability.
336 Added attempt to use an SMC9332 with broken SROM.
337 Added fix for ZYNX multi-mac cards that didn't
338 get their IRQs wired correctly.
339 0.51 13-Feb-97 Added endian fixes for the SROM accesses from
340 <paubert@iram.es>
341 Fix init_connection() to remove extra device reset.
342 Fix MAC/PHY reset ordering in dc21140m_autoconf().
343 Fix initialisation problem with lp->timeout in
344 typeX_infoblock() from <paubert@iram.es>.
345 Fix MII PHY reset problem from work done by
346 <paubert@iram.es>.
347 0.52 26-Apr-97 Some changes may not credit the right people -
348 a disk crash meant I lost some mail.
349 Change RX interrupt routine to drop rather than
350 defer packets to avoid hang reported by
351 <g.thomas@opengroup.org>.
352 Fix srom_exec() to return for COMPACT and type 1
353 infoblocks.
354 Added DC21142 and DC21143 functions.
355 Added byte counters from <phil@tazenda.demon.co.uk>
356 Added SA_INTERRUPT temporary fix from
357 <mjacob@feral.com>.
358 0.53 12-Nov-97 Fix the *_probe() to include 'eth??' name during
359 module load: bug reported by
360 <Piete.Brooks@cl.cam.ac.uk>
361 Fix multi-MAC, one SROM, to work with 2114x chips:
362 bug reported by <cmetz@inner.net>.
363 Make above search independent of BIOS device scan
364 direction.
365 Completed DC2114[23] autosense functions.
366 0.531 21-Dec-97 Fix DE500-XA 100Mb/s bug reported by
367 <robin@intercore.com
368 Fix type1_infoblock() bug introduced in 0.53, from
369 problem reports by
370 <parmee@postecss.ncrfran.france.ncr.com> and
371 <jo@ice.dillingen.baynet.de>.
372 Added argument list to set up each board from either
373 a module's command line or a compiled in #define.
374 Added generic MII PHY functionality to deal with
375 newer PHY chips.
376 Fix the mess in 2.1.67.
377 0.532 5-Jan-98 Fix bug in mii_get_phy() reported by
378 <redhat@cococo.net>.
379 Fix bug in pci_probe() for 64 bit systems reported
380 by <belliott@accessone.com>.
381 0.533 9-Jan-98 Fix more 64 bit bugs reported by <jal@cs.brown.edu>.
382 0.534 24-Jan-98 Fix last (?) endian bug from <geert@linux-m68k.org>
383 0.535 21-Feb-98 Fix Ethernet Address PROM reset bug for DC21040.
384 0.536 21-Mar-98 Change pci_probe() to use the pci_dev structure.
385 **Incompatible with 2.0.x from here.**
386 0.540 5-Jul-98 Atomicize assertion of dev->interrupt for SMP
387 from <lma@varesearch.com>
388 Add TP, AUI and BNC cases to 21140m_autoconf() for
389 case where a 21140 under SROM control uses, e.g. AUI
390 from problem report by <delchini@lpnp09.in2p3.fr>
391 Add MII parallel detection to 2114x_autoconf() for
392 case where no autonegotiation partner exists from
393 problem report by <mlapsley@ndirect.co.uk>.
394 Add ability to force connection type directly even
395 when using SROM control from problem report by
396 <earl@exis.net>.
397 Updated the PCI interface to conform with the latest
398 version. I hope nothing is broken...
399 Add TX done interrupt modification from suggestion
400 by <Austin.Donnelly@cl.cam.ac.uk>.
401 Fix is_anc_capable() bug reported by
402 <Austin.Donnelly@cl.cam.ac.uk>.
403 Fix type[13]_infoblock() bug: during MII search, PHY
404 lp->rst not run because lp->ibn not initialised -
405 from report & fix by <paubert@iram.es>.
406 Fix probe bug with EISA & PCI cards present from
407 report by <eirik@netcom.com>.
408 0.541 24-Aug-98 Fix compiler problems associated with i386-string
409 ops from multiple bug reports and temporary fix
410 from <paubert@iram.es>.
411 Fix pci_probe() to correctly emulate the old
412 pcibios_find_class() function.
413 Add an_exception() for old ZYNX346 and fix compile
414 warning on PPC & SPARC, from <ecd@skynet.be>.
415 Fix lastPCI to correctly work with compiled in
416 kernels and modules from bug report by
417 <Zlatko.Calusic@CARNet.hr> et al.
418 0.542 15-Sep-98 Fix dc2114x_autoconf() to stop multiple messages
419 when media is unconnected.
420 Change dev->interrupt to lp->interrupt to ensure
421 alignment for Alpha's and avoid their unaligned
422 access traps. This flag is merely for log messages:
423 should do something more definitive though...
424 0.543 30-Dec-98 Add SMP spin locking.
425 0.544 8-May-99 Fix for buggy SROM in Motorola embedded boards using
426 a 21143 by <mmporter@home.com>.
427 Change PCI/EISA bus probing order.
428 0.545 28-Nov-99 Further Moto SROM bug fix from
429 <mporter@eng.mcd.mot.com>
430 Remove double checking for DEBUG_RX in de4x5_dbg_rx()
431 from report by <geert@linux-m68k.org>
432 0.546 22-Feb-01 Fixes Alpha XP1000 oops. The srom_search function
433 was causing a page fault when initializing the
434 variable 'pb', on a non de4x5 PCI device, in this
435 case a PCI bridge (DEC chip 21152). The value of
436 'pb' is now only initialized if a de4x5 chip is
437 present.
438 <france@handhelds.org>
439 0.547 08-Nov-01 Use library crc32 functions by <Matt_Domsch@dell.com>
440 0.548 30-Aug-03 Big 2.6 cleanup. Ported to PCI/EISA probing and
441 generic DMA APIs. Fixed DE425 support on Alpha.
442 <maz@wild-wind.fr.eu.org>
443 =========================================================================
444*/
445
446#include <linux/config.h>
447#include <linux/module.h>
448#include <linux/kernel.h>
449#include <linux/string.h>
450#include <linux/interrupt.h>
451#include <linux/ptrace.h>
452#include <linux/errno.h>
453#include <linux/ioport.h>
454#include <linux/slab.h>
455#include <linux/pci.h>
456#include <linux/eisa.h>
457#include <linux/delay.h>
458#include <linux/init.h>
459#include <linux/spinlock.h>
460#include <linux/crc32.h>
461#include <linux/netdevice.h>
462#include <linux/etherdevice.h>
463#include <linux/skbuff.h>
464#include <linux/time.h>
465#include <linux/types.h>
466#include <linux/unistd.h>
467#include <linux/ctype.h>
468#include <linux/dma-mapping.h>
469#include <linux/moduleparam.h>
470#include <linux/bitops.h>
471
472#include <asm/io.h>
473#include <asm/dma.h>
474#include <asm/byteorder.h>
475#include <asm/unaligned.h>
476#include <asm/uaccess.h>
477#ifdef CONFIG_PPC_MULTIPLATFORM
478#include <asm/machdep.h>
479#endif /* CONFIG_PPC_MULTIPLATFORM */
480
481#include "de4x5.h"
482
483static char version[] __devinitdata = "de4x5.c:V0.546 2001/02/22 davies@maniac.ultranet.com\n";
484
485#define c_char const char
486#define TWIDDLE(a) (u_short)le16_to_cpu(get_unaligned((u_short *)(a)))
487
488/*
489** MII Information
490*/
491struct phy_table {
492 int reset; /* Hard reset required? */
493 int id; /* IEEE OUI */
494 int ta; /* One cycle TA time - 802.3u is confusing here */
495 struct { /* Non autonegotiation (parallel) speed det. */
496 int reg;
497 int mask;
498 int value;
499 } spd;
500};
501
502struct mii_phy {
503 int reset; /* Hard reset required? */
504 int id; /* IEEE OUI */
505 int ta; /* One cycle TA time */
506 struct { /* Non autonegotiation (parallel) speed det. */
507 int reg;
508 int mask;
509 int value;
510 } spd;
511 int addr; /* MII address for the PHY */
512 u_char *gep; /* Start of GEP sequence block in SROM */
513 u_char *rst; /* Start of reset sequence in SROM */
514 u_int mc; /* Media Capabilities */
515 u_int ana; /* NWay Advertisement */
516 u_int fdx; /* Full DupleX capabilites for each media */
517 u_int ttm; /* Transmit Threshold Mode for each media */
518 u_int mci; /* 21142 MII Connector Interrupt info */
519};
520
521#define DE4X5_MAX_PHY 8 /* Allow upto 8 attached PHY devices per board */
522
523struct sia_phy {
524 u_char mc; /* Media Code */
525 u_char ext; /* csr13-15 valid when set */
526 int csr13; /* SIA Connectivity Register */
527 int csr14; /* SIA TX/RX Register */
528 int csr15; /* SIA General Register */
529 int gepc; /* SIA GEP Control Information */
530 int gep; /* SIA GEP Data */
531};
532
533/*
534** Define the know universe of PHY devices that can be
535** recognised by this driver.
536*/
537static struct phy_table phy_info[] = {
538 {0, NATIONAL_TX, 1, {0x19, 0x40, 0x00}}, /* National TX */
539 {1, BROADCOM_T4, 1, {0x10, 0x02, 0x02}}, /* Broadcom T4 */
540 {0, SEEQ_T4 , 1, {0x12, 0x10, 0x10}}, /* SEEQ T4 */
541 {0, CYPRESS_T4 , 1, {0x05, 0x20, 0x20}}, /* Cypress T4 */
542 {0, 0x7810 , 1, {0x14, 0x0800, 0x0800}} /* Level One LTX970 */
543};
544
545/*
546** These GENERIC values assumes that the PHY devices follow 802.3u and
547** allow parallel detection to set the link partner ability register.
548** Detection of 100Base-TX [H/F Duplex] and 100Base-T4 is supported.
549*/
550#define GENERIC_REG 0x05 /* Autoneg. Link Partner Advertisement Reg. */
551#define GENERIC_MASK MII_ANLPA_100M /* All 100Mb/s Technologies */
552#define GENERIC_VALUE MII_ANLPA_100M /* 100B-TX, 100B-TX FDX, 100B-T4 */
553
554/*
555** Define special SROM detection cases
556*/
557static c_char enet_det[][ETH_ALEN] = {
558 {0x00, 0x00, 0xc0, 0x00, 0x00, 0x00},
559 {0x00, 0x00, 0xe8, 0x00, 0x00, 0x00}
560};
561
562#define SMC 1
563#define ACCTON 2
564
565/*
566** SROM Repair definitions. If a broken SROM is detected a card may
567** use this information to help figure out what to do. This is a
568** "stab in the dark" and so far for SMC9332's only.
569*/
570static c_char srom_repair_info[][100] = {
571 {0x00,0x1e,0x00,0x00,0x00,0x08, /* SMC9332 */
572 0x1f,0x01,0x8f,0x01,0x00,0x01,0x00,0x02,
573 0x01,0x00,0x00,0x78,0xe0,0x01,0x00,0x50,
574 0x00,0x18,}
575};
576
577
578#ifdef DE4X5_DEBUG
579static int de4x5_debug = DE4X5_DEBUG;
580#else
581/*static int de4x5_debug = (DEBUG_MII | DEBUG_SROM | DEBUG_PCICFG | DEBUG_MEDIA | DEBUG_VERSION);*/
582static int de4x5_debug = (DEBUG_MEDIA | DEBUG_VERSION);
583#endif
584
585/*
586** Allow per adapter set up. For modules this is simply a command line
587** parameter, e.g.:
588** insmod de4x5 args='eth1:fdx autosense=BNC eth0:autosense=100Mb'.
589**
590** For a compiled in driver, place e.g.
591** #define DE4X5_PARM "eth0:fdx autosense=AUI eth2:autosense=TP"
592** here
593*/
594#ifdef DE4X5_PARM
595static char *args = DE4X5_PARM;
596#else
597static char *args;
598#endif
599
600struct parameters {
601 int fdx;
602 int autosense;
603};
604
605#define DE4X5_AUTOSENSE_MS 250 /* msec autosense tick (DE500) */
606
607#define DE4X5_NDA 0xffe0 /* No Device (I/O) Address */
608
609/*
610** Ethernet PROM defines
611*/
612#define PROBE_LENGTH 32
613#define ETH_PROM_SIG 0xAA5500FFUL
614
615/*
616** Ethernet Info
617*/
618#define PKT_BUF_SZ 1536 /* Buffer size for each Tx/Rx buffer */
619#define IEEE802_3_SZ 1518 /* Packet + CRC */
620#define MAX_PKT_SZ 1514 /* Maximum ethernet packet length */
621#define MAX_DAT_SZ 1500 /* Maximum ethernet data length */
622#define MIN_DAT_SZ 1 /* Minimum ethernet data length */
623#define PKT_HDR_LEN 14 /* Addresses and data length info */
624#define FAKE_FRAME_LEN (MAX_PKT_SZ + 1)
625#define QUEUE_PKT_TIMEOUT (3*HZ) /* 3 second timeout */
626
627
628/*
629** EISA bus defines
630*/
631#define DE4X5_EISA_IO_PORTS 0x0c00 /* I/O port base address, slot 0 */
632#define DE4X5_EISA_TOTAL_SIZE 0x100 /* I/O address extent */
633
634#define EISA_ALLOWED_IRQ_LIST {5, 9, 10, 11}
635
636#define DE4X5_SIGNATURE {"DE425","DE434","DE435","DE450","DE500"}
637#define DE4X5_NAME_LENGTH 8
638
639static c_char *de4x5_signatures[] = DE4X5_SIGNATURE;
640
641/*
642** Ethernet PROM defines for DC21040
643*/
644#define PROBE_LENGTH 32
645#define ETH_PROM_SIG 0xAA5500FFUL
646
647/*
648** PCI Bus defines
649*/
650#define PCI_MAX_BUS_NUM 8
651#define DE4X5_PCI_TOTAL_SIZE 0x80 /* I/O address extent */
652#define DE4X5_CLASS_CODE 0x00020000 /* Network controller, Ethernet */
653
654/*
655** Memory Alignment. Each descriptor is 4 longwords long. To force a
656** particular alignment on the TX descriptor, adjust DESC_SKIP_LEN and
657** DESC_ALIGN. ALIGN aligns the start address of the private memory area
658** and hence the RX descriptor ring's first entry.
659*/
660#define DE4X5_ALIGN4 ((u_long)4 - 1) /* 1 longword align */
661#define DE4X5_ALIGN8 ((u_long)8 - 1) /* 2 longword align */
662#define DE4X5_ALIGN16 ((u_long)16 - 1) /* 4 longword align */
663#define DE4X5_ALIGN32 ((u_long)32 - 1) /* 8 longword align */
664#define DE4X5_ALIGN64 ((u_long)64 - 1) /* 16 longword align */
665#define DE4X5_ALIGN128 ((u_long)128 - 1) /* 32 longword align */
666
667#define DE4X5_ALIGN DE4X5_ALIGN32 /* Keep the DC21040 happy... */
668#define DE4X5_CACHE_ALIGN CAL_16LONG
669#define DESC_SKIP_LEN DSL_0 /* Must agree with DESC_ALIGN */
670/*#define DESC_ALIGN u32 dummy[4]; / * Must agree with DESC_SKIP_LEN */
671#define DESC_ALIGN
672
673#ifndef DEC_ONLY /* See README.de4x5 for using this */
674static int dec_only;
675#else
676static int dec_only = 1;
677#endif
678
679/*
680** DE4X5 IRQ ENABLE/DISABLE
681*/
682#define ENABLE_IRQs { \
683 imr |= lp->irq_en;\
684 outl(imr, DE4X5_IMR); /* Enable the IRQs */\
685}
686
687#define DISABLE_IRQs {\
688 imr = inl(DE4X5_IMR);\
689 imr &= ~lp->irq_en;\
690 outl(imr, DE4X5_IMR); /* Disable the IRQs */\
691}
692
693#define UNMASK_IRQs {\
694 imr |= lp->irq_mask;\
695 outl(imr, DE4X5_IMR); /* Unmask the IRQs */\
696}
697
698#define MASK_IRQs {\
699 imr = inl(DE4X5_IMR);\
700 imr &= ~lp->irq_mask;\
701 outl(imr, DE4X5_IMR); /* Mask the IRQs */\
702}
703
704/*
705** DE4X5 START/STOP
706*/
707#define START_DE4X5 {\
708 omr = inl(DE4X5_OMR);\
709 omr |= OMR_ST | OMR_SR;\
710 outl(omr, DE4X5_OMR); /* Enable the TX and/or RX */\
711}
712
713#define STOP_DE4X5 {\
714 omr = inl(DE4X5_OMR);\
715 omr &= ~(OMR_ST|OMR_SR);\
716 outl(omr, DE4X5_OMR); /* Disable the TX and/or RX */ \
717}
718
719/*
720** DE4X5 SIA RESET
721*/
722#define RESET_SIA outl(0, DE4X5_SICR); /* Reset SIA connectivity regs */
723
724/*
725** DE500 AUTOSENSE TIMER INTERVAL (MILLISECS)
726*/
727#define DE4X5_AUTOSENSE_MS 250
728
729/*
730** SROM Structure
731*/
732struct de4x5_srom {
733 char sub_vendor_id[2];
734 char sub_system_id[2];
735 char reserved[12];
736 char id_block_crc;
737 char reserved2;
738 char version;
739 char num_controllers;
740 char ieee_addr[6];
741 char info[100];
742 short chksum;
743};
744#define SUB_VENDOR_ID 0x500a
745
746/*
747** DE4X5 Descriptors. Make sure that all the RX buffers are contiguous
748** and have sizes of both a power of 2 and a multiple of 4.
749** A size of 256 bytes for each buffer could be chosen because over 90% of
750** all packets in our network are <256 bytes long and 64 longword alignment
751** is possible. 1536 showed better 'ttcp' performance. Take your pick. 32 TX
752** descriptors are needed for machines with an ALPHA CPU.
753*/
754#define NUM_RX_DESC 8 /* Number of RX descriptors */
755#define NUM_TX_DESC 32 /* Number of TX descriptors */
756#define RX_BUFF_SZ 1536 /* Power of 2 for kmalloc and */
757 /* Multiple of 4 for DC21040 */
758 /* Allows 512 byte alignment */
759struct de4x5_desc {
760 volatile s32 status;
761 u32 des1;
762 u32 buf;
763 u32 next;
764 DESC_ALIGN
765};
766
767/*
768** The DE4X5 private structure
769*/
770#define DE4X5_PKT_STAT_SZ 16
771#define DE4X5_PKT_BIN_SZ 128 /* Should be >=100 unless you
772 increase DE4X5_PKT_STAT_SZ */
773
774struct pkt_stats {
775 u_int bins[DE4X5_PKT_STAT_SZ]; /* Private stats counters */
776 u_int unicast;
777 u_int multicast;
778 u_int broadcast;
779 u_int excessive_collisions;
780 u_int tx_underruns;
781 u_int excessive_underruns;
782 u_int rx_runt_frames;
783 u_int rx_collision;
784 u_int rx_dribble;
785 u_int rx_overflow;
786};
787
788struct de4x5_private {
789 char adapter_name[80]; /* Adapter name */
790 u_long interrupt; /* Aligned ISR flag */
791 struct de4x5_desc *rx_ring; /* RX descriptor ring */
792 struct de4x5_desc *tx_ring; /* TX descriptor ring */
793 struct sk_buff *tx_skb[NUM_TX_DESC]; /* TX skb for freeing when sent */
794 struct sk_buff *rx_skb[NUM_RX_DESC]; /* RX skb's */
795 int rx_new, rx_old; /* RX descriptor ring pointers */
796 int tx_new, tx_old; /* TX descriptor ring pointers */
797 char setup_frame[SETUP_FRAME_LEN]; /* Holds MCA and PA info. */
798 char frame[64]; /* Min sized packet for loopback*/
799 spinlock_t lock; /* Adapter specific spinlock */
800 struct net_device_stats stats; /* Public stats */
801 struct pkt_stats pktStats; /* Private stats counters */
802 char rxRingSize;
803 char txRingSize;
804 int bus; /* EISA or PCI */
805 int bus_num; /* PCI Bus number */
806 int device; /* Device number on PCI bus */
807 int state; /* Adapter OPENED or CLOSED */
808 int chipset; /* DC21040, DC21041 or DC21140 */
809 s32 irq_mask; /* Interrupt Mask (Enable) bits */
810 s32 irq_en; /* Summary interrupt bits */
811 int media; /* Media (eg TP), mode (eg 100B)*/
812 int c_media; /* Remember the last media conn */
813 int fdx; /* media full duplex flag */
814 int linkOK; /* Link is OK */
815 int autosense; /* Allow/disallow autosensing */
816 int tx_enable; /* Enable descriptor polling */
817 int setup_f; /* Setup frame filtering type */
818 int local_state; /* State within a 'media' state */
819 struct mii_phy phy[DE4X5_MAX_PHY]; /* List of attached PHY devices */
820 struct sia_phy sia; /* SIA PHY Information */
821 int active; /* Index to active PHY device */
822 int mii_cnt; /* Number of attached PHY's */
823 int timeout; /* Scheduling counter */
824 struct timer_list timer; /* Timer info for kernel */
825 int tmp; /* Temporary global per card */
826 struct {
827 u_long lock; /* Lock the cache accesses */
828 s32 csr0; /* Saved Bus Mode Register */
829 s32 csr6; /* Saved Operating Mode Reg. */
830 s32 csr7; /* Saved IRQ Mask Register */
831 s32 gep; /* Saved General Purpose Reg. */
832 s32 gepc; /* Control info for GEP */
833 s32 csr13; /* Saved SIA Connectivity Reg. */
834 s32 csr14; /* Saved SIA TX/RX Register */
835 s32 csr15; /* Saved SIA General Register */
836 int save_cnt; /* Flag if state already saved */
837 struct sk_buff *skb; /* Save the (re-ordered) skb's */
838 } cache;
839 struct de4x5_srom srom; /* A copy of the SROM */
840 int cfrv; /* Card CFRV copy */
841 int rx_ovf; /* Check for 'RX overflow' tag */
842 int useSROM; /* For non-DEC card use SROM */
843 int useMII; /* Infoblock using the MII */
844 int asBitValid; /* Autosense bits in GEP? */
845 int asPolarity; /* 0 => asserted high */
846 int asBit; /* Autosense bit number in GEP */
847 int defMedium; /* SROM default medium */
848 int tcount; /* Last infoblock number */
849 int infoblock_init; /* Initialised this infoblock? */
850 int infoleaf_offset; /* SROM infoleaf for controller */
851 s32 infoblock_csr6; /* csr6 value in SROM infoblock */
852 int infoblock_media; /* infoblock media */
853 int (*infoleaf_fn)(struct net_device *); /* Pointer to infoleaf function */
854 u_char *rst; /* Pointer to Type 5 reset info */
855 u_char ibn; /* Infoblock number */
856 struct parameters params; /* Command line/ #defined params */
857 struct device *gendev; /* Generic device */
858 dma_addr_t dma_rings; /* DMA handle for rings */
859 int dma_size; /* Size of the DMA area */
860 char *rx_bufs; /* rx bufs on alpha, sparc, ... */
861};
862
863/*
864** To get around certain poxy cards that don't provide an SROM
865** for the second and more DECchip, I have to key off the first
866** chip's address. I'll assume there's not a bad SROM iff:
867**
868** o the chipset is the same
869** o the bus number is the same and > 0
870** o the sum of all the returned hw address bytes is 0 or 0x5fa
871**
872** Also have to save the irq for those cards whose hardware designers
873** can't follow the PCI to PCI Bridge Architecture spec.
874*/
875static struct {
876 int chipset;
877 int bus;
878 int irq;
879 u_char addr[ETH_ALEN];
880} last = {0,};
881
882/*
883** The transmit ring full condition is described by the tx_old and tx_new
884** pointers by:
885** tx_old = tx_new Empty ring
886** tx_old = tx_new+1 Full ring
887** tx_old+txRingSize = tx_new+1 Full ring (wrapped condition)
888*/
889#define TX_BUFFS_AVAIL ((lp->tx_old<=lp->tx_new)?\
890 lp->tx_old+lp->txRingSize-lp->tx_new-1:\
891 lp->tx_old -lp->tx_new-1)
892
893#define TX_PKT_PENDING (lp->tx_old != lp->tx_new)
894
895/*
896** Public Functions
897*/
898static int de4x5_open(struct net_device *dev);
899static int de4x5_queue_pkt(struct sk_buff *skb, struct net_device *dev);
900static irqreturn_t de4x5_interrupt(int irq, void *dev_id, struct pt_regs *regs);
901static int de4x5_close(struct net_device *dev);
902static struct net_device_stats *de4x5_get_stats(struct net_device *dev);
903static void de4x5_local_stats(struct net_device *dev, char *buf, int pkt_len);
904static void set_multicast_list(struct net_device *dev);
905static int de4x5_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
906
907/*
908** Private functions
909*/
910static int de4x5_hw_init(struct net_device *dev, u_long iobase, struct device *gendev);
911static int de4x5_init(struct net_device *dev);
912static int de4x5_sw_reset(struct net_device *dev);
913static int de4x5_rx(struct net_device *dev);
914static int de4x5_tx(struct net_device *dev);
915static int de4x5_ast(struct net_device *dev);
916static int de4x5_txur(struct net_device *dev);
917static int de4x5_rx_ovfc(struct net_device *dev);
918
919static int autoconf_media(struct net_device *dev);
920static void create_packet(struct net_device *dev, char *frame, int len);
921static void load_packet(struct net_device *dev, char *buf, u32 flags, struct sk_buff *skb);
922static int dc21040_autoconf(struct net_device *dev);
923static int dc21041_autoconf(struct net_device *dev);
924static int dc21140m_autoconf(struct net_device *dev);
925static int dc2114x_autoconf(struct net_device *dev);
926static int srom_autoconf(struct net_device *dev);
927static int de4x5_suspect_state(struct net_device *dev, int timeout, int prev_state, int (*fn)(struct net_device *, int), int (*asfn)(struct net_device *));
928static int dc21040_state(struct net_device *dev, int csr13, int csr14, int csr15, int timeout, int next_state, int suspect_state, int (*fn)(struct net_device *, int));
929static int test_media(struct net_device *dev, s32 irqs, s32 irq_mask, s32 csr13, s32 csr14, s32 csr15, s32 msec);
930static int test_for_100Mb(struct net_device *dev, int msec);
931static int wait_for_link(struct net_device *dev);
932static int test_mii_reg(struct net_device *dev, int reg, int mask, int pol, long msec);
933static int is_spd_100(struct net_device *dev);
934static int is_100_up(struct net_device *dev);
935static int is_10_up(struct net_device *dev);
936static int is_anc_capable(struct net_device *dev);
937static int ping_media(struct net_device *dev, int msec);
938static struct sk_buff *de4x5_alloc_rx_buff(struct net_device *dev, int index, int len);
939static void de4x5_free_rx_buffs(struct net_device *dev);
940static void de4x5_free_tx_buffs(struct net_device *dev);
941static void de4x5_save_skbs(struct net_device *dev);
942static void de4x5_rst_desc_ring(struct net_device *dev);
943static void de4x5_cache_state(struct net_device *dev, int flag);
944static void de4x5_put_cache(struct net_device *dev, struct sk_buff *skb);
945static void de4x5_putb_cache(struct net_device *dev, struct sk_buff *skb);
946static struct sk_buff *de4x5_get_cache(struct net_device *dev);
947static void de4x5_setup_intr(struct net_device *dev);
948static void de4x5_init_connection(struct net_device *dev);
949static int de4x5_reset_phy(struct net_device *dev);
950static void reset_init_sia(struct net_device *dev, s32 sicr, s32 strr, s32 sigr);
951static int test_ans(struct net_device *dev, s32 irqs, s32 irq_mask, s32 msec);
952static int test_tp(struct net_device *dev, s32 msec);
953static int EISA_signature(char *name, struct device *device);
954static int PCI_signature(char *name, struct de4x5_private *lp);
955static void DevicePresent(struct net_device *dev, u_long iobase);
956static void enet_addr_rst(u_long aprom_addr);
957static int de4x5_bad_srom(struct de4x5_private *lp);
958static short srom_rd(u_long address, u_char offset);
959static void srom_latch(u_int command, u_long address);
960static void srom_command(u_int command, u_long address);
961static void srom_address(u_int command, u_long address, u_char offset);
962static short srom_data(u_int command, u_long address);
963/*static void srom_busy(u_int command, u_long address);*/
964static void sendto_srom(u_int command, u_long addr);
965static int getfrom_srom(u_long addr);
966static int srom_map_media(struct net_device *dev);
967static int srom_infoleaf_info(struct net_device *dev);
968static void srom_init(struct net_device *dev);
969static void srom_exec(struct net_device *dev, u_char *p);
970static int mii_rd(u_char phyreg, u_char phyaddr, u_long ioaddr);
971static void mii_wr(int data, u_char phyreg, u_char phyaddr, u_long ioaddr);
972static int mii_rdata(u_long ioaddr);
973static void mii_wdata(int data, int len, u_long ioaddr);
974static void mii_ta(u_long rw, u_long ioaddr);
975static int mii_swap(int data, int len);
976static void mii_address(u_char addr, u_long ioaddr);
977static void sendto_mii(u32 command, int data, u_long ioaddr);
978static int getfrom_mii(u32 command, u_long ioaddr);
979static int mii_get_oui(u_char phyaddr, u_long ioaddr);
980static int mii_get_phy(struct net_device *dev);
981static void SetMulticastFilter(struct net_device *dev);
982static int get_hw_addr(struct net_device *dev);
983static void srom_repair(struct net_device *dev, int card);
984static int test_bad_enet(struct net_device *dev, int status);
985static int an_exception(struct de4x5_private *lp);
986static char *build_setup_frame(struct net_device *dev, int mode);
987static void disable_ast(struct net_device *dev);
988static void enable_ast(struct net_device *dev, u32 time_out);
989static long de4x5_switch_mac_port(struct net_device *dev);
990static int gep_rd(struct net_device *dev);
991static void gep_wr(s32 data, struct net_device *dev);
992static void timeout(struct net_device *dev, void (*fn)(u_long data), u_long data, u_long msec);
993static void yawn(struct net_device *dev, int state);
994static void de4x5_parse_params(struct net_device *dev);
995static void de4x5_dbg_open(struct net_device *dev);
996static void de4x5_dbg_mii(struct net_device *dev, int k);
997static void de4x5_dbg_media(struct net_device *dev);
998static void de4x5_dbg_srom(struct de4x5_srom *p);
999static void de4x5_dbg_rx(struct sk_buff *skb, int len);
1000static int de4x5_strncmp(char *a, char *b, int n);
1001static int dc21041_infoleaf(struct net_device *dev);
1002static int dc21140_infoleaf(struct net_device *dev);
1003static int dc21142_infoleaf(struct net_device *dev);
1004static int dc21143_infoleaf(struct net_device *dev);
1005static int type0_infoblock(struct net_device *dev, u_char count, u_char *p);
1006static int type1_infoblock(struct net_device *dev, u_char count, u_char *p);
1007static int type2_infoblock(struct net_device *dev, u_char count, u_char *p);
1008static int type3_infoblock(struct net_device *dev, u_char count, u_char *p);
1009static int type4_infoblock(struct net_device *dev, u_char count, u_char *p);
1010static int type5_infoblock(struct net_device *dev, u_char count, u_char *p);
1011static int compact_infoblock(struct net_device *dev, u_char count, u_char *p);
1012
1013/*
1014** Note now that module autoprobing is allowed under EISA and PCI. The
1015** IRQ lines will not be auto-detected; instead I'll rely on the BIOSes
1016** to "do the right thing".
1017*/
1018
1019static int io=0x0;/* EDIT THIS LINE FOR YOUR CONFIGURATION IF NEEDED */
1020
1021module_param(io, int, 0);
1022module_param(de4x5_debug, int, 0);
1023module_param(dec_only, int, 0);
1024module_param(args, charp, 0);
1025
1026MODULE_PARM_DESC(io, "de4x5 I/O base address");
1027MODULE_PARM_DESC(de4x5_debug, "de4x5 debug mask");
1028MODULE_PARM_DESC(dec_only, "de4x5 probe only for Digital boards (0-1)");
1029MODULE_PARM_DESC(args, "de4x5 full duplex and media type settings; see de4x5.c for details");
1030MODULE_LICENSE("GPL");
1031
1032/*
1033** List the SROM infoleaf functions and chipsets
1034*/
1035struct InfoLeaf {
1036 int chipset;
1037 int (*fn)(struct net_device *);
1038};
1039static struct InfoLeaf infoleaf_array[] = {
1040 {DC21041, dc21041_infoleaf},
1041 {DC21140, dc21140_infoleaf},
1042 {DC21142, dc21142_infoleaf},
1043 {DC21143, dc21143_infoleaf}
1044};
1045#define INFOLEAF_SIZE (sizeof(infoleaf_array)/(sizeof(int)+sizeof(int *)))
1046
1047/*
1048** List the SROM info block functions
1049*/
1050static int (*dc_infoblock[])(struct net_device *dev, u_char, u_char *) = {
1051 type0_infoblock,
1052 type1_infoblock,
1053 type2_infoblock,
1054 type3_infoblock,
1055 type4_infoblock,
1056 type5_infoblock,
1057 compact_infoblock
1058};
1059
1060#define COMPACT (sizeof(dc_infoblock)/sizeof(int *) - 1)
1061
1062/*
1063** Miscellaneous defines...
1064*/
1065#define RESET_DE4X5 {\
1066 int i;\
1067 i=inl(DE4X5_BMR);\
1068 mdelay(1);\
1069 outl(i | BMR_SWR, DE4X5_BMR);\
1070 mdelay(1);\
1071 outl(i, DE4X5_BMR);\
1072 mdelay(1);\
1073 for (i=0;i<5;i++) {inl(DE4X5_BMR); mdelay(1);}\
1074 mdelay(1);\
1075}
1076
1077#define PHY_HARD_RESET {\
1078 outl(GEP_HRST, DE4X5_GEP); /* Hard RESET the PHY dev. */\
1079 mdelay(1); /* Assert for 1ms */\
1080 outl(0x00, DE4X5_GEP);\
1081 mdelay(2); /* Wait for 2ms */\
1082}
1083
1084
1085static int __devinit
1086de4x5_hw_init(struct net_device *dev, u_long iobase, struct device *gendev)
1087{
1088 char name[DE4X5_NAME_LENGTH + 1];
1089 struct de4x5_private *lp = netdev_priv(dev);
1090 struct pci_dev *pdev = NULL;
1091 int i, status=0;
1092
1093 gendev->driver_data = dev;
1094
1095 /* Ensure we're not sleeping */
1096 if (lp->bus == EISA) {
1097 outb(WAKEUP, PCI_CFPM);
1098 } else {
1099 pdev = to_pci_dev (gendev);
1100 pci_write_config_byte(pdev, PCI_CFDA_PSM, WAKEUP);
1101 }
1102 mdelay(10);
1103
1104 RESET_DE4X5;
1105
1106 if ((inl(DE4X5_STS) & (STS_TS | STS_RS)) != 0) {
1107 return -ENXIO; /* Hardware could not reset */
1108 }
1109
1110 /*
1111 ** Now find out what kind of DC21040/DC21041/DC21140 board we have.
1112 */
1113 lp->useSROM = FALSE;
1114 if (lp->bus == PCI) {
1115 PCI_signature(name, lp);
1116 } else {
1117 EISA_signature(name, gendev);
1118 }
1119
1120 if (*name == '\0') { /* Not found a board signature */
1121 return -ENXIO;
1122 }
1123
1124 dev->base_addr = iobase;
1125 printk ("%s: %s at 0x%04lx", gendev->bus_id, name, iobase);
1126
1127 printk(", h/w address ");
1128 status = get_hw_addr(dev);
1129 for (i = 0; i < ETH_ALEN - 1; i++) { /* get the ethernet addr. */
1130 printk("%2.2x:", dev->dev_addr[i]);
1131 }
1132 printk("%2.2x,\n", dev->dev_addr[i]);
1133
1134 if (status != 0) {
1135 printk(" which has an Ethernet PROM CRC error.\n");
1136 return -ENXIO;
1137 } else {
1138 lp->cache.gepc = GEP_INIT;
1139 lp->asBit = GEP_SLNK;
1140 lp->asPolarity = GEP_SLNK;
1141 lp->asBitValid = TRUE;
1142 lp->timeout = -1;
1143 lp->gendev = gendev;
1144 spin_lock_init(&lp->lock);
1145 init_timer(&lp->timer);
1146 de4x5_parse_params(dev);
1147
1148 /*
1149 ** Choose correct autosensing in case someone messed up
1150 */
1151 lp->autosense = lp->params.autosense;
1152 if (lp->chipset != DC21140) {
1153 if ((lp->chipset==DC21040) && (lp->params.autosense&TP_NW)) {
1154 lp->params.autosense = TP;
1155 }
1156 if ((lp->chipset==DC21041) && (lp->params.autosense&BNC_AUI)) {
1157 lp->params.autosense = BNC;
1158 }
1159 }
1160 lp->fdx = lp->params.fdx;
1161 sprintf(lp->adapter_name,"%s (%s)", name, gendev->bus_id);
1162
1163 lp->dma_size = (NUM_RX_DESC + NUM_TX_DESC) * sizeof(struct de4x5_desc);
1164#if defined(__alpha__) || defined(__powerpc__) || defined(__sparc_v9__) || defined(DE4X5_DO_MEMCPY)
1165 lp->dma_size += RX_BUFF_SZ * NUM_RX_DESC + DE4X5_ALIGN;
1166#endif
1167 lp->rx_ring = dma_alloc_coherent(gendev, lp->dma_size,
1168 &lp->dma_rings, GFP_ATOMIC);
1169 if (lp->rx_ring == NULL) {
1170 return -ENOMEM;
1171 }
1172
1173 lp->tx_ring = lp->rx_ring + NUM_RX_DESC;
1174
1175 /*
1176 ** Set up the RX descriptor ring (Intels)
1177 ** Allocate contiguous receive buffers, long word aligned (Alphas)
1178 */
1179#if !defined(__alpha__) && !defined(__powerpc__) && !defined(__sparc_v9__) && !defined(DE4X5_DO_MEMCPY)
1180 for (i=0; i<NUM_RX_DESC; i++) {
1181 lp->rx_ring[i].status = 0;
1182 lp->rx_ring[i].des1 = cpu_to_le32(RX_BUFF_SZ);
1183 lp->rx_ring[i].buf = 0;
1184 lp->rx_ring[i].next = 0;
1185 lp->rx_skb[i] = (struct sk_buff *) 1; /* Dummy entry */
1186 }
1187
1188#else
1189 {
1190 dma_addr_t dma_rx_bufs;
1191
1192 dma_rx_bufs = lp->dma_rings + (NUM_RX_DESC + NUM_TX_DESC)
1193 * sizeof(struct de4x5_desc);
1194 dma_rx_bufs = (dma_rx_bufs + DE4X5_ALIGN) & ~DE4X5_ALIGN;
1195 lp->rx_bufs = (char *)(((long)(lp->rx_ring + NUM_RX_DESC
1196 + NUM_TX_DESC) + DE4X5_ALIGN) & ~DE4X5_ALIGN);
1197 for (i=0; i<NUM_RX_DESC; i++) {
1198 lp->rx_ring[i].status = 0;
1199 lp->rx_ring[i].des1 = cpu_to_le32(RX_BUFF_SZ);
1200 lp->rx_ring[i].buf =
1201 cpu_to_le32(dma_rx_bufs+i*RX_BUFF_SZ);
1202 lp->rx_ring[i].next = 0;
1203 lp->rx_skb[i] = (struct sk_buff *) 1; /* Dummy entry */
1204 }
1205
1206 }
1207#endif
1208
1209 barrier();
1210
1211 lp->rxRingSize = NUM_RX_DESC;
1212 lp->txRingSize = NUM_TX_DESC;
1213
1214 /* Write the end of list marker to the descriptor lists */
1215 lp->rx_ring[lp->rxRingSize - 1].des1 |= cpu_to_le32(RD_RER);
1216 lp->tx_ring[lp->txRingSize - 1].des1 |= cpu_to_le32(TD_TER);
1217
1218 /* Tell the adapter where the TX/RX rings are located. */
1219 outl(lp->dma_rings, DE4X5_RRBA);
1220 outl(lp->dma_rings + NUM_RX_DESC * sizeof(struct de4x5_desc),
1221 DE4X5_TRBA);
1222
1223 /* Initialise the IRQ mask and Enable/Disable */
1224 lp->irq_mask = IMR_RIM | IMR_TIM | IMR_TUM | IMR_UNM;
1225 lp->irq_en = IMR_NIM | IMR_AIM;
1226
1227 /* Create a loopback packet frame for later media probing */
1228 create_packet(dev, lp->frame, sizeof(lp->frame));
1229
1230 /* Check if the RX overflow bug needs testing for */
1231 i = lp->cfrv & 0x000000fe;
1232 if ((lp->chipset == DC21140) && (i == 0x20)) {
1233 lp->rx_ovf = 1;
1234 }
1235
1236 /* Initialise the SROM pointers if possible */
1237 if (lp->useSROM) {
1238 lp->state = INITIALISED;
1239 if (srom_infoleaf_info(dev)) {
1240 dma_free_coherent (gendev, lp->dma_size,
1241 lp->rx_ring, lp->dma_rings);
1242 return -ENXIO;
1243 }
1244 srom_init(dev);
1245 }
1246
1247 lp->state = CLOSED;
1248
1249 /*
1250 ** Check for an MII interface
1251 */
1252 if ((lp->chipset != DC21040) && (lp->chipset != DC21041)) {
1253 mii_get_phy(dev);
1254 }
1255
1256#ifndef __sparc_v9__
1257 printk(" and requires IRQ%d (provided by %s).\n", dev->irq,
1258#else
1259 printk(" and requires IRQ%x (provided by %s).\n", dev->irq,
1260#endif
1261 ((lp->bus == PCI) ? "PCI BIOS" : "EISA CNFG"));
1262 }
1263
1264 if (de4x5_debug & DEBUG_VERSION) {
1265 printk(version);
1266 }
1267
1268 /* The DE4X5-specific entries in the device structure. */
1269 SET_MODULE_OWNER(dev);
1270 SET_NETDEV_DEV(dev, gendev);
1271 dev->open = &de4x5_open;
1272 dev->hard_start_xmit = &de4x5_queue_pkt;
1273 dev->stop = &de4x5_close;
1274 dev->get_stats = &de4x5_get_stats;
1275 dev->set_multicast_list = &set_multicast_list;
1276 dev->do_ioctl = &de4x5_ioctl;
1277
1278 dev->mem_start = 0;
1279
1280 /* Fill in the generic fields of the device structure. */
1281 if ((status = register_netdev (dev))) {
1282 dma_free_coherent (gendev, lp->dma_size,
1283 lp->rx_ring, lp->dma_rings);
1284 return status;
1285 }
1286
1287 /* Let the adapter sleep to save power */
1288 yawn(dev, SLEEP);
1289
1290 return status;
1291}
1292
1293
1294static int
1295de4x5_open(struct net_device *dev)
1296{
1297 struct de4x5_private *lp = netdev_priv(dev);
1298 u_long iobase = dev->base_addr;
1299 int i, status = 0;
1300 s32 omr;
1301
1302 /* Allocate the RX buffers */
1303 for (i=0; i<lp->rxRingSize; i++) {
1304 if (de4x5_alloc_rx_buff(dev, i, 0) == NULL) {
1305 de4x5_free_rx_buffs(dev);
1306 return -EAGAIN;
1307 }
1308 }
1309
1310 /*
1311 ** Wake up the adapter
1312 */
1313 yawn(dev, WAKEUP);
1314
1315 /*
1316 ** Re-initialize the DE4X5...
1317 */
1318 status = de4x5_init(dev);
1319 spin_lock_init(&lp->lock);
1320 lp->state = OPEN;
1321 de4x5_dbg_open(dev);
1322
1323 if (request_irq(dev->irq, (void *)de4x5_interrupt, SA_SHIRQ,
1324 lp->adapter_name, dev)) {
1325 printk("de4x5_open(): Requested IRQ%d is busy - attemping FAST/SHARE...", dev->irq);
1326 if (request_irq(dev->irq, de4x5_interrupt, SA_INTERRUPT | SA_SHIRQ,
1327 lp->adapter_name, dev)) {
1328 printk("\n Cannot get IRQ- reconfigure your hardware.\n");
1329 disable_ast(dev);
1330 de4x5_free_rx_buffs(dev);
1331 de4x5_free_tx_buffs(dev);
1332 yawn(dev, SLEEP);
1333 lp->state = CLOSED;
1334 return -EAGAIN;
1335 } else {
1336 printk("\n Succeeded, but you should reconfigure your hardware to avoid this.\n");
1337 printk("WARNING: there may be IRQ related problems in heavily loaded systems.\n");
1338 }
1339 }
1340
1341 lp->interrupt = UNMASK_INTERRUPTS;
1342 dev->trans_start = jiffies;
1343
1344 START_DE4X5;
1345
1346 de4x5_setup_intr(dev);
1347
1348 if (de4x5_debug & DEBUG_OPEN) {
1349 printk("\tsts: 0x%08x\n", inl(DE4X5_STS));
1350 printk("\tbmr: 0x%08x\n", inl(DE4X5_BMR));
1351 printk("\timr: 0x%08x\n", inl(DE4X5_IMR));
1352 printk("\tomr: 0x%08x\n", inl(DE4X5_OMR));
1353 printk("\tsisr: 0x%08x\n", inl(DE4X5_SISR));
1354 printk("\tsicr: 0x%08x\n", inl(DE4X5_SICR));
1355 printk("\tstrr: 0x%08x\n", inl(DE4X5_STRR));
1356 printk("\tsigr: 0x%08x\n", inl(DE4X5_SIGR));
1357 }
1358
1359 return status;
1360}
1361
1362/*
1363** Initialize the DE4X5 operating conditions. NB: a chip problem with the
1364** DC21140 requires using perfect filtering mode for that chip. Since I can't
1365** see why I'd want > 14 multicast addresses, I have changed all chips to use
1366** the perfect filtering mode. Keep the DMA burst length at 8: there seems
1367** to be data corruption problems if it is larger (UDP errors seen from a
1368** ttcp source).
1369*/
1370static int
1371de4x5_init(struct net_device *dev)
1372{
1373 /* Lock out other processes whilst setting up the hardware */
1374 netif_stop_queue(dev);
1375
1376 de4x5_sw_reset(dev);
1377
1378 /* Autoconfigure the connected port */
1379 autoconf_media(dev);
1380
1381 return 0;
1382}
1383
1384static int
1385de4x5_sw_reset(struct net_device *dev)
1386{
1387 struct de4x5_private *lp = netdev_priv(dev);
1388 u_long iobase = dev->base_addr;
1389 int i, j, status = 0;
1390 s32 bmr, omr;
1391
1392 /* Select the MII or SRL port now and RESET the MAC */
1393 if (!lp->useSROM) {
1394 if (lp->phy[lp->active].id != 0) {
1395 lp->infoblock_csr6 = OMR_SDP | OMR_PS | OMR_HBD;
1396 } else {
1397 lp->infoblock_csr6 = OMR_SDP | OMR_TTM;
1398 }
1399 de4x5_switch_mac_port(dev);
1400 }
1401
1402 /*
1403 ** Set the programmable burst length to 8 longwords for all the DC21140
1404 ** Fasternet chips and 4 longwords for all others: DMA errors result
1405 ** without these values. Cache align 16 long.
1406 */
1407 bmr = (lp->chipset==DC21140 ? PBL_8 : PBL_4) | DESC_SKIP_LEN | DE4X5_CACHE_ALIGN;
1408 bmr |= ((lp->chipset & ~0x00ff)==DC2114x ? BMR_RML : 0);
1409 outl(bmr, DE4X5_BMR);
1410
1411 omr = inl(DE4X5_OMR) & ~OMR_PR; /* Turn off promiscuous mode */
1412 if (lp->chipset == DC21140) {
1413 omr |= (OMR_SDP | OMR_SB);
1414 }
1415 lp->setup_f = PERFECT;
1416 outl(lp->dma_rings, DE4X5_RRBA);
1417 outl(lp->dma_rings + NUM_RX_DESC * sizeof(struct de4x5_desc),
1418 DE4X5_TRBA);
1419
1420 lp->rx_new = lp->rx_old = 0;
1421 lp->tx_new = lp->tx_old = 0;
1422
1423 for (i = 0; i < lp->rxRingSize; i++) {
1424 lp->rx_ring[i].status = cpu_to_le32(R_OWN);
1425 }
1426
1427 for (i = 0; i < lp->txRingSize; i++) {
1428 lp->tx_ring[i].status = cpu_to_le32(0);
1429 }
1430
1431 barrier();
1432
1433 /* Build the setup frame depending on filtering mode */
1434 SetMulticastFilter(dev);
1435
1436 load_packet(dev, lp->setup_frame, PERFECT_F|TD_SET|SETUP_FRAME_LEN, (struct sk_buff *)1);
1437 outl(omr|OMR_ST, DE4X5_OMR);
1438
1439 /* Poll for setup frame completion (adapter interrupts are disabled now) */
1440
1441 for (j=0, i=0;(i<500) && (j==0);i++) { /* Upto 500ms delay */
1442 mdelay(1);
1443 if ((s32)le32_to_cpu(lp->tx_ring[lp->tx_new].status) >= 0) j=1;
1444 }
1445 outl(omr, DE4X5_OMR); /* Stop everything! */
1446
1447 if (j == 0) {
1448 printk("%s: Setup frame timed out, status %08x\n", dev->name,
1449 inl(DE4X5_STS));
1450 status = -EIO;
1451 }
1452
1453 lp->tx_new = (++lp->tx_new) % lp->txRingSize;
1454 lp->tx_old = lp->tx_new;
1455
1456 return status;
1457}
1458
1459/*
1460** Writes a socket buffer address to the next available transmit descriptor.
1461*/
1462static int
1463de4x5_queue_pkt(struct sk_buff *skb, struct net_device *dev)
1464{
1465 struct de4x5_private *lp = netdev_priv(dev);
1466 u_long iobase = dev->base_addr;
1467 int status = 0;
1468 u_long flags = 0;
1469
1470 netif_stop_queue(dev);
1471 if (lp->tx_enable == NO) { /* Cannot send for now */
1472 return -1;
1473 }
1474
1475 /*
1476 ** Clean out the TX ring asynchronously to interrupts - sometimes the
1477 ** interrupts are lost by delayed descriptor status updates relative to
1478 ** the irq assertion, especially with a busy PCI bus.
1479 */
1480 spin_lock_irqsave(&lp->lock, flags);
1481 de4x5_tx(dev);
1482 spin_unlock_irqrestore(&lp->lock, flags);
1483
1484 /* Test if cache is already locked - requeue skb if so */
1485 if (test_and_set_bit(0, (void *)&lp->cache.lock) && !lp->interrupt)
1486 return -1;
1487
1488 /* Transmit descriptor ring full or stale skb */
1489 if (netif_queue_stopped(dev) || (u_long) lp->tx_skb[lp->tx_new] > 1) {
1490 if (lp->interrupt) {
1491 de4x5_putb_cache(dev, skb); /* Requeue the buffer */
1492 } else {
1493 de4x5_put_cache(dev, skb);
1494 }
1495 if (de4x5_debug & DEBUG_TX) {
1496 printk("%s: transmit busy, lost media or stale skb found:\n STS:%08x\n tbusy:%d\n IMR:%08x\n OMR:%08x\n Stale skb: %s\n",dev->name, inl(DE4X5_STS), netif_queue_stopped(dev), inl(DE4X5_IMR), inl(DE4X5_OMR), ((u_long) lp->tx_skb[lp->tx_new] > 1) ? "YES" : "NO");
1497 }
1498 } else if (skb->len > 0) {
1499 /* If we already have stuff queued locally, use that first */
1500 if (lp->cache.skb && !lp->interrupt) {
1501 de4x5_put_cache(dev, skb);
1502 skb = de4x5_get_cache(dev);
1503 }
1504
1505 while (skb && !netif_queue_stopped(dev) &&
1506 (u_long) lp->tx_skb[lp->tx_new] <= 1) {
1507 spin_lock_irqsave(&lp->lock, flags);
1508 netif_stop_queue(dev);
1509 load_packet(dev, skb->data, TD_IC | TD_LS | TD_FS | skb->len, skb);
1510 lp->stats.tx_bytes += skb->len;
1511 outl(POLL_DEMAND, DE4X5_TPD);/* Start the TX */
1512
1513 lp->tx_new = (++lp->tx_new) % lp->txRingSize;
1514 dev->trans_start = jiffies;
1515
1516 if (TX_BUFFS_AVAIL) {
1517 netif_start_queue(dev); /* Another pkt may be queued */
1518 }
1519 skb = de4x5_get_cache(dev);
1520 spin_unlock_irqrestore(&lp->lock, flags);
1521 }
1522 if (skb) de4x5_putb_cache(dev, skb);
1523 }
1524
1525 lp->cache.lock = 0;
1526
1527 return status;
1528}
1529
1530/*
1531** The DE4X5 interrupt handler.
1532**
1533** I/O Read/Writes through intermediate PCI bridges are never 'posted',
1534** so that the asserted interrupt always has some real data to work with -
1535** if these I/O accesses are ever changed to memory accesses, ensure the
1536** STS write is read immediately to complete the transaction if the adapter
1537** is not on bus 0. Lost interrupts can still occur when the PCI bus load
1538** is high and descriptor status bits cannot be set before the associated
1539** interrupt is asserted and this routine entered.
1540*/
1541static irqreturn_t
1542de4x5_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1543{
1544 struct net_device *dev = (struct net_device *)dev_id;
1545 struct de4x5_private *lp;
1546 s32 imr, omr, sts, limit;
1547 u_long iobase;
1548 unsigned int handled = 0;
1549
1550 if (dev == NULL) {
1551 printk ("de4x5_interrupt(): irq %d for unknown device.\n", irq);
1552 return IRQ_NONE;
1553 }
1554 lp = netdev_priv(dev);
1555 spin_lock(&lp->lock);
1556 iobase = dev->base_addr;
1557
1558 DISABLE_IRQs; /* Ensure non re-entrancy */
1559
1560 if (test_and_set_bit(MASK_INTERRUPTS, (void*) &lp->interrupt))
1561 printk("%s: Re-entering the interrupt handler.\n", dev->name);
1562
1563 synchronize_irq(dev->irq);
1564
1565 for (limit=0; limit<8; limit++) {
1566 sts = inl(DE4X5_STS); /* Read IRQ status */
1567 outl(sts, DE4X5_STS); /* Reset the board interrupts */
1568
1569 if (!(sts & lp->irq_mask)) break;/* All done */
1570 handled = 1;
1571
1572 if (sts & (STS_RI | STS_RU)) /* Rx interrupt (packet[s] arrived) */
1573 de4x5_rx(dev);
1574
1575 if (sts & (STS_TI | STS_TU)) /* Tx interrupt (packet sent) */
1576 de4x5_tx(dev);
1577
1578 if (sts & STS_LNF) { /* TP Link has failed */
1579 lp->irq_mask &= ~IMR_LFM;
1580 }
1581
1582 if (sts & STS_UNF) { /* Transmit underrun */
1583 de4x5_txur(dev);
1584 }
1585
1586 if (sts & STS_SE) { /* Bus Error */
1587 STOP_DE4X5;
1588 printk("%s: Fatal bus error occurred, sts=%#8x, device stopped.\n",
1589 dev->name, sts);
1590 spin_unlock(&lp->lock);
1591 return IRQ_HANDLED;
1592 }
1593 }
1594
1595 /* Load the TX ring with any locally stored packets */
1596 if (!test_and_set_bit(0, (void *)&lp->cache.lock)) {
1597 while (lp->cache.skb && !netif_queue_stopped(dev) && lp->tx_enable) {
1598 de4x5_queue_pkt(de4x5_get_cache(dev), dev);
1599 }
1600 lp->cache.lock = 0;
1601 }
1602
1603 lp->interrupt = UNMASK_INTERRUPTS;
1604 ENABLE_IRQs;
1605 spin_unlock(&lp->lock);
1606
1607 return IRQ_RETVAL(handled);
1608}
1609
1610static int
1611de4x5_rx(struct net_device *dev)
1612{
1613 struct de4x5_private *lp = netdev_priv(dev);
1614 u_long iobase = dev->base_addr;
1615 int entry;
1616 s32 status;
1617
1618 for (entry=lp->rx_new; (s32)le32_to_cpu(lp->rx_ring[entry].status)>=0;
1619 entry=lp->rx_new) {
1620 status = (s32)le32_to_cpu(lp->rx_ring[entry].status);
1621
1622 if (lp->rx_ovf) {
1623 if (inl(DE4X5_MFC) & MFC_FOCM) {
1624 de4x5_rx_ovfc(dev);
1625 break;
1626 }
1627 }
1628
1629 if (status & RD_FS) { /* Remember the start of frame */
1630 lp->rx_old = entry;
1631 }
1632
1633 if (status & RD_LS) { /* Valid frame status */
1634 if (lp->tx_enable) lp->linkOK++;
1635 if (status & RD_ES) { /* There was an error. */
1636 lp->stats.rx_errors++; /* Update the error stats. */
1637 if (status & (RD_RF | RD_TL)) lp->stats.rx_frame_errors++;
1638 if (status & RD_CE) lp->stats.rx_crc_errors++;
1639 if (status & RD_OF) lp->stats.rx_fifo_errors++;
1640 if (status & RD_TL) lp->stats.rx_length_errors++;
1641 if (status & RD_RF) lp->pktStats.rx_runt_frames++;
1642 if (status & RD_CS) lp->pktStats.rx_collision++;
1643 if (status & RD_DB) lp->pktStats.rx_dribble++;
1644 if (status & RD_OF) lp->pktStats.rx_overflow++;
1645 } else { /* A valid frame received */
1646 struct sk_buff *skb;
1647 short pkt_len = (short)(le32_to_cpu(lp->rx_ring[entry].status)
1648 >> 16) - 4;
1649
1650 if ((skb = de4x5_alloc_rx_buff(dev, entry, pkt_len)) == NULL) {
1651 printk("%s: Insufficient memory; nuking packet.\n",
1652 dev->name);
1653 lp->stats.rx_dropped++;
1654 } else {
1655 de4x5_dbg_rx(skb, pkt_len);
1656
1657 /* Push up the protocol stack */
1658 skb->protocol=eth_type_trans(skb,dev);
1659 de4x5_local_stats(dev, skb->data, pkt_len);
1660 netif_rx(skb);
1661
1662 /* Update stats */
1663 dev->last_rx = jiffies;
1664 lp->stats.rx_packets++;
1665 lp->stats.rx_bytes += pkt_len;
1666 }
1667 }
1668
1669 /* Change buffer ownership for this frame, back to the adapter */
1670 for (;lp->rx_old!=entry;lp->rx_old=(++lp->rx_old)%lp->rxRingSize) {
1671 lp->rx_ring[lp->rx_old].status = cpu_to_le32(R_OWN);
1672 barrier();
1673 }
1674 lp->rx_ring[entry].status = cpu_to_le32(R_OWN);
1675 barrier();
1676 }
1677
1678 /*
1679 ** Update entry information
1680 */
1681 lp->rx_new = (++lp->rx_new) % lp->rxRingSize;
1682 }
1683
1684 return 0;
1685}
1686
1687static inline void
1688de4x5_free_tx_buff(struct de4x5_private *lp, int entry)
1689{
1690 dma_unmap_single(lp->gendev, le32_to_cpu(lp->tx_ring[entry].buf),
1691 le32_to_cpu(lp->tx_ring[entry].des1) & TD_TBS1,
1692 DMA_TO_DEVICE);
1693 if ((u_long) lp->tx_skb[entry] > 1)
1694 dev_kfree_skb_irq(lp->tx_skb[entry]);
1695 lp->tx_skb[entry] = NULL;
1696}
1697
1698/*
1699** Buffer sent - check for TX buffer errors.
1700*/
1701static int
1702de4x5_tx(struct net_device *dev)
1703{
1704 struct de4x5_private *lp = netdev_priv(dev);
1705 u_long iobase = dev->base_addr;
1706 int entry;
1707 s32 status;
1708
1709 for (entry = lp->tx_old; entry != lp->tx_new; entry = lp->tx_old) {
1710 status = (s32)le32_to_cpu(lp->tx_ring[entry].status);
1711 if (status < 0) { /* Buffer not sent yet */
1712 break;
1713 } else if (status != 0x7fffffff) { /* Not setup frame */
1714 if (status & TD_ES) { /* An error happened */
1715 lp->stats.tx_errors++;
1716 if (status & TD_NC) lp->stats.tx_carrier_errors++;
1717 if (status & TD_LC) lp->stats.tx_window_errors++;
1718 if (status & TD_UF) lp->stats.tx_fifo_errors++;
1719 if (status & TD_EC) lp->pktStats.excessive_collisions++;
1720 if (status & TD_DE) lp->stats.tx_aborted_errors++;
1721
1722 if (TX_PKT_PENDING) {
1723 outl(POLL_DEMAND, DE4X5_TPD);/* Restart a stalled TX */
1724 }
1725 } else { /* Packet sent */
1726 lp->stats.tx_packets++;
1727 if (lp->tx_enable) lp->linkOK++;
1728 }
1729 /* Update the collision counter */
1730 lp->stats.collisions += ((status & TD_EC) ? 16 :
1731 ((status & TD_CC) >> 3));
1732
1733 /* Free the buffer. */
1734 if (lp->tx_skb[entry] != NULL)
1735 de4x5_free_tx_buff(lp, entry);
1736 }
1737
1738 /* Update all the pointers */
1739 lp->tx_old = (++lp->tx_old) % lp->txRingSize;
1740 }
1741
1742 /* Any resources available? */
1743 if (TX_BUFFS_AVAIL && netif_queue_stopped(dev)) {
1744 if (lp->interrupt)
1745 netif_wake_queue(dev);
1746 else
1747 netif_start_queue(dev);
1748 }
1749
1750 return 0;
1751}
1752
1753static int
1754de4x5_ast(struct net_device *dev)
1755{
1756 struct de4x5_private *lp = netdev_priv(dev);
1757 int next_tick = DE4X5_AUTOSENSE_MS;
1758
1759 disable_ast(dev);
1760
1761 if (lp->useSROM) {
1762 next_tick = srom_autoconf(dev);
1763 } else if (lp->chipset == DC21140) {
1764 next_tick = dc21140m_autoconf(dev);
1765 } else if (lp->chipset == DC21041) {
1766 next_tick = dc21041_autoconf(dev);
1767 } else if (lp->chipset == DC21040) {
1768 next_tick = dc21040_autoconf(dev);
1769 }
1770 lp->linkOK = 0;
1771 enable_ast(dev, next_tick);
1772
1773 return 0;
1774}
1775
1776static int
1777de4x5_txur(struct net_device *dev)
1778{
1779 struct de4x5_private *lp = netdev_priv(dev);
1780 u_long iobase = dev->base_addr;
1781 int omr;
1782
1783 omr = inl(DE4X5_OMR);
1784 if (!(omr & OMR_SF) || (lp->chipset==DC21041) || (lp->chipset==DC21040)) {
1785 omr &= ~(OMR_ST|OMR_SR);
1786 outl(omr, DE4X5_OMR);
1787 while (inl(DE4X5_STS) & STS_TS);
1788 if ((omr & OMR_TR) < OMR_TR) {
1789 omr += 0x4000;
1790 } else {
1791 omr |= OMR_SF;
1792 }
1793 outl(omr | OMR_ST | OMR_SR, DE4X5_OMR);
1794 }
1795
1796 return 0;
1797}
1798
1799static int
1800de4x5_rx_ovfc(struct net_device *dev)
1801{
1802 struct de4x5_private *lp = netdev_priv(dev);
1803 u_long iobase = dev->base_addr;
1804 int omr;
1805
1806 omr = inl(DE4X5_OMR);
1807 outl(omr & ~OMR_SR, DE4X5_OMR);
1808 while (inl(DE4X5_STS) & STS_RS);
1809
1810 for (; (s32)le32_to_cpu(lp->rx_ring[lp->rx_new].status)>=0;) {
1811 lp->rx_ring[lp->rx_new].status = cpu_to_le32(R_OWN);
1812 lp->rx_new = (++lp->rx_new % lp->rxRingSize);
1813 }
1814
1815 outl(omr, DE4X5_OMR);
1816
1817 return 0;
1818}
1819
1820static int
1821de4x5_close(struct net_device *dev)
1822{
1823 struct de4x5_private *lp = netdev_priv(dev);
1824 u_long iobase = dev->base_addr;
1825 s32 imr, omr;
1826
1827 disable_ast(dev);
1828
1829 netif_stop_queue(dev);
1830
1831 if (de4x5_debug & DEBUG_CLOSE) {
1832 printk("%s: Shutting down ethercard, status was %8.8x.\n",
1833 dev->name, inl(DE4X5_STS));
1834 }
1835
1836 /*
1837 ** We stop the DE4X5 here... mask interrupts and stop TX & RX
1838 */
1839 DISABLE_IRQs;
1840 STOP_DE4X5;
1841
1842 /* Free the associated irq */
1843 free_irq(dev->irq, dev);
1844 lp->state = CLOSED;
1845
1846 /* Free any socket buffers */
1847 de4x5_free_rx_buffs(dev);
1848 de4x5_free_tx_buffs(dev);
1849
1850 /* Put the adapter to sleep to save power */
1851 yawn(dev, SLEEP);
1852
1853 return 0;
1854}
1855
1856static struct net_device_stats *
1857de4x5_get_stats(struct net_device *dev)
1858{
1859 struct de4x5_private *lp = netdev_priv(dev);
1860 u_long iobase = dev->base_addr;
1861
1862 lp->stats.rx_missed_errors = (int)(inl(DE4X5_MFC) & (MFC_OVFL | MFC_CNTR));
1863
1864 return &lp->stats;
1865}
1866
1867static void
1868de4x5_local_stats(struct net_device *dev, char *buf, int pkt_len)
1869{
1870 struct de4x5_private *lp = netdev_priv(dev);
1871 int i;
1872
1873 for (i=1; i<DE4X5_PKT_STAT_SZ-1; i++) {
1874 if (pkt_len < (i*DE4X5_PKT_BIN_SZ)) {
1875 lp->pktStats.bins[i]++;
1876 i = DE4X5_PKT_STAT_SZ;
1877 }
1878 }
1879 if (buf[0] & 0x01) { /* Multicast/Broadcast */
1880 if ((*(s32 *)&buf[0] == -1) && (*(s16 *)&buf[4] == -1)) {
1881 lp->pktStats.broadcast++;
1882 } else {
1883 lp->pktStats.multicast++;
1884 }
1885 } else if ((*(s32 *)&buf[0] == *(s32 *)&dev->dev_addr[0]) &&
1886 (*(s16 *)&buf[4] == *(s16 *)&dev->dev_addr[4])) {
1887 lp->pktStats.unicast++;
1888 }
1889
1890 lp->pktStats.bins[0]++; /* Duplicates stats.rx_packets */
1891 if (lp->pktStats.bins[0] == 0) { /* Reset counters */
1892 memset((char *)&lp->pktStats, 0, sizeof(lp->pktStats));
1893 }
1894
1895 return;
1896}
1897
1898/*
1899** Removes the TD_IC flag from previous descriptor to improve TX performance.
1900** If the flag is changed on a descriptor that is being read by the hardware,
1901** I assume PCI transaction ordering will mean you are either successful or
1902** just miss asserting the change to the hardware. Anyway you're messing with
1903** a descriptor you don't own, but this shouldn't kill the chip provided
1904** the descriptor register is read only to the hardware.
1905*/
1906static void
1907load_packet(struct net_device *dev, char *buf, u32 flags, struct sk_buff *skb)
1908{
1909 struct de4x5_private *lp = netdev_priv(dev);
1910 int entry = (lp->tx_new ? lp->tx_new-1 : lp->txRingSize-1);
1911 dma_addr_t buf_dma = dma_map_single(lp->gendev, buf, flags & TD_TBS1, DMA_TO_DEVICE);
1912
1913 lp->tx_ring[lp->tx_new].buf = cpu_to_le32(buf_dma);
1914 lp->tx_ring[lp->tx_new].des1 &= cpu_to_le32(TD_TER);
1915 lp->tx_ring[lp->tx_new].des1 |= cpu_to_le32(flags);
1916 lp->tx_skb[lp->tx_new] = skb;
1917 lp->tx_ring[entry].des1 &= cpu_to_le32(~TD_IC);
1918 barrier();
1919
1920 lp->tx_ring[lp->tx_new].status = cpu_to_le32(T_OWN);
1921 barrier();
1922}
1923
1924/*
1925** Set or clear the multicast filter for this adaptor.
1926*/
1927static void
1928set_multicast_list(struct net_device *dev)
1929{
1930 struct de4x5_private *lp = netdev_priv(dev);
1931 u_long iobase = dev->base_addr;
1932
1933 /* First, double check that the adapter is open */
1934 if (lp->state == OPEN) {
1935 if (dev->flags & IFF_PROMISC) { /* set promiscuous mode */
1936 u32 omr;
1937 omr = inl(DE4X5_OMR);
1938 omr |= OMR_PR;
1939 outl(omr, DE4X5_OMR);
1940 } else {
1941 SetMulticastFilter(dev);
1942 load_packet(dev, lp->setup_frame, TD_IC | PERFECT_F | TD_SET |
1943 SETUP_FRAME_LEN, (struct sk_buff *)1);
1944
1945 lp->tx_new = (++lp->tx_new) % lp->txRingSize;
1946 outl(POLL_DEMAND, DE4X5_TPD); /* Start the TX */
1947 dev->trans_start = jiffies;
1948 }
1949 }
1950}
1951
1952/*
1953** Calculate the hash code and update the logical address filter
1954** from a list of ethernet multicast addresses.
1955** Little endian crc one liner from Matt Thomas, DEC.
1956*/
1957static void
1958SetMulticastFilter(struct net_device *dev)
1959{
1960 struct de4x5_private *lp = netdev_priv(dev);
1961 struct dev_mc_list *dmi=dev->mc_list;
1962 u_long iobase = dev->base_addr;
1963 int i, j, bit, byte;
1964 u16 hashcode;
1965 u32 omr, crc;
1966 char *pa;
1967 unsigned char *addrs;
1968
1969 omr = inl(DE4X5_OMR);
1970 omr &= ~(OMR_PR | OMR_PM);
1971 pa = build_setup_frame(dev, ALL); /* Build the basic frame */
1972
1973 if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 14)) {
1974 omr |= OMR_PM; /* Pass all multicasts */
1975 } else if (lp->setup_f == HASH_PERF) { /* Hash Filtering */
1976 for (i=0;i<dev->mc_count;i++) { /* for each address in the list */
1977 addrs=dmi->dmi_addr;
1978 dmi=dmi->next;
1979 if ((*addrs & 0x01) == 1) { /* multicast address? */
1980 crc = ether_crc_le(ETH_ALEN, addrs);
1981 hashcode = crc & HASH_BITS; /* hashcode is 9 LSb of CRC */
1982
1983 byte = hashcode >> 3; /* bit[3-8] -> byte in filter */
1984 bit = 1 << (hashcode & 0x07);/* bit[0-2] -> bit in byte */
1985
1986 byte <<= 1; /* calc offset into setup frame */
1987 if (byte & 0x02) {
1988 byte -= 1;
1989 }
1990 lp->setup_frame[byte] |= bit;
1991 }
1992 }
1993 } else { /* Perfect filtering */
1994 for (j=0; j<dev->mc_count; j++) {
1995 addrs=dmi->dmi_addr;
1996 dmi=dmi->next;
1997 for (i=0; i<ETH_ALEN; i++) {
1998 *(pa + (i&1)) = *addrs++;
1999 if (i & 0x01) pa += 4;
2000 }
2001 }
2002 }
2003 outl(omr, DE4X5_OMR);
2004
2005 return;
2006}
2007
2008#ifdef CONFIG_EISA
2009
2010static u_char de4x5_irq[] = EISA_ALLOWED_IRQ_LIST;
2011
2012static int __init de4x5_eisa_probe (struct device *gendev)
2013{
2014 struct eisa_device *edev;
2015 u_long iobase;
2016 u_char irq, regval;
2017 u_short vendor;
2018 u32 cfid;
2019 int status, device;
2020 struct net_device *dev;
2021 struct de4x5_private *lp;
2022
2023 edev = to_eisa_device (gendev);
2024 iobase = edev->base_addr;
2025
2026 if (!request_region (iobase, DE4X5_EISA_TOTAL_SIZE, "de4x5"))
2027 return -EBUSY;
2028
2029 if (!request_region (iobase + DE4X5_EISA_IO_PORTS,
2030 DE4X5_EISA_TOTAL_SIZE, "de4x5")) {
2031 status = -EBUSY;
2032 goto release_reg_1;
2033 }
2034
2035 if (!(dev = alloc_etherdev (sizeof (struct de4x5_private)))) {
2036 status = -ENOMEM;
2037 goto release_reg_2;
2038 }
2039 lp = netdev_priv(dev);
2040
2041 cfid = (u32) inl(PCI_CFID);
2042 lp->cfrv = (u_short) inl(PCI_CFRV);
2043 device = (cfid >> 8) & 0x00ffff00;
2044 vendor = (u_short) cfid;
2045
2046 /* Read the EISA Configuration Registers */
2047 regval = inb(EISA_REG0) & (ER0_INTL | ER0_INTT);
2048#ifdef CONFIG_ALPHA
2049 /* Looks like the Jensen firmware (rev 2.2) doesn't really
2050 * care about the EISA configuration, and thus doesn't
2051 * configure the PLX bridge properly. Oh well... Simply mimic
2052 * the EISA config file to sort it out. */
2053
2054 /* EISA REG1: Assert DecChip 21040 HW Reset */
2055 outb (ER1_IAM | 1, EISA_REG1);
2056 mdelay (1);
2057
2058 /* EISA REG1: Deassert DecChip 21040 HW Reset */
2059 outb (ER1_IAM, EISA_REG1);
2060 mdelay (1);
2061
2062 /* EISA REG3: R/W Burst Transfer Enable */
2063 outb (ER3_BWE | ER3_BRE, EISA_REG3);
2064
2065 /* 32_bit slave/master, Preempt Time=23 bclks, Unlatched Interrupt */
2066 outb (ER0_BSW | ER0_BMW | ER0_EPT | regval, EISA_REG0);
2067#endif
2068 irq = de4x5_irq[(regval >> 1) & 0x03];
2069
2070 if (is_DC2114x) {
2071 device = ((lp->cfrv & CFRV_RN) < DC2114x_BRK ? DC21142 : DC21143);
2072 }
2073 lp->chipset = device;
2074 lp->bus = EISA;
2075
2076 /* Write the PCI Configuration Registers */
2077 outl(PCI_COMMAND_IO | PCI_COMMAND_MASTER, PCI_CFCS);
2078 outl(0x00006000, PCI_CFLT);
2079 outl(iobase, PCI_CBIO);
2080
2081 DevicePresent(dev, EISA_APROM);
2082
2083 dev->irq = irq;
2084
2085 if (!(status = de4x5_hw_init (dev, iobase, gendev))) {
2086 return 0;
2087 }
2088
2089 free_netdev (dev);
2090 release_reg_2:
2091 release_region (iobase + DE4X5_EISA_IO_PORTS, DE4X5_EISA_TOTAL_SIZE);
2092 release_reg_1:
2093 release_region (iobase, DE4X5_EISA_TOTAL_SIZE);
2094
2095 return status;
2096}
2097
2098static int __devexit de4x5_eisa_remove (struct device *device)
2099{
2100 struct net_device *dev;
2101 u_long iobase;
2102
2103 dev = device->driver_data;
2104 iobase = dev->base_addr;
2105
2106 unregister_netdev (dev);
2107 free_netdev (dev);
2108 release_region (iobase + DE4X5_EISA_IO_PORTS, DE4X5_EISA_TOTAL_SIZE);
2109 release_region (iobase, DE4X5_EISA_TOTAL_SIZE);
2110
2111 return 0;
2112}
2113
2114static struct eisa_device_id de4x5_eisa_ids[] = {
2115 { "DEC4250", 0 }, /* 0 is the board name index... */
2116 { "" }
2117};
2118
2119static struct eisa_driver de4x5_eisa_driver = {
2120 .id_table = de4x5_eisa_ids,
2121 .driver = {
2122 .name = "de4x5",
2123 .probe = de4x5_eisa_probe,
2124 .remove = __devexit_p (de4x5_eisa_remove),
2125 }
2126};
2127MODULE_DEVICE_TABLE(eisa, de4x5_eisa_ids);
2128#endif
2129
2130#ifdef CONFIG_PCI
2131
2132/*
2133** This function searches the current bus (which is >0) for a DECchip with an
2134** SROM, so that in multiport cards that have one SROM shared between multiple
2135** DECchips, we can find the base SROM irrespective of the BIOS scan direction.
2136** For single port cards this is a time waster...
2137*/
2138static void __devinit
2139srom_search(struct net_device *dev, struct pci_dev *pdev)
2140{
2141 u_char pb;
2142 u_short vendor, status;
2143 u_int irq = 0, device;
2144 u_long iobase = 0; /* Clear upper 32 bits in Alphas */
2145 int i, j, cfrv;
2146 struct de4x5_private *lp = netdev_priv(dev);
Domen Puncer0c5719c2005-09-10 00:27:10 -0700[diff] [blame]2147 struct list_head *walk;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2148
Domen Puncer0c5719c2005-09-10 00:27:10 -0700[diff] [blame]2149 list_for_each(walk, &pdev->bus_list) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2150 struct pci_dev *this_dev = pci_dev_b(walk);
2151
2152 /* Skip the pci_bus list entry */
2153 if (list_entry(walk, struct pci_bus, devices) == pdev->bus) continue;
2154
2155 vendor = this_dev->vendor;
2156 device = this_dev->device << 8;
2157 if (!(is_DC21040 || is_DC21041 || is_DC21140 || is_DC2114x)) continue;
2158
2159 /* Get the chip configuration revision register */
2160 pb = this_dev->bus->number;
2161 pci_read_config_dword(this_dev, PCI_REVISION_ID, &cfrv);
2162
2163 /* Set the device number information */
2164 lp->device = PCI_SLOT(this_dev->devfn);
2165 lp->bus_num = pb;
2166
2167 /* Set the chipset information */
2168 if (is_DC2114x) {
2169 device = ((cfrv & CFRV_RN) < DC2114x_BRK ? DC21142 : DC21143);
2170 }
2171 lp->chipset = device;
2172
2173 /* Get the board I/O address (64 bits on sparc64) */
2174 iobase = pci_resource_start(this_dev, 0);
2175
2176 /* Fetch the IRQ to be used */
2177 irq = this_dev->irq;
2178 if ((irq == 0) || (irq == 0xff) || ((int)irq == -1)) continue;
2179
2180 /* Check if I/O accesses are enabled */
2181 pci_read_config_word(this_dev, PCI_COMMAND, &status);
2182 if (!(status & PCI_COMMAND_IO)) continue;
2183
2184 /* Search for a valid SROM attached to this DECchip */
2185 DevicePresent(dev, DE4X5_APROM);
2186 for (j=0, i=0; i<ETH_ALEN; i++) {
2187 j += (u_char) *((u_char *)&lp->srom + SROM_HWADD + i);
2188 }
2189 if ((j != 0) && (j != 0x5fa)) {
2190 last.chipset = device;
2191 last.bus = pb;
2192 last.irq = irq;
2193 for (i=0; i<ETH_ALEN; i++) {
2194 last.addr[i] = (u_char)*((u_char *)&lp->srom + SROM_HWADD + i);
2195 }
2196 return;
2197 }
2198 }
2199
2200 return;
2201}
2202
2203/*
2204** PCI bus I/O device probe
2205** NB: PCI I/O accesses and Bus Mastering are enabled by the PCI BIOS, not
2206** the driver. Some PCI BIOS's, pre V2.1, need the slot + features to be
2207** enabled by the user first in the set up utility. Hence we just check for
2208** enabled features and silently ignore the card if they're not.
2209**
2210** STOP PRESS: Some BIOS's __require__ the driver to enable the bus mastering
2211** bit. Here, check for I/O accesses and then set BM. If you put the card in
2212** a non BM slot, you're on your own (and complain to the PC vendor that your
2213** PC doesn't conform to the PCI standard)!
2214**
2215** This function is only compatible with the *latest* 2.1.x kernels. For 2.0.x
2216** kernels use the V0.535[n] drivers.
2217*/
2218
2219static int __devinit de4x5_pci_probe (struct pci_dev *pdev,
2220 const struct pci_device_id *ent)
2221{
2222 u_char pb, pbus = 0, dev_num, dnum = 0, timer;
2223 u_short vendor, status;
2224 u_int irq = 0, device;
2225 u_long iobase = 0; /* Clear upper 32 bits in Alphas */
2226 int error;
2227 struct net_device *dev;
2228 struct de4x5_private *lp;
2229
2230 dev_num = PCI_SLOT(pdev->devfn);
2231 pb = pdev->bus->number;
2232
2233 if (io) { /* probe a single PCI device */
2234 pbus = (u_short)(io >> 8);
2235 dnum = (u_short)(io & 0xff);
2236 if ((pbus != pb) || (dnum != dev_num))
2237 return -ENODEV;
2238 }
2239
2240 vendor = pdev->vendor;
2241 device = pdev->device << 8;
2242 if (!(is_DC21040 || is_DC21041 || is_DC21140 || is_DC2114x))
2243 return -ENODEV;
2244
2245 /* Ok, the device seems to be for us. */
2246 if ((error = pci_enable_device (pdev)))
2247 return error;
2248
2249 if (!(dev = alloc_etherdev (sizeof (struct de4x5_private)))) {
2250 error = -ENOMEM;
2251 goto disable_dev;
2252 }
2253
2254 lp = netdev_priv(dev);
2255 lp->bus = PCI;
2256 lp->bus_num = 0;
2257
2258 /* Search for an SROM on this bus */
2259 if (lp->bus_num != pb) {
2260 lp->bus_num = pb;
2261 srom_search(dev, pdev);
2262 }
2263
2264 /* Get the chip configuration revision register */
2265 pci_read_config_dword(pdev, PCI_REVISION_ID, &lp->cfrv);
2266
2267 /* Set the device number information */
2268 lp->device = dev_num;
2269 lp->bus_num = pb;
2270
2271 /* Set the chipset information */
2272 if (is_DC2114x) {
2273 device = ((lp->cfrv & CFRV_RN) < DC2114x_BRK ? DC21142 : DC21143);
2274 }
2275 lp->chipset = device;
2276
2277 /* Get the board I/O address (64 bits on sparc64) */
2278 iobase = pci_resource_start(pdev, 0);
2279
2280 /* Fetch the IRQ to be used */
2281 irq = pdev->irq;
2282 if ((irq == 0) || (irq == 0xff) || ((int)irq == -1)) {
2283 error = -ENODEV;
2284 goto free_dev;
2285 }
2286
2287 /* Check if I/O accesses and Bus Mastering are enabled */
2288 pci_read_config_word(pdev, PCI_COMMAND, &status);
2289#ifdef __powerpc__
2290 if (!(status & PCI_COMMAND_IO)) {
2291 status |= PCI_COMMAND_IO;
2292 pci_write_config_word(pdev, PCI_COMMAND, status);
2293 pci_read_config_word(pdev, PCI_COMMAND, &status);
2294 }
2295#endif /* __powerpc__ */
2296 if (!(status & PCI_COMMAND_IO)) {
2297 error = -ENODEV;
2298 goto free_dev;
2299 }
2300
2301 if (!(status & PCI_COMMAND_MASTER)) {
2302 status |= PCI_COMMAND_MASTER;
2303 pci_write_config_word(pdev, PCI_COMMAND, status);
2304 pci_read_config_word(pdev, PCI_COMMAND, &status);
2305 }
2306 if (!(status & PCI_COMMAND_MASTER)) {
2307 error = -ENODEV;
2308 goto free_dev;
2309 }
2310
2311 /* Check the latency timer for values >= 0x60 */
2312 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &timer);
2313 if (timer < 0x60) {
2314 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x60);
2315 }
2316
2317 DevicePresent(dev, DE4X5_APROM);
2318
2319 if (!request_region (iobase, DE4X5_PCI_TOTAL_SIZE, "de4x5")) {
2320 error = -EBUSY;
2321 goto free_dev;
2322 }
2323
2324 dev->irq = irq;
2325
2326 if ((error = de4x5_hw_init(dev, iobase, &pdev->dev))) {
2327 goto release;
2328 }
2329
2330 return 0;
2331
2332 release:
2333 release_region (iobase, DE4X5_PCI_TOTAL_SIZE);
2334 free_dev:
2335 free_netdev (dev);
2336 disable_dev:
2337 pci_disable_device (pdev);
2338 return error;
2339}
2340
2341static void __devexit de4x5_pci_remove (struct pci_dev *pdev)
2342{
2343 struct net_device *dev;
2344 u_long iobase;
2345
2346 dev = pdev->dev.driver_data;
2347 iobase = dev->base_addr;
2348
2349 unregister_netdev (dev);
2350 free_netdev (dev);
2351 release_region (iobase, DE4X5_PCI_TOTAL_SIZE);
2352 pci_disable_device (pdev);
2353}
2354
2355static struct pci_device_id de4x5_pci_tbl[] = {
2356 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP,
2357 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
2358 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP_PLUS,
2359 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 },
2360 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP_FAST,
2361 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2 },
2362 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142,
2363 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3 },
2364 { },
2365};
2366
2367static struct pci_driver de4x5_pci_driver = {
2368 .name = "de4x5",
2369 .id_table = de4x5_pci_tbl,
2370 .probe = de4x5_pci_probe,
2371 .remove = __devexit_p (de4x5_pci_remove),
2372};
2373
2374#endif
2375
2376/*
2377** Auto configure the media here rather than setting the port at compile
2378** time. This routine is called by de4x5_init() and when a loss of media is
2379** detected (excessive collisions, loss of carrier, no carrier or link fail
2380** [TP] or no recent receive activity) to check whether the user has been
2381** sneaky and changed the port on us.
2382*/
2383static int
2384autoconf_media(struct net_device *dev)
2385{
2386 struct de4x5_private *lp = netdev_priv(dev);
2387 u_long iobase = dev->base_addr;
2388 int next_tick = DE4X5_AUTOSENSE_MS;
2389
2390 lp->linkOK = 0;
2391 lp->c_media = AUTO; /* Bogus last media */
2392 disable_ast(dev);
2393 inl(DE4X5_MFC); /* Zero the lost frames counter */
2394 lp->media = INIT;
2395 lp->tcount = 0;
2396
2397 if (lp->useSROM) {
2398 next_tick = srom_autoconf(dev);
2399 } else if (lp->chipset == DC21040) {
2400 next_tick = dc21040_autoconf(dev);
2401 } else if (lp->chipset == DC21041) {
2402 next_tick = dc21041_autoconf(dev);
2403 } else if (lp->chipset == DC21140) {
2404 next_tick = dc21140m_autoconf(dev);
2405 }
2406
2407 enable_ast(dev, next_tick);
2408
2409 return (lp->media);
2410}
2411
2412/*
2413** Autoconfigure the media when using the DC21040. AUI cannot be distinguished
2414** from BNC as the port has a jumper to set thick or thin wire. When set for
2415** BNC, the BNC port will indicate activity if it's not terminated correctly.
2416** The only way to test for that is to place a loopback packet onto the
2417** network and watch for errors. Since we're messing with the interrupt mask
2418** register, disable the board interrupts and do not allow any more packets to
2419** be queued to the hardware. Re-enable everything only when the media is
2420** found.
2421** I may have to "age out" locally queued packets so that the higher layer
2422** timeouts don't effectively duplicate packets on the network.
2423*/
2424static int
2425dc21040_autoconf(struct net_device *dev)
2426{
2427 struct de4x5_private *lp = netdev_priv(dev);
2428 u_long iobase = dev->base_addr;
2429 int next_tick = DE4X5_AUTOSENSE_MS;
2430 s32 imr;
2431
2432 switch (lp->media) {
2433 case INIT:
2434 DISABLE_IRQs;
2435 lp->tx_enable = NO;
2436 lp->timeout = -1;
2437 de4x5_save_skbs(dev);
2438 if ((lp->autosense == AUTO) || (lp->autosense == TP)) {
2439 lp->media = TP;
2440 } else if ((lp->autosense == BNC) || (lp->autosense == AUI) || (lp->autosense == BNC_AUI)) {
2441 lp->media = BNC_AUI;
2442 } else if (lp->autosense == EXT_SIA) {
2443 lp->media = EXT_SIA;
2444 } else {
2445 lp->media = NC;
2446 }
2447 lp->local_state = 0;
2448 next_tick = dc21040_autoconf(dev);
2449 break;
2450
2451 case TP:
2452 next_tick = dc21040_state(dev, 0x8f01, 0xffff, 0x0000, 3000, BNC_AUI,
2453 TP_SUSPECT, test_tp);
2454 break;
2455
2456 case TP_SUSPECT:
2457 next_tick = de4x5_suspect_state(dev, 1000, TP, test_tp, dc21040_autoconf);
2458 break;
2459
2460 case BNC:
2461 case AUI:
2462 case BNC_AUI:
2463 next_tick = dc21040_state(dev, 0x8f09, 0x0705, 0x0006, 3000, EXT_SIA,
2464 BNC_AUI_SUSPECT, ping_media);
2465 break;
2466
2467 case BNC_AUI_SUSPECT:
2468 next_tick = de4x5_suspect_state(dev, 1000, BNC_AUI, ping_media, dc21040_autoconf);
2469 break;
2470
2471 case EXT_SIA:
2472 next_tick = dc21040_state(dev, 0x3041, 0x0000, 0x0006, 3000,
2473 NC, EXT_SIA_SUSPECT, ping_media);
2474 break;
2475
2476 case EXT_SIA_SUSPECT:
2477 next_tick = de4x5_suspect_state(dev, 1000, EXT_SIA, ping_media, dc21040_autoconf);
2478 break;
2479
2480 case NC:
2481 /* default to TP for all */
2482 reset_init_sia(dev, 0x8f01, 0xffff, 0x0000);
2483 if (lp->media != lp->c_media) {
2484 de4x5_dbg_media(dev);
2485 lp->c_media = lp->media;
2486 }
2487 lp->media = INIT;
2488 lp->tx_enable = NO;
2489 break;
2490 }
2491
2492 return next_tick;
2493}
2494
2495static int
2496dc21040_state(struct net_device *dev, int csr13, int csr14, int csr15, int timeout,
2497 int next_state, int suspect_state,
2498 int (*fn)(struct net_device *, int))
2499{
2500 struct de4x5_private *lp = netdev_priv(dev);
2501 int next_tick = DE4X5_AUTOSENSE_MS;
2502 int linkBad;
2503
2504 switch (lp->local_state) {
2505 case 0:
2506 reset_init_sia(dev, csr13, csr14, csr15);
2507 lp->local_state++;
2508 next_tick = 500;
2509 break;
2510
2511 case 1:
2512 if (!lp->tx_enable) {
2513 linkBad = fn(dev, timeout);
2514 if (linkBad < 0) {
2515 next_tick = linkBad & ~TIMER_CB;
2516 } else {
2517 if (linkBad && (lp->autosense == AUTO)) {
2518 lp->local_state = 0;
2519 lp->media = next_state;
2520 } else {
2521 de4x5_init_connection(dev);
2522 }
2523 }
2524 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2525 lp->media = suspect_state;
2526 next_tick = 3000;
2527 }
2528 break;
2529 }
2530
2531 return next_tick;
2532}
2533
2534static int
2535de4x5_suspect_state(struct net_device *dev, int timeout, int prev_state,
2536 int (*fn)(struct net_device *, int),
2537 int (*asfn)(struct net_device *))
2538{
2539 struct de4x5_private *lp = netdev_priv(dev);
2540 int next_tick = DE4X5_AUTOSENSE_MS;
2541 int linkBad;
2542
2543 switch (lp->local_state) {
2544 case 1:
2545 if (lp->linkOK) {
2546 lp->media = prev_state;
2547 } else {
2548 lp->local_state++;
2549 next_tick = asfn(dev);
2550 }
2551 break;
2552
2553 case 2:
2554 linkBad = fn(dev, timeout);
2555 if (linkBad < 0) {
2556 next_tick = linkBad & ~TIMER_CB;
2557 } else if (!linkBad) {
2558 lp->local_state--;
2559 lp->media = prev_state;
2560 } else {
2561 lp->media = INIT;
2562 lp->tcount++;
2563 }
2564 }
2565
2566 return next_tick;
2567}
2568
2569/*
2570** Autoconfigure the media when using the DC21041. AUI needs to be tested
2571** before BNC, because the BNC port will indicate activity if it's not
2572** terminated correctly. The only way to test for that is to place a loopback
2573** packet onto the network and watch for errors. Since we're messing with
2574** the interrupt mask register, disable the board interrupts and do not allow
2575** any more packets to be queued to the hardware. Re-enable everything only
2576** when the media is found.
2577*/
2578static int
2579dc21041_autoconf(struct net_device *dev)
2580{
2581 struct de4x5_private *lp = netdev_priv(dev);
2582 u_long iobase = dev->base_addr;
2583 s32 sts, irqs, irq_mask, imr, omr;
2584 int next_tick = DE4X5_AUTOSENSE_MS;
2585
2586 switch (lp->media) {
2587 case INIT:
2588 DISABLE_IRQs;
2589 lp->tx_enable = NO;
2590 lp->timeout = -1;
2591 de4x5_save_skbs(dev); /* Save non transmitted skb's */
2592 if ((lp->autosense == AUTO) || (lp->autosense == TP_NW)) {
2593 lp->media = TP; /* On chip auto negotiation is broken */
2594 } else if (lp->autosense == TP) {
2595 lp->media = TP;
2596 } else if (lp->autosense == BNC) {
2597 lp->media = BNC;
2598 } else if (lp->autosense == AUI) {
2599 lp->media = AUI;
2600 } else {
2601 lp->media = NC;
2602 }
2603 lp->local_state = 0;
2604 next_tick = dc21041_autoconf(dev);
2605 break;
2606
2607 case TP_NW:
2608 if (lp->timeout < 0) {
2609 omr = inl(DE4X5_OMR);/* Set up full duplex for the autonegotiate */
2610 outl(omr | OMR_FDX, DE4X5_OMR);
2611 }
2612 irqs = STS_LNF | STS_LNP;
2613 irq_mask = IMR_LFM | IMR_LPM;
2614 sts = test_media(dev, irqs, irq_mask, 0xef01, 0xffff, 0x0008, 2400);
2615 if (sts < 0) {
2616 next_tick = sts & ~TIMER_CB;
2617 } else {
2618 if (sts & STS_LNP) {
2619 lp->media = ANS;
2620 } else {
2621 lp->media = AUI;
2622 }
2623 next_tick = dc21041_autoconf(dev);
2624 }
2625 break;
2626
2627 case ANS:
2628 if (!lp->tx_enable) {
2629 irqs = STS_LNP;
2630 irq_mask = IMR_LPM;
2631 sts = test_ans(dev, irqs, irq_mask, 3000);
2632 if (sts < 0) {
2633 next_tick = sts & ~TIMER_CB;
2634 } else {
2635 if (!(sts & STS_LNP) && (lp->autosense == AUTO)) {
2636 lp->media = TP;
2637 next_tick = dc21041_autoconf(dev);
2638 } else {
2639 lp->local_state = 1;
2640 de4x5_init_connection(dev);
2641 }
2642 }
2643 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2644 lp->media = ANS_SUSPECT;
2645 next_tick = 3000;
2646 }
2647 break;
2648
2649 case ANS_SUSPECT:
2650 next_tick = de4x5_suspect_state(dev, 1000, ANS, test_tp, dc21041_autoconf);
2651 break;
2652
2653 case TP:
2654 if (!lp->tx_enable) {
2655 if (lp->timeout < 0) {
2656 omr = inl(DE4X5_OMR); /* Set up half duplex for TP */
2657 outl(omr & ~OMR_FDX, DE4X5_OMR);
2658 }
2659 irqs = STS_LNF | STS_LNP;
2660 irq_mask = IMR_LFM | IMR_LPM;
2661 sts = test_media(dev,irqs, irq_mask, 0xef01, 0xff3f, 0x0008, 2400);
2662 if (sts < 0) {
2663 next_tick = sts & ~TIMER_CB;
2664 } else {
2665 if (!(sts & STS_LNP) && (lp->autosense == AUTO)) {
2666 if (inl(DE4X5_SISR) & SISR_NRA) {
2667 lp->media = AUI; /* Non selected port activity */
2668 } else {
2669 lp->media = BNC;
2670 }
2671 next_tick = dc21041_autoconf(dev);
2672 } else {
2673 lp->local_state = 1;
2674 de4x5_init_connection(dev);
2675 }
2676 }
2677 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2678 lp->media = TP_SUSPECT;
2679 next_tick = 3000;
2680 }
2681 break;
2682
2683 case TP_SUSPECT:
2684 next_tick = de4x5_suspect_state(dev, 1000, TP, test_tp, dc21041_autoconf);
2685 break;
2686
2687 case AUI:
2688 if (!lp->tx_enable) {
2689 if (lp->timeout < 0) {
2690 omr = inl(DE4X5_OMR); /* Set up half duplex for AUI */
2691 outl(omr & ~OMR_FDX, DE4X5_OMR);
2692 }
2693 irqs = 0;
2694 irq_mask = 0;
2695 sts = test_media(dev,irqs, irq_mask, 0xef09, 0xf73d, 0x000e, 1000);
2696 if (sts < 0) {
2697 next_tick = sts & ~TIMER_CB;
2698 } else {
2699 if (!(inl(DE4X5_SISR) & SISR_SRA) && (lp->autosense == AUTO)) {
2700 lp->media = BNC;
2701 next_tick = dc21041_autoconf(dev);
2702 } else {
2703 lp->local_state = 1;
2704 de4x5_init_connection(dev);
2705 }
2706 }
2707 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2708 lp->media = AUI_SUSPECT;
2709 next_tick = 3000;
2710 }
2711 break;
2712
2713 case AUI_SUSPECT:
2714 next_tick = de4x5_suspect_state(dev, 1000, AUI, ping_media, dc21041_autoconf);
2715 break;
2716
2717 case BNC:
2718 switch (lp->local_state) {
2719 case 0:
2720 if (lp->timeout < 0) {
2721 omr = inl(DE4X5_OMR); /* Set up half duplex for BNC */
2722 outl(omr & ~OMR_FDX, DE4X5_OMR);
2723 }
2724 irqs = 0;
2725 irq_mask = 0;
2726 sts = test_media(dev,irqs, irq_mask, 0xef09, 0xf73d, 0x0006, 1000);
2727 if (sts < 0) {
2728 next_tick = sts & ~TIMER_CB;
2729 } else {
2730 lp->local_state++; /* Ensure media connected */
2731 next_tick = dc21041_autoconf(dev);
2732 }
2733 break;
2734
2735 case 1:
2736 if (!lp->tx_enable) {
2737 if ((sts = ping_media(dev, 3000)) < 0) {
2738 next_tick = sts & ~TIMER_CB;
2739 } else {
2740 if (sts) {
2741 lp->local_state = 0;
2742 lp->media = NC;
2743 } else {
2744 de4x5_init_connection(dev);
2745 }
2746 }
2747 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2748 lp->media = BNC_SUSPECT;
2749 next_tick = 3000;
2750 }
2751 break;
2752 }
2753 break;
2754
2755 case BNC_SUSPECT:
2756 next_tick = de4x5_suspect_state(dev, 1000, BNC, ping_media, dc21041_autoconf);
2757 break;
2758
2759 case NC:
2760 omr = inl(DE4X5_OMR); /* Set up full duplex for the autonegotiate */
2761 outl(omr | OMR_FDX, DE4X5_OMR);
2762 reset_init_sia(dev, 0xef01, 0xffff, 0x0008);/* Initialise the SIA */
2763 if (lp->media != lp->c_media) {
2764 de4x5_dbg_media(dev);
2765 lp->c_media = lp->media;
2766 }
2767 lp->media = INIT;
2768 lp->tx_enable = NO;
2769 break;
2770 }
2771
2772 return next_tick;
2773}
2774
2775/*
2776** Some autonegotiation chips are broken in that they do not return the
2777** acknowledge bit (anlpa & MII_ANLPA_ACK) in the link partner advertisement
2778** register, except at the first power up negotiation.
2779*/
2780static int
2781dc21140m_autoconf(struct net_device *dev)
2782{
2783 struct de4x5_private *lp = netdev_priv(dev);
2784 int ana, anlpa, cap, cr, slnk, sr;
2785 int next_tick = DE4X5_AUTOSENSE_MS;
2786 u_long imr, omr, iobase = dev->base_addr;
2787
2788 switch(lp->media) {
2789 case INIT:
2790 if (lp->timeout < 0) {
2791 DISABLE_IRQs;
2792 lp->tx_enable = FALSE;
2793 lp->linkOK = 0;
2794 de4x5_save_skbs(dev); /* Save non transmitted skb's */
2795 }
2796 if ((next_tick = de4x5_reset_phy(dev)) < 0) {
2797 next_tick &= ~TIMER_CB;
2798 } else {
2799 if (lp->useSROM) {
2800 if (srom_map_media(dev) < 0) {
2801 lp->tcount++;
2802 return next_tick;
2803 }
2804 srom_exec(dev, lp->phy[lp->active].gep);
2805 if (lp->infoblock_media == ANS) {
2806 ana = lp->phy[lp->active].ana | MII_ANA_CSMA;
2807 mii_wr(ana, MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
2808 }
2809 } else {
2810 lp->tmp = MII_SR_ASSC; /* Fake out the MII speed set */
2811 SET_10Mb;
2812 if (lp->autosense == _100Mb) {
2813 lp->media = _100Mb;
2814 } else if (lp->autosense == _10Mb) {
2815 lp->media = _10Mb;
2816 } else if ((lp->autosense == AUTO) &&
2817 ((sr=is_anc_capable(dev)) & MII_SR_ANC)) {
2818 ana = (((sr >> 6) & MII_ANA_TAF) | MII_ANA_CSMA);
2819 ana &= (lp->fdx ? ~0 : ~MII_ANA_FDAM);
2820 mii_wr(ana, MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
2821 lp->media = ANS;
2822 } else if (lp->autosense == AUTO) {
2823 lp->media = SPD_DET;
2824 } else if (is_spd_100(dev) && is_100_up(dev)) {
2825 lp->media = _100Mb;
2826 } else {
2827 lp->media = NC;
2828 }
2829 }
2830 lp->local_state = 0;
2831 next_tick = dc21140m_autoconf(dev);
2832 }
2833 break;
2834
2835 case ANS:
2836 switch (lp->local_state) {
2837 case 0:
2838 if (lp->timeout < 0) {
2839 mii_wr(MII_CR_ASSE | MII_CR_RAN, MII_CR, lp->phy[lp->active].addr, DE4X5_MII);
2840 }
2841 cr = test_mii_reg(dev, MII_CR, MII_CR_RAN, FALSE, 500);
2842 if (cr < 0) {
2843 next_tick = cr & ~TIMER_CB;
2844 } else {
2845 if (cr) {
2846 lp->local_state = 0;
2847 lp->media = SPD_DET;
2848 } else {
2849 lp->local_state++;
2850 }
2851 next_tick = dc21140m_autoconf(dev);
2852 }
2853 break;
2854
2855 case 1:
2856 if ((sr=test_mii_reg(dev, MII_SR, MII_SR_ASSC, TRUE, 2000)) < 0) {
2857 next_tick = sr & ~TIMER_CB;
2858 } else {
2859 lp->media = SPD_DET;
2860 lp->local_state = 0;
2861 if (sr) { /* Success! */
2862 lp->tmp = MII_SR_ASSC;
2863 anlpa = mii_rd(MII_ANLPA, lp->phy[lp->active].addr, DE4X5_MII);
2864 ana = mii_rd(MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
2865 if (!(anlpa & MII_ANLPA_RF) &&
2866 (cap = anlpa & MII_ANLPA_TAF & ana)) {
2867 if (cap & MII_ANA_100M) {
2868 lp->fdx = ((ana & anlpa & MII_ANA_FDAM & MII_ANA_100M) ? TRUE : FALSE);
2869 lp->media = _100Mb;
2870 } else if (cap & MII_ANA_10M) {
2871 lp->fdx = ((ana & anlpa & MII_ANA_FDAM & MII_ANA_10M) ? TRUE : FALSE);
2872
2873 lp->media = _10Mb;
2874 }
2875 }
2876 } /* Auto Negotiation failed to finish */
2877 next_tick = dc21140m_autoconf(dev);
2878 } /* Auto Negotiation failed to start */
2879 break;
2880 }
2881 break;
2882
2883 case SPD_DET: /* Choose 10Mb/s or 100Mb/s */
2884 if (lp->timeout < 0) {
2885 lp->tmp = (lp->phy[lp->active].id ? MII_SR_LKS :
2886 (~gep_rd(dev) & GEP_LNP));
2887 SET_100Mb_PDET;
2888 }
2889 if ((slnk = test_for_100Mb(dev, 6500)) < 0) {
2890 next_tick = slnk & ~TIMER_CB;
2891 } else {
2892 if (is_spd_100(dev) && is_100_up(dev)) {
2893 lp->media = _100Mb;
2894 } else if ((!is_spd_100(dev) && (is_10_up(dev) & lp->tmp))) {
2895 lp->media = _10Mb;
2896 } else {
2897 lp->media = NC;
2898 }
2899 next_tick = dc21140m_autoconf(dev);
2900 }
2901 break;
2902
2903 case _100Mb: /* Set 100Mb/s */
2904 next_tick = 3000;
2905 if (!lp->tx_enable) {
2906 SET_100Mb;
2907 de4x5_init_connection(dev);
2908 } else {
2909 if (!lp->linkOK && (lp->autosense == AUTO)) {
2910 if (!is_100_up(dev) || (!lp->useSROM && !is_spd_100(dev))) {
2911 lp->media = INIT;
2912 lp->tcount++;
2913 next_tick = DE4X5_AUTOSENSE_MS;
2914 }
2915 }
2916 }
2917 break;
2918
2919 case BNC:
2920 case AUI:
2921 case _10Mb: /* Set 10Mb/s */
2922 next_tick = 3000;
2923 if (!lp->tx_enable) {
2924 SET_10Mb;
2925 de4x5_init_connection(dev);
2926 } else {
2927 if (!lp->linkOK && (lp->autosense == AUTO)) {
2928 if (!is_10_up(dev) || (!lp->useSROM && is_spd_100(dev))) {
2929 lp->media = INIT;
2930 lp->tcount++;
2931 next_tick = DE4X5_AUTOSENSE_MS;
2932 }
2933 }
2934 }
2935 break;
2936
2937 case NC:
2938 if (lp->media != lp->c_media) {
2939 de4x5_dbg_media(dev);
2940 lp->c_media = lp->media;
2941 }
2942 lp->media = INIT;
2943 lp->tx_enable = FALSE;
2944 break;
2945 }
2946
2947 return next_tick;
2948}
2949
2950/*
2951** This routine may be merged into dc21140m_autoconf() sometime as I'm
2952** changing how I figure out the media - but trying to keep it backwards
2953** compatible with the de500-xa and de500-aa.
2954** Whether it's BNC, AUI, SYM or MII is sorted out in the infoblock
2955** functions and set during de4x5_mac_port() and/or de4x5_reset_phy().
2956** This routine just has to figure out whether 10Mb/s or 100Mb/s is
2957** active.
2958** When autonegotiation is working, the ANS part searches the SROM for
2959** the highest common speed (TP) link that both can run and if that can
2960** be full duplex. That infoblock is executed and then the link speed set.
2961**
2962** Only _10Mb and _100Mb are tested here.
2963*/
2964static int
2965dc2114x_autoconf(struct net_device *dev)
2966{
2967 struct de4x5_private *lp = netdev_priv(dev);
2968 u_long iobase = dev->base_addr;
2969 s32 cr, anlpa, ana, cap, irqs, irq_mask, imr, omr, slnk, sr, sts;
2970 int next_tick = DE4X5_AUTOSENSE_MS;
2971
2972 switch (lp->media) {
2973 case INIT:
2974 if (lp->timeout < 0) {
2975 DISABLE_IRQs;
2976 lp->tx_enable = FALSE;
2977 lp->linkOK = 0;
2978 lp->timeout = -1;
2979 de4x5_save_skbs(dev); /* Save non transmitted skb's */
2980 if (lp->params.autosense & ~AUTO) {
2981 srom_map_media(dev); /* Fixed media requested */
2982 if (lp->media != lp->params.autosense) {
2983 lp->tcount++;
2984 lp->media = INIT;
2985 return next_tick;
2986 }
2987 lp->media = INIT;
2988 }
2989 }
2990 if ((next_tick = de4x5_reset_phy(dev)) < 0) {
2991 next_tick &= ~TIMER_CB;
2992 } else {
2993 if (lp->autosense == _100Mb) {
2994 lp->media = _100Mb;
2995 } else if (lp->autosense == _10Mb) {
2996 lp->media = _10Mb;
2997 } else if (lp->autosense == TP) {
2998 lp->media = TP;
2999 } else if (lp->autosense == BNC) {
3000 lp->media = BNC;
3001 } else if (lp->autosense == AUI) {
3002 lp->media = AUI;
3003 } else {
3004 lp->media = SPD_DET;
3005 if ((lp->infoblock_media == ANS) &&
3006 ((sr=is_anc_capable(dev)) & MII_SR_ANC)) {
3007 ana = (((sr >> 6) & MII_ANA_TAF) | MII_ANA_CSMA);
3008 ana &= (lp->fdx ? ~0 : ~MII_ANA_FDAM);
3009 mii_wr(ana, MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
3010 lp->media = ANS;
3011 }
3012 }
3013 lp->local_state = 0;
3014 next_tick = dc2114x_autoconf(dev);
3015 }
3016 break;
3017
3018 case ANS:
3019 switch (lp->local_state) {
3020 case 0:
3021 if (lp->timeout < 0) {
3022 mii_wr(MII_CR_ASSE | MII_CR_RAN, MII_CR, lp->phy[lp->active].addr, DE4X5_MII);
3023 }
3024 cr = test_mii_reg(dev, MII_CR, MII_CR_RAN, FALSE, 500);
3025 if (cr < 0) {
3026 next_tick = cr & ~TIMER_CB;
3027 } else {
3028 if (cr) {
3029 lp->local_state = 0;
3030 lp->media = SPD_DET;
3031 } else {
3032 lp->local_state++;
3033 }
3034 next_tick = dc2114x_autoconf(dev);
3035 }
3036 break;
3037
3038 case 1:
3039 if ((sr=test_mii_reg(dev, MII_SR, MII_SR_ASSC, TRUE, 2000)) < 0) {
3040 next_tick = sr & ~TIMER_CB;
3041 } else {
3042 lp->media = SPD_DET;
3043 lp->local_state = 0;
3044 if (sr) { /* Success! */
3045 lp->tmp = MII_SR_ASSC;
3046 anlpa = mii_rd(MII_ANLPA, lp->phy[lp->active].addr, DE4X5_MII);
3047 ana = mii_rd(MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
3048 if (!(anlpa & MII_ANLPA_RF) &&
3049 (cap = anlpa & MII_ANLPA_TAF & ana)) {
3050 if (cap & MII_ANA_100M) {
3051 lp->fdx = ((ana & anlpa & MII_ANA_FDAM & MII_ANA_100M) ? TRUE : FALSE);
3052 lp->media = _100Mb;
3053 } else if (cap & MII_ANA_10M) {
3054 lp->fdx = ((ana & anlpa & MII_ANA_FDAM & MII_ANA_10M) ? TRUE : FALSE);
3055 lp->media = _10Mb;
3056 }
3057 }
3058 } /* Auto Negotiation failed to finish */
3059 next_tick = dc2114x_autoconf(dev);
3060 } /* Auto Negotiation failed to start */
3061 break;
3062 }
3063 break;
3064
3065 case AUI:
3066 if (!lp->tx_enable) {
3067 if (lp->timeout < 0) {
3068 omr = inl(DE4X5_OMR); /* Set up half duplex for AUI */
3069 outl(omr & ~OMR_FDX, DE4X5_OMR);
3070 }
3071 irqs = 0;
3072 irq_mask = 0;
3073 sts = test_media(dev,irqs, irq_mask, 0, 0, 0, 1000);
3074 if (sts < 0) {
3075 next_tick = sts & ~TIMER_CB;
3076 } else {
3077 if (!(inl(DE4X5_SISR) & SISR_SRA) && (lp->autosense == AUTO)) {
3078 lp->media = BNC;
3079 next_tick = dc2114x_autoconf(dev);
3080 } else {
3081 lp->local_state = 1;
3082 de4x5_init_connection(dev);
3083 }
3084 }
3085 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
3086 lp->media = AUI_SUSPECT;
3087 next_tick = 3000;
3088 }
3089 break;
3090
3091 case AUI_SUSPECT:
3092 next_tick = de4x5_suspect_state(dev, 1000, AUI, ping_media, dc2114x_autoconf);
3093 break;
3094
3095 case BNC:
3096 switch (lp->local_state) {
3097 case 0:
3098 if (lp->timeout < 0) {
3099 omr = inl(DE4X5_OMR); /* Set up half duplex for BNC */
3100 outl(omr & ~OMR_FDX, DE4X5_OMR);
3101 }
3102 irqs = 0;
3103 irq_mask = 0;
3104 sts = test_media(dev,irqs, irq_mask, 0, 0, 0, 1000);
3105 if (sts < 0) {
3106 next_tick = sts & ~TIMER_CB;
3107 } else {
3108 lp->local_state++; /* Ensure media connected */
3109 next_tick = dc2114x_autoconf(dev);
3110 }
3111 break;
3112
3113 case 1:
3114 if (!lp->tx_enable) {
3115 if ((sts = ping_media(dev, 3000)) < 0) {
3116 next_tick = sts & ~TIMER_CB;
3117 } else {
3118 if (sts) {
3119 lp->local_state = 0;
3120 lp->tcount++;
3121 lp->media = INIT;
3122 } else {
3123 de4x5_init_connection(dev);
3124 }
3125 }
3126 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
3127 lp->media = BNC_SUSPECT;
3128 next_tick = 3000;
3129 }
3130 break;
3131 }
3132 break;
3133
3134 case BNC_SUSPECT:
3135 next_tick = de4x5_suspect_state(dev, 1000, BNC, ping_media, dc2114x_autoconf);
3136 break;
3137
3138 case SPD_DET: /* Choose 10Mb/s or 100Mb/s */
3139 if (srom_map_media(dev) < 0) {
3140 lp->tcount++;
3141 lp->media = INIT;
3142 return next_tick;
3143 }
3144 if (lp->media == _100Mb) {
3145 if ((slnk = test_for_100Mb(dev, 6500)) < 0) {
3146 lp->media = SPD_DET;
3147 return (slnk & ~TIMER_CB);
3148 }
3149 } else {
3150 if (wait_for_link(dev) < 0) {
3151 lp->media = SPD_DET;
3152 return PDET_LINK_WAIT;
3153 }
3154 }
3155 if (lp->media == ANS) { /* Do MII parallel detection */
3156 if (is_spd_100(dev)) {
3157 lp->media = _100Mb;
3158 } else {
3159 lp->media = _10Mb;
3160 }
3161 next_tick = dc2114x_autoconf(dev);
3162 } else if (((lp->media == _100Mb) && is_100_up(dev)) ||
3163 (((lp->media == _10Mb) || (lp->media == TP) ||
3164 (lp->media == BNC) || (lp->media == AUI)) &&
3165 is_10_up(dev))) {
3166 next_tick = dc2114x_autoconf(dev);
3167 } else {
3168 lp->tcount++;
3169 lp->media = INIT;
3170 }
3171 break;
3172
3173 case _10Mb:
3174 next_tick = 3000;
3175 if (!lp->tx_enable) {
3176 SET_10Mb;
3177 de4x5_init_connection(dev);
3178 } else {
3179 if (!lp->linkOK && (lp->autosense == AUTO)) {
3180 if (!is_10_up(dev) || (!lp->useSROM && is_spd_100(dev))) {
3181 lp->media = INIT;
3182 lp->tcount++;
3183 next_tick = DE4X5_AUTOSENSE_MS;
3184 }
3185 }
3186 }
3187 break;
3188
3189 case _100Mb:
3190 next_tick = 3000;
3191 if (!lp->tx_enable) {
3192 SET_100Mb;
3193 de4x5_init_connection(dev);
3194 } else {
3195 if (!lp->linkOK && (lp->autosense == AUTO)) {
3196 if (!is_100_up(dev) || (!lp->useSROM && !is_spd_100(dev))) {
3197 lp->media = INIT;
3198 lp->tcount++;
3199 next_tick = DE4X5_AUTOSENSE_MS;
3200 }
3201 }
3202 }
3203 break;
3204
3205 default:
3206 lp->tcount++;
3207printk("Huh?: media:%02x\n", lp->media);
3208 lp->media = INIT;
3209 break;
3210 }
3211
3212 return next_tick;
3213}
3214
3215static int
3216srom_autoconf(struct net_device *dev)
3217{
3218 struct de4x5_private *lp = netdev_priv(dev);
3219
3220 return lp->infoleaf_fn(dev);
3221}
3222
3223/*
3224** This mapping keeps the original media codes and FDX flag unchanged.
3225** While it isn't strictly necessary, it helps me for the moment...
3226** The early return avoids a media state / SROM media space clash.
3227*/
3228static int
3229srom_map_media(struct net_device *dev)
3230{
3231 struct de4x5_private *lp = netdev_priv(dev);
3232
3233 lp->fdx = 0;
3234 if (lp->infoblock_media == lp->media)
3235 return 0;
3236
3237 switch(lp->infoblock_media) {
3238 case SROM_10BASETF:
3239 if (!lp->params.fdx) return -1;
3240 lp->fdx = TRUE;
3241 case SROM_10BASET:
3242 if (lp->params.fdx && !lp->fdx) return -1;
3243 if ((lp->chipset == DC21140) || ((lp->chipset & ~0x00ff) == DC2114x)) {
3244 lp->media = _10Mb;
3245 } else {
3246 lp->media = TP;
3247 }
3248 break;
3249
3250 case SROM_10BASE2:
3251 lp->media = BNC;
3252 break;
3253
3254 case SROM_10BASE5:
3255 lp->media = AUI;
3256 break;
3257
3258 case SROM_100BASETF:
3259 if (!lp->params.fdx) return -1;
3260 lp->fdx = TRUE;
3261 case SROM_100BASET:
3262 if (lp->params.fdx && !lp->fdx) return -1;
3263 lp->media = _100Mb;
3264 break;
3265
3266 case SROM_100BASET4:
3267 lp->media = _100Mb;
3268 break;
3269
3270 case SROM_100BASEFF:
3271 if (!lp->params.fdx) return -1;
3272 lp->fdx = TRUE;
3273 case SROM_100BASEF:
3274 if (lp->params.fdx && !lp->fdx) return -1;
3275 lp->media = _100Mb;
3276 break;
3277
3278 case ANS:
3279 lp->media = ANS;
3280 lp->fdx = lp->params.fdx;
3281 break;
3282
3283 default:
3284 printk("%s: Bad media code [%d] detected in SROM!\n", dev->name,
3285 lp->infoblock_media);
3286 return -1;
3287 break;
3288 }
3289
3290 return 0;
3291}
3292
3293static void
3294de4x5_init_connection(struct net_device *dev)
3295{
3296 struct de4x5_private *lp = netdev_priv(dev);
3297 u_long iobase = dev->base_addr;
3298 u_long flags = 0;
3299
3300 if (lp->media != lp->c_media) {
3301 de4x5_dbg_media(dev);
3302 lp->c_media = lp->media; /* Stop scrolling media messages */
3303 }
3304
3305 spin_lock_irqsave(&lp->lock, flags);
3306 de4x5_rst_desc_ring(dev);
3307 de4x5_setup_intr(dev);
3308 lp->tx_enable = YES;
3309 spin_unlock_irqrestore(&lp->lock, flags);
3310 outl(POLL_DEMAND, DE4X5_TPD);
3311
3312 netif_wake_queue(dev);
3313
3314 return;
3315}
3316
3317/*
3318** General PHY reset function. Some MII devices don't reset correctly
3319** since their MII address pins can float at voltages that are dependent
3320** on the signal pin use. Do a double reset to ensure a reset.
3321*/
3322static int
3323de4x5_reset_phy(struct net_device *dev)
3324{
3325 struct de4x5_private *lp = netdev_priv(dev);
3326 u_long iobase = dev->base_addr;
3327 int next_tick = 0;
3328
3329 if ((lp->useSROM) || (lp->phy[lp->active].id)) {
3330 if (lp->timeout < 0) {
3331 if (lp->useSROM) {
3332 if (lp->phy[lp->active].rst) {
3333 srom_exec(dev, lp->phy[lp->active].rst);
3334 srom_exec(dev, lp->phy[lp->active].rst);
3335 } else if (lp->rst) { /* Type 5 infoblock reset */
3336 srom_exec(dev, lp->rst);
3337 srom_exec(dev, lp->rst);
3338 }
3339 } else {
3340 PHY_HARD_RESET;
3341 }
3342 if (lp->useMII) {
3343 mii_wr(MII_CR_RST, MII_CR, lp->phy[lp->active].addr, DE4X5_MII);
3344 }
3345 }
3346 if (lp->useMII) {
3347 next_tick = test_mii_reg(dev, MII_CR, MII_CR_RST, FALSE, 500);
3348 }
3349 } else if (lp->chipset == DC21140) {
3350 PHY_HARD_RESET;
3351 }
3352
3353 return next_tick;
3354}
3355
3356static int
3357test_media(struct net_device *dev, s32 irqs, s32 irq_mask, s32 csr13, s32 csr14, s32 csr15, s32 msec)
3358{
3359 struct de4x5_private *lp = netdev_priv(dev);
3360 u_long iobase = dev->base_addr;
3361 s32 sts, csr12;
3362
3363 if (lp->timeout < 0) {
3364 lp->timeout = msec/100;
3365 if (!lp->useSROM) { /* Already done if by SROM, else dc2104[01] */
3366 reset_init_sia(dev, csr13, csr14, csr15);
3367 }
3368
3369 /* set up the interrupt mask */
3370 outl(irq_mask, DE4X5_IMR);
3371
3372 /* clear all pending interrupts */
3373 sts = inl(DE4X5_STS);
3374 outl(sts, DE4X5_STS);
3375
3376 /* clear csr12 NRA and SRA bits */
3377 if ((lp->chipset == DC21041) || lp->useSROM) {
3378 csr12 = inl(DE4X5_SISR);
3379 outl(csr12, DE4X5_SISR);
3380 }
3381 }
3382
3383 sts = inl(DE4X5_STS) & ~TIMER_CB;
3384
3385 if (!(sts & irqs) && --lp->timeout) {
3386 sts = 100 | TIMER_CB;
3387 } else {
3388 lp->timeout = -1;
3389 }
3390
3391 return sts;
3392}
3393
3394static int
3395test_tp(struct net_device *dev, s32 msec)
3396{
3397 struct de4x5_private *lp = netdev_priv(dev);
3398 u_long iobase = dev->base_addr;
3399 int sisr;
3400
3401 if (lp->timeout < 0) {
3402 lp->timeout = msec/100;
3403 }
3404
3405 sisr = (inl(DE4X5_SISR) & ~TIMER_CB) & (SISR_LKF | SISR_NCR);
3406
3407 if (sisr && --lp->timeout) {
3408 sisr = 100 | TIMER_CB;
3409 } else {
3410 lp->timeout = -1;
3411 }
3412
3413 return sisr;
3414}
3415
3416/*
3417** Samples the 100Mb Link State Signal. The sample interval is important
3418** because too fast a rate can give erroneous results and confuse the
3419** speed sense algorithm.
3420*/
3421#define SAMPLE_INTERVAL 500 /* ms */
3422#define SAMPLE_DELAY 2000 /* ms */
3423static int
3424test_for_100Mb(struct net_device *dev, int msec)
3425{
3426 struct de4x5_private *lp = netdev_priv(dev);
3427 int gep = 0, ret = ((lp->chipset & ~0x00ff)==DC2114x? -1 :GEP_SLNK);
3428
3429 if (lp->timeout < 0) {
3430 if ((msec/SAMPLE_INTERVAL) <= 0) return 0;
3431 if (msec > SAMPLE_DELAY) {
3432 lp->timeout = (msec - SAMPLE_DELAY)/SAMPLE_INTERVAL;
3433 gep = SAMPLE_DELAY | TIMER_CB;
3434 return gep;
3435 } else {
3436 lp->timeout = msec/SAMPLE_INTERVAL;
3437 }
3438 }
3439
3440 if (lp->phy[lp->active].id || lp->useSROM) {
3441 gep = is_100_up(dev) | is_spd_100(dev);
3442 } else {
3443 gep = (~gep_rd(dev) & (GEP_SLNK | GEP_LNP));
3444 }
3445 if (!(gep & ret) && --lp->timeout) {
3446 gep = SAMPLE_INTERVAL | TIMER_CB;
3447 } else {
3448 lp->timeout = -1;
3449 }
3450
3451 return gep;
3452}
3453
3454static int
3455wait_for_link(struct net_device *dev)
3456{
3457 struct de4x5_private *lp = netdev_priv(dev);
3458
3459 if (lp->timeout < 0) {
3460 lp->timeout = 1;
3461 }
3462
3463 if (lp->timeout--) {
3464 return TIMER_CB;
3465 } else {
3466 lp->timeout = -1;
3467 }
3468
3469 return 0;
3470}
3471
3472/*
3473**
3474**
3475*/
3476static int
3477test_mii_reg(struct net_device *dev, int reg, int mask, int pol, long msec)
3478{
3479 struct de4x5_private *lp = netdev_priv(dev);
3480 int test;
3481 u_long iobase = dev->base_addr;
3482
3483 if (lp->timeout < 0) {
3484 lp->timeout = msec/100;
3485 }
3486
3487 if (pol) pol = ~0;
3488 reg = mii_rd((u_char)reg, lp->phy[lp->active].addr, DE4X5_MII) & mask;
3489 test = (reg ^ pol) & mask;
3490
3491 if (test && --lp->timeout) {
3492 reg = 100 | TIMER_CB;
3493 } else {
3494 lp->timeout = -1;
3495 }
3496
3497 return reg;
3498}
3499
3500static int
3501is_spd_100(struct net_device *dev)
3502{
3503 struct de4x5_private *lp = netdev_priv(dev);
3504 u_long iobase = dev->base_addr;
3505 int spd;
3506
3507 if (lp->useMII) {
3508 spd = mii_rd(lp->phy[lp->active].spd.reg, lp->phy[lp->active].addr, DE4X5_MII);
3509 spd = ~(spd ^ lp->phy[lp->active].spd.value);
3510 spd &= lp->phy[lp->active].spd.mask;
3511 } else if (!lp->useSROM) { /* de500-xa */
3512 spd = ((~gep_rd(dev)) & GEP_SLNK);
3513 } else {
3514 if ((lp->ibn == 2) || !lp->asBitValid)
3515 return ((lp->chipset == DC21143)?(~inl(DE4X5_SISR)&SISR_LS100):0);
3516
3517 spd = (lp->asBitValid & (lp->asPolarity ^ (gep_rd(dev) & lp->asBit))) |
3518 (lp->linkOK & ~lp->asBitValid);
3519 }
3520
3521 return spd;
3522}
3523
3524static int
3525is_100_up(struct net_device *dev)
3526{
3527 struct de4x5_private *lp = netdev_priv(dev);
3528 u_long iobase = dev->base_addr;
3529
3530 if (lp->useMII) {
3531 /* Double read for sticky bits & temporary drops */
3532 mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII);
3533 return (mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII) & MII_SR_LKS);
3534 } else if (!lp->useSROM) { /* de500-xa */
3535 return ((~gep_rd(dev)) & GEP_SLNK);
3536 } else {
3537 if ((lp->ibn == 2) || !lp->asBitValid)
3538 return ((lp->chipset == DC21143)?(~inl(DE4X5_SISR)&SISR_LS100):0);
3539
3540 return ((lp->asBitValid&(lp->asPolarity^(gep_rd(dev)&lp->asBit))) |
3541 (lp->linkOK & ~lp->asBitValid));
3542 }
3543}
3544
3545static int
3546is_10_up(struct net_device *dev)
3547{
3548 struct de4x5_private *lp = netdev_priv(dev);
3549 u_long iobase = dev->base_addr;
3550
3551 if (lp->useMII) {
3552 /* Double read for sticky bits & temporary drops */
3553 mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII);
3554 return (mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII) & MII_SR_LKS);
3555 } else if (!lp->useSROM) { /* de500-xa */
3556 return ((~gep_rd(dev)) & GEP_LNP);
3557 } else {
3558 if ((lp->ibn == 2) || !lp->asBitValid)
3559 return (((lp->chipset & ~0x00ff) == DC2114x) ?
3560 (~inl(DE4X5_SISR)&SISR_LS10):
3561 0);
3562
3563 return ((lp->asBitValid&(lp->asPolarity^(gep_rd(dev)&lp->asBit))) |
3564 (lp->linkOK & ~lp->asBitValid));
3565 }
3566}
3567
3568static int
3569is_anc_capable(struct net_device *dev)
3570{
3571 struct de4x5_private *lp = netdev_priv(dev);
3572 u_long iobase = dev->base_addr;
3573
3574 if (lp->phy[lp->active].id && (!lp->useSROM || lp->useMII)) {
3575 return (mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII));
3576 } else if ((lp->chipset & ~0x00ff) == DC2114x) {
3577 return (inl(DE4X5_SISR) & SISR_LPN) >> 12;
3578 } else {
3579 return 0;
3580 }
3581}
3582
3583/*
3584** Send a packet onto the media and watch for send errors that indicate the
3585** media is bad or unconnected.
3586*/
3587static int
3588ping_media(struct net_device *dev, int msec)
3589{
3590 struct de4x5_private *lp = netdev_priv(dev);
3591 u_long iobase = dev->base_addr;
3592 int sisr;
3593
3594 if (lp->timeout < 0) {
3595 lp->timeout = msec/100;
3596
3597 lp->tmp = lp->tx_new; /* Remember the ring position */
3598 load_packet(dev, lp->frame, TD_LS | TD_FS | sizeof(lp->frame), (struct sk_buff *)1);
3599 lp->tx_new = (++lp->tx_new) % lp->txRingSize;
3600 outl(POLL_DEMAND, DE4X5_TPD);
3601 }
3602
3603 sisr = inl(DE4X5_SISR);
3604
3605 if ((!(sisr & SISR_NCR)) &&
3606 ((s32)le32_to_cpu(lp->tx_ring[lp->tmp].status) < 0) &&
3607 (--lp->timeout)) {
3608 sisr = 100 | TIMER_CB;
3609 } else {
3610 if ((!(sisr & SISR_NCR)) &&
3611 !(le32_to_cpu(lp->tx_ring[lp->tmp].status) & (T_OWN | TD_ES)) &&
3612 lp->timeout) {
3613 sisr = 0;
3614 } else {
3615 sisr = 1;
3616 }
3617 lp->timeout = -1;
3618 }
3619
3620 return sisr;
3621}
3622
3623/*
3624** This function does 2 things: on Intels it kmalloc's another buffer to
3625** replace the one about to be passed up. On Alpha's it kmallocs a buffer
3626** into which the packet is copied.
3627*/
3628static struct sk_buff *
3629de4x5_alloc_rx_buff(struct net_device *dev, int index, int len)
3630{
3631 struct de4x5_private *lp = netdev_priv(dev);
3632 struct sk_buff *p;
3633
3634#if !defined(__alpha__) && !defined(__powerpc__) && !defined(__sparc_v9__) && !defined(DE4X5_DO_MEMCPY)
3635 struct sk_buff *ret;
3636 u_long i=0, tmp;
3637
3638 p = dev_alloc_skb(IEEE802_3_SZ + DE4X5_ALIGN + 2);
3639 if (!p) return NULL;
3640
3641 p->dev = dev;
3642 tmp = virt_to_bus(p->data);
3643 i = ((tmp + DE4X5_ALIGN) & ~DE4X5_ALIGN) - tmp;
3644 skb_reserve(p, i);
3645 lp->rx_ring[index].buf = cpu_to_le32(tmp + i);
3646
3647 ret = lp->rx_skb[index];
3648 lp->rx_skb[index] = p;
3649
3650 if ((u_long) ret > 1) {
3651 skb_put(ret, len);
3652 }
3653
3654 return ret;
3655
3656#else
3657 if (lp->state != OPEN) return (struct sk_buff *)1; /* Fake out the open */
3658
3659 p = dev_alloc_skb(len + 2);
3660 if (!p) return NULL;
3661
3662 p->dev = dev;
3663 skb_reserve(p, 2); /* Align */
3664 if (index < lp->rx_old) { /* Wrapped buffer */
3665 short tlen = (lp->rxRingSize - lp->rx_old) * RX_BUFF_SZ;
3666 memcpy(skb_put(p,tlen),lp->rx_bufs + lp->rx_old * RX_BUFF_SZ,tlen);
3667 memcpy(skb_put(p,len-tlen),lp->rx_bufs,len-tlen);
3668 } else { /* Linear buffer */
3669 memcpy(skb_put(p,len),lp->rx_bufs + lp->rx_old * RX_BUFF_SZ,len);
3670 }
3671
3672 return p;
3673#endif
3674}
3675
3676static void
3677de4x5_free_rx_buffs(struct net_device *dev)
3678{
3679 struct de4x5_private *lp = netdev_priv(dev);
3680 int i;
3681
3682 for (i=0; i<lp->rxRingSize; i++) {
3683 if ((u_long) lp->rx_skb[i] > 1) {
3684 dev_kfree_skb(lp->rx_skb[i]);
3685 }
3686 lp->rx_ring[i].status = 0;
3687 lp->rx_skb[i] = (struct sk_buff *)1; /* Dummy entry */
3688 }
3689
3690 return;
3691}
3692
3693static void
3694de4x5_free_tx_buffs(struct net_device *dev)
3695{
3696 struct de4x5_private *lp = netdev_priv(dev);
3697 int i;
3698
3699 for (i=0; i<lp->txRingSize; i++) {
3700 if (lp->tx_skb[i])
3701 de4x5_free_tx_buff(lp, i);
3702 lp->tx_ring[i].status = 0;
3703 }
3704
3705 /* Unload the locally queued packets */
3706 while (lp->cache.skb) {
3707 dev_kfree_skb(de4x5_get_cache(dev));
3708 }
3709
3710 return;
3711}
3712
3713/*
3714** When a user pulls a connection, the DECchip can end up in a
3715** 'running - waiting for end of transmission' state. This means that we
3716** have to perform a chip soft reset to ensure that we can synchronize
3717** the hardware and software and make any media probes using a loopback
3718** packet meaningful.
3719*/
3720static void
3721de4x5_save_skbs(struct net_device *dev)
3722{
3723 struct de4x5_private *lp = netdev_priv(dev);
3724 u_long iobase = dev->base_addr;
3725 s32 omr;
3726
3727 if (!lp->cache.save_cnt) {
3728 STOP_DE4X5;
3729 de4x5_tx(dev); /* Flush any sent skb's */
3730 de4x5_free_tx_buffs(dev);
3731 de4x5_cache_state(dev, DE4X5_SAVE_STATE);
3732 de4x5_sw_reset(dev);
3733 de4x5_cache_state(dev, DE4X5_RESTORE_STATE);
3734 lp->cache.save_cnt++;
3735 START_DE4X5;
3736 }
3737
3738 return;
3739}
3740
3741static void
3742de4x5_rst_desc_ring(struct net_device *dev)
3743{
3744 struct de4x5_private *lp = netdev_priv(dev);
3745 u_long iobase = dev->base_addr;
3746 int i;
3747 s32 omr;
3748
3749 if (lp->cache.save_cnt) {
3750 STOP_DE4X5;
3751 outl(lp->dma_rings, DE4X5_RRBA);
3752 outl(lp->dma_rings + NUM_RX_DESC * sizeof(struct de4x5_desc),
3753 DE4X5_TRBA);
3754
3755 lp->rx_new = lp->rx_old = 0;
3756 lp->tx_new = lp->tx_old = 0;
3757
3758 for (i = 0; i < lp->rxRingSize; i++) {
3759 lp->rx_ring[i].status = cpu_to_le32(R_OWN);
3760 }
3761
3762 for (i = 0; i < lp->txRingSize; i++) {
3763 lp->tx_ring[i].status = cpu_to_le32(0);
3764 }
3765
3766 barrier();
3767 lp->cache.save_cnt--;
3768 START_DE4X5;
3769 }
3770
3771 return;
3772}
3773
3774static void
3775de4x5_cache_state(struct net_device *dev, int flag)
3776{
3777 struct de4x5_private *lp = netdev_priv(dev);
3778 u_long iobase = dev->base_addr;
3779
3780 switch(flag) {
3781 case DE4X5_SAVE_STATE:
3782 lp->cache.csr0 = inl(DE4X5_BMR);
3783 lp->cache.csr6 = (inl(DE4X5_OMR) & ~(OMR_ST | OMR_SR));
3784 lp->cache.csr7 = inl(DE4X5_IMR);
3785 break;
3786
3787 case DE4X5_RESTORE_STATE:
3788 outl(lp->cache.csr0, DE4X5_BMR);
3789 outl(lp->cache.csr6, DE4X5_OMR);
3790 outl(lp->cache.csr7, DE4X5_IMR);
3791 if (lp->chipset == DC21140) {
3792 gep_wr(lp->cache.gepc, dev);
3793 gep_wr(lp->cache.gep, dev);
3794 } else {
3795 reset_init_sia(dev, lp->cache.csr13, lp->cache.csr14,
3796 lp->cache.csr15);
3797 }
3798 break;
3799 }
3800
3801 return;
3802}
3803
3804static void
3805de4x5_put_cache(struct net_device *dev, struct sk_buff *skb)
3806{
3807 struct de4x5_private *lp = netdev_priv(dev);
3808 struct sk_buff *p;
3809
3810 if (lp->cache.skb) {
3811 for (p=lp->cache.skb; p->next; p=p->next);
3812 p->next = skb;
3813 } else {
3814 lp->cache.skb = skb;
3815 }
3816 skb->next = NULL;
3817
3818 return;
3819}
3820
3821static void
3822de4x5_putb_cache(struct net_device *dev, struct sk_buff *skb)
3823{
3824 struct de4x5_private *lp = netdev_priv(dev);
3825 struct sk_buff *p = lp->cache.skb;
3826
3827 lp->cache.skb = skb;
3828 skb->next = p;
3829
3830 return;
3831}
3832
3833static struct sk_buff *
3834de4x5_get_cache(struct net_device *dev)
3835{
3836 struct de4x5_private *lp = netdev_priv(dev);
3837 struct sk_buff *p = lp->cache.skb;
3838
3839 if (p) {
3840 lp->cache.skb = p->next;
3841 p->next = NULL;
3842 }
3843
3844 return p;
3845}
3846
3847/*
3848** Check the Auto Negotiation State. Return OK when a link pass interrupt
3849** is received and the auto-negotiation status is NWAY OK.
3850*/
3851static int
3852test_ans(struct net_device *dev, s32 irqs, s32 irq_mask, s32 msec)
3853{
3854 struct de4x5_private *lp = netdev_priv(dev);
3855 u_long iobase = dev->base_addr;
3856 s32 sts, ans;
3857
3858 if (lp->timeout < 0) {
3859 lp->timeout = msec/100;
3860 outl(irq_mask, DE4X5_IMR);
3861
3862 /* clear all pending interrupts */
3863 sts = inl(DE4X5_STS);
3864 outl(sts, DE4X5_STS);
3865 }
3866
3867 ans = inl(DE4X5_SISR) & SISR_ANS;
3868 sts = inl(DE4X5_STS) & ~TIMER_CB;
3869
3870 if (!(sts & irqs) && (ans ^ ANS_NWOK) && --lp->timeout) {
3871 sts = 100 | TIMER_CB;
3872 } else {
3873 lp->timeout = -1;
3874 }
3875
3876 return sts;
3877}
3878
3879static void
3880de4x5_setup_intr(struct net_device *dev)
3881{
3882 struct de4x5_private *lp = netdev_priv(dev);
3883 u_long iobase = dev->base_addr;
3884 s32 imr, sts;
3885
3886 if (inl(DE4X5_OMR) & OMR_SR) { /* Only unmask if TX/RX is enabled */
3887 imr = 0;
3888 UNMASK_IRQs;
3889 sts = inl(DE4X5_STS); /* Reset any pending (stale) interrupts */
3890 outl(sts, DE4X5_STS);
3891 ENABLE_IRQs;
3892 }
3893
3894 return;
3895}
3896
3897/*
3898**
3899*/
3900static void
3901reset_init_sia(struct net_device *dev, s32 csr13, s32 csr14, s32 csr15)
3902{
3903 struct de4x5_private *lp = netdev_priv(dev);
3904 u_long iobase = dev->base_addr;
3905
3906 RESET_SIA;
3907 if (lp->useSROM) {
3908 if (lp->ibn == 3) {
3909 srom_exec(dev, lp->phy[lp->active].rst);
3910 srom_exec(dev, lp->phy[lp->active].gep);
3911 outl(1, DE4X5_SICR);
3912 return;
3913 } else {
3914 csr15 = lp->cache.csr15;
3915 csr14 = lp->cache.csr14;
3916 csr13 = lp->cache.csr13;
3917 outl(csr15 | lp->cache.gepc, DE4X5_SIGR);
3918 outl(csr15 | lp->cache.gep, DE4X5_SIGR);
3919 }
3920 } else {
3921 outl(csr15, DE4X5_SIGR);
3922 }
3923 outl(csr14, DE4X5_STRR);
3924 outl(csr13, DE4X5_SICR);
3925
3926 mdelay(10);
3927
3928 return;
3929}
3930
3931/*
3932** Create a loopback ethernet packet
3933*/
3934static void
3935create_packet(struct net_device *dev, char *frame, int len)
3936{
3937 int i;
3938 char *buf = frame;
3939
3940 for (i=0; i<ETH_ALEN; i++) { /* Use this source address */
3941 *buf++ = dev->dev_addr[i];
3942 }
3943 for (i=0; i<ETH_ALEN; i++) { /* Use this destination address */
3944 *buf++ = dev->dev_addr[i];
3945 }
3946
3947 *buf++ = 0; /* Packet length (2 bytes) */
3948 *buf++ = 1;
3949
3950 return;
3951}
3952
3953/*
3954** Look for a particular board name in the EISA configuration space
3955*/
3956static int
3957EISA_signature(char *name, struct device *device)
3958{
3959 int i, status = 0, siglen = sizeof(de4x5_signatures)/sizeof(c_char *);
3960 struct eisa_device *edev;
3961
3962 *name = '\0';
3963 edev = to_eisa_device (device);
3964 i = edev->id.driver_data;
3965
3966 if (i >= 0 && i < siglen) {
3967 strcpy (name, de4x5_signatures[i]);
3968 status = 1;
3969 }
3970
3971 return status; /* return the device name string */
3972}
3973
3974/*
3975** Look for a particular board name in the PCI configuration space
3976*/
3977static int
3978PCI_signature(char *name, struct de4x5_private *lp)
3979{
3980 int i, status = 0, siglen = sizeof(de4x5_signatures)/sizeof(c_char *);
3981
3982 if (lp->chipset == DC21040) {
3983 strcpy(name, "DE434/5");
3984 return status;
3985 } else { /* Search for a DEC name in the SROM */
3986 int i = *((char *)&lp->srom + 19) * 3;
3987 strncpy(name, (char *)&lp->srom + 26 + i, 8);
3988 }
3989 name[8] = '\0';
3990 for (i=0; i<siglen; i++) {
3991 if (strstr(name,de4x5_signatures[i])!=NULL) break;
3992 }
3993 if (i == siglen) {
3994 if (dec_only) {
3995 *name = '\0';
3996 } else { /* Use chip name to avoid confusion */
3997 strcpy(name, (((lp->chipset == DC21040) ? "DC21040" :
3998 ((lp->chipset == DC21041) ? "DC21041" :
3999 ((lp->chipset == DC21140) ? "DC21140" :
4000 ((lp->chipset == DC21142) ? "DC21142" :
4001 ((lp->chipset == DC21143) ? "DC21143" : "UNKNOWN"
4002 )))))));
4003 }
4004 if (lp->chipset != DC21041) {
4005 lp->useSROM = TRUE; /* card is not recognisably DEC */
4006 }
4007 } else if ((lp->chipset & ~0x00ff) == DC2114x) {
4008 lp->useSROM = TRUE;
4009 }
4010
4011 return status;
4012}
4013
4014/*
4015** Set up the Ethernet PROM counter to the start of the Ethernet address on
4016** the DC21040, else read the SROM for the other chips.
4017** The SROM may not be present in a multi-MAC card, so first read the
4018** MAC address and check for a bad address. If there is a bad one then exit
4019** immediately with the prior srom contents intact (the h/w address will
4020** be fixed up later).
4021*/
4022static void
4023DevicePresent(struct net_device *dev, u_long aprom_addr)
4024{
4025 int i, j=0;
4026 struct de4x5_private *lp = netdev_priv(dev);
4027
4028 if (lp->chipset == DC21040) {
4029 if (lp->bus == EISA) {
4030 enet_addr_rst(aprom_addr); /* Reset Ethernet Address ROM Pointer */
4031 } else {
4032 outl(0, aprom_addr); /* Reset Ethernet Address ROM Pointer */
4033 }
4034 } else { /* Read new srom */
4035 u_short tmp, *p = (short *)((char *)&lp->srom + SROM_HWADD);
4036 for (i=0; i<(ETH_ALEN>>1); i++) {
4037 tmp = srom_rd(aprom_addr, (SROM_HWADD>>1) + i);
4038 *p = le16_to_cpu(tmp);
4039 j += *p++;
4040 }
4041 if ((j == 0) || (j == 0x2fffd)) {
4042 return;
4043 }
4044
4045 p=(short *)&lp->srom;
4046 for (i=0; i<(sizeof(struct de4x5_srom)>>1); i++) {
4047 tmp = srom_rd(aprom_addr, i);
4048 *p++ = le16_to_cpu(tmp);
4049 }
4050 de4x5_dbg_srom((struct de4x5_srom *)&lp->srom);
4051 }
4052
4053 return;
4054}
4055
4056/*
4057** Since the write on the Enet PROM register doesn't seem to reset the PROM
4058** pointer correctly (at least on my DE425 EISA card), this routine should do
4059** it...from depca.c.
4060*/
4061static void
4062enet_addr_rst(u_long aprom_addr)
4063{
4064 union {
4065 struct {
4066 u32 a;
4067 u32 b;
4068 } llsig;
4069 char Sig[sizeof(u32) << 1];
4070 } dev;
4071 short sigLength=0;
4072 s8 data;
4073 int i, j;
4074
4075 dev.llsig.a = ETH_PROM_SIG;
4076 dev.llsig.b = ETH_PROM_SIG;
4077 sigLength = sizeof(u32) << 1;
4078
4079 for (i=0,j=0;j<sigLength && i<PROBE_LENGTH+sigLength-1;i++) {
4080 data = inb(aprom_addr);
4081 if (dev.Sig[j] == data) { /* track signature */
4082 j++;
4083 } else { /* lost signature; begin search again */
4084 if (data == dev.Sig[0]) { /* rare case.... */
4085 j=1;
4086 } else {
4087 j=0;
4088 }
4089 }
4090 }
4091
4092 return;
4093}
4094
4095/*
4096** For the bad status case and no SROM, then add one to the previous
4097** address. However, need to add one backwards in case we have 0xff
4098** as one or more of the bytes. Only the last 3 bytes should be checked
4099** as the first three are invariant - assigned to an organisation.
4100*/
4101static int
4102get_hw_addr(struct net_device *dev)
4103{
4104 u_long iobase = dev->base_addr;
4105 int broken, i, k, tmp, status = 0;
4106 u_short j,chksum;
4107 struct de4x5_private *lp = netdev_priv(dev);
4108
4109 broken = de4x5_bad_srom(lp);
4110
4111 for (i=0,k=0,j=0;j<3;j++) {
4112 k <<= 1;
4113 if (k > 0xffff) k-=0xffff;
4114
4115 if (lp->bus == PCI) {
4116 if (lp->chipset == DC21040) {
4117 while ((tmp = inl(DE4X5_APROM)) < 0);
4118 k += (u_char) tmp;
4119 dev->dev_addr[i++] = (u_char) tmp;
4120 while ((tmp = inl(DE4X5_APROM)) < 0);
4121 k += (u_short) (tmp << 8);
4122 dev->dev_addr[i++] = (u_char) tmp;
4123 } else if (!broken) {
4124 dev->dev_addr[i] = (u_char) lp->srom.ieee_addr[i]; i++;
4125 dev->dev_addr[i] = (u_char) lp->srom.ieee_addr[i]; i++;
4126 } else if ((broken == SMC) || (broken == ACCTON)) {
4127 dev->dev_addr[i] = *((u_char *)&lp->srom + i); i++;
4128 dev->dev_addr[i] = *((u_char *)&lp->srom + i); i++;
4129 }
4130 } else {
4131 k += (u_char) (tmp = inb(EISA_APROM));
4132 dev->dev_addr[i++] = (u_char) tmp;
4133 k += (u_short) ((tmp = inb(EISA_APROM)) << 8);
4134 dev->dev_addr[i++] = (u_char) tmp;
4135 }
4136
4137 if (k > 0xffff) k-=0xffff;
4138 }
4139 if (k == 0xffff) k=0;
4140
4141 if (lp->bus == PCI) {
4142 if (lp->chipset == DC21040) {
4143 while ((tmp = inl(DE4X5_APROM)) < 0);
4144 chksum = (u_char) tmp;
4145 while ((tmp = inl(DE4X5_APROM)) < 0);
4146 chksum |= (u_short) (tmp << 8);
4147 if ((k != chksum) && (dec_only)) status = -1;
4148 }
4149 } else {
4150 chksum = (u_char) inb(EISA_APROM);
4151 chksum |= (u_short) (inb(EISA_APROM) << 8);
4152 if ((k != chksum) && (dec_only)) status = -1;
4153 }
4154
4155 /* If possible, try to fix a broken card - SMC only so far */
4156 srom_repair(dev, broken);
4157
4158#ifdef CONFIG_PPC_MULTIPLATFORM
4159 /*
4160 ** If the address starts with 00 a0, we have to bit-reverse
4161 ** each byte of the address.
4162 */
4163 if ( (_machine & _MACH_Pmac) &&
4164 (dev->dev_addr[0] == 0) &&
4165 (dev->dev_addr[1] == 0xa0) )
4166 {
4167 for (i = 0; i < ETH_ALEN; ++i)
4168 {
4169 int x = dev->dev_addr[i];
4170 x = ((x & 0xf) << 4) + ((x & 0xf0) >> 4);
4171 x = ((x & 0x33) << 2) + ((x & 0xcc) >> 2);
4172 dev->dev_addr[i] = ((x & 0x55) << 1) + ((x & 0xaa) >> 1);
4173 }
4174 }
4175#endif /* CONFIG_PPC_MULTIPLATFORM */
4176
4177 /* Test for a bad enet address */
4178 status = test_bad_enet(dev, status);
4179
4180 return status;
4181}
4182
4183/*
4184** Test for enet addresses in the first 32 bytes. The built-in strncmp
4185** didn't seem to work here...?
4186*/
4187static int
4188de4x5_bad_srom(struct de4x5_private *lp)
4189{
4190 int i, status = 0;
4191
4192 for (i=0; i<sizeof(enet_det)/ETH_ALEN; i++) {
4193 if (!de4x5_strncmp((char *)&lp->srom, (char *)&enet_det[i], 3) &&
4194 !de4x5_strncmp((char *)&lp->srom+0x10, (char *)&enet_det[i], 3)) {
4195 if (i == 0) {
4196 status = SMC;
4197 } else if (i == 1) {
4198 status = ACCTON;
4199 }
4200 break;
4201 }
4202 }
4203
4204 return status;
4205}
4206
4207static int
4208de4x5_strncmp(char *a, char *b, int n)
4209{
4210 int ret=0;
4211
4212 for (;n && !ret;n--) {
4213 ret = *a++ - *b++;
4214 }
4215
4216 return ret;
4217}
4218
4219static void
4220srom_repair(struct net_device *dev, int card)
4221{
4222 struct de4x5_private *lp = netdev_priv(dev);
4223
4224 switch(card) {
4225 case SMC:
4226 memset((char *)&lp->srom, 0, sizeof(struct de4x5_srom));
4227 memcpy(lp->srom.ieee_addr, (char *)dev->dev_addr, ETH_ALEN);
4228 memcpy(lp->srom.info, (char *)&srom_repair_info[SMC-1], 100);
4229 lp->useSROM = TRUE;
4230 break;
4231 }
4232
4233 return;
4234}
4235
4236/*
4237** Assume that the irq's do not follow the PCI spec - this is seems
4238** to be true so far (2 for 2).
4239*/
4240static int
4241test_bad_enet(struct net_device *dev, int status)
4242{
4243 struct de4x5_private *lp = netdev_priv(dev);
4244 int i, tmp;
4245
4246 for (tmp=0,i=0; i<ETH_ALEN; i++) tmp += (u_char)dev->dev_addr[i];
4247 if ((tmp == 0) || (tmp == 0x5fa)) {
4248 if ((lp->chipset == last.chipset) &&
4249 (lp->bus_num == last.bus) && (lp->bus_num > 0)) {
4250 for (i=0; i<ETH_ALEN; i++) dev->dev_addr[i] = last.addr[i];
4251 for (i=ETH_ALEN-1; i>2; --i) {
4252 dev->dev_addr[i] += 1;
4253 if (dev->dev_addr[i] != 0) break;
4254 }
4255 for (i=0; i<ETH_ALEN; i++) last.addr[i] = dev->dev_addr[i];
4256 if (!an_exception(lp)) {
4257 dev->irq = last.irq;
4258 }
4259
4260 status = 0;
4261 }
4262 } else if (!status) {
4263 last.chipset = lp->chipset;
4264 last.bus = lp->bus_num;
4265 last.irq = dev->irq;
4266 for (i=0; i<ETH_ALEN; i++) last.addr[i] = dev->dev_addr[i];
4267 }
4268
4269 return status;
4270}
4271
4272/*
4273** List of board exceptions with correctly wired IRQs
4274*/
4275static int
4276an_exception(struct de4x5_private *lp)
4277{
4278 if ((*(u_short *)lp->srom.sub_vendor_id == 0x00c0) &&
4279 (*(u_short *)lp->srom.sub_system_id == 0x95e0)) {
4280 return -1;
4281 }
4282
4283 return 0;
4284}
4285
4286/*
4287** SROM Read
4288*/
4289static short
4290srom_rd(u_long addr, u_char offset)
4291{
4292 sendto_srom(SROM_RD | SROM_SR, addr);
4293
4294 srom_latch(SROM_RD | SROM_SR | DT_CS, addr);
4295 srom_command(SROM_RD | SROM_SR | DT_IN | DT_CS, addr);
4296 srom_address(SROM_RD | SROM_SR | DT_CS, addr, offset);
4297
4298 return srom_data(SROM_RD | SROM_SR | DT_CS, addr);
4299}
4300
4301static void
4302srom_latch(u_int command, u_long addr)
4303{
4304 sendto_srom(command, addr);
4305 sendto_srom(command | DT_CLK, addr);
4306 sendto_srom(command, addr);
4307
4308 return;
4309}
4310
4311static void
4312srom_command(u_int command, u_long addr)
4313{
4314 srom_latch(command, addr);
4315 srom_latch(command, addr);
4316 srom_latch((command & 0x0000ff00) | DT_CS, addr);
4317
4318 return;
4319}
4320
4321static void
4322srom_address(u_int command, u_long addr, u_char offset)
4323{
4324 int i, a;
4325
4326 a = offset << 2;
4327 for (i=0; i<6; i++, a <<= 1) {
4328 srom_latch(command | ((a & 0x80) ? DT_IN : 0), addr);
4329 }
4330 udelay(1);
4331
4332 i = (getfrom_srom(addr) >> 3) & 0x01;
4333
4334 return;
4335}
4336
4337static short
4338srom_data(u_int command, u_long addr)
4339{
4340 int i;
4341 short word = 0;
4342 s32 tmp;
4343
4344 for (i=0; i<16; i++) {
4345 sendto_srom(command | DT_CLK, addr);
4346 tmp = getfrom_srom(addr);
4347 sendto_srom(command, addr);
4348
4349 word = (word << 1) | ((tmp >> 3) & 0x01);
4350 }
4351
4352 sendto_srom(command & 0x0000ff00, addr);
4353
4354 return word;
4355}
4356
4357/*
4358static void
4359srom_busy(u_int command, u_long addr)
4360{
4361 sendto_srom((command & 0x0000ff00) | DT_CS, addr);
4362
4363 while (!((getfrom_srom(addr) >> 3) & 0x01)) {
4364 mdelay(1);
4365 }
4366
4367 sendto_srom(command & 0x0000ff00, addr);
4368
4369 return;
4370}
4371*/
4372
4373static void
4374sendto_srom(u_int command, u_long addr)
4375{
4376 outl(command, addr);
4377 udelay(1);
4378
4379 return;
4380}
4381
4382static int
4383getfrom_srom(u_long addr)
4384{
4385 s32 tmp;
4386
4387 tmp = inl(addr);
4388 udelay(1);
4389
4390 return tmp;
4391}
4392
4393static int
4394srom_infoleaf_info(struct net_device *dev)
4395{
4396 struct de4x5_private *lp = netdev_priv(dev);
4397 int i, count;
4398 u_char *p;
4399
4400 /* Find the infoleaf decoder function that matches this chipset */
4401 for (i=0; i<INFOLEAF_SIZE; i++) {
4402 if (lp->chipset == infoleaf_array[i].chipset) break;
4403 }
4404 if (i == INFOLEAF_SIZE) {
4405 lp->useSROM = FALSE;
4406 printk("%s: Cannot find correct chipset for SROM decoding!\n",
4407 dev->name);
4408 return -ENXIO;
4409 }
4410
4411 lp->infoleaf_fn = infoleaf_array[i].fn;
4412
4413 /* Find the information offset that this function should use */
4414 count = *((u_char *)&lp->srom + 19);
4415 p = (u_char *)&lp->srom + 26;
4416
4417 if (count > 1) {
4418 for (i=count; i; --i, p+=3) {
4419 if (lp->device == *p) break;
4420 }
4421 if (i == 0) {
4422 lp->useSROM = FALSE;
4423 printk("%s: Cannot find correct PCI device [%d] for SROM decoding!\n",
4424 dev->name, lp->device);
4425 return -ENXIO;
4426 }
4427 }
4428
4429 lp->infoleaf_offset = TWIDDLE(p+1);
4430
4431 return 0;
4432}
4433
4434/*
4435** This routine loads any type 1 or 3 MII info into the mii device
4436** struct and executes any type 5 code to reset PHY devices for this
4437** controller.
4438** The info for the MII devices will be valid since the index used
4439** will follow the discovery process from MII address 1-31 then 0.
4440*/
4441static void
4442srom_init(struct net_device *dev)
4443{
4444 struct de4x5_private *lp = netdev_priv(dev);
4445 u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
4446 u_char count;
4447
4448 p+=2;
4449 if (lp->chipset == DC21140) {
4450 lp->cache.gepc = (*p++ | GEP_CTRL);
4451 gep_wr(lp->cache.gepc, dev);
4452 }
4453
4454 /* Block count */
4455 count = *p++;
4456
4457 /* Jump the infoblocks to find types */
4458 for (;count; --count) {
4459 if (*p < 128) {
4460 p += COMPACT_LEN;
4461 } else if (*(p+1) == 5) {
4462 type5_infoblock(dev, 1, p);
4463 p += ((*p & BLOCK_LEN) + 1);
4464 } else if (*(p+1) == 4) {
4465 p += ((*p & BLOCK_LEN) + 1);
4466 } else if (*(p+1) == 3) {
4467 type3_infoblock(dev, 1, p);
4468 p += ((*p & BLOCK_LEN) + 1);
4469 } else if (*(p+1) == 2) {
4470 p += ((*p & BLOCK_LEN) + 1);
4471 } else if (*(p+1) == 1) {
4472 type1_infoblock(dev, 1, p);
4473 p += ((*p & BLOCK_LEN) + 1);
4474 } else {
4475 p += ((*p & BLOCK_LEN) + 1);
4476 }
4477 }
4478
4479 return;
4480}
4481
4482/*
4483** A generic routine that writes GEP control, data and reset information
4484** to the GEP register (21140) or csr15 GEP portion (2114[23]).
4485*/
4486static void
4487srom_exec(struct net_device *dev, u_char *p)
4488{
4489 struct de4x5_private *lp = netdev_priv(dev);
4490 u_long iobase = dev->base_addr;
4491 u_char count = (p ? *p++ : 0);
4492 u_short *w = (u_short *)p;
4493
4494 if (((lp->ibn != 1) && (lp->ibn != 3) && (lp->ibn != 5)) || !count) return;
4495
4496 if (lp->chipset != DC21140) RESET_SIA;
4497
4498 while (count--) {
4499 gep_wr(((lp->chipset==DC21140) && (lp->ibn!=5) ?
4500 *p++ : TWIDDLE(w++)), dev);
4501 mdelay(2); /* 2ms per action */
4502 }
4503
4504 if (lp->chipset != DC21140) {
4505 outl(lp->cache.csr14, DE4X5_STRR);
4506 outl(lp->cache.csr13, DE4X5_SICR);
4507 }
4508
4509 return;
4510}
4511
4512/*
4513** Basically this function is a NOP since it will never be called,
4514** unless I implement the DC21041 SROM functions. There's no need
4515** since the existing code will be satisfactory for all boards.
4516*/
4517static int
4518dc21041_infoleaf(struct net_device *dev)
4519{
4520 return DE4X5_AUTOSENSE_MS;
4521}
4522
4523static int
4524dc21140_infoleaf(struct net_device *dev)
4525{
4526 struct de4x5_private *lp = netdev_priv(dev);
4527 u_char count = 0;
4528 u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
4529 int next_tick = DE4X5_AUTOSENSE_MS;
4530
4531 /* Read the connection type */
4532 p+=2;
4533
4534 /* GEP control */
4535 lp->cache.gepc = (*p++ | GEP_CTRL);
4536
4537 /* Block count */
4538 count = *p++;
4539
4540 /* Recursively figure out the info blocks */
4541 if (*p < 128) {
4542 next_tick = dc_infoblock[COMPACT](dev, count, p);
4543 } else {
4544 next_tick = dc_infoblock[*(p+1)](dev, count, p);
4545 }
4546
4547 if (lp->tcount == count) {
4548 lp->media = NC;
4549 if (lp->media != lp->c_media) {
4550 de4x5_dbg_media(dev);
4551 lp->c_media = lp->media;
4552 }
4553 lp->media = INIT;
4554 lp->tcount = 0;
4555 lp->tx_enable = FALSE;
4556 }
4557
4558 return next_tick & ~TIMER_CB;
4559}
4560
4561static int
4562dc21142_infoleaf(struct net_device *dev)
4563{
4564 struct de4x5_private *lp = netdev_priv(dev);
4565 u_char count = 0;
4566 u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
4567 int next_tick = DE4X5_AUTOSENSE_MS;
4568
4569 /* Read the connection type */
4570 p+=2;
4571
4572 /* Block count */
4573 count = *p++;
4574
4575 /* Recursively figure out the info blocks */
4576 if (*p < 128) {
4577 next_tick = dc_infoblock[COMPACT](dev, count, p);
4578 } else {
4579 next_tick = dc_infoblock[*(p+1)](dev, count, p);
4580 }
4581
4582 if (lp->tcount == count) {
4583 lp->media = NC;
4584 if (lp->media != lp->c_media) {
4585 de4x5_dbg_media(dev);
4586 lp->c_media = lp->media;
4587 }
4588 lp->media = INIT;
4589 lp->tcount = 0;
4590 lp->tx_enable = FALSE;
4591 }
4592
4593 return next_tick & ~TIMER_CB;
4594}
4595
4596static int
4597dc21143_infoleaf(struct net_device *dev)
4598{
4599 struct de4x5_private *lp = netdev_priv(dev);
4600 u_char count = 0;
4601 u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
4602 int next_tick = DE4X5_AUTOSENSE_MS;
4603
4604 /* Read the connection type */
4605 p+=2;
4606
4607 /* Block count */
4608 count = *p++;
4609
4610 /* Recursively figure out the info blocks */
4611 if (*p < 128) {
4612 next_tick = dc_infoblock[COMPACT](dev, count, p);
4613 } else {
4614 next_tick = dc_infoblock[*(p+1)](dev, count, p);
4615 }
4616 if (lp->tcount == count) {
4617 lp->media = NC;
4618 if (lp->media != lp->c_media) {
4619 de4x5_dbg_media(dev);
4620 lp->c_media = lp->media;
4621 }
4622 lp->media = INIT;
4623 lp->tcount = 0;
4624 lp->tx_enable = FALSE;
4625 }
4626
4627 return next_tick & ~TIMER_CB;
4628}
4629
4630/*
4631** The compact infoblock is only designed for DC21140[A] chips, so
4632** we'll reuse the dc21140m_autoconf function. Non MII media only.
4633*/
4634static int
4635compact_infoblock(struct net_device *dev, u_char count, u_char *p)
4636{
4637 struct de4x5_private *lp = netdev_priv(dev);
4638 u_char flags, csr6;
4639
4640 /* Recursively figure out the info blocks */
4641 if (--count > lp->tcount) {
4642 if (*(p+COMPACT_LEN) < 128) {
4643 return dc_infoblock[COMPACT](dev, count, p+COMPACT_LEN);
4644 } else {
4645 return dc_infoblock[*(p+COMPACT_LEN+1)](dev, count, p+COMPACT_LEN);
4646 }
4647 }
4648
4649 if ((lp->media == INIT) && (lp->timeout < 0)) {
4650 lp->ibn = COMPACT;
4651 lp->active = 0;
4652 gep_wr(lp->cache.gepc, dev);
4653 lp->infoblock_media = (*p++) & COMPACT_MC;
4654 lp->cache.gep = *p++;
4655 csr6 = *p++;
4656 flags = *p++;
4657
4658 lp->asBitValid = (flags & 0x80) ? 0 : -1;
4659 lp->defMedium = (flags & 0x40) ? -1 : 0;
4660 lp->asBit = 1 << ((csr6 >> 1) & 0x07);
4661 lp->asPolarity = ((csr6 & 0x80) ? -1 : 0) & lp->asBit;
4662 lp->infoblock_csr6 = OMR_DEF | ((csr6 & 0x71) << 18);
4663 lp->useMII = FALSE;
4664
4665 de4x5_switch_mac_port(dev);
4666 }
4667
4668 return dc21140m_autoconf(dev);
4669}
4670
4671/*
4672** This block describes non MII media for the DC21140[A] only.
4673*/
4674static int
4675type0_infoblock(struct net_device *dev, u_char count, u_char *p)
4676{
4677 struct de4x5_private *lp = netdev_priv(dev);
4678 u_char flags, csr6, len = (*p & BLOCK_LEN)+1;
4679
4680 /* Recursively figure out the info blocks */
4681 if (--count > lp->tcount) {
4682 if (*(p+len) < 128) {
4683 return dc_infoblock[COMPACT](dev, count, p+len);
4684 } else {
4685 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4686 }
4687 }
4688
4689 if ((lp->media == INIT) && (lp->timeout < 0)) {
4690 lp->ibn = 0;
4691 lp->active = 0;
4692 gep_wr(lp->cache.gepc, dev);
4693 p+=2;
4694 lp->infoblock_media = (*p++) & BLOCK0_MC;
4695 lp->cache.gep = *p++;
4696 csr6 = *p++;
4697 flags = *p++;
4698
4699 lp->asBitValid = (flags & 0x80) ? 0 : -1;
4700 lp->defMedium = (flags & 0x40) ? -1 : 0;
4701 lp->asBit = 1 << ((csr6 >> 1) & 0x07);
4702 lp->asPolarity = ((csr6 & 0x80) ? -1 : 0) & lp->asBit;
4703 lp->infoblock_csr6 = OMR_DEF | ((csr6 & 0x71) << 18);
4704 lp->useMII = FALSE;
4705
4706 de4x5_switch_mac_port(dev);
4707 }
4708
4709 return dc21140m_autoconf(dev);
4710}
4711
4712/* These functions are under construction! */
4713
4714static int
4715type1_infoblock(struct net_device *dev, u_char count, u_char *p)
4716{
4717 struct de4x5_private *lp = netdev_priv(dev);
4718 u_char len = (*p & BLOCK_LEN)+1;
4719
4720 /* Recursively figure out the info blocks */
4721 if (--count > lp->tcount) {
4722 if (*(p+len) < 128) {
4723 return dc_infoblock[COMPACT](dev, count, p+len);
4724 } else {
4725 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4726 }
4727 }
4728
4729 p += 2;
4730 if (lp->state == INITIALISED) {
4731 lp->ibn = 1;
4732 lp->active = *p++;
4733 lp->phy[lp->active].gep = (*p ? p : NULL); p += (*p + 1);
4734 lp->phy[lp->active].rst = (*p ? p : NULL); p += (*p + 1);
4735 lp->phy[lp->active].mc = TWIDDLE(p); p += 2;
4736 lp->phy[lp->active].ana = TWIDDLE(p); p += 2;
4737 lp->phy[lp->active].fdx = TWIDDLE(p); p += 2;
4738 lp->phy[lp->active].ttm = TWIDDLE(p);
4739 return 0;
4740 } else if ((lp->media == INIT) && (lp->timeout < 0)) {
4741 lp->ibn = 1;
4742 lp->active = *p;
4743 lp->infoblock_csr6 = OMR_MII_100;
4744 lp->useMII = TRUE;
4745 lp->infoblock_media = ANS;
4746
4747 de4x5_switch_mac_port(dev);
4748 }
4749
4750 return dc21140m_autoconf(dev);
4751}
4752
4753static int
4754type2_infoblock(struct net_device *dev, u_char count, u_char *p)
4755{
4756 struct de4x5_private *lp = netdev_priv(dev);
4757 u_char len = (*p & BLOCK_LEN)+1;
4758
4759 /* Recursively figure out the info blocks */
4760 if (--count > lp->tcount) {
4761 if (*(p+len) < 128) {
4762 return dc_infoblock[COMPACT](dev, count, p+len);
4763 } else {
4764 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4765 }
4766 }
4767
4768 if ((lp->media == INIT) && (lp->timeout < 0)) {
4769 lp->ibn = 2;
4770 lp->active = 0;
4771 p += 2;
4772 lp->infoblock_media = (*p) & MEDIA_CODE;
4773
4774 if ((*p++) & EXT_FIELD) {
4775 lp->cache.csr13 = TWIDDLE(p); p += 2;
4776 lp->cache.csr14 = TWIDDLE(p); p += 2;
4777 lp->cache.csr15 = TWIDDLE(p); p += 2;
4778 } else {
4779 lp->cache.csr13 = CSR13;
4780 lp->cache.csr14 = CSR14;
4781 lp->cache.csr15 = CSR15;
4782 }
4783 lp->cache.gepc = ((s32)(TWIDDLE(p)) << 16); p += 2;
4784 lp->cache.gep = ((s32)(TWIDDLE(p)) << 16);
4785 lp->infoblock_csr6 = OMR_SIA;
4786 lp->useMII = FALSE;
4787
4788 de4x5_switch_mac_port(dev);
4789 }
4790
4791 return dc2114x_autoconf(dev);
4792}
4793
4794static int
4795type3_infoblock(struct net_device *dev, u_char count, u_char *p)
4796{
4797 struct de4x5_private *lp = netdev_priv(dev);
4798 u_char len = (*p & BLOCK_LEN)+1;
4799
4800 /* Recursively figure out the info blocks */
4801 if (--count > lp->tcount) {
4802 if (*(p+len) < 128) {
4803 return dc_infoblock[COMPACT](dev, count, p+len);
4804 } else {
4805 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4806 }
4807 }
4808
4809 p += 2;
4810 if (lp->state == INITIALISED) {
4811 lp->ibn = 3;
4812 lp->active = *p++;
4813 if (MOTO_SROM_BUG) lp->active = 0;
4814 lp->phy[lp->active].gep = (*p ? p : NULL); p += (2 * (*p) + 1);
4815 lp->phy[lp->active].rst = (*p ? p : NULL); p += (2 * (*p) + 1);
4816 lp->phy[lp->active].mc = TWIDDLE(p); p += 2;
4817 lp->phy[lp->active].ana = TWIDDLE(p); p += 2;
4818 lp->phy[lp->active].fdx = TWIDDLE(p); p += 2;
4819 lp->phy[lp->active].ttm = TWIDDLE(p); p += 2;
4820 lp->phy[lp->active].mci = *p;
4821 return 0;
4822 } else if ((lp->media == INIT) && (lp->timeout < 0)) {
4823 lp->ibn = 3;
4824 lp->active = *p;
4825 if (MOTO_SROM_BUG) lp->active = 0;
4826 lp->infoblock_csr6 = OMR_MII_100;
4827 lp->useMII = TRUE;
4828 lp->infoblock_media = ANS;
4829
4830 de4x5_switch_mac_port(dev);
4831 }
4832
4833 return dc2114x_autoconf(dev);
4834}
4835
4836static int
4837type4_infoblock(struct net_device *dev, u_char count, u_char *p)
4838{
4839 struct de4x5_private *lp = netdev_priv(dev);
4840 u_char flags, csr6, len = (*p & BLOCK_LEN)+1;
4841
4842 /* Recursively figure out the info blocks */
4843 if (--count > lp->tcount) {
4844 if (*(p+len) < 128) {
4845 return dc_infoblock[COMPACT](dev, count, p+len);
4846 } else {
4847 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4848 }
4849 }
4850
4851 if ((lp->media == INIT) && (lp->timeout < 0)) {
4852 lp->ibn = 4;
4853 lp->active = 0;
4854 p+=2;
4855 lp->infoblock_media = (*p++) & MEDIA_CODE;
4856 lp->cache.csr13 = CSR13; /* Hard coded defaults */
4857 lp->cache.csr14 = CSR14;
4858 lp->cache.csr15 = CSR15;
4859 lp->cache.gepc = ((s32)(TWIDDLE(p)) << 16); p += 2;
4860 lp->cache.gep = ((s32)(TWIDDLE(p)) << 16); p += 2;
4861 csr6 = *p++;
4862 flags = *p++;
4863
4864 lp->asBitValid = (flags & 0x80) ? 0 : -1;
4865 lp->defMedium = (flags & 0x40) ? -1 : 0;
4866 lp->asBit = 1 << ((csr6 >> 1) & 0x07);
4867 lp->asPolarity = ((csr6 & 0x80) ? -1 : 0) & lp->asBit;
4868 lp->infoblock_csr6 = OMR_DEF | ((csr6 & 0x71) << 18);
4869 lp->useMII = FALSE;
4870
4871 de4x5_switch_mac_port(dev);
4872 }
4873
4874 return dc2114x_autoconf(dev);
4875}
4876
4877/*
4878** This block type provides information for resetting external devices
4879** (chips) through the General Purpose Register.
4880*/
4881static int
4882type5_infoblock(struct net_device *dev, u_char count, u_char *p)
4883{
4884 struct de4x5_private *lp = netdev_priv(dev);
4885 u_char len = (*p & BLOCK_LEN)+1;
4886
4887 /* Recursively figure out the info blocks */
4888 if (--count > lp->tcount) {
4889 if (*(p+len) < 128) {
4890 return dc_infoblock[COMPACT](dev, count, p+len);
4891 } else {
4892 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4893 }
4894 }
4895
4896 /* Must be initializing to run this code */
4897 if ((lp->state == INITIALISED) || (lp->media == INIT)) {
4898 p+=2;
4899 lp->rst = p;
4900 srom_exec(dev, lp->rst);
4901 }
4902
4903 return DE4X5_AUTOSENSE_MS;
4904}
4905
4906/*
4907** MII Read/Write
4908*/
4909
4910static int
4911mii_rd(u_char phyreg, u_char phyaddr, u_long ioaddr)
4912{
4913 mii_wdata(MII_PREAMBLE, 2, ioaddr); /* Start of 34 bit preamble... */
4914 mii_wdata(MII_PREAMBLE, 32, ioaddr); /* ...continued */
4915 mii_wdata(MII_STRD, 4, ioaddr); /* SFD and Read operation */
4916 mii_address(phyaddr, ioaddr); /* PHY address to be accessed */
4917 mii_address(phyreg, ioaddr); /* PHY Register to read */
4918 mii_ta(MII_STRD, ioaddr); /* Turn around time - 2 MDC */
4919
4920 return mii_rdata(ioaddr); /* Read data */
4921}
4922
4923static void
4924mii_wr(int data, u_char phyreg, u_char phyaddr, u_long ioaddr)
4925{
4926 mii_wdata(MII_PREAMBLE, 2, ioaddr); /* Start of 34 bit preamble... */
4927 mii_wdata(MII_PREAMBLE, 32, ioaddr); /* ...continued */
4928 mii_wdata(MII_STWR, 4, ioaddr); /* SFD and Write operation */
4929 mii_address(phyaddr, ioaddr); /* PHY address to be accessed */
4930 mii_address(phyreg, ioaddr); /* PHY Register to write */
4931 mii_ta(MII_STWR, ioaddr); /* Turn around time - 2 MDC */
4932 data = mii_swap(data, 16); /* Swap data bit ordering */
4933 mii_wdata(data, 16, ioaddr); /* Write data */
4934
4935 return;
4936}
4937
4938static int
4939mii_rdata(u_long ioaddr)
4940{
4941 int i;
4942 s32 tmp = 0;
4943
4944 for (i=0; i<16; i++) {
4945 tmp <<= 1;
4946 tmp |= getfrom_mii(MII_MRD | MII_RD, ioaddr);
4947 }
4948
4949 return tmp;
4950}
4951
4952static void
4953mii_wdata(int data, int len, u_long ioaddr)
4954{
4955 int i;
4956
4957 for (i=0; i<len; i++) {
4958 sendto_mii(MII_MWR | MII_WR, data, ioaddr);
4959 data >>= 1;
4960 }
4961
4962 return;
4963}
4964
4965static void
4966mii_address(u_char addr, u_long ioaddr)
4967{
4968 int i;
4969
4970 addr = mii_swap(addr, 5);
4971 for (i=0; i<5; i++) {
4972 sendto_mii(MII_MWR | MII_WR, addr, ioaddr);
4973 addr >>= 1;
4974 }
4975
4976 return;
4977}
4978
4979static void
4980mii_ta(u_long rw, u_long ioaddr)
4981{
4982 if (rw == MII_STWR) {
4983 sendto_mii(MII_MWR | MII_WR, 1, ioaddr);
4984 sendto_mii(MII_MWR | MII_WR, 0, ioaddr);
4985 } else {
4986 getfrom_mii(MII_MRD | MII_RD, ioaddr); /* Tri-state MDIO */
4987 }
4988
4989 return;
4990}
4991
4992static int
4993mii_swap(int data, int len)
4994{
4995 int i, tmp = 0;
4996
4997 for (i=0; i<len; i++) {
4998 tmp <<= 1;
4999 tmp |= (data & 1);
5000 data >>= 1;
5001 }
5002
5003 return tmp;
5004}
5005
5006static void
5007sendto_mii(u32 command, int data, u_long ioaddr)
5008{
5009 u32 j;
5010
5011 j = (data & 1) << 17;
5012 outl(command | j, ioaddr);
5013 udelay(1);
5014 outl(command | MII_MDC | j, ioaddr);
5015 udelay(1);
5016
5017 return;
5018}
5019
5020static int
5021getfrom_mii(u32 command, u_long ioaddr)
5022{
5023 outl(command, ioaddr);
5024 udelay(1);
5025 outl(command | MII_MDC, ioaddr);
5026 udelay(1);
5027
5028 return ((inl(ioaddr) >> 19) & 1);
5029}
5030
5031/*
5032** Here's 3 ways to calculate the OUI from the ID registers.
5033*/
5034static int
5035mii_get_oui(u_char phyaddr, u_long ioaddr)
5036{
5037/*
5038 union {
5039 u_short reg;
5040 u_char breg[2];
5041 } a;
5042 int i, r2, r3, ret=0;*/
5043 int r2, r3;
5044
5045 /* Read r2 and r3 */
5046 r2 = mii_rd(MII_ID0, phyaddr, ioaddr);
5047 r3 = mii_rd(MII_ID1, phyaddr, ioaddr);
5048 /* SEEQ and Cypress way * /
5049 / * Shuffle r2 and r3 * /
5050 a.reg=0;
5051 r3 = ((r3>>10)|(r2<<6))&0x0ff;
5052 r2 = ((r2>>2)&0x3fff);
5053
5054 / * Bit reverse r3 * /
5055 for (i=0;i<8;i++) {
5056 ret<<=1;
5057 ret |= (r3&1);
5058 r3>>=1;
5059 }
5060
5061 / * Bit reverse r2 * /
5062 for (i=0;i<16;i++) {
5063 a.reg<<=1;
5064 a.reg |= (r2&1);
5065 r2>>=1;
5066 }
5067
5068 / * Swap r2 bytes * /
5069 i=a.breg[0];
5070 a.breg[0]=a.breg[1];
5071 a.breg[1]=i;
5072
5073 return ((a.reg<<8)|ret); */ /* SEEQ and Cypress way */
5074/* return ((r2<<6)|(u_int)(r3>>10)); */ /* NATIONAL and BROADCOM way */
5075 return r2; /* (I did it) My way */
5076}
5077
5078/*
5079** The SROM spec forces us to search addresses [1-31 0]. Bummer.
5080*/
5081static int
5082mii_get_phy(struct net_device *dev)
5083{
5084 struct de4x5_private *lp = netdev_priv(dev);
5085 u_long iobase = dev->base_addr;
5086 int i, j, k, n, limit=sizeof(phy_info)/sizeof(struct phy_table);
5087 int id;
5088
5089 lp->active = 0;
5090 lp->useMII = TRUE;
5091
5092 /* Search the MII address space for possible PHY devices */
5093 for (n=0, lp->mii_cnt=0, i=1; !((i==1) && (n==1)); i=(i+1)%DE4X5_MAX_MII) {
5094 lp->phy[lp->active].addr = i;
5095 if (i==0) n++; /* Count cycles */
5096 while (de4x5_reset_phy(dev)<0) udelay(100);/* Wait for reset */
5097 id = mii_get_oui(i, DE4X5_MII);
5098 if ((id == 0) || (id == 65535)) continue; /* Valid ID? */
5099 for (j=0; j<limit; j++) { /* Search PHY table */
5100 if (id != phy_info[j].id) continue; /* ID match? */
5101 for (k=0; lp->phy[k].id && (k < DE4X5_MAX_PHY); k++);
5102 if (k < DE4X5_MAX_PHY) {
5103 memcpy((char *)&lp->phy[k],
5104 (char *)&phy_info[j], sizeof(struct phy_table));
5105 lp->phy[k].addr = i;
5106 lp->mii_cnt++;
5107 lp->active++;
5108 } else {
5109 goto purgatory; /* Stop the search */
5110 }
5111 break;
5112 }
5113 if ((j == limit) && (i < DE4X5_MAX_MII)) {
5114 for (k=0; lp->phy[k].id && (k < DE4X5_MAX_PHY); k++);
5115 lp->phy[k].addr = i;
5116 lp->phy[k].id = id;
5117 lp->phy[k].spd.reg = GENERIC_REG; /* ANLPA register */
5118 lp->phy[k].spd.mask = GENERIC_MASK; /* 100Mb/s technologies */
5119 lp->phy[k].spd.value = GENERIC_VALUE; /* TX & T4, H/F Duplex */
5120 lp->mii_cnt++;
5121 lp->active++;
5122 printk("%s: Using generic MII device control. If the board doesn't operate, \nplease mail the following dump to the author:\n", dev->name);
5123 j = de4x5_debug;
5124 de4x5_debug |= DEBUG_MII;
5125 de4x5_dbg_mii(dev, k);
5126 de4x5_debug = j;
5127 printk("\n");
5128 }
5129 }
5130 purgatory:
5131 lp->active = 0;
5132 if (lp->phy[0].id) { /* Reset the PHY devices */
5133 for (k=0; lp->phy[k].id && (k < DE4X5_MAX_PHY); k++) { /*For each PHY*/
5134 mii_wr(MII_CR_RST, MII_CR, lp->phy[k].addr, DE4X5_MII);
5135 while (mii_rd(MII_CR, lp->phy[k].addr, DE4X5_MII) & MII_CR_RST);
5136
5137 de4x5_dbg_mii(dev, k);
5138 }
5139 }
5140 if (!lp->mii_cnt) lp->useMII = FALSE;
5141
5142 return lp->mii_cnt;
5143}
5144
5145static char *
5146build_setup_frame(struct net_device *dev, int mode)
5147{
5148 struct de4x5_private *lp = netdev_priv(dev);
5149 int i;
5150 char *pa = lp->setup_frame;
5151
5152 /* Initialise the setup frame */
5153 if (mode == ALL) {
5154 memset(lp->setup_frame, 0, SETUP_FRAME_LEN);
5155 }
5156
5157 if (lp->setup_f == HASH_PERF) {
5158 for (pa=lp->setup_frame+IMPERF_PA_OFFSET, i=0; i<ETH_ALEN; i++) {
5159 *(pa + i) = dev->dev_addr[i]; /* Host address */
5160 if (i & 0x01) pa += 2;
5161 }
5162 *(lp->setup_frame + (HASH_TABLE_LEN >> 3) - 3) = 0x80;
5163 } else {
5164 for (i=0; i<ETH_ALEN; i++) { /* Host address */
5165 *(pa + (i&1)) = dev->dev_addr[i];
5166 if (i & 0x01) pa += 4;
5167 }
5168 for (i=0; i<ETH_ALEN; i++) { /* Broadcast address */
5169 *(pa + (i&1)) = (char) 0xff;
5170 if (i & 0x01) pa += 4;
5171 }
5172 }
5173
5174 return pa; /* Points to the next entry */
5175}
5176
5177static void
5178enable_ast(struct net_device *dev, u32 time_out)
5179{
5180 timeout(dev, (void *)&de4x5_ast, (u_long)dev, time_out);
5181
5182 return;
5183}
5184
5185static void
5186disable_ast(struct net_device *dev)
5187{
5188 struct de4x5_private *lp = netdev_priv(dev);
5189
5190 del_timer(&lp->timer);
5191
5192 return;
5193}
5194
5195static long
5196de4x5_switch_mac_port(struct net_device *dev)
5197{
5198 struct de4x5_private *lp = netdev_priv(dev);
5199 u_long iobase = dev->base_addr;
5200 s32 omr;
5201
5202 STOP_DE4X5;
5203
5204 /* Assert the OMR_PS bit in CSR6 */
5205 omr = (inl(DE4X5_OMR) & ~(OMR_PS | OMR_HBD | OMR_TTM | OMR_PCS | OMR_SCR |
5206 OMR_FDX));
5207 omr |= lp->infoblock_csr6;
5208 if (omr & OMR_PS) omr |= OMR_HBD;
5209 outl(omr, DE4X5_OMR);
5210
5211 /* Soft Reset */
5212 RESET_DE4X5;
5213
5214 /* Restore the GEP - especially for COMPACT and Type 0 Infoblocks */
5215 if (lp->chipset == DC21140) {
5216 gep_wr(lp->cache.gepc, dev);
5217 gep_wr(lp->cache.gep, dev);
5218 } else if ((lp->chipset & ~0x0ff) == DC2114x) {
5219 reset_init_sia(dev, lp->cache.csr13, lp->cache.csr14, lp->cache.csr15);
5220 }
5221
5222 /* Restore CSR6 */
5223 outl(omr, DE4X5_OMR);
5224
5225 /* Reset CSR8 */
5226 inl(DE4X5_MFC);
5227
5228 return omr;
5229}
5230
5231static void
5232gep_wr(s32 data, struct net_device *dev)
5233{
5234 struct de4x5_private *lp = netdev_priv(dev);
5235 u_long iobase = dev->base_addr;
5236
5237 if (lp->chipset == DC21140) {
5238 outl(data, DE4X5_GEP);
5239 } else if ((lp->chipset & ~0x00ff) == DC2114x) {
5240 outl((data<<16) | lp->cache.csr15, DE4X5_SIGR);
5241 }
5242
5243 return;
5244}
5245
5246static int
5247gep_rd(struct net_device *dev)
5248{
5249 struct de4x5_private *lp = netdev_priv(dev);
5250 u_long iobase = dev->base_addr;
5251
5252 if (lp->chipset == DC21140) {
5253 return inl(DE4X5_GEP);
5254 } else if ((lp->chipset & ~0x00ff) == DC2114x) {
5255 return (inl(DE4X5_SIGR) & 0x000fffff);
5256 }
5257
5258 return 0;
5259}
5260
5261static void
5262timeout(struct net_device *dev, void (*fn)(u_long data), u_long data, u_long msec)
5263{
5264 struct de4x5_private *lp = netdev_priv(dev);
5265 int dt;
5266
5267 /* First, cancel any pending timer events */
5268 del_timer(&lp->timer);
5269
5270 /* Convert msec to ticks */
5271 dt = (msec * HZ) / 1000;
5272 if (dt==0) dt=1;
5273
5274 /* Set up timer */
5275 init_timer(&lp->timer);
5276 lp->timer.expires = jiffies + dt;
5277 lp->timer.function = fn;
5278 lp->timer.data = data;
5279 add_timer(&lp->timer);
5280
5281 return;
5282}
5283
5284static void
5285yawn(struct net_device *dev, int state)
5286{
5287 struct de4x5_private *lp = netdev_priv(dev);
5288 u_long iobase = dev->base_addr;
5289
5290 if ((lp->chipset == DC21040) || (lp->chipset == DC21140)) return;
5291
5292 if(lp->bus == EISA) {
5293 switch(state) {
5294 case WAKEUP:
5295 outb(WAKEUP, PCI_CFPM);
5296 mdelay(10);
5297 break;
5298
5299 case SNOOZE:
5300 outb(SNOOZE, PCI_CFPM);
5301 break;
5302
5303 case SLEEP:
5304 outl(0, DE4X5_SICR);
5305 outb(SLEEP, PCI_CFPM);
5306 break;
5307 }
5308 } else {
5309 struct pci_dev *pdev = to_pci_dev (lp->gendev);
5310 switch(state) {
5311 case WAKEUP:
5312 pci_write_config_byte(pdev, PCI_CFDA_PSM, WAKEUP);
5313 mdelay(10);
5314 break;
5315
5316 case SNOOZE:
5317 pci_write_config_byte(pdev, PCI_CFDA_PSM, SNOOZE);
5318 break;
5319
5320 case SLEEP:
5321 outl(0, DE4X5_SICR);
5322 pci_write_config_byte(pdev, PCI_CFDA_PSM, SLEEP);
5323 break;
5324 }
5325 }
5326
5327 return;
5328}
5329
5330static void
5331de4x5_parse_params(struct net_device *dev)
5332{
5333 struct de4x5_private *lp = netdev_priv(dev);
5334 char *p, *q, t;
5335
5336 lp->params.fdx = 0;
5337 lp->params.autosense = AUTO;
5338
5339 if (args == NULL) return;
5340
5341 if ((p = strstr(args, dev->name))) {
5342 if (!(q = strstr(p+strlen(dev->name), "eth"))) q = p + strlen(p);
5343 t = *q;
5344 *q = '\0';
5345
5346 if (strstr(p, "fdx") || strstr(p, "FDX")) lp->params.fdx = 1;
5347
5348 if (strstr(p, "autosense") || strstr(p, "AUTOSENSE")) {
5349 if (strstr(p, "TP")) {
5350 lp->params.autosense = TP;
5351 } else if (strstr(p, "TP_NW")) {
5352 lp->params.autosense = TP_NW;
5353 } else if (strstr(p, "BNC")) {
5354 lp->params.autosense = BNC;
5355 } else if (strstr(p, "AUI")) {
5356 lp->params.autosense = AUI;
5357 } else if (strstr(p, "BNC_AUI")) {
5358 lp->params.autosense = BNC;
5359 } else if (strstr(p, "10Mb")) {
5360 lp->params.autosense = _10Mb;
5361 } else if (strstr(p, "100Mb")) {
5362 lp->params.autosense = _100Mb;
5363 } else if (strstr(p, "AUTO")) {
5364 lp->params.autosense = AUTO;
5365 }
5366 }
5367 *q = t;
5368 }
5369
5370 return;
5371}
5372
5373static void
5374de4x5_dbg_open(struct net_device *dev)
5375{
5376 struct de4x5_private *lp = netdev_priv(dev);
5377 int i;
5378
5379 if (de4x5_debug & DEBUG_OPEN) {
5380 printk("%s: de4x5 opening with irq %d\n",dev->name,dev->irq);
5381 printk("\tphysical address: ");
5382 for (i=0;i<6;i++) {
5383 printk("%2.2x:",(short)dev->dev_addr[i]);
5384 }
5385 printk("\n");
5386 printk("Descriptor head addresses:\n");
5387 printk("\t0x%8.8lx 0x%8.8lx\n",(u_long)lp->rx_ring,(u_long)lp->tx_ring);
5388 printk("Descriptor addresses:\nRX: ");
5389 for (i=0;i<lp->rxRingSize-1;i++){
5390 if (i < 3) {
5391 printk("0x%8.8lx ",(u_long)&lp->rx_ring[i].status);
5392 }
5393 }
5394 printk("...0x%8.8lx\n",(u_long)&lp->rx_ring[i].status);
5395 printk("TX: ");
5396 for (i=0;i<lp->txRingSize-1;i++){
5397 if (i < 3) {
5398 printk("0x%8.8lx ", (u_long)&lp->tx_ring[i].status);
5399 }
5400 }
5401 printk("...0x%8.8lx\n", (u_long)&lp->tx_ring[i].status);
5402 printk("Descriptor buffers:\nRX: ");
5403 for (i=0;i<lp->rxRingSize-1;i++){
5404 if (i < 3) {
5405 printk("0x%8.8x ",le32_to_cpu(lp->rx_ring[i].buf));
5406 }
5407 }
5408 printk("...0x%8.8x\n",le32_to_cpu(lp->rx_ring[i].buf));
5409 printk("TX: ");
5410 for (i=0;i<lp->txRingSize-1;i++){
5411 if (i < 3) {
5412 printk("0x%8.8x ", le32_to_cpu(lp->tx_ring[i].buf));
5413 }
5414 }
5415 printk("...0x%8.8x\n", le32_to_cpu(lp->tx_ring[i].buf));
5416 printk("Ring size: \nRX: %d\nTX: %d\n",
5417 (short)lp->rxRingSize,
5418 (short)lp->txRingSize);
5419 }
5420
5421 return;
5422}
5423
5424static void
5425de4x5_dbg_mii(struct net_device *dev, int k)
5426{
5427 struct de4x5_private *lp = netdev_priv(dev);
5428 u_long iobase = dev->base_addr;
5429
5430 if (de4x5_debug & DEBUG_MII) {
5431 printk("\nMII device address: %d\n", lp->phy[k].addr);
5432 printk("MII CR: %x\n",mii_rd(MII_CR,lp->phy[k].addr,DE4X5_MII));
5433 printk("MII SR: %x\n",mii_rd(MII_SR,lp->phy[k].addr,DE4X5_MII));
5434 printk("MII ID0: %x\n",mii_rd(MII_ID0,lp->phy[k].addr,DE4X5_MII));
5435 printk("MII ID1: %x\n",mii_rd(MII_ID1,lp->phy[k].addr,DE4X5_MII));
5436 if (lp->phy[k].id != BROADCOM_T4) {
5437 printk("MII ANA: %x\n",mii_rd(0x04,lp->phy[k].addr,DE4X5_MII));
5438 printk("MII ANC: %x\n",mii_rd(0x05,lp->phy[k].addr,DE4X5_MII));
5439 }
5440 printk("MII 16: %x\n",mii_rd(0x10,lp->phy[k].addr,DE4X5_MII));
5441 if (lp->phy[k].id != BROADCOM_T4) {
5442 printk("MII 17: %x\n",mii_rd(0x11,lp->phy[k].addr,DE4X5_MII));
5443 printk("MII 18: %x\n",mii_rd(0x12,lp->phy[k].addr,DE4X5_MII));
5444 } else {
5445 printk("MII 20: %x\n",mii_rd(0x14,lp->phy[k].addr,DE4X5_MII));
5446 }
5447 }
5448
5449 return;
5450}
5451
5452static void
5453de4x5_dbg_media(struct net_device *dev)
5454{
5455 struct de4x5_private *lp = netdev_priv(dev);
5456
5457 if (lp->media != lp->c_media) {
5458 if (de4x5_debug & DEBUG_MEDIA) {
5459 printk("%s: media is %s%s\n", dev->name,
5460 (lp->media == NC ? "unconnected, link down or incompatible connection" :
5461 (lp->media == TP ? "TP" :
5462 (lp->media == ANS ? "TP/Nway" :
5463 (lp->media == BNC ? "BNC" :
5464 (lp->media == AUI ? "AUI" :
5465 (lp->media == BNC_AUI ? "BNC/AUI" :
5466 (lp->media == EXT_SIA ? "EXT SIA" :
5467 (lp->media == _100Mb ? "100Mb/s" :
5468 (lp->media == _10Mb ? "10Mb/s" :
5469 "???"
5470 ))))))))), (lp->fdx?" full duplex.":"."));
5471 }
5472 lp->c_media = lp->media;
5473 }
5474
5475 return;
5476}
5477
5478static void
5479de4x5_dbg_srom(struct de4x5_srom *p)
5480{
5481 int i;
5482
5483 if (de4x5_debug & DEBUG_SROM) {
5484 printk("Sub-system Vendor ID: %04x\n", *((u_short *)p->sub_vendor_id));
5485 printk("Sub-system ID: %04x\n", *((u_short *)p->sub_system_id));
5486 printk("ID Block CRC: %02x\n", (u_char)(p->id_block_crc));
5487 printk("SROM version: %02x\n", (u_char)(p->version));
5488 printk("# controllers: %02x\n", (u_char)(p->num_controllers));
5489
5490 printk("Hardware Address: ");
5491 for (i=0;i<ETH_ALEN-1;i++) {
5492 printk("%02x:", (u_char)*(p->ieee_addr+i));
5493 }
5494 printk("%02x\n", (u_char)*(p->ieee_addr+i));
5495 printk("CRC checksum: %04x\n", (u_short)(p->chksum));
5496 for (i=0; i<64; i++) {
5497 printk("%3d %04x\n", i<<1, (u_short)*((u_short *)p+i));
5498 }
5499 }
5500
5501 return;
5502}
5503
5504static void
5505de4x5_dbg_rx(struct sk_buff *skb, int len)
5506{
5507 int i, j;
5508
5509 if (de4x5_debug & DEBUG_RX) {
5510 printk("R: %02x:%02x:%02x:%02x:%02x:%02x <- %02x:%02x:%02x:%02x:%02x:%02x len/SAP:%02x%02x [%d]\n",
5511 (u_char)skb->data[0],
5512 (u_char)skb->data[1],
5513 (u_char)skb->data[2],
5514 (u_char)skb->data[3],
5515 (u_char)skb->data[4],
5516 (u_char)skb->data[5],
5517 (u_char)skb->data[6],
5518 (u_char)skb->data[7],
5519 (u_char)skb->data[8],
5520 (u_char)skb->data[9],
5521 (u_char)skb->data[10],
5522 (u_char)skb->data[11],
5523 (u_char)skb->data[12],
5524 (u_char)skb->data[13],
5525 len);
5526 for (j=0; len>0;j+=16, len-=16) {
5527 printk(" %03x: ",j);
5528 for (i=0; i<16 && i<len; i++) {
5529 printk("%02x ",(u_char)skb->data[i+j]);
5530 }
5531 printk("\n");
5532 }
5533 }
5534
5535 return;
5536}
5537
5538/*
5539** Perform IOCTL call functions here. Some are privileged operations and the
5540** effective uid is checked in those cases. In the normal course of events
5541** this function is only used for my testing.
5542*/
5543static int
5544de4x5_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
5545{
5546 struct de4x5_private *lp = netdev_priv(dev);
5547 struct de4x5_ioctl *ioc = (struct de4x5_ioctl *) &rq->ifr_ifru;
5548 u_long iobase = dev->base_addr;
5549 int i, j, status = 0;
5550 s32 omr;
5551 union {
5552 u8 addr[144];
5553 u16 sval[72];
5554 u32 lval[36];
5555 } tmp;
5556 u_long flags = 0;
5557
5558 switch(ioc->cmd) {
5559 case DE4X5_GET_HWADDR: /* Get the hardware address */
5560 ioc->len = ETH_ALEN;
5561 for (i=0; i<ETH_ALEN; i++) {
5562 tmp.addr[i] = dev->dev_addr[i];
5563 }
5564 if (copy_to_user(ioc->data, tmp.addr, ioc->len)) return -EFAULT;
5565 break;
5566
5567 case DE4X5_SET_HWADDR: /* Set the hardware address */
5568 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5569 if (copy_from_user(tmp.addr, ioc->data, ETH_ALEN)) return -EFAULT;
5570 if (netif_queue_stopped(dev))
5571 return -EBUSY;
5572 netif_stop_queue(dev);
5573 for (i=0; i<ETH_ALEN; i++) {
5574 dev->dev_addr[i] = tmp.addr[i];
5575 }
5576 build_setup_frame(dev, PHYS_ADDR_ONLY);
5577 /* Set up the descriptor and give ownership to the card */
5578 load_packet(dev, lp->setup_frame, TD_IC | PERFECT_F | TD_SET |
5579 SETUP_FRAME_LEN, (struct sk_buff *)1);
5580 lp->tx_new = (++lp->tx_new) % lp->txRingSize;
5581 outl(POLL_DEMAND, DE4X5_TPD); /* Start the TX */
5582 netif_wake_queue(dev); /* Unlock the TX ring */
5583 break;
5584
5585 case DE4X5_SET_PROM: /* Set Promiscuous Mode */
5586 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5587 omr = inl(DE4X5_OMR);
5588 omr |= OMR_PR;
5589 outl(omr, DE4X5_OMR);
5590 dev->flags |= IFF_PROMISC;
5591 break;
5592
5593 case DE4X5_CLR_PROM: /* Clear Promiscuous Mode */
5594 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5595 omr = inl(DE4X5_OMR);
5596 omr &= ~OMR_PR;
5597 outl(omr, DE4X5_OMR);
5598 dev->flags &= ~IFF_PROMISC;
5599 break;
5600
5601 case DE4X5_SAY_BOO: /* Say "Boo!" to the kernel log file */
5602 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5603 printk("%s: Boo!\n", dev->name);
5604 break;
5605
5606 case DE4X5_MCA_EN: /* Enable pass all multicast addressing */
5607 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5608 omr = inl(DE4X5_OMR);
5609 omr |= OMR_PM;
5610 outl(omr, DE4X5_OMR);
5611 break;
5612
5613 case DE4X5_GET_STATS: /* Get the driver statistics */
5614 {
5615 struct pkt_stats statbuf;
5616 ioc->len = sizeof(statbuf);
5617 spin_lock_irqsave(&lp->lock, flags);
5618 memcpy(&statbuf, &lp->pktStats, ioc->len);
5619 spin_unlock_irqrestore(&lp->lock, flags);
5620 if (copy_to_user(ioc->data, &statbuf, ioc->len))
5621 return -EFAULT;
5622 break;
5623 }
5624 case DE4X5_CLR_STATS: /* Zero out the driver statistics */
5625 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5626 spin_lock_irqsave(&lp->lock, flags);
5627 memset(&lp->pktStats, 0, sizeof(lp->pktStats));
5628 spin_unlock_irqrestore(&lp->lock, flags);
5629 break;
5630
5631 case DE4X5_GET_OMR: /* Get the OMR Register contents */
5632 tmp.addr[0] = inl(DE4X5_OMR);
5633 if (copy_to_user(ioc->data, tmp.addr, 1)) return -EFAULT;
5634 break;
5635
5636 case DE4X5_SET_OMR: /* Set the OMR Register contents */
5637 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5638 if (copy_from_user(tmp.addr, ioc->data, 1)) return -EFAULT;
5639 outl(tmp.addr[0], DE4X5_OMR);
5640 break;
5641
5642 case DE4X5_GET_REG: /* Get the DE4X5 Registers */
5643 j = 0;
5644 tmp.lval[0] = inl(DE4X5_STS); j+=4;
5645 tmp.lval[1] = inl(DE4X5_BMR); j+=4;
5646 tmp.lval[2] = inl(DE4X5_IMR); j+=4;
5647 tmp.lval[3] = inl(DE4X5_OMR); j+=4;
5648 tmp.lval[4] = inl(DE4X5_SISR); j+=4;
5649 tmp.lval[5] = inl(DE4X5_SICR); j+=4;
5650 tmp.lval[6] = inl(DE4X5_STRR); j+=4;
5651 tmp.lval[7] = inl(DE4X5_SIGR); j+=4;
5652 ioc->len = j;
5653 if (copy_to_user(ioc->data, tmp.addr, ioc->len)) return -EFAULT;
5654 break;
5655
5656#define DE4X5_DUMP 0x0f /* Dump the DE4X5 Status */
5657/*
5658 case DE4X5_DUMP:
5659 j = 0;
5660 tmp.addr[j++] = dev->irq;
5661 for (i=0; i<ETH_ALEN; i++) {
5662 tmp.addr[j++] = dev->dev_addr[i];
5663 }
5664 tmp.addr[j++] = lp->rxRingSize;
5665 tmp.lval[j>>2] = (long)lp->rx_ring; j+=4;
5666 tmp.lval[j>>2] = (long)lp->tx_ring; j+=4;
5667
5668 for (i=0;i<lp->rxRingSize-1;i++){
5669 if (i < 3) {
5670 tmp.lval[j>>2] = (long)&lp->rx_ring[i].status; j+=4;
5671 }
5672 }
5673 tmp.lval[j>>2] = (long)&lp->rx_ring[i].status; j+=4;
5674 for (i=0;i<lp->txRingSize-1;i++){
5675 if (i < 3) {
5676 tmp.lval[j>>2] = (long)&lp->tx_ring[i].status; j+=4;
5677 }
5678 }
5679 tmp.lval[j>>2] = (long)&lp->tx_ring[i].status; j+=4;
5680
5681 for (i=0;i<lp->rxRingSize-1;i++){
5682 if (i < 3) {
5683 tmp.lval[j>>2] = (s32)le32_to_cpu(lp->rx_ring[i].buf); j+=4;
5684 }
5685 }
5686 tmp.lval[j>>2] = (s32)le32_to_cpu(lp->rx_ring[i].buf); j+=4;
5687 for (i=0;i<lp->txRingSize-1;i++){
5688 if (i < 3) {
5689 tmp.lval[j>>2] = (s32)le32_to_cpu(lp->tx_ring[i].buf); j+=4;
5690 }
5691 }
5692 tmp.lval[j>>2] = (s32)le32_to_cpu(lp->tx_ring[i].buf); j+=4;
5693
5694 for (i=0;i<lp->rxRingSize;i++){
5695 tmp.lval[j>>2] = le32_to_cpu(lp->rx_ring[i].status); j+=4;
5696 }
5697 for (i=0;i<lp->txRingSize;i++){
5698 tmp.lval[j>>2] = le32_to_cpu(lp->tx_ring[i].status); j+=4;
5699 }
5700
5701 tmp.lval[j>>2] = inl(DE4X5_BMR); j+=4;
5702 tmp.lval[j>>2] = inl(DE4X5_TPD); j+=4;
5703 tmp.lval[j>>2] = inl(DE4X5_RPD); j+=4;
5704 tmp.lval[j>>2] = inl(DE4X5_RRBA); j+=4;
5705 tmp.lval[j>>2] = inl(DE4X5_TRBA); j+=4;
5706 tmp.lval[j>>2] = inl(DE4X5_STS); j+=4;
5707 tmp.lval[j>>2] = inl(DE4X5_OMR); j+=4;
5708 tmp.lval[j>>2] = inl(DE4X5_IMR); j+=4;
5709 tmp.lval[j>>2] = lp->chipset; j+=4;
5710 if (lp->chipset == DC21140) {
5711 tmp.lval[j>>2] = gep_rd(dev); j+=4;
5712 } else {
5713 tmp.lval[j>>2] = inl(DE4X5_SISR); j+=4;
5714 tmp.lval[j>>2] = inl(DE4X5_SICR); j+=4;
5715 tmp.lval[j>>2] = inl(DE4X5_STRR); j+=4;
5716 tmp.lval[j>>2] = inl(DE4X5_SIGR); j+=4;
5717 }
5718 tmp.lval[j>>2] = lp->phy[lp->active].id; j+=4;
5719 if (lp->phy[lp->active].id && (!lp->useSROM || lp->useMII)) {
5720 tmp.lval[j>>2] = lp->active; j+=4;
5721 tmp.lval[j>>2]=mii_rd(MII_CR,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5722 tmp.lval[j>>2]=mii_rd(MII_SR,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5723 tmp.lval[j>>2]=mii_rd(MII_ID0,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5724 tmp.lval[j>>2]=mii_rd(MII_ID1,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5725 if (lp->phy[lp->active].id != BROADCOM_T4) {
5726 tmp.lval[j>>2]=mii_rd(MII_ANA,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5727 tmp.lval[j>>2]=mii_rd(MII_ANLPA,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5728 }
5729 tmp.lval[j>>2]=mii_rd(0x10,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5730 if (lp->phy[lp->active].id != BROADCOM_T4) {
5731 tmp.lval[j>>2]=mii_rd(0x11,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5732 tmp.lval[j>>2]=mii_rd(0x12,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5733 } else {
5734 tmp.lval[j>>2]=mii_rd(0x14,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5735 }
5736 }
5737
5738 tmp.addr[j++] = lp->txRingSize;
5739 tmp.addr[j++] = netif_queue_stopped(dev);
5740
5741 ioc->len = j;
5742 if (copy_to_user(ioc->data, tmp.addr, ioc->len)) return -EFAULT;
5743 break;
5744
5745*/
5746 default:
5747 return -EOPNOTSUPP;
5748 }
5749
5750 return status;
5751}
5752
5753static int __init de4x5_module_init (void)
5754{
5755 int err = 0;
5756
5757#ifdef CONFIG_PCI
5758 err = pci_module_init (&de4x5_pci_driver);
5759#endif
5760#ifdef CONFIG_EISA
5761 err |= eisa_driver_register (&de4x5_eisa_driver);
5762#endif
5763
5764 return err;
5765}
5766
5767static void __exit de4x5_module_exit (void)
5768{
5769#ifdef CONFIG_PCI
5770 pci_unregister_driver (&de4x5_pci_driver);
5771#endif
5772#ifdef CONFIG_EISA
5773 eisa_driver_unregister (&de4x5_eisa_driver);
5774#endif
5775}
5776
5777module_init (de4x5_module_init);
5778module_exit (de4x5_module_exit);