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David Brownella30d46c2008-10-20 23:46:28 +02001/*
2 * twl4030-irq.c - TWL4030/TPS659x0 irq support
3 *
4 * Copyright (C) 2005-2006 Texas Instruments, Inc.
5 *
6 * Modifications to defer interrupt handling to a kernel thread:
7 * Copyright (C) 2006 MontaVista Software, Inc.
8 *
9 * Based on tlv320aic23.c:
10 * Copyright (c) by Kai Svahn <kai.svahn@nokia.com>
11 *
12 * Code cleanup and modifications to IRQ handler.
13 * by syed khasim <x0khasim@ti.com>
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
28 */
29
30#include <linux/init.h>
Benoit Cousson78518ff2012-02-29 19:40:31 +010031#include <linux/export.h>
David Brownella30d46c2008-10-20 23:46:28 +020032#include <linux/interrupt.h>
33#include <linux/irq.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090034#include <linux/slab.h>
Benoit Cousson78518ff2012-02-29 19:40:31 +010035#include <linux/of.h>
36#include <linux/irqdomain.h>
Santosh Shilimkarb07682b2009-12-13 20:05:51 +010037#include <linux/i2c/twl.h>
David Brownella30d46c2008-10-20 23:46:28 +020038
G, Manjunath Kondaiahb0b4a7c2010-10-19 11:02:48 +020039#include "twl-core.h"
David Brownella30d46c2008-10-20 23:46:28 +020040
41/*
42 * TWL4030 IRQ handling has two stages in hardware, and thus in software.
43 * The Primary Interrupt Handler (PIH) stage exposes status bits saying
44 * which Secondary Interrupt Handler (SIH) stage is raising an interrupt.
45 * SIH modules are more traditional IRQ components, which support per-IRQ
46 * enable/disable and trigger controls; they do most of the work.
47 *
48 * These chips are designed to support IRQ handling from two different
49 * I2C masters. Each has a dedicated IRQ line, and dedicated IRQ status
50 * and mask registers in the PIH and SIH modules.
51 *
52 * We set up IRQs starting at a platform-specified base, always starting
53 * with PIH and the SIH for PWR_INT and then usually adding GPIO:
54 * base + 0 .. base + 7 PIH
55 * base + 8 .. base + 15 SIH for PWR_INT
56 * base + 16 .. base + 33 SIH for GPIO
57 */
Benoit Cousson78518ff2012-02-29 19:40:31 +010058#define TWL4030_CORE_NR_IRQS 8
59#define TWL4030_PWR_NR_IRQS 8
David Brownella30d46c2008-10-20 23:46:28 +020060
61/* PIH register offsets */
62#define REG_PIH_ISR_P1 0x01
63#define REG_PIH_ISR_P2 0x02
64#define REG_PIH_SIR 0x03 /* for testing */
65
David Brownella30d46c2008-10-20 23:46:28 +020066/* Linux could (eventually) use either IRQ line */
67static int irq_line;
68
69struct sih {
70 char name[8];
71 u8 module; /* module id */
72 u8 control_offset; /* for SIH_CTRL */
73 bool set_cor;
74
75 u8 bits; /* valid in isr/imr */
76 u8 bytes_ixr; /* bytelen of ISR/IMR/SIR */
77
78 u8 edr_offset;
79 u8 bytes_edr; /* bytelen of EDR */
80
Ilkka Koskinen1920a612009-11-10 17:26:15 +020081 u8 irq_lines; /* number of supported irq lines */
82
David Brownella30d46c2008-10-20 23:46:28 +020083 /* SIR ignored -- set interrupt, for testing only */
Thomas Gleixner35a27e82010-10-01 16:35:59 +020084 struct sih_irq_data {
David Brownella30d46c2008-10-20 23:46:28 +020085 u8 isr_offset;
86 u8 imr_offset;
87 } mask[2];
88 /* + 2 bytes padding */
89};
90
Ilkka Koskinen1920a612009-11-10 17:26:15 +020091static const struct sih *sih_modules;
92static int nr_sih_modules;
93
David Brownella30d46c2008-10-20 23:46:28 +020094#define SIH_INITIALIZER(modname, nbits) \
95 .module = TWL4030_MODULE_ ## modname, \
96 .control_offset = TWL4030_ ## modname ## _SIH_CTRL, \
97 .bits = nbits, \
98 .bytes_ixr = DIV_ROUND_UP(nbits, 8), \
99 .edr_offset = TWL4030_ ## modname ## _EDR, \
100 .bytes_edr = DIV_ROUND_UP((2*(nbits)), 8), \
Ilkka Koskinen1920a612009-11-10 17:26:15 +0200101 .irq_lines = 2, \
David Brownella30d46c2008-10-20 23:46:28 +0200102 .mask = { { \
103 .isr_offset = TWL4030_ ## modname ## _ISR1, \
104 .imr_offset = TWL4030_ ## modname ## _IMR1, \
105 }, \
106 { \
107 .isr_offset = TWL4030_ ## modname ## _ISR2, \
108 .imr_offset = TWL4030_ ## modname ## _IMR2, \
109 }, },
110
111/* register naming policies are inconsistent ... */
112#define TWL4030_INT_PWR_EDR TWL4030_INT_PWR_EDR1
113#define TWL4030_MODULE_KEYPAD_KEYP TWL4030_MODULE_KEYPAD
114#define TWL4030_MODULE_INT_PWR TWL4030_MODULE_INT
115
116
Felipe Contrerascbcde052012-02-01 03:02:48 +0200117/*
118 * Order in this table matches order in PIH_ISR. That is,
David Brownella30d46c2008-10-20 23:46:28 +0200119 * BIT(n) in PIH_ISR is sih_modules[n].
120 */
Ilkka Koskinen1920a612009-11-10 17:26:15 +0200121/* sih_modules_twl4030 is used both in twl4030 and twl5030 */
122static const struct sih sih_modules_twl4030[6] = {
David Brownella30d46c2008-10-20 23:46:28 +0200123 [0] = {
124 .name = "gpio",
125 .module = TWL4030_MODULE_GPIO,
126 .control_offset = REG_GPIO_SIH_CTRL,
127 .set_cor = true,
128 .bits = TWL4030_GPIO_MAX,
129 .bytes_ixr = 3,
130 /* Note: *all* of these IRQs default to no-trigger */
131 .edr_offset = REG_GPIO_EDR1,
132 .bytes_edr = 5,
Ilkka Koskinen1920a612009-11-10 17:26:15 +0200133 .irq_lines = 2,
David Brownella30d46c2008-10-20 23:46:28 +0200134 .mask = { {
135 .isr_offset = REG_GPIO_ISR1A,
136 .imr_offset = REG_GPIO_IMR1A,
137 }, {
138 .isr_offset = REG_GPIO_ISR1B,
139 .imr_offset = REG_GPIO_IMR1B,
140 }, },
141 },
142 [1] = {
143 .name = "keypad",
144 .set_cor = true,
145 SIH_INITIALIZER(KEYPAD_KEYP, 4)
146 },
147 [2] = {
148 .name = "bci",
149 .module = TWL4030_MODULE_INTERRUPTS,
150 .control_offset = TWL4030_INTERRUPTS_BCISIHCTRL,
Grazvydas Ignotas8e52e272010-09-28 16:22:19 +0300151 .set_cor = true,
David Brownella30d46c2008-10-20 23:46:28 +0200152 .bits = 12,
153 .bytes_ixr = 2,
154 .edr_offset = TWL4030_INTERRUPTS_BCIEDR1,
155 /* Note: most of these IRQs default to no-trigger */
156 .bytes_edr = 3,
Ilkka Koskinen1920a612009-11-10 17:26:15 +0200157 .irq_lines = 2,
David Brownella30d46c2008-10-20 23:46:28 +0200158 .mask = { {
159 .isr_offset = TWL4030_INTERRUPTS_BCIISR1A,
160 .imr_offset = TWL4030_INTERRUPTS_BCIIMR1A,
161 }, {
162 .isr_offset = TWL4030_INTERRUPTS_BCIISR1B,
163 .imr_offset = TWL4030_INTERRUPTS_BCIIMR1B,
164 }, },
165 },
166 [3] = {
167 .name = "madc",
168 SIH_INITIALIZER(MADC, 4)
169 },
170 [4] = {
171 /* USB doesn't use the same SIH organization */
172 .name = "usb",
173 },
174 [5] = {
175 .name = "power",
176 .set_cor = true,
177 SIH_INITIALIZER(INT_PWR, 8)
178 },
179 /* there are no SIH modules #6 or #7 ... */
180};
181
Ilkka Koskinen1920a612009-11-10 17:26:15 +0200182static const struct sih sih_modules_twl5031[8] = {
183 [0] = {
184 .name = "gpio",
185 .module = TWL4030_MODULE_GPIO,
186 .control_offset = REG_GPIO_SIH_CTRL,
187 .set_cor = true,
188 .bits = TWL4030_GPIO_MAX,
189 .bytes_ixr = 3,
190 /* Note: *all* of these IRQs default to no-trigger */
191 .edr_offset = REG_GPIO_EDR1,
192 .bytes_edr = 5,
193 .irq_lines = 2,
194 .mask = { {
195 .isr_offset = REG_GPIO_ISR1A,
196 .imr_offset = REG_GPIO_IMR1A,
197 }, {
198 .isr_offset = REG_GPIO_ISR1B,
199 .imr_offset = REG_GPIO_IMR1B,
200 }, },
201 },
202 [1] = {
203 .name = "keypad",
204 .set_cor = true,
205 SIH_INITIALIZER(KEYPAD_KEYP, 4)
206 },
207 [2] = {
208 .name = "bci",
209 .module = TWL5031_MODULE_INTERRUPTS,
210 .control_offset = TWL5031_INTERRUPTS_BCISIHCTRL,
211 .bits = 7,
212 .bytes_ixr = 1,
213 .edr_offset = TWL5031_INTERRUPTS_BCIEDR1,
214 /* Note: most of these IRQs default to no-trigger */
215 .bytes_edr = 2,
216 .irq_lines = 2,
217 .mask = { {
218 .isr_offset = TWL5031_INTERRUPTS_BCIISR1,
219 .imr_offset = TWL5031_INTERRUPTS_BCIIMR1,
220 }, {
221 .isr_offset = TWL5031_INTERRUPTS_BCIISR2,
222 .imr_offset = TWL5031_INTERRUPTS_BCIIMR2,
223 }, },
224 },
225 [3] = {
226 .name = "madc",
227 SIH_INITIALIZER(MADC, 4)
228 },
229 [4] = {
230 /* USB doesn't use the same SIH organization */
231 .name = "usb",
232 },
233 [5] = {
234 .name = "power",
235 .set_cor = true,
236 SIH_INITIALIZER(INT_PWR, 8)
237 },
238 [6] = {
239 /*
Ilkka Koskinen191211f2010-05-20 13:04:20 +0300240 * ECI/DBI doesn't use the same SIH organization.
241 * For example, it supports only one interrupt output line.
242 * That is, the interrupts are seen on both INT1 and INT2 lines.
Ilkka Koskinen1920a612009-11-10 17:26:15 +0200243 */
Ilkka Koskinen191211f2010-05-20 13:04:20 +0300244 .name = "eci_dbi",
Ilkka Koskinen1920a612009-11-10 17:26:15 +0200245 .module = TWL5031_MODULE_ACCESSORY,
246 .bits = 9,
247 .bytes_ixr = 2,
248 .irq_lines = 1,
249 .mask = { {
250 .isr_offset = TWL5031_ACIIDR_LSB,
251 .imr_offset = TWL5031_ACIIMR_LSB,
252 }, },
253
254 },
255 [7] = {
Ilkka Koskinen191211f2010-05-20 13:04:20 +0300256 /* Audio accessory */
257 .name = "audio",
Ilkka Koskinen1920a612009-11-10 17:26:15 +0200258 .module = TWL5031_MODULE_ACCESSORY,
259 .control_offset = TWL5031_ACCSIHCTRL,
260 .bits = 2,
261 .bytes_ixr = 1,
262 .edr_offset = TWL5031_ACCEDR1,
263 /* Note: most of these IRQs default to no-trigger */
264 .bytes_edr = 1,
265 .irq_lines = 2,
266 .mask = { {
267 .isr_offset = TWL5031_ACCISR1,
268 .imr_offset = TWL5031_ACCIMR1,
269 }, {
270 .isr_offset = TWL5031_ACCISR2,
271 .imr_offset = TWL5031_ACCIMR2,
272 }, },
273 },
274};
275
David Brownella30d46c2008-10-20 23:46:28 +0200276#undef TWL4030_MODULE_KEYPAD_KEYP
277#undef TWL4030_MODULE_INT_PWR
278#undef TWL4030_INT_PWR_EDR
279
280/*----------------------------------------------------------------------*/
281
282static unsigned twl4030_irq_base;
283
David Brownella30d46c2008-10-20 23:46:28 +0200284/*
285 * handle_twl4030_pih() is the desc->handle method for the twl4030 interrupt.
286 * This is a chained interrupt, so there is no desc->action method for it.
287 * Now we need to query the interrupt controller in the twl4030 to determine
288 * which module is generating the interrupt request. However, we can't do i2c
289 * transactions in interrupt context, so we must defer that work to a kernel
290 * thread. All we do here is acknowledge and mask the interrupt and wakeup
291 * the kernel thread.
292 */
Russell King1cef8e42009-07-27 11:30:48 +0530293static irqreturn_t handle_twl4030_pih(int irq, void *devid)
David Brownella30d46c2008-10-20 23:46:28 +0200294{
Felipe Balbi7750c9b2011-06-30 12:51:06 +0300295 irqreturn_t ret;
296 u8 pih_isr;
297
298 ret = twl_i2c_read_u8(TWL4030_MODULE_PIH, &pih_isr,
299 REG_PIH_ISR_P1);
300 if (ret) {
301 pr_warning("twl4030: I2C error %d reading PIH ISR\n", ret);
302 return IRQ_NONE;
303 }
304
Felipe Balbi5a903092012-02-22 14:53:59 +0200305 while (pih_isr) {
306 unsigned long pending = __ffs(pih_isr);
307 unsigned int irq;
308
309 pih_isr &= ~BIT(pending);
310 irq = pending + twl4030_irq_base;
311 handle_nested_irq(irq);
Felipe Balbi7750c9b2011-06-30 12:51:06 +0300312 }
313
Russell King1cef8e42009-07-27 11:30:48 +0530314 return IRQ_HANDLED;
David Brownella30d46c2008-10-20 23:46:28 +0200315}
Felipe Contrerascbcde052012-02-01 03:02:48 +0200316
David Brownella30d46c2008-10-20 23:46:28 +0200317/*----------------------------------------------------------------------*/
318
319/*
320 * twl4030_init_sih_modules() ... start from a known state where no
321 * IRQs will be coming in, and where we can quickly enable them then
322 * handle them as they arrive. Mask all IRQs: maybe init SIH_CTRL.
323 *
324 * NOTE: we don't touch EDR registers here; they stay with hardware
325 * defaults or whatever the last value was. Note that when both EDR
326 * bits for an IRQ are clear, that's as if its IMR bit is set...
327 */
328static int twl4030_init_sih_modules(unsigned line)
329{
330 const struct sih *sih;
331 u8 buf[4];
332 int i;
333 int status;
334
335 /* line 0 == int1_n signal; line 1 == int2_n signal */
336 if (line > 1)
337 return -EINVAL;
338
339 irq_line = line;
340
341 /* disable all interrupts on our line */
342 memset(buf, 0xff, sizeof buf);
343 sih = sih_modules;
Ilkka Koskinen1920a612009-11-10 17:26:15 +0200344 for (i = 0; i < nr_sih_modules; i++, sih++) {
David Brownella30d46c2008-10-20 23:46:28 +0200345 /* skip USB -- it's funky */
346 if (!sih->bytes_ixr)
347 continue;
348
Ilkka Koskinen1920a612009-11-10 17:26:15 +0200349 /* Not all the SIH modules support multiple interrupt lines */
350 if (sih->irq_lines <= line)
351 continue;
352
Balaji T Kfc7b92f2009-12-13 21:23:33 +0100353 status = twl_i2c_write(sih->module, buf,
David Brownella30d46c2008-10-20 23:46:28 +0200354 sih->mask[line].imr_offset, sih->bytes_ixr);
355 if (status < 0)
356 pr_err("twl4030: err %d initializing %s %s\n",
357 status, sih->name, "IMR");
358
Felipe Contrerascbcde052012-02-01 03:02:48 +0200359 /*
360 * Maybe disable "exclusive" mode; buffer second pending irq;
David Brownella30d46c2008-10-20 23:46:28 +0200361 * set Clear-On-Read (COR) bit.
362 *
363 * NOTE that sometimes COR polarity is documented as being
Grazvydas Ignotas8e52e272010-09-28 16:22:19 +0300364 * inverted: for MADC, COR=1 means "clear on write".
David Brownella30d46c2008-10-20 23:46:28 +0200365 * And for PWR_INT it's not documented...
366 */
367 if (sih->set_cor) {
Balaji T Kfc7b92f2009-12-13 21:23:33 +0100368 status = twl_i2c_write_u8(sih->module,
David Brownella30d46c2008-10-20 23:46:28 +0200369 TWL4030_SIH_CTRL_COR_MASK,
370 sih->control_offset);
371 if (status < 0)
372 pr_err("twl4030: err %d initializing %s %s\n",
373 status, sih->name, "SIH_CTRL");
374 }
375 }
376
377 sih = sih_modules;
Ilkka Koskinen1920a612009-11-10 17:26:15 +0200378 for (i = 0; i < nr_sih_modules; i++, sih++) {
David Brownella30d46c2008-10-20 23:46:28 +0200379 u8 rxbuf[4];
380 int j;
381
382 /* skip USB */
383 if (!sih->bytes_ixr)
384 continue;
385
Ilkka Koskinen1920a612009-11-10 17:26:15 +0200386 /* Not all the SIH modules support multiple interrupt lines */
387 if (sih->irq_lines <= line)
388 continue;
389
Felipe Contrerascbcde052012-02-01 03:02:48 +0200390 /*
391 * Clear pending interrupt status. Either the read was
David Brownella30d46c2008-10-20 23:46:28 +0200392 * enough, or we need to write those bits. Repeat, in
393 * case an IRQ is pending (PENDDIS=0) ... that's not
394 * uncommon with PWR_INT.PWRON.
395 */
396 for (j = 0; j < 2; j++) {
Balaji T Kfc7b92f2009-12-13 21:23:33 +0100397 status = twl_i2c_read(sih->module, rxbuf,
David Brownella30d46c2008-10-20 23:46:28 +0200398 sih->mask[line].isr_offset, sih->bytes_ixr);
399 if (status < 0)
400 pr_err("twl4030: err %d initializing %s %s\n",
401 status, sih->name, "ISR");
402
403 if (!sih->set_cor)
Balaji T Kfc7b92f2009-12-13 21:23:33 +0100404 status = twl_i2c_write(sih->module, buf,
David Brownella30d46c2008-10-20 23:46:28 +0200405 sih->mask[line].isr_offset,
406 sih->bytes_ixr);
Felipe Contrerascbcde052012-02-01 03:02:48 +0200407 /*
408 * else COR=1 means read sufficed.
David Brownella30d46c2008-10-20 23:46:28 +0200409 * (for most SIH modules...)
410 */
411 }
412 }
413
414 return 0;
415}
416
417static inline void activate_irq(int irq)
418{
419#ifdef CONFIG_ARM
Felipe Contrerascbcde052012-02-01 03:02:48 +0200420 /*
421 * ARM requires an extra step to clear IRQ_NOREQUEST, which it
David Brownella30d46c2008-10-20 23:46:28 +0200422 * sets on behalf of every irq_chip. Also sets IRQ_NOPROBE.
423 */
424 set_irq_flags(irq, IRQF_VALID);
425#else
426 /* same effect on other architectures */
Thomas Gleixnerd5bb1222011-03-25 11:12:32 +0000427 irq_set_noprobe(irq);
David Brownella30d46c2008-10-20 23:46:28 +0200428#endif
429}
430
431/*----------------------------------------------------------------------*/
432
David Brownella30d46c2008-10-20 23:46:28 +0200433struct sih_agent {
434 int irq_base;
435 const struct sih *sih;
436
437 u32 imr;
438 bool imr_change_pending;
David Brownella30d46c2008-10-20 23:46:28 +0200439
440 u32 edge_change;
Felipe Balbi91e35692011-06-30 12:51:05 +0300441
442 struct mutex irq_lock;
NeilBrownc1e61bc2011-11-27 07:17:41 +1100443 char *irq_name;
David Brownella30d46c2008-10-20 23:46:28 +0200444};
445
David Brownella30d46c2008-10-20 23:46:28 +0200446/*----------------------------------------------------------------------*/
447
448/*
449 * All irq_chip methods get issued from code holding irq_desc[irq].lock,
450 * which can't perform the underlying I2C operations (because they sleep).
451 * So we must hand them off to a thread (workqueue) and cope with asynch
452 * completion, potentially including some re-ordering, of these requests.
453 */
454
Mark Brown845aeab2010-12-12 12:51:39 +0000455static void twl4030_sih_mask(struct irq_data *data)
David Brownella30d46c2008-10-20 23:46:28 +0200456{
Felipe Balbi84868422011-06-30 12:51:07 +0300457 struct sih_agent *agent = irq_data_get_irq_chip_data(data);
David Brownella30d46c2008-10-20 23:46:28 +0200458
Felipe Balbi84868422011-06-30 12:51:07 +0300459 agent->imr |= BIT(data->irq - agent->irq_base);
460 agent->imr_change_pending = true;
David Brownella30d46c2008-10-20 23:46:28 +0200461}
462
Mark Brown845aeab2010-12-12 12:51:39 +0000463static void twl4030_sih_unmask(struct irq_data *data)
David Brownella30d46c2008-10-20 23:46:28 +0200464{
Felipe Balbi84868422011-06-30 12:51:07 +0300465 struct sih_agent *agent = irq_data_get_irq_chip_data(data);
David Brownella30d46c2008-10-20 23:46:28 +0200466
Felipe Balbi84868422011-06-30 12:51:07 +0300467 agent->imr &= ~BIT(data->irq - agent->irq_base);
468 agent->imr_change_pending = true;
David Brownella30d46c2008-10-20 23:46:28 +0200469}
470
Mark Brown845aeab2010-12-12 12:51:39 +0000471static int twl4030_sih_set_type(struct irq_data *data, unsigned trigger)
David Brownella30d46c2008-10-20 23:46:28 +0200472{
Felipe Balbi84868422011-06-30 12:51:07 +0300473 struct sih_agent *agent = irq_data_get_irq_chip_data(data);
David Brownella30d46c2008-10-20 23:46:28 +0200474
David Brownella30d46c2008-10-20 23:46:28 +0200475 if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
476 return -EINVAL;
477
Felipe Balbi2f2a7d52011-06-30 12:51:08 +0300478 if (irqd_get_trigger_type(data) != trigger)
Felipe Balbi84868422011-06-30 12:51:07 +0300479 agent->edge_change |= BIT(data->irq - agent->irq_base);
Felipe Balbi91e35692011-06-30 12:51:05 +0300480
David Brownella30d46c2008-10-20 23:46:28 +0200481 return 0;
482}
483
Felipe Balbi91e35692011-06-30 12:51:05 +0300484static void twl4030_sih_bus_lock(struct irq_data *data)
485{
Felipe Balbi84868422011-06-30 12:51:07 +0300486 struct sih_agent *agent = irq_data_get_irq_chip_data(data);
Felipe Balbi91e35692011-06-30 12:51:05 +0300487
Felipe Balbi84868422011-06-30 12:51:07 +0300488 mutex_lock(&agent->irq_lock);
Felipe Balbi91e35692011-06-30 12:51:05 +0300489}
490
491static void twl4030_sih_bus_sync_unlock(struct irq_data *data)
492{
Felipe Balbi84868422011-06-30 12:51:07 +0300493 struct sih_agent *agent = irq_data_get_irq_chip_data(data);
494 const struct sih *sih = agent->sih;
495 int status;
Felipe Balbi91e35692011-06-30 12:51:05 +0300496
Felipe Balbi84868422011-06-30 12:51:07 +0300497 if (agent->imr_change_pending) {
498 union {
499 u32 word;
500 u8 bytes[4];
501 } imr;
502
NeilBrownc9531222011-11-27 07:17:41 +1100503 /* byte[0] gets overwritten as we write ... */
Felipe Balbi84868422011-06-30 12:51:07 +0300504 imr.word = cpu_to_le32(agent->imr << 8);
505 agent->imr_change_pending = false;
506
507 /* write the whole mask ... simpler than subsetting it */
508 status = twl_i2c_write(sih->module, imr.bytes,
509 sih->mask[irq_line].imr_offset,
510 sih->bytes_ixr);
511 if (status)
512 pr_err("twl4030: %s, %s --> %d\n", __func__,
513 "write", status);
514 }
515
Felipe Balbi2f2a7d52011-06-30 12:51:08 +0300516 if (agent->edge_change) {
517 u32 edge_change;
518 u8 bytes[6];
519
520 edge_change = agent->edge_change;
521 agent->edge_change = 0;
522
523 /*
524 * Read, reserving first byte for write scratch. Yes, this
525 * could be cached for some speedup ... but be careful about
526 * any processor on the other IRQ line, EDR registers are
527 * shared.
528 */
529 status = twl_i2c_read(sih->module, bytes + 1,
530 sih->edr_offset, sih->bytes_edr);
531 if (status) {
532 pr_err("twl4030: %s, %s --> %d\n", __func__,
533 "read", status);
534 return;
535 }
536
537 /* Modify only the bits we know must change */
538 while (edge_change) {
539 int i = fls(edge_change) - 1;
540 struct irq_data *idata;
541 int byte = 1 + (i >> 2);
542 int off = (i & 0x3) * 2;
543 unsigned int type;
544
545 idata = irq_get_irq_data(i + agent->irq_base);
546
547 bytes[byte] &= ~(0x03 << off);
548
549 type = irqd_get_trigger_type(idata);
550 if (type & IRQ_TYPE_EDGE_RISING)
551 bytes[byte] |= BIT(off + 1);
552 if (type & IRQ_TYPE_EDGE_FALLING)
553 bytes[byte] |= BIT(off + 0);
554
555 edge_change &= ~BIT(i);
556 }
557
558 /* Write */
559 status = twl_i2c_write(sih->module, bytes,
560 sih->edr_offset, sih->bytes_edr);
561 if (status)
562 pr_err("twl4030: %s, %s --> %d\n", __func__,
563 "write", status);
564 }
565
Felipe Balbi84868422011-06-30 12:51:07 +0300566 mutex_unlock(&agent->irq_lock);
Felipe Balbi91e35692011-06-30 12:51:05 +0300567}
568
David Brownella30d46c2008-10-20 23:46:28 +0200569static struct irq_chip twl4030_sih_irq_chip = {
570 .name = "twl4030",
Felipe Balbi8cd6af22011-06-30 12:51:04 +0300571 .irq_mask = twl4030_sih_mask,
Mark Brown845aeab2010-12-12 12:51:39 +0000572 .irq_unmask = twl4030_sih_unmask,
573 .irq_set_type = twl4030_sih_set_type,
Felipe Balbi91e35692011-06-30 12:51:05 +0300574 .irq_bus_lock = twl4030_sih_bus_lock,
575 .irq_bus_sync_unlock = twl4030_sih_bus_sync_unlock,
David Brownella30d46c2008-10-20 23:46:28 +0200576};
577
578/*----------------------------------------------------------------------*/
579
580static inline int sih_read_isr(const struct sih *sih)
581{
582 int status;
583 union {
584 u8 bytes[4];
585 u32 word;
586 } isr;
587
588 /* FIXME need retry-on-error ... */
589
590 isr.word = 0;
Balaji T Kfc7b92f2009-12-13 21:23:33 +0100591 status = twl_i2c_read(sih->module, isr.bytes,
David Brownella30d46c2008-10-20 23:46:28 +0200592 sih->mask[irq_line].isr_offset, sih->bytes_ixr);
593
594 return (status < 0) ? status : le32_to_cpu(isr.word);
595}
596
597/*
598 * Generic handler for SIH interrupts ... we "know" this is called
599 * in task context, with IRQs enabled.
600 */
NeilBrownc1e61bc2011-11-27 07:17:41 +1100601static irqreturn_t handle_twl4030_sih(int irq, void *data)
David Brownella30d46c2008-10-20 23:46:28 +0200602{
Thomas Gleixnerd5bb1222011-03-25 11:12:32 +0000603 struct sih_agent *agent = irq_get_handler_data(irq);
David Brownella30d46c2008-10-20 23:46:28 +0200604 const struct sih *sih = agent->sih;
605 int isr;
606
607 /* reading ISR acks the IRQs, using clear-on-read mode */
David Brownella30d46c2008-10-20 23:46:28 +0200608 isr = sih_read_isr(sih);
David Brownella30d46c2008-10-20 23:46:28 +0200609
610 if (isr < 0) {
611 pr_err("twl4030: %s SIH, read ISR error %d\n",
612 sih->name, isr);
613 /* REVISIT: recover; eventually mask it all, etc */
NeilBrownc1e61bc2011-11-27 07:17:41 +1100614 return IRQ_HANDLED;
David Brownella30d46c2008-10-20 23:46:28 +0200615 }
616
617 while (isr) {
618 irq = fls(isr);
619 irq--;
620 isr &= ~BIT(irq);
621
622 if (irq < sih->bits)
Felipe Balbi925e8532011-06-30 12:51:09 +0300623 handle_nested_irq(agent->irq_base + irq);
David Brownella30d46c2008-10-20 23:46:28 +0200624 else
625 pr_err("twl4030: %s SIH, invalid ISR bit %d\n",
626 sih->name, irq);
627 }
NeilBrownc1e61bc2011-11-27 07:17:41 +1100628 return IRQ_HANDLED;
David Brownella30d46c2008-10-20 23:46:28 +0200629}
630
Felipe Contrerascbcde052012-02-01 03:02:48 +0200631/* returns the first IRQ used by this SIH bank, or negative errno */
Benoit Coussonf01b1f92012-02-29 22:38:06 +0100632int twl4030_sih_setup(struct device *dev, int module, int irq_base)
David Brownella30d46c2008-10-20 23:46:28 +0200633{
634 int sih_mod;
635 const struct sih *sih = NULL;
636 struct sih_agent *agent;
637 int i, irq;
638 int status = -EINVAL;
David Brownella30d46c2008-10-20 23:46:28 +0200639
640 /* only support modules with standard clear-on-read for now */
Benoit Coussonec1a07b2012-03-02 11:11:26 +0100641 for (sih_mod = 0, sih = sih_modules; sih_mod < nr_sih_modules;
David Brownella30d46c2008-10-20 23:46:28 +0200642 sih_mod++, sih++) {
643 if (sih->module == module && sih->set_cor) {
Benoit Coussonf01b1f92012-02-29 22:38:06 +0100644 status = 0;
David Brownella30d46c2008-10-20 23:46:28 +0200645 break;
646 }
647 }
Benoit Coussonec1a07b2012-03-02 11:11:26 +0100648
David Brownella30d46c2008-10-20 23:46:28 +0200649 if (status < 0)
650 return status;
651
652 agent = kzalloc(sizeof *agent, GFP_KERNEL);
653 if (!agent)
654 return -ENOMEM;
655
David Brownella30d46c2008-10-20 23:46:28 +0200656 agent->irq_base = irq_base;
657 agent->sih = sih;
658 agent->imr = ~0;
Felipe Balbi91e35692011-06-30 12:51:05 +0300659 mutex_init(&agent->irq_lock);
David Brownella30d46c2008-10-20 23:46:28 +0200660
661 for (i = 0; i < sih->bits; i++) {
662 irq = irq_base + i;
663
Felipe Balbi91e35692011-06-30 12:51:05 +0300664 irq_set_chip_data(irq, agent);
Thomas Gleixnerd5bb1222011-03-25 11:12:32 +0000665 irq_set_chip_and_handler(irq, &twl4030_sih_irq_chip,
666 handle_edge_irq);
NeilBrownb18d1f02011-11-27 07:17:41 +1100667 irq_set_nested_thread(irq, 1);
David Brownella30d46c2008-10-20 23:46:28 +0200668 activate_irq(irq);
669 }
670
David Brownella30d46c2008-10-20 23:46:28 +0200671 /* replace generic PIH handler (handle_simple_irq) */
672 irq = sih_mod + twl4030_irq_base;
Thomas Gleixnerd5bb1222011-03-25 11:12:32 +0000673 irq_set_handler_data(irq, agent);
NeilBrownc1e61bc2011-11-27 07:17:41 +1100674 agent->irq_name = kasprintf(GFP_KERNEL, "twl4030_%s", sih->name);
675 status = request_threaded_irq(irq, NULL, handle_twl4030_sih, 0,
676 agent->irq_name ?: sih->name, NULL);
David Brownella30d46c2008-10-20 23:46:28 +0200677
Benoit Coussonec1a07b2012-03-02 11:11:26 +0100678 dev_info(dev, "%s (irq %d) chaining IRQs %d..%d\n", sih->name,
Benoit Coussonf01b1f92012-02-29 22:38:06 +0100679 irq, irq_base, irq_base + i - 1);
David Brownella30d46c2008-10-20 23:46:28 +0200680
NeilBrownc1e61bc2011-11-27 07:17:41 +1100681 return status < 0 ? status : irq_base;
David Brownella30d46c2008-10-20 23:46:28 +0200682}
683
684/* FIXME need a call to reverse twl4030_sih_setup() ... */
685
David Brownella30d46c2008-10-20 23:46:28 +0200686/*----------------------------------------------------------------------*/
687
688/* FIXME pass in which interrupt line we'll use ... */
689#define twl_irq_line 0
690
Benoit Cousson78518ff2012-02-29 19:40:31 +0100691int twl4030_init_irq(struct device *dev, int irq_num)
David Brownella30d46c2008-10-20 23:46:28 +0200692{
693 static struct irq_chip twl4030_irq_chip;
Benoit Coussonec1a07b2012-03-02 11:11:26 +0100694 int status, i;
Benoit Cousson78518ff2012-02-29 19:40:31 +0100695 int irq_base, irq_end, nr_irqs;
696 struct device_node *node = dev->of_node;
David Brownella30d46c2008-10-20 23:46:28 +0200697
David Brownella30d46c2008-10-20 23:46:28 +0200698 /*
Benoit Cousson78518ff2012-02-29 19:40:31 +0100699 * TWL core and pwr interrupts must be contiguous because
700 * the hwirqs numbers are defined contiguously from 1 to 15.
701 * Create only one domain for both.
702 */
703 nr_irqs = TWL4030_PWR_NR_IRQS + TWL4030_CORE_NR_IRQS;
704
705 irq_base = irq_alloc_descs(-1, 0, nr_irqs, 0);
706 if (IS_ERR_VALUE(irq_base)) {
707 dev_err(dev, "Fail to allocate IRQ descs\n");
708 return irq_base;
709 }
710
711 irq_domain_add_legacy(node, nr_irqs, irq_base, 0,
712 &irq_domain_simple_ops, NULL);
713
714 irq_end = irq_base + TWL4030_CORE_NR_IRQS;
715
716 /*
David Brownella30d46c2008-10-20 23:46:28 +0200717 * Mask and clear all TWL4030 interrupts since initially we do
718 * not have any TWL4030 module interrupt handlers present
719 */
720 status = twl4030_init_sih_modules(twl_irq_line);
721 if (status < 0)
722 return status;
723
David Brownella30d46c2008-10-20 23:46:28 +0200724 twl4030_irq_base = irq_base;
725
Felipe Contrerascbcde052012-02-01 03:02:48 +0200726 /*
Benoit Coussonec1a07b2012-03-02 11:11:26 +0100727 * Install an irq handler for each of the SIH modules;
David Brownella30d46c2008-10-20 23:46:28 +0200728 * clone dummy irq_chip since PIH can't *do* anything
729 */
730 twl4030_irq_chip = dummy_irq_chip;
731 twl4030_irq_chip.name = "twl4030";
732
Thomas Gleixnerfe212212010-10-08 15:33:01 +0200733 twl4030_sih_irq_chip.irq_ack = dummy_irq_chip.irq_ack;
David Brownella30d46c2008-10-20 23:46:28 +0200734
735 for (i = irq_base; i < irq_end; i++) {
Thomas Gleixnerd5bb1222011-03-25 11:12:32 +0000736 irq_set_chip_and_handler(i, &twl4030_irq_chip,
737 handle_simple_irq);
Felipe Balbi925e8532011-06-30 12:51:09 +0300738 irq_set_nested_thread(i, 1);
David Brownella30d46c2008-10-20 23:46:28 +0200739 activate_irq(i);
740 }
Benoit Coussonf01b1f92012-02-29 22:38:06 +0100741
Benoit Coussonec1a07b2012-03-02 11:11:26 +0100742 dev_info(dev, "%s (irq %d) chaining IRQs %d..%d\n", "PIH",
Benoit Coussonf01b1f92012-02-29 22:38:06 +0100743 irq_num, irq_base, irq_end);
David Brownella30d46c2008-10-20 23:46:28 +0200744
745 /* ... and the PWR_INT module ... */
Benoit Coussonf01b1f92012-02-29 22:38:06 +0100746 status = twl4030_sih_setup(dev, TWL4030_MODULE_INT, irq_end);
David Brownella30d46c2008-10-20 23:46:28 +0200747 if (status < 0) {
Benoit Coussonec1a07b2012-03-02 11:11:26 +0100748 dev_err(dev, "sih_setup PWR INT --> %d\n", status);
David Brownella30d46c2008-10-20 23:46:28 +0200749 goto fail;
750 }
751
752 /* install an irq handler to demultiplex the TWL4030 interrupt */
NeilBrown286f8f32011-11-27 07:17:41 +1100753 status = request_threaded_irq(irq_num, NULL, handle_twl4030_pih,
754 IRQF_ONESHOT,
755 "TWL4030-PIH", NULL);
Russell King1cef8e42009-07-27 11:30:48 +0530756 if (status < 0) {
Benoit Coussonec1a07b2012-03-02 11:11:26 +0100757 dev_err(dev, "could not claim irq%d: %d\n", irq_num, status);
Russell King1cef8e42009-07-27 11:30:48 +0530758 goto fail_rqirq;
David Brownella30d46c2008-10-20 23:46:28 +0200759 }
760
Benoit Cousson78518ff2012-02-29 19:40:31 +0100761 return irq_base;
Russell King1cef8e42009-07-27 11:30:48 +0530762fail_rqirq:
763 /* clean up twl4030_sih_setup */
David Brownella30d46c2008-10-20 23:46:28 +0200764fail:
Felipe Balbi925e8532011-06-30 12:51:09 +0300765 for (i = irq_base; i < irq_end; i++) {
766 irq_set_nested_thread(i, 0);
Thomas Gleixnerd5bb1222011-03-25 11:12:32 +0000767 irq_set_chip_and_handler(i, NULL, NULL);
Felipe Balbi925e8532011-06-30 12:51:09 +0300768 }
Felipe Balbi2f2a7d52011-06-30 12:51:08 +0300769
David Brownella30d46c2008-10-20 23:46:28 +0200770 return status;
771}
772
Balaji T Ke8deb282009-12-14 00:25:31 +0100773int twl4030_exit_irq(void)
David Brownella30d46c2008-10-20 23:46:28 +0200774{
775 /* FIXME undo twl_init_irq() */
776 if (twl4030_irq_base) {
777 pr_err("twl4030: can't yet clean up IRQs?\n");
778 return -ENOSYS;
779 }
780 return 0;
781}
Ilkka Koskinen1920a612009-11-10 17:26:15 +0200782
Balaji T Ke8deb282009-12-14 00:25:31 +0100783int twl4030_init_chip_irq(const char *chip)
Ilkka Koskinen1920a612009-11-10 17:26:15 +0200784{
785 if (!strcmp(chip, "twl5031")) {
786 sih_modules = sih_modules_twl5031;
787 nr_sih_modules = ARRAY_SIZE(sih_modules_twl5031);
788 } else {
789 sih_modules = sih_modules_twl4030;
790 nr_sih_modules = ARRAY_SIZE(sih_modules_twl4030);
791 }
792
793 return 0;
794}