blob: 265a685fa4397fc6ff16cd04b707fd784c391a44 [file] [log] [blame]
Felipe Balbi72246da2011-08-19 18:10:58 +03001/**
2 * core.c - DesignWare USB3 DRD Controller Core file
3 *
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
Felipe Balbi72246da2011-08-19 18:10:58 +03005 *
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions, and the following disclaimer,
14 * without modification.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. The names of the above-listed copyright holders may not be used
19 * to endorse or promote products derived from this software without
20 * specific prior written permission.
21 *
22 * ALTERNATIVELY, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2, as published by the Free
24 * Software Foundation.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
27 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
28 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
30 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
31 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
32 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
33 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
34 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
35 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
36 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 */
38
Felipe Balbia72e6582011-09-05 13:37:28 +030039#include <linux/module.h>
Felipe Balbi72246da2011-08-19 18:10:58 +030040#include <linux/kernel.h>
41#include <linux/slab.h>
42#include <linux/spinlock.h>
43#include <linux/platform_device.h>
44#include <linux/pm_runtime.h>
45#include <linux/interrupt.h>
46#include <linux/ioport.h>
47#include <linux/io.h>
48#include <linux/list.h>
49#include <linux/delay.h>
50#include <linux/dma-mapping.h>
Felipe Balbi457e84b2012-01-18 18:04:09 +020051#include <linux/of.h>
Felipe Balbi72246da2011-08-19 18:10:58 +030052
53#include <linux/usb/ch9.h>
54#include <linux/usb/gadget.h>
55
56#include "core.h"
57#include "gadget.h"
58#include "io.h"
59
60#include "debug.h"
61
Felipe Balbi6c167fc2011-10-07 22:55:04 +030062static char *maximum_speed = "super";
63module_param(maximum_speed, charp, 0);
64MODULE_PARM_DESC(maximum_speed, "Maximum supported speed.");
65
Felipe Balbi8300dd22011-10-18 13:54:01 +030066/* -------------------------------------------------------------------------- */
67
68#define DWC3_DEVS_POSSIBLE 32
69
70static DECLARE_BITMAP(dwc3_devs, DWC3_DEVS_POSSIBLE);
71
72int dwc3_get_device_id(void)
73{
74 int id;
75
76again:
77 id = find_first_zero_bit(dwc3_devs, DWC3_DEVS_POSSIBLE);
78 if (id < DWC3_DEVS_POSSIBLE) {
79 int old;
80
81 old = test_and_set_bit(id, dwc3_devs);
82 if (old)
83 goto again;
84 } else {
85 pr_err("dwc3: no space for new device\n");
86 id = -ENOMEM;
87 }
88
Dan Carpenter075cd142012-02-04 16:37:14 +030089 return id;
Felipe Balbi8300dd22011-10-18 13:54:01 +030090}
91EXPORT_SYMBOL_GPL(dwc3_get_device_id);
92
93void dwc3_put_device_id(int id)
94{
95 int ret;
96
97 if (id < 0)
98 return;
99
100 ret = test_bit(id, dwc3_devs);
101 WARN(!ret, "dwc3: ID %d not in use\n", id);
Oliver Neukum5fdeeb82012-08-26 21:34:19 +0200102 smp_mb__before_clear_bit();
Felipe Balbi8300dd22011-10-18 13:54:01 +0300103 clear_bit(id, dwc3_devs);
104}
105EXPORT_SYMBOL_GPL(dwc3_put_device_id);
106
Sebastian Andrzej Siewior3140e8c2011-10-31 22:25:40 +0100107void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
108{
109 u32 reg;
110
111 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
112 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
113 reg |= DWC3_GCTL_PRTCAPDIR(mode);
114 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
115}
Felipe Balbi8300dd22011-10-18 13:54:01 +0300116
Felipe Balbi72246da2011-08-19 18:10:58 +0300117/**
118 * dwc3_core_soft_reset - Issues core soft reset and PHY reset
119 * @dwc: pointer to our context structure
120 */
121static void dwc3_core_soft_reset(struct dwc3 *dwc)
122{
123 u32 reg;
124
125 /* Before Resetting PHY, put Core in Reset */
126 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
127 reg |= DWC3_GCTL_CORESOFTRESET;
128 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
129
130 /* Assert USB3 PHY reset */
131 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
132 reg |= DWC3_GUSB3PIPECTL_PHYSOFTRST;
133 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
134
135 /* Assert USB2 PHY reset */
136 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
137 reg |= DWC3_GUSB2PHYCFG_PHYSOFTRST;
138 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
139
140 mdelay(100);
141
142 /* Clear USB3 PHY reset */
143 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
144 reg &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST;
145 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
146
147 /* Clear USB2 PHY reset */
148 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
149 reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST;
150 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
151
Pratyush Anand38a535c2012-06-21 17:44:28 +0530152 mdelay(100);
153
Felipe Balbi72246da2011-08-19 18:10:58 +0300154 /* After PHYs are stable we can take Core out of reset state */
155 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
156 reg &= ~DWC3_GCTL_CORESOFTRESET;
157 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
158}
159
160/**
161 * dwc3_free_one_event_buffer - Frees one event buffer
162 * @dwc: Pointer to our controller context structure
163 * @evt: Pointer to event buffer to be freed
164 */
165static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
166 struct dwc3_event_buffer *evt)
167{
168 dma_free_coherent(dwc->dev, evt->length, evt->buf, evt->dma);
169 kfree(evt);
170}
171
172/**
Paul Zimmerman1d046792012-02-15 18:56:56 -0800173 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
Felipe Balbi72246da2011-08-19 18:10:58 +0300174 * @dwc: Pointer to our controller context structure
175 * @length: size of the event buffer
176 *
Paul Zimmerman1d046792012-02-15 18:56:56 -0800177 * Returns a pointer to the allocated event buffer structure on success
Felipe Balbi72246da2011-08-19 18:10:58 +0300178 * otherwise ERR_PTR(errno).
179 */
180static struct dwc3_event_buffer *__devinit
181dwc3_alloc_one_event_buffer(struct dwc3 *dwc, unsigned length)
182{
183 struct dwc3_event_buffer *evt;
184
185 evt = kzalloc(sizeof(*evt), GFP_KERNEL);
186 if (!evt)
187 return ERR_PTR(-ENOMEM);
188
189 evt->dwc = dwc;
190 evt->length = length;
191 evt->buf = dma_alloc_coherent(dwc->dev, length,
192 &evt->dma, GFP_KERNEL);
193 if (!evt->buf) {
194 kfree(evt);
195 return ERR_PTR(-ENOMEM);
196 }
197
198 return evt;
199}
200
201/**
202 * dwc3_free_event_buffers - frees all allocated event buffers
203 * @dwc: Pointer to our controller context structure
204 */
205static void dwc3_free_event_buffers(struct dwc3 *dwc)
206{
207 struct dwc3_event_buffer *evt;
208 int i;
209
Felipe Balbi9f622b22011-10-12 10:31:04 +0300210 for (i = 0; i < dwc->num_event_buffers; i++) {
Felipe Balbi72246da2011-08-19 18:10:58 +0300211 evt = dwc->ev_buffs[i];
Anton Tikhomirov64b6c8a2012-03-06 17:05:15 +0900212 if (evt)
Felipe Balbi72246da2011-08-19 18:10:58 +0300213 dwc3_free_one_event_buffer(dwc, evt);
Felipe Balbi72246da2011-08-19 18:10:58 +0300214 }
Anton Tikhomirov64b6c8a2012-03-06 17:05:15 +0900215
216 kfree(dwc->ev_buffs);
Felipe Balbi72246da2011-08-19 18:10:58 +0300217}
218
219/**
220 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
Paul Zimmerman1d046792012-02-15 18:56:56 -0800221 * @dwc: pointer to our controller context structure
Felipe Balbi72246da2011-08-19 18:10:58 +0300222 * @length: size of event buffer
223 *
Paul Zimmerman1d046792012-02-15 18:56:56 -0800224 * Returns 0 on success otherwise negative errno. In the error case, dwc
Felipe Balbi72246da2011-08-19 18:10:58 +0300225 * may contain some buffers allocated but not all which were requested.
226 */
Felipe Balbi9f622b22011-10-12 10:31:04 +0300227static int __devinit dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
Felipe Balbi72246da2011-08-19 18:10:58 +0300228{
Felipe Balbi9f622b22011-10-12 10:31:04 +0300229 int num;
Felipe Balbi72246da2011-08-19 18:10:58 +0300230 int i;
231
Felipe Balbi9f622b22011-10-12 10:31:04 +0300232 num = DWC3_NUM_INT(dwc->hwparams.hwparams1);
233 dwc->num_event_buffers = num;
234
Felipe Balbi457d3f22011-10-24 12:03:13 +0300235 dwc->ev_buffs = kzalloc(sizeof(*dwc->ev_buffs) * num, GFP_KERNEL);
236 if (!dwc->ev_buffs) {
237 dev_err(dwc->dev, "can't allocate event buffers array\n");
238 return -ENOMEM;
239 }
240
Felipe Balbi72246da2011-08-19 18:10:58 +0300241 for (i = 0; i < num; i++) {
242 struct dwc3_event_buffer *evt;
243
244 evt = dwc3_alloc_one_event_buffer(dwc, length);
245 if (IS_ERR(evt)) {
246 dev_err(dwc->dev, "can't allocate event buffer\n");
247 return PTR_ERR(evt);
248 }
249 dwc->ev_buffs[i] = evt;
250 }
251
252 return 0;
253}
254
255/**
256 * dwc3_event_buffers_setup - setup our allocated event buffers
Paul Zimmerman1d046792012-02-15 18:56:56 -0800257 * @dwc: pointer to our controller context structure
Felipe Balbi72246da2011-08-19 18:10:58 +0300258 *
259 * Returns 0 on success otherwise negative errno.
260 */
Paul Zimmerman43fa01a2012-04-27 14:28:02 +0300261static int dwc3_event_buffers_setup(struct dwc3 *dwc)
Felipe Balbi72246da2011-08-19 18:10:58 +0300262{
263 struct dwc3_event_buffer *evt;
264 int n;
265
Felipe Balbi9f622b22011-10-12 10:31:04 +0300266 for (n = 0; n < dwc->num_event_buffers; n++) {
Felipe Balbi72246da2011-08-19 18:10:58 +0300267 evt = dwc->ev_buffs[n];
268 dev_dbg(dwc->dev, "Event buf %p dma %08llx length %d\n",
269 evt->buf, (unsigned long long) evt->dma,
270 evt->length);
271
Paul Zimmerman43fa01a2012-04-27 14:28:02 +0300272 evt->lpos = 0;
273
Felipe Balbi72246da2011-08-19 18:10:58 +0300274 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n),
275 lower_32_bits(evt->dma));
276 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n),
277 upper_32_bits(evt->dma));
278 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n),
279 evt->length & 0xffff);
280 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
281 }
282
283 return 0;
284}
285
286static void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
287{
288 struct dwc3_event_buffer *evt;
289 int n;
290
Felipe Balbi9f622b22011-10-12 10:31:04 +0300291 for (n = 0; n < dwc->num_event_buffers; n++) {
Felipe Balbi72246da2011-08-19 18:10:58 +0300292 evt = dwc->ev_buffs[n];
Paul Zimmerman43fa01a2012-04-27 14:28:02 +0300293
294 evt->lpos = 0;
295
Felipe Balbi72246da2011-08-19 18:10:58 +0300296 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 0);
297 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 0);
298 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), 0);
299 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
300 }
301}
302
Vijayavardhan Vennapusab7434562012-12-12 16:48:49 +0530303static void dwc3_cache_hwparams(struct dwc3 *dwc)
Felipe Balbi26ceca92011-09-30 10:58:49 +0300304{
305 struct dwc3_hwparams *parms = &dwc->hwparams;
306
307 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
308 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
309 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
310 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
311 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
312 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
313 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
314 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
315 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
316}
317
Felipe Balbi72246da2011-08-19 18:10:58 +0300318/**
319 * dwc3_core_init - Low-level initialization of DWC3 Core
320 * @dwc: Pointer to our controller context structure
321 *
322 * Returns 0 on success otherwise negative errno.
323 */
Vijayavardhan Vennapusab7434562012-12-12 16:48:49 +0530324static int dwc3_core_init(struct dwc3 *dwc)
Felipe Balbi72246da2011-08-19 18:10:58 +0300325{
326 unsigned long timeout;
327 u32 reg;
328 int ret;
329
Sebastian Andrzej Siewior7650bd72011-08-29 13:56:36 +0200330 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
331 /* This should read as U3 followed by revision number */
332 if ((reg & DWC3_GSNPSID_MASK) != 0x55330000) {
333 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
334 ret = -ENODEV;
335 goto err0;
336 }
Felipe Balbi248b1222011-12-14 21:59:30 +0200337 dwc->revision = reg;
Sebastian Andrzej Siewior7650bd72011-08-29 13:56:36 +0200338
Felipe Balbi72246da2011-08-19 18:10:58 +0300339 /* issue device SoftReset too */
340 timeout = jiffies + msecs_to_jiffies(500);
341 dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST);
342 do {
343 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
344 if (!(reg & DWC3_DCTL_CSFTRST))
345 break;
346
347 if (time_after(jiffies, timeout)) {
348 dev_err(dwc->dev, "Reset Timed Out\n");
349 ret = -ETIMEDOUT;
350 goto err0;
351 }
352
353 cpu_relax();
354 } while (true);
355
Pratyush Anand99d4da82012-06-21 17:44:29 +0530356 dwc3_core_soft_reset(dwc);
357
Felipe Balbi9f622b22011-10-12 10:31:04 +0300358 dwc3_cache_hwparams(dwc);
359
Sebastian Andrzej Siewior4878a022011-10-31 22:25:41 +0100360 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
Paul Zimmerman3e87c422012-02-24 17:32:13 -0800361 reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
Sebastian Andrzej Siewior4878a022011-10-31 22:25:41 +0100362 reg &= ~DWC3_GCTL_DISSCRAMBLE;
363
Sebastian Andrzej Siewior164d7732011-11-24 11:22:05 +0100364 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
Sebastian Andrzej Siewior4878a022011-10-31 22:25:41 +0100365 case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
366 reg &= ~DWC3_GCTL_DSBLCLKGTNG;
367 break;
368 default:
369 dev_dbg(dwc->dev, "No power optimization available\n");
370 }
371
372 /*
373 * WORKAROUND: DWC3 revisions <1.90a have a bug
Paul Zimmerman1d046792012-02-15 18:56:56 -0800374 * where the device can fail to connect at SuperSpeed
Sebastian Andrzej Siewior4878a022011-10-31 22:25:41 +0100375 * and falls back to high-speed mode which causes
Paul Zimmerman1d046792012-02-15 18:56:56 -0800376 * the device to enter a Connect/Disconnect loop
Sebastian Andrzej Siewior4878a022011-10-31 22:25:41 +0100377 */
378 if (dwc->revision < DWC3_REVISION_190A)
379 reg |= DWC3_GCTL_U2RSTECN;
380
381 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
382
Pavankumar Kondetife2c0632012-06-12 15:21:13 +0530383 /*
Pavankumar Kondetic6e15aa2012-07-16 11:37:15 +0530384 * The default value of GUCTL[31:22] should be 0x8. But on cores
385 * revision < 2.30a, the default value is mistakenly overridden
386 * with 0x0. Restore the correct default value.
387 */
388 if (dwc->revision < DWC3_REVISION_230A) {
389 reg = dwc3_readl(dwc->regs, DWC3_GUCTL);
390 reg &= ~DWC3_GUCTL_REFCLKPER;
391 reg |= 0x8 << __ffs(DWC3_GUCTL_REFCLKPER);
392 dwc3_writel(dwc->regs, DWC3_GUCTL, reg);
393 }
394 /*
Pavankumar Kondetife2c0632012-06-12 15:21:13 +0530395 * Currently, the default and the recommended value for GUSB3PIPECTL
396 * [21:19] in the RTL is 3'b100 or 32 consecutive errors. Based on
397 * analysis and experiments in the lab, it is found that there is a
398 * relatively low probability of getting 32 consecutive word errors
399 * in the presence of random recovered noise (during electrical idle).
400 * This can delay the entry to a low power state such that for
401 * applications where the link stays in a non-U0 state for a short
402 * duration (< 1 microsecond), the local PHY does not enter the low
403 * power state prior to receiving a potential LFPS wakeup. This causes
404 * the PHY CDR (Clock and Data Recovery) operation to be unstable for
405 * some Synopsys PHYs.
406 *
407 * The proposal now is to change the default and the recommended value
408 * for GUSB3PIPECTL[21:19] in the RTL from 3'b100 to a minimum of
409 * 3'b001. Perform the same in software for controllers prior to 2.30a
410 * revision.
411 */
412
413 if (dwc->revision < DWC3_REVISION_230A) {
414 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
415 reg &= ~DWC3_GUSB3PIPECTL_DELAY_P1P2P3;
416 reg |= 1 << __ffs(DWC3_GUSB3PIPECTL_DELAY_P1P2P3);
Pavankumar Kondeti5acb4ba2012-07-16 11:44:46 +0530417 /*
418 * Receiver Detection in U3/Rx.Det is mistakenly disabled in
419 * cores < 2.30a. Fix it here.
420 */
421 reg &= ~DWC3_GUSB3PIPECTL_DIS_RXDET_U3_RXDET;
Pavankumar Kondetife2c0632012-06-12 15:21:13 +0530422 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
423 }
424
Vijayavardhan Vennapusab7434562012-12-12 16:48:49 +0530425 if (!dwc->ev_buffs) {
426 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
427 if (ret) {
428 dev_err(dwc->dev, "failed to allocate event buffers\n");
429 ret = -ENOMEM;
430 goto err1;
431 }
Felipe Balbi72246da2011-08-19 18:10:58 +0300432 }
433
434 ret = dwc3_event_buffers_setup(dwc);
435 if (ret) {
436 dev_err(dwc->dev, "failed to setup event buffers\n");
437 goto err1;
438 }
439
Felipe Balbi72246da2011-08-19 18:10:58 +0300440 return 0;
441
442err1:
443 dwc3_free_event_buffers(dwc);
444
445err0:
446 return ret;
447}
448
449static void dwc3_core_exit(struct dwc3 *dwc)
450{
451 dwc3_event_buffers_cleanup(dwc);
452 dwc3_free_event_buffers(dwc);
453}
454
Vijayavardhan Vennapusab7434562012-12-12 16:48:49 +0530455/* XHCI reset, resets other CORE registers as well, re-init those */
456void dwc3_post_host_reset_core_init(struct dwc3 *dwc)
457{
458 dwc3_core_init(dwc);
459 dwc3_gadget_restart(dwc);
460}
461
Felipe Balbi72246da2011-08-19 18:10:58 +0300462#define DWC3_ALIGN_MASK (16 - 1)
463
464static int __devinit dwc3_probe(struct platform_device *pdev)
465{
Felipe Balbi457e84b2012-01-18 18:04:09 +0200466 struct device_node *node = pdev->dev.of_node;
Felipe Balbi72246da2011-08-19 18:10:58 +0300467 struct resource *res;
468 struct dwc3 *dwc;
Chanho Park802ca852012-02-15 18:27:55 +0900469 struct device *dev = &pdev->dev;
Felipe Balbi0949e992011-10-12 10:44:56 +0300470
Felipe Balbi72246da2011-08-19 18:10:58 +0300471 int ret = -ENOMEM;
Felipe Balbi0949e992011-10-12 10:44:56 +0300472
473 void __iomem *regs;
Felipe Balbi72246da2011-08-19 18:10:58 +0300474 void *mem;
475
Felipe Balbi0949e992011-10-12 10:44:56 +0300476 u8 mode;
477
Chanho Park802ca852012-02-15 18:27:55 +0900478 mem = devm_kzalloc(dev, sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL);
Felipe Balbi72246da2011-08-19 18:10:58 +0300479 if (!mem) {
Chanho Park802ca852012-02-15 18:27:55 +0900480 dev_err(dev, "not enough memory\n");
481 return -ENOMEM;
Felipe Balbi72246da2011-08-19 18:10:58 +0300482 }
483 dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1);
484 dwc->mem = mem;
485
Ido Shayevitz4a187332012-04-23 14:53:37 +0200486 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
Felipe Balbi72246da2011-08-19 18:10:58 +0300487 if (!res) {
Ido Shayevitz4a187332012-04-23 14:53:37 +0200488 dev_err(dev, "missing IRQ\n");
Chanho Park802ca852012-02-15 18:27:55 +0900489 return -ENODEV;
Felipe Balbi72246da2011-08-19 18:10:58 +0300490 }
Kishon Vijay Abraham I2f8ae022012-08-21 14:56:16 +0530491 dwc->xhci_resources[1].start = res->start;
492 dwc->xhci_resources[1].end = res->end;
493 dwc->xhci_resources[1].flags = res->flags;
494 dwc->xhci_resources[1].name = res->name;
Felipe Balbi72246da2011-08-19 18:10:58 +0300495
Ido Shayevitz4a187332012-04-23 14:53:37 +0200496 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
497 if (!res) {
498 dev_err(dev, "missing memory resource\n");
499 return -ENODEV;
500 }
Kishon Vijay Abraham I2f8ae022012-08-21 14:56:16 +0530501 dwc->xhci_resources[0].start = res->start;
Ido Shayevitz4a187332012-04-23 14:53:37 +0200502 dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
503 DWC3_XHCI_REGS_END;
Kishon Vijay Abraham I2f8ae022012-08-21 14:56:16 +0530504 dwc->xhci_resources[0].flags = res->flags;
505 dwc->xhci_resources[0].name = res->name;
Felipe Balbid07e8812011-10-12 14:08:26 +0300506
Ido Shayevitz4a187332012-04-23 14:53:37 +0200507 /*
508 * Request memory region but exclude xHCI regs,
509 * since it will be requested by the xhci-plat driver.
510 */
511 res = devm_request_mem_region(dev, res->start + DWC3_GLOBALS_REGS_START,
512 resource_size(res) - DWC3_GLOBALS_REGS_START,
Chanho Park802ca852012-02-15 18:27:55 +0900513 dev_name(dev));
Ido Shayevitz4a187332012-04-23 14:53:37 +0200514
Felipe Balbi72246da2011-08-19 18:10:58 +0300515 if (!res) {
Chanho Park802ca852012-02-15 18:27:55 +0900516 dev_err(dev, "can't request mem region\n");
517 return -ENOMEM;
Felipe Balbi72246da2011-08-19 18:10:58 +0300518 }
519
Felipe Balbi497a2a32012-08-10 09:16:43 +0300520 regs = devm_ioremap_nocache(dev, res->start, resource_size(res));
Felipe Balbi72246da2011-08-19 18:10:58 +0300521 if (!regs) {
Chanho Park802ca852012-02-15 18:27:55 +0900522 dev_err(dev, "ioremap failed\n");
523 return -ENOMEM;
Felipe Balbi72246da2011-08-19 18:10:58 +0300524 }
525
Felipe Balbi72246da2011-08-19 18:10:58 +0300526 spin_lock_init(&dwc->lock);
527 platform_set_drvdata(pdev, dwc);
528
529 dwc->regs = regs;
530 dwc->regs_size = resource_size(res);
Chanho Park802ca852012-02-15 18:27:55 +0900531 dwc->dev = dev;
Felipe Balbi72246da2011-08-19 18:10:58 +0300532
Felipe Balbi6c167fc2011-10-07 22:55:04 +0300533 if (!strncmp("super", maximum_speed, 5))
534 dwc->maximum_speed = DWC3_DCFG_SUPERSPEED;
535 else if (!strncmp("high", maximum_speed, 4))
536 dwc->maximum_speed = DWC3_DCFG_HIGHSPEED;
537 else if (!strncmp("full", maximum_speed, 4))
538 dwc->maximum_speed = DWC3_DCFG_FULLSPEED1;
539 else if (!strncmp("low", maximum_speed, 3))
540 dwc->maximum_speed = DWC3_DCFG_LOWSPEED;
541 else
542 dwc->maximum_speed = DWC3_DCFG_SUPERSPEED;
543
Felipe Balbi457e84b2012-01-18 18:04:09 +0200544 if (of_get_property(node, "tx-fifo-resize", NULL))
545 dwc->needs_fifo_resize = true;
546
Manu Gautamb5067272012-07-02 09:53:41 +0530547 pm_runtime_no_callbacks(dev);
548 pm_runtime_set_active(dev);
Chanho Park802ca852012-02-15 18:27:55 +0900549 pm_runtime_enable(dev);
Felipe Balbi72246da2011-08-19 18:10:58 +0300550
551 ret = dwc3_core_init(dwc);
552 if (ret) {
Chanho Park802ca852012-02-15 18:27:55 +0900553 dev_err(dev, "failed to initialize core\n");
554 return ret;
Felipe Balbi72246da2011-08-19 18:10:58 +0300555 }
556
Felipe Balbi0949e992011-10-12 10:44:56 +0300557 mode = DWC3_MODE(dwc->hwparams.hwparams0);
558
559 switch (mode) {
Felipe Balbi0949e992011-10-12 10:44:56 +0300560 case DWC3_MODE_DEVICE:
Sebastian Andrzej Siewior3140e8c2011-10-31 22:25:40 +0100561 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
Felipe Balbi72246da2011-08-19 18:10:58 +0300562 ret = dwc3_gadget_init(dwc);
563 if (ret) {
Chanho Park802ca852012-02-15 18:27:55 +0900564 dev_err(dev, "failed to initialize gadget\n");
565 goto err1;
Felipe Balbi72246da2011-08-19 18:10:58 +0300566 }
Felipe Balbi0949e992011-10-12 10:44:56 +0300567 break;
Felipe Balbid07e8812011-10-12 14:08:26 +0300568 case DWC3_MODE_HOST:
Sebastian Andrzej Siewior3140e8c2011-10-31 22:25:40 +0100569 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST);
Felipe Balbid07e8812011-10-12 14:08:26 +0300570 ret = dwc3_host_init(dwc);
571 if (ret) {
Chanho Park802ca852012-02-15 18:27:55 +0900572 dev_err(dev, "failed to initialize host\n");
573 goto err1;
Felipe Balbid07e8812011-10-12 14:08:26 +0300574 }
575 break;
576 case DWC3_MODE_DRD:
Sebastian Andrzej Siewior3140e8c2011-10-31 22:25:40 +0100577 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG);
Ido Shayevitzcdeef4c2012-05-29 13:17:41 +0200578 ret = dwc3_otg_init(dwc);
579 if (ret) {
580 dev_err(dev, "failed to initialize otg\n");
581 goto err1;
582 }
583
Manu Gautamf1fceddf2012-10-12 14:02:50 +0530584 ret = dwc3_host_init(dwc);
585 if (ret) {
586 dev_err(dev, "failed to initialize host\n");
587 dwc3_otg_exit(dwc);
588 goto err1;
589 }
590
Felipe Balbid07e8812011-10-12 14:08:26 +0300591 ret = dwc3_gadget_init(dwc);
592 if (ret) {
Chanho Park802ca852012-02-15 18:27:55 +0900593 dev_err(dev, "failed to initialize gadget\n");
Ido Shayevitzcdeef4c2012-05-29 13:17:41 +0200594 dwc3_host_exit(dwc);
595 dwc3_otg_exit(dwc);
Chanho Park802ca852012-02-15 18:27:55 +0900596 goto err1;
Felipe Balbid07e8812011-10-12 14:08:26 +0300597 }
598 break;
Felipe Balbi0949e992011-10-12 10:44:56 +0300599 default:
Chanho Park802ca852012-02-15 18:27:55 +0900600 dev_err(dev, "Unsupported mode of operation %d\n", mode);
601 goto err1;
Felipe Balbi72246da2011-08-19 18:10:58 +0300602 }
Felipe Balbi0949e992011-10-12 10:44:56 +0300603 dwc->mode = mode;
Felipe Balbi72246da2011-08-19 18:10:58 +0300604
605 ret = dwc3_debugfs_init(dwc);
606 if (ret) {
Chanho Park802ca852012-02-15 18:27:55 +0900607 dev_err(dev, "failed to initialize debugfs\n");
608 goto err2;
Felipe Balbi72246da2011-08-19 18:10:58 +0300609 }
610
Felipe Balbi72246da2011-08-19 18:10:58 +0300611 return 0;
612
Chanho Park802ca852012-02-15 18:27:55 +0900613err2:
Felipe Balbi0949e992011-10-12 10:44:56 +0300614 switch (mode) {
Felipe Balbi0949e992011-10-12 10:44:56 +0300615 case DWC3_MODE_DEVICE:
Felipe Balbi72246da2011-08-19 18:10:58 +0300616 dwc3_gadget_exit(dwc);
Felipe Balbi0949e992011-10-12 10:44:56 +0300617 break;
Felipe Balbid07e8812011-10-12 14:08:26 +0300618 case DWC3_MODE_HOST:
619 dwc3_host_exit(dwc);
620 break;
621 case DWC3_MODE_DRD:
Felipe Balbid07e8812011-10-12 14:08:26 +0300622 dwc3_gadget_exit(dwc);
Ido Shayevitzcdeef4c2012-05-29 13:17:41 +0200623 dwc3_host_exit(dwc);
624 dwc3_otg_exit(dwc);
Felipe Balbid07e8812011-10-12 14:08:26 +0300625 break;
Felipe Balbi0949e992011-10-12 10:44:56 +0300626 default:
627 /* do nothing */
628 break;
629 }
Felipe Balbi72246da2011-08-19 18:10:58 +0300630
Chanho Park802ca852012-02-15 18:27:55 +0900631err1:
Felipe Balbi72246da2011-08-19 18:10:58 +0300632 dwc3_core_exit(dwc);
633
Felipe Balbi72246da2011-08-19 18:10:58 +0300634 return ret;
635}
636
637static int __devexit dwc3_remove(struct platform_device *pdev)
638{
Felipe Balbi72246da2011-08-19 18:10:58 +0300639 struct dwc3 *dwc = platform_get_drvdata(pdev);
640 struct resource *res;
Felipe Balbi72246da2011-08-19 18:10:58 +0300641
642 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
643
Felipe Balbi72246da2011-08-19 18:10:58 +0300644 pm_runtime_disable(&pdev->dev);
645
646 dwc3_debugfs_exit(dwc);
647
Felipe Balbi0949e992011-10-12 10:44:56 +0300648 switch (dwc->mode) {
Felipe Balbi0949e992011-10-12 10:44:56 +0300649 case DWC3_MODE_DEVICE:
Felipe Balbi72246da2011-08-19 18:10:58 +0300650 dwc3_gadget_exit(dwc);
Felipe Balbi0949e992011-10-12 10:44:56 +0300651 break;
Felipe Balbid07e8812011-10-12 14:08:26 +0300652 case DWC3_MODE_HOST:
653 dwc3_host_exit(dwc);
654 break;
655 case DWC3_MODE_DRD:
Felipe Balbid07e8812011-10-12 14:08:26 +0300656 dwc3_gadget_exit(dwc);
Ido Shayevitzcdeef4c2012-05-29 13:17:41 +0200657 dwc3_host_exit(dwc);
658 dwc3_otg_exit(dwc);
Felipe Balbid07e8812011-10-12 14:08:26 +0300659 break;
Felipe Balbi0949e992011-10-12 10:44:56 +0300660 default:
661 /* do nothing */
662 break;
663 }
Felipe Balbi72246da2011-08-19 18:10:58 +0300664
665 dwc3_core_exit(dwc);
Felipe Balbi72246da2011-08-19 18:10:58 +0300666
667 return 0;
668}
669
Felipe Balbi72246da2011-08-19 18:10:58 +0300670static struct platform_driver dwc3_driver = {
671 .probe = dwc3_probe,
672 .remove = __devexit_p(dwc3_remove),
673 .driver = {
674 .name = "dwc3",
675 },
Felipe Balbi72246da2011-08-19 18:10:58 +0300676};
677
Tobias Klauserb1116dc2012-02-28 12:57:20 +0100678module_platform_driver(dwc3_driver);
679
Sebastian Andrzej Siewior7ae4fc42011-10-19 19:39:50 +0200680MODULE_ALIAS("platform:dwc3");
Felipe Balbi72246da2011-08-19 18:10:58 +0300681MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
682MODULE_LICENSE("Dual BSD/GPL");
683MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");