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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
2 */
Dave Airlie0d6aa602006-01-02 20:14:23 +11003/*
Dave Airliebc54fd12005-06-23 22:46:46 +10004 *
Linus Torvalds1da177e2005-04-16 15:20:36 -07005 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
Dave Airliebc54fd12005-06-23 22:46:46 +10007 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
Dave Airlie0d6aa602006-01-02 20:14:23 +110028 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070029
30#ifndef _I915_DRV_H_
31#define _I915_DRV_H_
32
Jesse Barnes585fb112008-07-29 11:54:06 -070033#include "i915_reg.h"
Jesse Barnes79e53942008-11-07 14:24:08 -080034#include "intel_bios.h"
Keith Packard0839ccb2008-10-30 19:38:48 -070035#include <linux/io-mapping.h>
Jesse Barnes585fb112008-07-29 11:54:06 -070036
Linus Torvalds1da177e2005-04-16 15:20:36 -070037/* General customization:
38 */
39
40#define DRIVER_AUTHOR "Tungsten Graphics, Inc."
41
42#define DRIVER_NAME "i915"
43#define DRIVER_DESC "Intel Graphics"
Eric Anholt673a3942008-07-30 12:06:12 -070044#define DRIVER_DATE "20080730"
Linus Torvalds1da177e2005-04-16 15:20:36 -070045
Jesse Barnes317c35d2008-08-25 15:11:06 -070046enum pipe {
47 PIPE_A = 0,
48 PIPE_B,
49};
50
Keith Packard52440212008-11-18 09:30:25 -080051#define I915_NUM_PIPE 2
52
Linus Torvalds1da177e2005-04-16 15:20:36 -070053/* Interface history:
54 *
55 * 1.1: Original.
Dave Airlie0d6aa602006-01-02 20:14:23 +110056 * 1.2: Add Power Management
57 * 1.3: Add vblank support
Dave Airliede227f52006-01-25 15:31:43 +110058 * 1.4: Fix cmdbuffer path, add heap destroy
Dave Airlie702880f2006-06-24 17:07:34 +100059 * 1.5: Add vblank pipe configuration
=?utf-8?q?Michel_D=C3=A4nzer?=2228ed62006-10-25 01:05:09 +100060 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
61 * - Support vertical blank on secondary display pipe
Linus Torvalds1da177e2005-04-16 15:20:36 -070062 */
63#define DRIVER_MAJOR 1
=?utf-8?q?Michel_D=C3=A4nzer?=2228ed62006-10-25 01:05:09 +100064#define DRIVER_MINOR 6
Linus Torvalds1da177e2005-04-16 15:20:36 -070065#define DRIVER_PATCHLEVEL 0
66
Eric Anholt673a3942008-07-30 12:06:12 -070067#define WATCH_COHERENCY 0
68#define WATCH_BUF 0
69#define WATCH_EXEC 0
70#define WATCH_LRU 0
71#define WATCH_RELOC 0
72#define WATCH_INACTIVE 0
73#define WATCH_PWRITE 0
74
Dave Airlie71acb5e2008-12-30 20:31:46 +100075#define I915_GEM_PHYS_CURSOR_0 1
76#define I915_GEM_PHYS_CURSOR_1 2
77#define I915_GEM_PHYS_OVERLAY_REGS 3
78#define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
79
80struct drm_i915_gem_phys_object {
81 int id;
82 struct page **page_list;
83 drm_dma_handle_t *handle;
84 struct drm_gem_object *cur_obj;
85};
86
Linus Torvalds1da177e2005-04-16 15:20:36 -070087typedef struct _drm_i915_ring_buffer {
Linus Torvalds1da177e2005-04-16 15:20:36 -070088 unsigned long Size;
89 u8 *virtual_start;
90 int head;
91 int tail;
92 int space;
93 drm_local_map_t map;
Eric Anholt673a3942008-07-30 12:06:12 -070094 struct drm_gem_object *ring_obj;
Linus Torvalds1da177e2005-04-16 15:20:36 -070095} drm_i915_ring_buffer_t;
96
97struct mem_block {
98 struct mem_block *next;
99 struct mem_block *prev;
100 int start;
101 int size;
Eric Anholt6c340ea2007-08-25 20:23:09 +1000102 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700103};
104
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700105struct opregion_header;
106struct opregion_acpi;
107struct opregion_swsci;
108struct opregion_asle;
109
Matthew Garrett8ee1c3d2008-08-05 19:37:25 +0100110struct intel_opregion {
111 struct opregion_header *header;
112 struct opregion_acpi *acpi;
113 struct opregion_swsci *swsci;
114 struct opregion_asle *asle;
115 int enabled;
116};
117
Dave Airlie7c1c2872008-11-28 14:22:24 +1000118struct drm_i915_master_private {
119 drm_local_map_t *sarea;
120 struct _drm_i915_sarea *sarea_priv;
121};
Jesse Barnesde151cf2008-11-12 10:03:55 -0800122#define I915_FENCE_REG_NONE -1
123
124struct drm_i915_fence_reg {
125 struct drm_gem_object *obj;
126};
Dave Airlie7c1c2872008-11-28 14:22:24 +1000127
yakui_zhao9b9d1722009-05-31 17:17:17 +0800128struct sdvo_device_mapping {
129 u8 dvo_port;
130 u8 slave_addr;
131 u8 dvo_wiring;
132 u8 initialized;
133};
134
Jesse Barnes63eeaf32009-06-18 16:56:52 -0700135struct drm_i915_error_state {
136 u32 eir;
137 u32 pgtbl_er;
138 u32 pipeastat;
139 u32 pipebstat;
140 u32 ipeir;
141 u32 ipehr;
142 u32 instdone;
143 u32 acthd;
144 u32 instpm;
145 u32 instps;
146 u32 instdone1;
147 u32 seqno;
148 struct timeval time;
149};
150
Linus Torvalds1da177e2005-04-16 15:20:36 -0700151typedef struct drm_i915_private {
Eric Anholt673a3942008-07-30 12:06:12 -0700152 struct drm_device *dev;
153
Dave Airlieac5c4e72008-12-19 15:38:34 +1000154 int has_gem;
155
Eric Anholt3043c602008-10-02 12:24:47 -0700156 void __iomem *regs;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700157
Dave Airlieec2a4c32009-08-04 11:43:41 +1000158 struct pci_dev *bridge_dev;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700159 drm_i915_ring_buffer_t ring;
160
Dave Airlie9c8da5e2005-07-10 15:38:56 +1000161 drm_dma_handle_t *status_page_dmah;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700162 void *hw_status_page;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700163 dma_addr_t dma_status_page;
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700164 uint32_t counter;
Wang Zhenyudc7a9312007-06-10 15:58:19 +1000165 unsigned int status_gfx_addr;
166 drm_local_map_t hws_map;
Eric Anholt673a3942008-07-30 12:06:12 -0700167 struct drm_gem_object *hws_obj;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700168
Jesse Barnesd7658982009-06-05 14:41:29 +0000169 struct resource mch_res;
170
=?utf-8?q?Michel_D=C3=A4nzer?=a6b54f32006-10-24 23:37:43 +1000171 unsigned int cpp;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700172 int back_offset;
173 int front_offset;
174 int current_page;
175 int page_flipping;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700176
177 wait_queue_head_t irq_queue;
178 atomic_t irq_received;
Eric Anholted4cb412008-07-29 12:10:39 -0700179 /** Protects user_irq_refcount and irq_mask_reg */
180 spinlock_t user_irq_lock;
181 /** Refcount for i915_user_irq_get() versus i915_user_irq_put(). */
182 int user_irq_refcount;
183 /** Cached value of IMR to avoid reads in updating the bitfield */
184 u32 irq_mask_reg;
Keith Packard7c463582008-11-04 02:03:27 -0800185 u32 pipestat[2];
Zhenyu Wang036a4a72009-06-08 14:40:19 +0800186 /** splitted irq regs for graphics and display engine on IGDNG,
187 irq_mask_reg is still used for display irq. */
188 u32 gt_irq_mask_reg;
189 u32 gt_irq_enable_reg;
190 u32 de_irq_enable_reg;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700191
Jesse Barnes5ca58282009-03-31 14:11:15 -0700192 u32 hotplug_supported_mask;
193 struct work_struct hotplug_work;
194
Linus Torvalds1da177e2005-04-16 15:20:36 -0700195 int tex_lru_log_granularity;
196 int allow_batchbuffer;
197 struct mem_block *agp_heap;
Dave Airlie0d6aa602006-01-02 20:14:23 +1100198 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
Dave Airlie702880f2006-06-24 17:07:34 +1000199 int vblank_pipe;
=?utf-8?q?Michel_D=C3=A4nzer?=a6b54f32006-10-24 23:37:43 +1000200
Jesse Barnes79e53942008-11-07 14:24:08 -0800201 bool cursor_needs_physical;
202
203 struct drm_mm vram;
204
205 int irq_enabled;
206
Matthew Garrett8ee1c3d2008-08-05 19:37:25 +0100207 struct intel_opregion opregion;
208
Jesse Barnes79e53942008-11-07 14:24:08 -0800209 /* LVDS info */
210 int backlight_duty_cycle; /* restore backlight to this value */
211 bool panel_wants_dither;
212 struct drm_display_mode *panel_fixed_mode;
Ma Ling88631702009-05-13 11:19:55 +0800213 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
214 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
Jesse Barnes79e53942008-11-07 14:24:08 -0800215
216 /* Feature bits from the VBIOS */
Hannes Eder95281e32008-12-18 15:09:00 +0100217 unsigned int int_tv_support:1;
218 unsigned int lvds_dither:1;
219 unsigned int lvds_vbt:1;
220 unsigned int int_crt_support:1;
Kristian Høgsberg43565a02009-02-13 20:56:52 -0500221 unsigned int lvds_use_ssc:1;
Zhenyu Wang32f9d652009-07-24 01:00:32 +0800222 unsigned int edp_support:1;
Kristian Høgsberg43565a02009-02-13 20:56:52 -0500223 int lvds_ssc_freq;
Jesse Barnes79e53942008-11-07 14:24:08 -0800224
David Müller (ELSOFT AG)db545012009-08-29 08:54:45 +0200225 int crt_ddc_bus; /* -1 = unknown, else GPIO to use for CRT DDC */
Jesse Barnesde151cf2008-11-12 10:03:55 -0800226 struct drm_i915_fence_reg fence_regs[16]; /* assume 965 */
227 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
228 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
229
Shaohua Li7662c8b2009-06-26 11:23:55 +0800230 unsigned int fsb_freq, mem_freq;
231
Jesse Barnes63eeaf32009-06-18 16:56:52 -0700232 spinlock_t error_lock;
233 struct drm_i915_error_state *first_error;
Jesse Barnes8a905232009-07-11 16:48:03 -0400234 struct work_struct error_work;
Eric Anholt9c9fe1f2009-08-03 16:09:16 -0700235 struct workqueue_struct *wq;
Jesse Barnes63eeaf32009-06-18 16:56:52 -0700236
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000237 /* Register state */
238 u8 saveLBB;
239 u32 saveDSPACNTR;
240 u32 saveDSPBCNTR;
Keith Packarde948e992008-05-07 12:27:53 +1000241 u32 saveDSPARB;
Keith Packard881ee982008-11-02 23:08:44 -0800242 u32 saveRENDERSTANDBY;
Peng Li461cba22008-11-18 12:39:02 +0800243 u32 saveHWS;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000244 u32 savePIPEACONF;
245 u32 savePIPEBCONF;
246 u32 savePIPEASRC;
247 u32 savePIPEBSRC;
248 u32 saveFPA0;
249 u32 saveFPA1;
250 u32 saveDPLL_A;
251 u32 saveDPLL_A_MD;
252 u32 saveHTOTAL_A;
253 u32 saveHBLANK_A;
254 u32 saveHSYNC_A;
255 u32 saveVTOTAL_A;
256 u32 saveVBLANK_A;
257 u32 saveVSYNC_A;
258 u32 saveBCLRPAT_A;
Jesse Barnes0da3ea12008-02-20 09:39:58 +1000259 u32 savePIPEASTAT;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000260 u32 saveDSPASTRIDE;
261 u32 saveDSPASIZE;
262 u32 saveDSPAPOS;
Jesse Barnes585fb112008-07-29 11:54:06 -0700263 u32 saveDSPAADDR;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000264 u32 saveDSPASURF;
265 u32 saveDSPATILEOFF;
266 u32 savePFIT_PGM_RATIOS;
267 u32 saveBLC_PWM_CTL;
268 u32 saveBLC_PWM_CTL2;
269 u32 saveFPB0;
270 u32 saveFPB1;
271 u32 saveDPLL_B;
272 u32 saveDPLL_B_MD;
273 u32 saveHTOTAL_B;
274 u32 saveHBLANK_B;
275 u32 saveHSYNC_B;
276 u32 saveVTOTAL_B;
277 u32 saveVBLANK_B;
278 u32 saveVSYNC_B;
279 u32 saveBCLRPAT_B;
Jesse Barnes0da3ea12008-02-20 09:39:58 +1000280 u32 savePIPEBSTAT;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000281 u32 saveDSPBSTRIDE;
282 u32 saveDSPBSIZE;
283 u32 saveDSPBPOS;
Jesse Barnes585fb112008-07-29 11:54:06 -0700284 u32 saveDSPBADDR;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000285 u32 saveDSPBSURF;
286 u32 saveDSPBTILEOFF;
Jesse Barnes585fb112008-07-29 11:54:06 -0700287 u32 saveVGA0;
288 u32 saveVGA1;
289 u32 saveVGA_PD;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000290 u32 saveVGACNTRL;
291 u32 saveADPA;
292 u32 saveLVDS;
Jesse Barnes585fb112008-07-29 11:54:06 -0700293 u32 savePP_ON_DELAYS;
294 u32 savePP_OFF_DELAYS;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000295 u32 saveDVOA;
296 u32 saveDVOB;
297 u32 saveDVOC;
298 u32 savePP_ON;
299 u32 savePP_OFF;
300 u32 savePP_CONTROL;
Jesse Barnes585fb112008-07-29 11:54:06 -0700301 u32 savePP_DIVISOR;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000302 u32 savePFIT_CONTROL;
303 u32 save_palette_a[256];
304 u32 save_palette_b[256];
305 u32 saveFBC_CFB_BASE;
306 u32 saveFBC_LL_BASE;
307 u32 saveFBC_CONTROL;
308 u32 saveFBC_CONTROL2;
Jesse Barnes0da3ea12008-02-20 09:39:58 +1000309 u32 saveIER;
310 u32 saveIIR;
311 u32 saveIMR;
Keith Packard1f84e552008-02-16 19:19:29 -0800312 u32 saveCACHE_MODE_0;
Keith Packarde948e992008-05-07 12:27:53 +1000313 u32 saveD_STATE;
Jesse Barnes652c3932009-08-17 13:31:43 -0700314 u32 saveDSPCLK_GATE_D;
Keith Packard1f84e552008-02-16 19:19:29 -0800315 u32 saveMI_ARB_STATE;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000316 u32 saveSWF0[16];
317 u32 saveSWF1[16];
318 u32 saveSWF2[3];
319 u8 saveMSR;
320 u8 saveSR[8];
Jesse Barnes123f7942008-02-07 11:15:20 -0800321 u8 saveGR[25];
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000322 u8 saveAR_INDEX;
Jesse Barnesa59e1222008-05-07 12:25:46 +1000323 u8 saveAR[21];
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000324 u8 saveDACMASK;
Jesse Barnesa59e1222008-05-07 12:25:46 +1000325 u8 saveCR[37];
Keith Packard79f11c12009-04-30 14:43:44 -0700326 uint64_t saveFENCE[16];
Eric Anholt1fd1c622009-06-03 07:26:58 +0000327 u32 saveCURACNTR;
328 u32 saveCURAPOS;
329 u32 saveCURABASE;
330 u32 saveCURBCNTR;
331 u32 saveCURBPOS;
332 u32 saveCURBBASE;
333 u32 saveCURSIZE;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700334 u32 saveDP_B;
335 u32 saveDP_C;
336 u32 saveDP_D;
337 u32 savePIPEA_GMCH_DATA_M;
338 u32 savePIPEB_GMCH_DATA_M;
339 u32 savePIPEA_GMCH_DATA_N;
340 u32 savePIPEB_GMCH_DATA_N;
341 u32 savePIPEA_DP_LINK_M;
342 u32 savePIPEB_DP_LINK_M;
343 u32 savePIPEA_DP_LINK_N;
344 u32 savePIPEB_DP_LINK_N;
Eric Anholt673a3942008-07-30 12:06:12 -0700345
346 struct {
347 struct drm_mm gtt_space;
348
Keith Packard0839ccb2008-10-30 19:38:48 -0700349 struct io_mapping *gtt_mapping;
Eric Anholtab657db12009-01-23 12:57:47 -0800350 int gtt_mtrr;
Keith Packard0839ccb2008-10-30 19:38:48 -0700351
Eric Anholt673a3942008-07-30 12:06:12 -0700352 /**
353 * List of objects currently involved in rendering from the
354 * ringbuffer.
355 *
Eric Anholtce44b0e2008-11-06 16:00:31 -0800356 * Includes buffers having the contents of their GPU caches
357 * flushed, not necessarily primitives. last_rendering_seqno
358 * represents when the rendering involved will be completed.
359 *
Eric Anholt673a3942008-07-30 12:06:12 -0700360 * A reference is held on the buffer while on this list.
361 */
Carl Worth5e118f42009-03-20 11:54:25 -0700362 spinlock_t active_list_lock;
Eric Anholt673a3942008-07-30 12:06:12 -0700363 struct list_head active_list;
364
365 /**
366 * List of objects which are not in the ringbuffer but which
367 * still have a write_domain which needs to be flushed before
368 * unbinding.
369 *
Eric Anholtce44b0e2008-11-06 16:00:31 -0800370 * last_rendering_seqno is 0 while an object is in this list.
371 *
Eric Anholt673a3942008-07-30 12:06:12 -0700372 * A reference is held on the buffer while on this list.
373 */
374 struct list_head flushing_list;
375
376 /**
377 * LRU list of objects which are not in the ringbuffer and
378 * are ready to unbind, but are still in the GTT.
379 *
Eric Anholtce44b0e2008-11-06 16:00:31 -0800380 * last_rendering_seqno is 0 while an object is in this list.
381 *
Eric Anholt673a3942008-07-30 12:06:12 -0700382 * A reference is not held on the buffer while on this list,
383 * as merely being GTT-bound shouldn't prevent its being
384 * freed, and we'll pull it off the list in the free path.
385 */
386 struct list_head inactive_list;
387
Eric Anholta09ba7f2009-08-29 12:49:51 -0700388 /** LRU list of objects with fence regs on them. */
389 struct list_head fence_list;
390
Eric Anholt673a3942008-07-30 12:06:12 -0700391 /**
392 * List of breadcrumbs associated with GPU requests currently
393 * outstanding.
394 */
395 struct list_head request_list;
396
397 /**
398 * We leave the user IRQ off as much as possible,
399 * but this means that requests will finish and never
400 * be retired once the system goes idle. Set a timer to
401 * fire periodically while the ring is running. When it
402 * fires, go retire requests.
403 */
404 struct delayed_work retire_work;
405
406 uint32_t next_gem_seqno;
407
408 /**
409 * Waiting sequence number, if any
410 */
411 uint32_t waiting_gem_seqno;
412
413 /**
414 * Last seq seen at irq time
415 */
416 uint32_t irq_gem_seqno;
417
418 /**
419 * Flag if the X Server, and thus DRM, is not currently in
420 * control of the device.
421 *
422 * This is set between LeaveVT and EnterVT. It needs to be
423 * replaced with a semaphore. It also needs to be
424 * transitioned away from for kernel modesetting.
425 */
426 int suspended;
427
428 /**
429 * Flag if the hardware appears to be wedged.
430 *
431 * This is set when attempts to idle the device timeout.
432 * It prevents command submission from occuring and makes
433 * every pending request fail
434 */
435 int wedged;
436
437 /** Bit 6 swizzling required for X tiling */
438 uint32_t bit_6_swizzle_x;
439 /** Bit 6 swizzling required for Y tiling */
440 uint32_t bit_6_swizzle_y;
Dave Airlie71acb5e2008-12-30 20:31:46 +1000441
442 /* storage for physical objects */
443 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
Eric Anholt673a3942008-07-30 12:06:12 -0700444 } mm;
yakui_zhao9b9d1722009-05-31 17:17:17 +0800445 struct sdvo_device_mapping sdvo_mappings[2];
Jesse Barnes652c3932009-08-17 13:31:43 -0700446
447 /* Reclocking support */
448 bool render_reclock_avail;
449 bool lvds_downclock_avail;
450 struct work_struct idle_work;
451 struct timer_list idle_timer;
452 bool busy;
453 u16 orig_clock;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700454} drm_i915_private_t;
455
Eric Anholt673a3942008-07-30 12:06:12 -0700456/** driver private structure attached to each drm_gem_object */
457struct drm_i915_gem_object {
458 struct drm_gem_object *obj;
459
460 /** Current space allocated to this object in the GTT, if any. */
461 struct drm_mm_node *gtt_space;
462
463 /** This object's place on the active/flushing/inactive lists */
464 struct list_head list;
465
Eric Anholta09ba7f2009-08-29 12:49:51 -0700466 /** This object's place on the fenced object LRU */
467 struct list_head fence_list;
468
Eric Anholt673a3942008-07-30 12:06:12 -0700469 /**
470 * This is set if the object is on the active or flushing lists
471 * (has pending rendering), and is not set if it's on inactive (ready
472 * to be unbound).
473 */
474 int active;
475
476 /**
477 * This is set if the object has been written to since last bound
478 * to the GTT
479 */
480 int dirty;
481
482 /** AGP memory structure for our GTT binding. */
483 DRM_AGP_MEM *agp_mem;
484
Eric Anholt856fa192009-03-19 14:10:50 -0700485 struct page **pages;
486 int pages_refcount;
Eric Anholt673a3942008-07-30 12:06:12 -0700487
488 /**
489 * Current offset of the object in GTT space.
490 *
491 * This is the same as gtt_space->start
492 */
493 uint32_t gtt_offset;
Jesse Barnesde151cf2008-11-12 10:03:55 -0800494 /**
495 * Required alignment for the object
496 */
497 uint32_t gtt_alignment;
498 /**
499 * Fake offset for use by mmap(2)
500 */
501 uint64_t mmap_offset;
502
503 /**
504 * Fence register bits (if any) for this object. Will be set
505 * as needed when mapped into the GTT.
506 * Protected by dev->struct_mutex.
507 */
508 int fence_reg;
Eric Anholt673a3942008-07-30 12:06:12 -0700509
Eric Anholt673a3942008-07-30 12:06:12 -0700510 /** How many users have pinned this object in GTT space */
511 int pin_count;
512
513 /** Breadcrumb of last rendering to the buffer. */
514 uint32_t last_rendering_seqno;
515
516 /** Current tiling mode for the object. */
517 uint32_t tiling_mode;
Jesse Barnesde151cf2008-11-12 10:03:55 -0800518 uint32_t stride;
Eric Anholt673a3942008-07-30 12:06:12 -0700519
Eric Anholt280b7132009-03-12 16:56:27 -0700520 /** Record of address bit 17 of each page at last unbind. */
521 long *bit_17;
522
Keith Packardba1eb1d2008-10-14 19:55:10 -0700523 /** AGP mapping type (AGP_USER_MEMORY or AGP_USER_CACHED_MEMORY */
524 uint32_t agp_type;
525
Eric Anholt673a3942008-07-30 12:06:12 -0700526 /**
Eric Anholte47c68e2008-11-14 13:35:19 -0800527 * If present, while GEM_DOMAIN_CPU is in the read domain this array
528 * flags which individual pages are valid.
Eric Anholt673a3942008-07-30 12:06:12 -0700529 */
530 uint8_t *page_cpu_valid;
Jesse Barnes79e53942008-11-07 14:24:08 -0800531
532 /** User space pin count and filp owning the pin */
533 uint32_t user_pin_count;
534 struct drm_file *pin_filp;
Dave Airlie71acb5e2008-12-30 20:31:46 +1000535
536 /** for phy allocated objects */
537 struct drm_i915_gem_phys_object *phys_obj;
Kristian Høgsbergb70d11d2009-03-03 14:45:57 -0500538
539 /**
540 * Used for checking the object doesn't appear more than once
541 * in an execbuffer object list.
542 */
543 int in_execbuffer;
Eric Anholt673a3942008-07-30 12:06:12 -0700544};
545
546/**
547 * Request queue structure.
548 *
549 * The request queue allows us to note sequence numbers that have been emitted
550 * and may be associated with active buffers to be retired.
551 *
552 * By keeping this list, we can avoid having to do questionable
553 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
554 * an emission time with seqnos for tracking how far ahead of the GPU we are.
555 */
556struct drm_i915_gem_request {
557 /** GEM sequence number associated with this request. */
558 uint32_t seqno;
559
560 /** Time at which this request was emitted, in jiffies. */
561 unsigned long emitted_jiffies;
562
Eric Anholtb9624422009-06-03 07:27:35 +0000563 /** global list entry for this request */
Eric Anholt673a3942008-07-30 12:06:12 -0700564 struct list_head list;
Eric Anholtb9624422009-06-03 07:27:35 +0000565
566 /** file_priv list entry for this request */
567 struct list_head client_list;
Eric Anholt673a3942008-07-30 12:06:12 -0700568};
569
570struct drm_i915_file_private {
571 struct {
Eric Anholtb9624422009-06-03 07:27:35 +0000572 struct list_head request_list;
Eric Anholt673a3942008-07-30 12:06:12 -0700573 } mm;
574};
575
Jesse Barnes79e53942008-11-07 14:24:08 -0800576enum intel_chip_family {
577 CHIP_I8XX = 0x01,
578 CHIP_I9XX = 0x02,
579 CHIP_I915 = 0x04,
580 CHIP_I965 = 0x08,
581};
582
Eric Anholtc153f452007-09-03 12:06:45 +1000583extern struct drm_ioctl_desc i915_ioctls[];
Dave Airlieb3a83632005-09-30 18:37:36 +1000584extern int i915_max_ioctl;
Jesse Barnes79e53942008-11-07 14:24:08 -0800585extern unsigned int i915_fbpercrtc;
Jesse Barnes652c3932009-08-17 13:31:43 -0700586extern unsigned int i915_powersave;
Dave Airlieb3a83632005-09-30 18:37:36 +1000587
Dave Airlie7c1c2872008-11-28 14:22:24 +1000588extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
589extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
590
Linus Torvalds1da177e2005-04-16 15:20:36 -0700591 /* i915_dma.c */
Dave Airlie84b1fd12007-07-11 15:53:27 +1000592extern void i915_kernel_lost_context(struct drm_device * dev);
Dave Airlie22eae942005-11-10 22:16:34 +1100593extern int i915_driver_load(struct drm_device *, unsigned long flags);
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000594extern int i915_driver_unload(struct drm_device *);
Eric Anholt673a3942008-07-30 12:06:12 -0700595extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
Dave Airlie84b1fd12007-07-11 15:53:27 +1000596extern void i915_driver_lastclose(struct drm_device * dev);
Eric Anholt6c340ea2007-08-25 20:23:09 +1000597extern void i915_driver_preclose(struct drm_device *dev,
598 struct drm_file *file_priv);
Eric Anholt673a3942008-07-30 12:06:12 -0700599extern void i915_driver_postclose(struct drm_device *dev,
600 struct drm_file *file_priv);
Dave Airlie84b1fd12007-07-11 15:53:27 +1000601extern int i915_driver_device_is_agp(struct drm_device * dev);
Dave Airlie0d6aa602006-01-02 20:14:23 +1100602extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
603 unsigned long arg);
Eric Anholt673a3942008-07-30 12:06:12 -0700604extern int i915_emit_box(struct drm_device *dev,
Eric Anholt201361a2009-03-11 12:30:04 -0700605 struct drm_clip_rect *boxes,
Eric Anholt673a3942008-07-30 12:06:12 -0700606 int i, int DR1, int DR4);
Dave Airlieaf6061a2008-05-07 12:15:39 +1000607
Linus Torvalds1da177e2005-04-16 15:20:36 -0700608/* i915_irq.c */
Eric Anholtc153f452007-09-03 12:06:45 +1000609extern int i915_irq_emit(struct drm_device *dev, void *data,
610 struct drm_file *file_priv);
611extern int i915_irq_wait(struct drm_device *dev, void *data,
612 struct drm_file *file_priv);
Eric Anholt673a3942008-07-30 12:06:12 -0700613void i915_user_irq_get(struct drm_device *dev);
614void i915_user_irq_put(struct drm_device *dev);
Jesse Barnes79e53942008-11-07 14:24:08 -0800615extern void i915_enable_interrupt (struct drm_device *dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700616
617extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
Dave Airlie84b1fd12007-07-11 15:53:27 +1000618extern void i915_driver_irq_preinstall(struct drm_device * dev);
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700619extern int i915_driver_irq_postinstall(struct drm_device *dev);
Dave Airlie84b1fd12007-07-11 15:53:27 +1000620extern void i915_driver_irq_uninstall(struct drm_device * dev);
Eric Anholtc153f452007-09-03 12:06:45 +1000621extern int i915_vblank_pipe_set(struct drm_device *dev, void *data,
622 struct drm_file *file_priv);
623extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,
624 struct drm_file *file_priv);
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700625extern int i915_enable_vblank(struct drm_device *dev, int crtc);
626extern void i915_disable_vblank(struct drm_device *dev, int crtc);
627extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc);
Jesse Barnes9880b7a2009-02-06 10:22:41 -0800628extern u32 gm45_get_vblank_counter(struct drm_device *dev, int crtc);
Eric Anholtc153f452007-09-03 12:06:45 +1000629extern int i915_vblank_swap(struct drm_device *dev, void *data,
630 struct drm_file *file_priv);
Matthew Garrett8ee1c3d2008-08-05 19:37:25 +0100631extern void i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700632
Keith Packard7c463582008-11-04 02:03:27 -0800633void
634i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
635
636void
637i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
638
639
Linus Torvalds1da177e2005-04-16 15:20:36 -0700640/* i915_mem.c */
Eric Anholtc153f452007-09-03 12:06:45 +1000641extern int i915_mem_alloc(struct drm_device *dev, void *data,
642 struct drm_file *file_priv);
643extern int i915_mem_free(struct drm_device *dev, void *data,
644 struct drm_file *file_priv);
645extern int i915_mem_init_heap(struct drm_device *dev, void *data,
646 struct drm_file *file_priv);
647extern int i915_mem_destroy_heap(struct drm_device *dev, void *data,
648 struct drm_file *file_priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700649extern void i915_mem_takedown(struct mem_block **heap);
Dave Airlie84b1fd12007-07-11 15:53:27 +1000650extern void i915_mem_release(struct drm_device * dev,
Eric Anholt6c340ea2007-08-25 20:23:09 +1000651 struct drm_file *file_priv, struct mem_block *heap);
Eric Anholt673a3942008-07-30 12:06:12 -0700652/* i915_gem.c */
653int i915_gem_init_ioctl(struct drm_device *dev, void *data,
654 struct drm_file *file_priv);
655int i915_gem_create_ioctl(struct drm_device *dev, void *data,
656 struct drm_file *file_priv);
657int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
658 struct drm_file *file_priv);
659int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
660 struct drm_file *file_priv);
661int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
662 struct drm_file *file_priv);
Jesse Barnesde151cf2008-11-12 10:03:55 -0800663int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
664 struct drm_file *file_priv);
Eric Anholt673a3942008-07-30 12:06:12 -0700665int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
666 struct drm_file *file_priv);
667int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
668 struct drm_file *file_priv);
669int i915_gem_execbuffer(struct drm_device *dev, void *data,
670 struct drm_file *file_priv);
671int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
672 struct drm_file *file_priv);
673int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
674 struct drm_file *file_priv);
675int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
676 struct drm_file *file_priv);
677int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
678 struct drm_file *file_priv);
679int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
680 struct drm_file *file_priv);
681int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
682 struct drm_file *file_priv);
683int i915_gem_set_tiling(struct drm_device *dev, void *data,
684 struct drm_file *file_priv);
685int i915_gem_get_tiling(struct drm_device *dev, void *data,
686 struct drm_file *file_priv);
Eric Anholt5a125c32008-10-22 21:40:13 -0700687int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
688 struct drm_file *file_priv);
Eric Anholt673a3942008-07-30 12:06:12 -0700689void i915_gem_load(struct drm_device *dev);
Eric Anholt673a3942008-07-30 12:06:12 -0700690int i915_gem_init_object(struct drm_gem_object *obj);
691void i915_gem_free_object(struct drm_gem_object *obj);
692int i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment);
693void i915_gem_object_unpin(struct drm_gem_object *obj);
Jesse Barnes0f973f22009-01-26 17:10:45 -0800694int i915_gem_object_unbind(struct drm_gem_object *obj);
Eric Anholtd05ca302009-07-10 13:02:26 -0700695void i915_gem_release_mmap(struct drm_gem_object *obj);
Eric Anholt673a3942008-07-30 12:06:12 -0700696void i915_gem_lastclose(struct drm_device *dev);
697uint32_t i915_get_gem_seqno(struct drm_device *dev);
Chris Wilson8c4b8c32009-06-17 22:08:52 +0100698int i915_gem_object_get_fence_reg(struct drm_gem_object *obj);
Chris Wilson52dc7d32009-06-06 09:46:01 +0100699int i915_gem_object_put_fence_reg(struct drm_gem_object *obj);
Eric Anholt673a3942008-07-30 12:06:12 -0700700void i915_gem_retire_requests(struct drm_device *dev);
701void i915_gem_retire_work_handler(struct work_struct *work);
702void i915_gem_clflush_object(struct drm_gem_object *obj);
Jesse Barnes79e53942008-11-07 14:24:08 -0800703int i915_gem_object_set_domain(struct drm_gem_object *obj,
704 uint32_t read_domains,
705 uint32_t write_domain);
706int i915_gem_init_ringbuffer(struct drm_device *dev);
707void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
708int i915_gem_do_init(struct drm_device *dev, unsigned long start,
709 unsigned long end);
Jesse Barnes5669fca2009-02-17 15:13:31 -0800710int i915_gem_idle(struct drm_device *dev);
Jesse Barnesde151cf2008-11-12 10:03:55 -0800711int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
Jesse Barnes79e53942008-11-07 14:24:08 -0800712int i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj,
713 int write);
Dave Airlie71acb5e2008-12-30 20:31:46 +1000714int i915_gem_attach_phys_object(struct drm_device *dev,
715 struct drm_gem_object *obj, int id);
716void i915_gem_detach_phys_object(struct drm_device *dev,
717 struct drm_gem_object *obj);
718void i915_gem_free_all_phys_object(struct drm_device *dev);
Ben Gamari6911a9b2009-04-02 11:24:54 -0700719int i915_gem_object_get_pages(struct drm_gem_object *obj);
720void i915_gem_object_put_pages(struct drm_gem_object *obj);
Eric Anholt1fd1c622009-06-03 07:26:58 +0000721void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv);
Eric Anholt673a3942008-07-30 12:06:12 -0700722
723/* i915_gem_tiling.c */
724void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
Eric Anholt280b7132009-03-12 16:56:27 -0700725void i915_gem_object_do_bit_17_swizzle(struct drm_gem_object *obj);
726void i915_gem_object_save_bit_17_swizzle(struct drm_gem_object *obj);
Eric Anholt673a3942008-07-30 12:06:12 -0700727
728/* i915_gem_debug.c */
729void i915_gem_dump_object(struct drm_gem_object *obj, int len,
730 const char *where, uint32_t mark);
731#if WATCH_INACTIVE
732void i915_verify_inactive(struct drm_device *dev, char *file, int line);
733#else
734#define i915_verify_inactive(dev, file, line)
735#endif
736void i915_gem_object_check_coherency(struct drm_gem_object *obj, int handle);
737void i915_gem_dump_object(struct drm_gem_object *obj, int len,
738 const char *where, uint32_t mark);
739void i915_dump_lru(struct drm_device *dev, const char *where);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700740
Ben Gamari20172632009-02-17 20:08:50 -0500741/* i915_debugfs.c */
Ben Gamari27c202a2009-07-01 22:26:52 -0400742int i915_debugfs_init(struct drm_minor *minor);
743void i915_debugfs_cleanup(struct drm_minor *minor);
Ben Gamari20172632009-02-17 20:08:50 -0500744
Jesse Barnes317c35d2008-08-25 15:11:06 -0700745/* i915_suspend.c */
746extern int i915_save_state(struct drm_device *dev);
747extern int i915_restore_state(struct drm_device *dev);
748
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700749/* i915_suspend.c */
750extern int i915_save_state(struct drm_device *dev);
751extern int i915_restore_state(struct drm_device *dev);
752
Len Brown65e082c2008-10-24 17:18:10 -0400753#ifdef CONFIG_ACPI
Matthew Garrett8ee1c3d2008-08-05 19:37:25 +0100754/* i915_opregion.c */
Matthew Garrett74a365b2009-03-19 21:35:39 +0000755extern int intel_opregion_init(struct drm_device *dev, int resume);
Matthew Garrett3b1c1c12009-04-01 19:52:29 +0100756extern void intel_opregion_free(struct drm_device *dev, int suspend);
Matthew Garrett8ee1c3d2008-08-05 19:37:25 +0100757extern void opregion_asle_intr(struct drm_device *dev);
758extern void opregion_enable_asle(struct drm_device *dev);
Len Brown65e082c2008-10-24 17:18:10 -0400759#else
Len Brown03ae61d2009-03-28 01:41:14 -0400760static inline int intel_opregion_init(struct drm_device *dev, int resume) { return 0; }
Matthew Garrett3b1c1c12009-04-01 19:52:29 +0100761static inline void intel_opregion_free(struct drm_device *dev, int suspend) { return; }
Len Brown65e082c2008-10-24 17:18:10 -0400762static inline void opregion_asle_intr(struct drm_device *dev) { return; }
763static inline void opregion_enable_asle(struct drm_device *dev) { return; }
764#endif
Matthew Garrett8ee1c3d2008-08-05 19:37:25 +0100765
Jesse Barnes79e53942008-11-07 14:24:08 -0800766/* modesetting */
767extern void intel_modeset_init(struct drm_device *dev);
768extern void intel_modeset_cleanup(struct drm_device *dev);
769
Eric Anholt546b0972008-09-01 16:45:29 -0700770/**
771 * Lock test for when it's just for synchronization of ring access.
772 *
773 * In that case, we don't need to do it when GEM is initialized as nobody else
774 * has access to the ring.
775 */
776#define RING_LOCK_TEST_WITH_RETURN(dev, file_priv) do { \
777 if (((drm_i915_private_t *)dev->dev_private)->ring.ring_obj == NULL) \
778 LOCK_TEST_WITH_RETURN(dev, file_priv); \
779} while (0)
780
Eric Anholt3043c602008-10-02 12:24:47 -0700781#define I915_READ(reg) readl(dev_priv->regs + (reg))
782#define I915_WRITE(reg, val) writel(val, dev_priv->regs + (reg))
783#define I915_READ16(reg) readw(dev_priv->regs + (reg))
784#define I915_WRITE16(reg, val) writel(val, dev_priv->regs + (reg))
785#define I915_READ8(reg) readb(dev_priv->regs + (reg))
786#define I915_WRITE8(reg, val) writeb(val, dev_priv->regs + (reg))
Jesse Barnesde151cf2008-11-12 10:03:55 -0800787#define I915_WRITE64(reg, val) writeq(val, dev_priv->regs + (reg))
Keith Packard049ef7e2009-04-30 14:43:43 -0700788#define I915_READ64(reg) readq(dev_priv->regs + (reg))
Eric Anholt7d573822009-01-02 13:33:00 -0800789#define POSTING_READ(reg) (void)I915_READ(reg)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700790
791#define I915_VERBOSE 0
792
Chris Wilson0ef82af2009-09-05 18:07:06 +0100793#define RING_LOCALS volatile unsigned int *ring_virt__;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700794
Chris Wilson0ef82af2009-09-05 18:07:06 +0100795#define BEGIN_LP_RING(n) do { \
796 int bytes__ = 4*(n); \
797 if (I915_VERBOSE) DRM_DEBUG("BEGIN_LP_RING(%d)\n", (n)); \
798 /* a wrap must occur between instructions so pad beforehand */ \
799 if (unlikely (dev_priv->ring.tail + bytes__ > dev_priv->ring.Size)) \
800 i915_wrap_ring(dev); \
801 if (unlikely (dev_priv->ring.space < bytes__)) \
802 i915_wait_ring(dev, bytes__, __func__); \
803 ring_virt__ = (unsigned int *) \
804 (dev_priv->ring.virtual_start + dev_priv->ring.tail); \
805 dev_priv->ring.tail += bytes__; \
806 dev_priv->ring.tail &= dev_priv->ring.Size - 1; \
807 dev_priv->ring.space -= bytes__; \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700808} while (0)
809
Chris Wilson0ef82af2009-09-05 18:07:06 +0100810#define OUT_RING(n) do { \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700811 if (I915_VERBOSE) DRM_DEBUG(" OUT_RING %x\n", (int)(n)); \
Chris Wilson0ef82af2009-09-05 18:07:06 +0100812 *ring_virt__++ = (n); \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700813} while (0)
814
815#define ADVANCE_LP_RING() do { \
Chris Wilson0ef82af2009-09-05 18:07:06 +0100816 if (I915_VERBOSE) \
817 DRM_DEBUG("ADVANCE_LP_RING %x\n", dev_priv->ring.tail); \
818 I915_WRITE(PRB0_TAIL, dev_priv->ring.tail); \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700819} while(0)
820
Jesse Barnes585fb112008-07-29 11:54:06 -0700821/**
822 * Reads a dword out of the status page, which is written to from the command
823 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
824 * MI_STORE_DATA_IMM.
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000825 *
Jesse Barnes585fb112008-07-29 11:54:06 -0700826 * The following dwords have a reserved meaning:
Keith Packard0cdad7e2008-10-14 17:19:38 -0700827 * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
828 * 0x04: ring 0 head pointer
829 * 0x05: ring 1 head pointer (915-class)
830 * 0x06: ring 2 head pointer (915-class)
831 * 0x10-0x1b: Context status DWords (GM45)
832 * 0x1f: Last written status offset. (GM45)
Jesse Barnes585fb112008-07-29 11:54:06 -0700833 *
Keith Packard0cdad7e2008-10-14 17:19:38 -0700834 * The area from dword 0x20 to 0x3ff is available for driver usage.
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000835 */
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000836#define READ_HWSP(dev_priv, reg) (((volatile u32*)(dev_priv->hw_status_page))[reg])
Keith Packard0baf8232008-11-08 11:44:14 +1000837#define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
Keith Packard0cdad7e2008-10-14 17:19:38 -0700838#define I915_GEM_HWS_INDEX 0x20
Keith Packard0baf8232008-11-08 11:44:14 +1000839#define I915_BREADCRUMB_INDEX 0x21
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000840
Chris Wilson0ef82af2009-09-05 18:07:06 +0100841extern int i915_wrap_ring(struct drm_device * dev);
Jesse Barnes585fb112008-07-29 11:54:06 -0700842extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000843
844#define IS_I830(dev) ((dev)->pci_device == 0x3577)
845#define IS_845G(dev) ((dev)->pci_device == 0x2562)
846#define IS_I85X(dev) ((dev)->pci_device == 0x3582)
847#define IS_I855(dev) ((dev)->pci_device == 0x3582)
848#define IS_I865G(dev) ((dev)->pci_device == 0x2572)
849
Carlos Martín4d1f7882008-01-23 16:41:17 +1000850#define IS_I915G(dev) ((dev)->pci_device == 0x2582 || (dev)->pci_device == 0x258a)
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000851#define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
852#define IS_I945G(dev) ((dev)->pci_device == 0x2772)
Jesse Barnes3bf48462008-04-06 11:55:04 -0700853#define IS_I945GM(dev) ((dev)->pci_device == 0x27A2 ||\
854 (dev)->pci_device == 0x27AE)
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000855#define IS_I965G(dev) ((dev)->pci_device == 0x2972 || \
856 (dev)->pci_device == 0x2982 || \
857 (dev)->pci_device == 0x2992 || \
858 (dev)->pci_device == 0x29A2 || \
859 (dev)->pci_device == 0x2A02 || \
Zhenyu Wang5f5f9d42008-01-24 16:46:36 +1000860 (dev)->pci_device == 0x2A12 || \
Zhenyu Wangd3adbc02008-06-20 12:12:56 +1000861 (dev)->pci_device == 0x2A42 || \
862 (dev)->pci_device == 0x2E02 || \
863 (dev)->pci_device == 0x2E12 || \
Zhenyu Wang72021782008-11-17 13:58:11 +0800864 (dev)->pci_device == 0x2E22 || \
Zhenyu Wang280da222009-06-05 15:38:37 +0800865 (dev)->pci_device == 0x2E32 || \
866 (dev)->pci_device == 0x0042 || \
867 (dev)->pci_device == 0x0046)
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000868
Ma Lingc9ed4482009-05-13 15:08:27 +0800869#define IS_I965GM(dev) ((dev)->pci_device == 0x2A02 || \
870 (dev)->pci_device == 0x2A12)
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000871
Jesse Barnesb9bfdfe2008-08-25 15:16:19 -0700872#define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
Zhenyu Wang5f5f9d42008-01-24 16:46:36 +1000873
Zhenyu Wangd3adbc02008-06-20 12:12:56 +1000874#define IS_G4X(dev) ((dev)->pci_device == 0x2E02 || \
875 (dev)->pci_device == 0x2E12 || \
Eric Anholt60fd99e2008-12-03 22:50:02 -0800876 (dev)->pci_device == 0x2E22 || \
Zhenyu Wang72021782008-11-17 13:58:11 +0800877 (dev)->pci_device == 0x2E32 || \
Eric Anholt60fd99e2008-12-03 22:50:02 -0800878 IS_GM45(dev))
Zhenyu Wangd3adbc02008-06-20 12:12:56 +1000879
Shaohua Li21778322009-02-23 15:19:16 +0800880#define IS_IGDG(dev) ((dev)->pci_device == 0xa001)
881#define IS_IGDGM(dev) ((dev)->pci_device == 0xa011)
882#define IS_IGD(dev) (IS_IGDG(dev) || IS_IGDGM(dev))
883
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000884#define IS_G33(dev) ((dev)->pci_device == 0x29C2 || \
885 (dev)->pci_device == 0x29B2 || \
Shaohua Li21778322009-02-23 15:19:16 +0800886 (dev)->pci_device == 0x29D2 || \
887 (IS_IGD(dev)))
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000888
Zhenyu Wang280da222009-06-05 15:38:37 +0800889#define IS_IGDNG_D(dev) ((dev)->pci_device == 0x0042)
890#define IS_IGDNG_M(dev) ((dev)->pci_device == 0x0046)
891#define IS_IGDNG(dev) (IS_IGDNG_D(dev) || IS_IGDNG_M(dev))
892
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000893#define IS_I9XX(dev) (IS_I915G(dev) || IS_I915GM(dev) || IS_I945G(dev) || \
Zhenyu Wang280da222009-06-05 15:38:37 +0800894 IS_I945GM(dev) || IS_I965G(dev) || IS_G33(dev) || \
895 IS_IGDNG(dev))
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000896
897#define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \
Shaohua Li21778322009-02-23 15:19:16 +0800898 IS_I945GM(dev) || IS_I965GM(dev) || IS_GM45(dev) || \
Zhenyu Wang280da222009-06-05 15:38:37 +0800899 IS_IGD(dev) || IS_IGDNG_M(dev))
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000900
Zhenyu Wang280da222009-06-05 15:38:37 +0800901#define I915_NEED_GFX_HWS(dev) (IS_G33(dev) || IS_GM45(dev) || IS_G4X(dev) || \
902 IS_IGDNG(dev))
Jesse Barnes0f973f22009-01-26 17:10:45 -0800903/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
904 * rows, which changed the alignment requirements and fence programming.
905 */
906#define HAS_128_BYTE_Y_TILING(dev) (IS_I9XX(dev) && !(IS_I915G(dev) || \
907 IS_I915GM(dev)))
Zhenyu Wang280da222009-06-05 15:38:37 +0800908#define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_IGDNG(dev))
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700909#define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_IGDNG(dev))
Zhenyu Wang32f9d652009-07-24 01:00:32 +0800910#define SUPPORTS_EDP(dev) (IS_IGDNG_M(dev))
Jesse Barnes5ca58282009-03-31 14:11:15 -0700911#define I915_HAS_HOTPLUG(dev) (IS_I945G(dev) || IS_I945GM(dev) || IS_I965G(dev))
Shaohua Li7662c8b2009-06-26 11:23:55 +0800912/* dsparb controlled by hw only */
Zhenyu Wang22bd50c2009-07-06 17:27:52 +0800913#define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IGDNG(dev))
Zhenyu Wangb39d50e2008-02-19 20:59:09 +1000914
Jesse Barnes652c3932009-08-17 13:31:43 -0700915#define HAS_FW_BLC(dev) (IS_I9XX(dev) || IS_G4X(dev) || IS_IGDNG(dev))
916#define HAS_PIPE_CXSR(dev) (IS_G4X(dev) || IS_IGDNG(dev))
917
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000918#define PRIMARY_RINGBUFFER_SIZE (128*1024)
Dave Airlie0d6aa602006-01-02 20:14:23 +1100919
Linus Torvalds1da177e2005-04-16 15:20:36 -0700920#endif