Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 1 | # Put here option for CPU selection and depending optimization |
| 2 | if !X86_ELAN |
| 3 | |
| 4 | choice |
| 5 | prompt "Processor family" |
| 6 | default M686 |
| 7 | |
| 8 | config M386 |
| 9 | bool "386" |
Paolo 'Blaisorblade' Giarrusso | 1b4ad24 | 2006-10-11 01:21:35 -0700 | [diff] [blame] | 10 | depends on !UML |
Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 11 | ---help--- |
| 12 | This is the processor type of your CPU. This information is used for |
| 13 | optimizing purposes. In order to compile a kernel that can run on |
| 14 | all x86 CPU types (albeit not optimally fast), you can specify |
| 15 | "386" here. |
| 16 | |
| 17 | The kernel will not necessarily run on earlier architectures than |
| 18 | the one you have chosen, e.g. a Pentium optimized kernel will run on |
| 19 | a PPro, but not necessarily on a i486. |
| 20 | |
| 21 | Here are the settings recommended for greatest speed: |
| 22 | - "386" for the AMD/Cyrix/Intel 386DX/DXL/SL/SLC/SX, Cyrix/TI |
| 23 | 486DLC/DLC2, UMC 486SX-S and NexGen Nx586. Only "386" kernels |
| 24 | will run on a 386 class machine. |
| 25 | - "486" for the AMD/Cyrix/IBM/Intel 486DX/DX2/DX4 or |
| 26 | SL/SLC/SLC2/SLC3/SX/SX2 and UMC U5D or U5S. |
| 27 | - "586" for generic Pentium CPUs lacking the TSC |
| 28 | (time stamp counter) register. |
| 29 | - "Pentium-Classic" for the Intel Pentium. |
| 30 | - "Pentium-MMX" for the Intel Pentium MMX. |
| 31 | - "Pentium-Pro" for the Intel Pentium Pro. |
| 32 | - "Pentium-II" for the Intel Pentium II or pre-Coppermine Celeron. |
| 33 | - "Pentium-III" for the Intel Pentium III or Coppermine Celeron. |
| 34 | - "Pentium-4" for the Intel Pentium 4 or P4-based Celeron. |
| 35 | - "K6" for the AMD K6, K6-II and K6-III (aka K6-3D). |
| 36 | - "Athlon" for the AMD K7 family (Athlon/Duron/Thunderbird). |
| 37 | - "Crusoe" for the Transmeta Crusoe series. |
| 38 | - "Efficeon" for the Transmeta Efficeon series. |
| 39 | - "Winchip-C6" for original IDT Winchip. |
| 40 | - "Winchip-2" for IDT Winchip 2. |
| 41 | - "Winchip-2A" for IDT Winchips with 3dNow! capabilities. |
| 42 | - "GeodeGX1" for Geode GX1 (Cyrix MediaGX). |
Jordan Crouse | f90b811 | 2006-01-06 00:12:14 -0800 | [diff] [blame] | 43 | - "Geode GX/LX" For AMD Geode GX and LX processors. |
Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 44 | - "CyrixIII/VIA C3" for VIA Cyrix III or VIA C3. |
Egry Gabor | 48a1204 | 2006-06-26 18:47:15 +0200 | [diff] [blame] | 45 | - "VIA C3-2" for VIA C3-2 "Nehemiah" (model 9 and above). |
Simon Arlott | 0949be3 | 2007-05-02 19:27:05 +0200 | [diff] [blame] | 46 | - "VIA C7" for VIA C7. |
Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 47 | |
| 48 | If you don't know what to do, choose "386". |
| 49 | |
| 50 | config M486 |
| 51 | bool "486" |
| 52 | help |
| 53 | Select this for a 486 series processor, either Intel or one of the |
| 54 | compatible processors from AMD, Cyrix, IBM, or Intel. Includes DX, |
| 55 | DX2, and DX4 variants; also SL/SLC/SLC2/SLC3/SX/SX2 and UMC U5D or |
| 56 | U5S. |
| 57 | |
| 58 | config M586 |
| 59 | bool "586/K5/5x86/6x86/6x86MX" |
| 60 | help |
| 61 | Select this for an 586 or 686 series processor such as the AMD K5, |
| 62 | the Cyrix 5x86, 6x86 and 6x86MX. This choice does not |
| 63 | assume the RDTSC (Read Time Stamp Counter) instruction. |
| 64 | |
| 65 | config M586TSC |
| 66 | bool "Pentium-Classic" |
| 67 | help |
| 68 | Select this for a Pentium Classic processor with the RDTSC (Read |
| 69 | Time Stamp Counter) instruction for benchmarking. |
| 70 | |
| 71 | config M586MMX |
| 72 | bool "Pentium-MMX" |
| 73 | help |
| 74 | Select this for a Pentium with the MMX graphics/multimedia |
| 75 | extended instructions. |
| 76 | |
| 77 | config M686 |
| 78 | bool "Pentium-Pro" |
| 79 | help |
| 80 | Select this for Intel Pentium Pro chips. This enables the use of |
| 81 | Pentium Pro extended instructions, and disables the init-time guard |
| 82 | against the f00f bug found in earlier Pentiums. |
| 83 | |
| 84 | config MPENTIUMII |
| 85 | bool "Pentium-II/Celeron(pre-Coppermine)" |
| 86 | help |
| 87 | Select this for Intel chips based on the Pentium-II and |
| 88 | pre-Coppermine Celeron core. This option enables an unaligned |
| 89 | copy optimization, compiles the kernel with optimization flags |
| 90 | tailored for the chip, and applies any applicable Pentium Pro |
| 91 | optimizations. |
| 92 | |
| 93 | config MPENTIUMIII |
| 94 | bool "Pentium-III/Celeron(Coppermine)/Pentium-III Xeon" |
| 95 | help |
| 96 | Select this for Intel chips based on the Pentium-III and |
| 97 | Celeron-Coppermine core. This option enables use of some |
| 98 | extended prefetch instructions in addition to the Pentium II |
| 99 | extensions. |
| 100 | |
| 101 | config MPENTIUMM |
| 102 | bool "Pentium M" |
| 103 | help |
| 104 | Select this for Intel Pentium M (not Pentium-4 M) |
| 105 | notebook chips. |
| 106 | |
Andi Kleen | c55d92d | 2006-12-07 02:14:09 +0100 | [diff] [blame] | 107 | config MCORE2 |
| 108 | bool "Core 2/newer Xeon" |
| 109 | help |
| 110 | Select this for Intel Core 2 and newer Core 2 Xeons (Xeon 51xx and 53xx) |
David Sterba | 3dde6ad | 2007-05-09 07:12:20 +0200 | [diff] [blame] | 111 | CPUs. You can distinguish newer from older Xeons by the CPU family |
Andi Kleen | c55d92d | 2006-12-07 02:14:09 +0100 | [diff] [blame] | 112 | in /proc/cpuinfo. Newer ones have 6. |
| 113 | |
Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 114 | config MPENTIUM4 |
Andi Kleen | c55d92d | 2006-12-07 02:14:09 +0100 | [diff] [blame] | 115 | bool "Pentium-4/Celeron(P4-based)/Pentium-4 M/older Xeon" |
Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 116 | help |
| 117 | Select this for Intel Pentium 4 chips. This includes the |
| 118 | Pentium 4, P4-based Celeron and Xeon, and Pentium-4 M |
| 119 | (not Pentium M) chips. This option enables compile flags |
| 120 | optimized for the chip, uses the correct cache shift, and |
| 121 | applies any applicable Pentium III optimizations. |
| 122 | |
| 123 | config MK6 |
| 124 | bool "K6/K6-II/K6-III" |
| 125 | help |
| 126 | Select this for an AMD K6-family processor. Enables use of |
| 127 | some extended instructions, and passes appropriate optimization |
| 128 | flags to GCC. |
| 129 | |
| 130 | config MK7 |
| 131 | bool "Athlon/Duron/K7" |
| 132 | help |
| 133 | Select this for an AMD Athlon K7-family processor. Enables use of |
| 134 | some extended instructions, and passes appropriate optimization |
| 135 | flags to GCC. |
| 136 | |
| 137 | config MK8 |
| 138 | bool "Opteron/Athlon64/Hammer/K8" |
| 139 | help |
| 140 | Select this for an AMD Opteron or Athlon64 Hammer-family processor. Enables |
| 141 | use of some extended instructions, and passes appropriate optimization |
| 142 | flags to GCC. |
| 143 | |
| 144 | config MCRUSOE |
| 145 | bool "Crusoe" |
| 146 | help |
| 147 | Select this for a Transmeta Crusoe processor. Treats the processor |
| 148 | like a 586 with TSC, and sets some GCC optimization flags (like a |
| 149 | Pentium Pro with no alignment requirements). |
| 150 | |
| 151 | config MEFFICEON |
| 152 | bool "Efficeon" |
| 153 | help |
| 154 | Select this for a Transmeta Efficeon processor. |
| 155 | |
| 156 | config MWINCHIPC6 |
| 157 | bool "Winchip-C6" |
| 158 | help |
| 159 | Select this for an IDT Winchip C6 chip. Linux and GCC |
| 160 | treat this chip as a 586TSC with some extended instructions |
| 161 | and alignment requirements. |
| 162 | |
| 163 | config MWINCHIP2 |
| 164 | bool "Winchip-2" |
| 165 | help |
| 166 | Select this for an IDT Winchip-2. Linux and GCC |
| 167 | treat this chip as a 586TSC with some extended instructions |
| 168 | and alignment requirements. |
| 169 | |
| 170 | config MWINCHIP3D |
| 171 | bool "Winchip-2A/Winchip-3" |
| 172 | help |
| 173 | Select this for an IDT Winchip-2A or 3. Linux and GCC |
| 174 | treat this chip as a 586TSC with some extended instructions |
David Sterba | 3dde6ad | 2007-05-09 07:12:20 +0200 | [diff] [blame] | 175 | and alignment requirements. Also enable out of order memory |
Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 176 | stores for this CPU, which can increase performance of some |
| 177 | operations. |
| 178 | |
| 179 | config MGEODEGX1 |
| 180 | bool "GeodeGX1" |
| 181 | help |
| 182 | Select this for a Geode GX1 (Cyrix MediaGX) chip. |
| 183 | |
Jordan Crouse | f90b811 | 2006-01-06 00:12:14 -0800 | [diff] [blame] | 184 | config MGEODE_LX |
| 185 | bool "Geode GX/LX" |
| 186 | help |
| 187 | Select this for AMD Geode GX and LX processors. |
| 188 | |
Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 189 | config MCYRIXIII |
| 190 | bool "CyrixIII/VIA-C3" |
| 191 | help |
| 192 | Select this for a Cyrix III or C3 chip. Presently Linux and GCC |
| 193 | treat this chip as a generic 586. Whilst the CPU is 686 class, |
| 194 | it lacks the cmov extension which gcc assumes is present when |
| 195 | generating 686 code. |
| 196 | Note that Nehemiah (Model 9) and above will not boot with this |
| 197 | kernel due to them lacking the 3DNow! instructions used in earlier |
| 198 | incarnations of the CPU. |
| 199 | |
| 200 | config MVIAC3_2 |
| 201 | bool "VIA C3-2 (Nehemiah)" |
| 202 | help |
| 203 | Select this for a VIA C3 "Nehemiah". Selecting this enables usage |
| 204 | of SSE and tells gcc to treat the CPU as a 686. |
| 205 | Note, this kernel will not boot on older (pre model 9) C3s. |
| 206 | |
Simon Arlott | 0949be3 | 2007-05-02 19:27:05 +0200 | [diff] [blame] | 207 | config MVIAC7 |
| 208 | bool "VIA C7" |
| 209 | help |
| 210 | Select this for a VIA C7. Selecting this uses the correct cache |
| 211 | shift and tells gcc to treat the CPU as a 686. |
| 212 | |
Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 213 | endchoice |
| 214 | |
| 215 | config X86_GENERIC |
| 216 | bool "Generic x86 support" |
| 217 | help |
| 218 | Instead of just including optimizations for the selected |
| 219 | x86 variant (e.g. PII, Crusoe or Athlon), include some more |
| 220 | generic optimizations as well. This will make the kernel |
| 221 | perform better on x86 CPUs other than that selected. |
| 222 | |
| 223 | This is really intended for distributors who need more |
| 224 | generic optimizations. |
| 225 | |
| 226 | endif |
| 227 | |
| 228 | # |
| 229 | # Define implied options from the CPU selection here |
| 230 | # |
| 231 | config X86_CMPXCHG |
| 232 | bool |
| 233 | depends on !M386 |
| 234 | default y |
| 235 | |
Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 236 | config X86_L1_CACHE_SHIFT |
| 237 | int |
| 238 | default "7" if MPENTIUM4 || X86_GENERIC |
Jordan Crouse | f90b811 | 2006-01-06 00:12:14 -0800 | [diff] [blame] | 239 | default "4" if X86_ELAN || M486 || M386 || MGEODEGX1 |
| 240 | default "5" if MWINCHIP3D || MWINCHIP2 || MWINCHIPC6 || MCRUSOE || MEFFICEON || MCYRIXIII || MK6 || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || M586 || MVIAC3_2 || MGEODE_LX |
Simon Arlott | 0949be3 | 2007-05-02 19:27:05 +0200 | [diff] [blame] | 241 | default "6" if MK7 || MK8 || MPENTIUMM || MCORE2 || MVIAC7 |
Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 242 | |
Andi Kleen | c7f81c9 | 2007-05-02 19:27:20 +0200 | [diff] [blame] | 243 | config X86_XADD |
| 244 | bool |
| 245 | depends on !M386 |
| 246 | default y |
| 247 | |
Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 248 | config RWSEM_GENERIC_SPINLOCK |
| 249 | bool |
Andi Kleen | c7f81c9 | 2007-05-02 19:27:20 +0200 | [diff] [blame] | 250 | depends on !X86_XADD |
Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 251 | default y |
| 252 | |
| 253 | config RWSEM_XCHGADD_ALGORITHM |
| 254 | bool |
Andi Kleen | c7f81c9 | 2007-05-02 19:27:20 +0200 | [diff] [blame] | 255 | depends on X86_XADD |
Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 256 | default y |
| 257 | |
David Howells | f0d1b0b | 2006-12-08 02:37:49 -0800 | [diff] [blame] | 258 | config ARCH_HAS_ILOG2_U32 |
| 259 | bool |
| 260 | default n |
| 261 | |
| 262 | config ARCH_HAS_ILOG2_U64 |
| 263 | bool |
| 264 | default n |
| 265 | |
Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 266 | config GENERIC_CALIBRATE_DELAY |
| 267 | bool |
| 268 | default y |
| 269 | |
| 270 | config X86_PPRO_FENCE |
| 271 | bool |
| 272 | depends on M686 || M586MMX || M586TSC || M586 || M486 || M386 || MGEODEGX1 |
| 273 | default y |
| 274 | |
| 275 | config X86_F00F_BUG |
| 276 | bool |
| 277 | depends on M586MMX || M586TSC || M586 || M486 || M386 |
| 278 | default y |
| 279 | |
| 280 | config X86_WP_WORKS_OK |
| 281 | bool |
| 282 | depends on !M386 |
| 283 | default y |
| 284 | |
| 285 | config X86_INVLPG |
| 286 | bool |
| 287 | depends on !M386 |
| 288 | default y |
| 289 | |
| 290 | config X86_BSWAP |
| 291 | bool |
| 292 | depends on !M386 |
| 293 | default y |
| 294 | |
| 295 | config X86_POPAD_OK |
| 296 | bool |
| 297 | depends on !M386 |
| 298 | default y |
| 299 | |
| 300 | config X86_CMPXCHG64 |
| 301 | bool |
Andi Kleen | 9d9bbd4 | 2007-06-23 02:29:23 +0200 | [diff] [blame] | 302 | depends on X86_PAE |
Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 303 | default y |
| 304 | |
| 305 | config X86_ALIGNMENT_16 |
| 306 | bool |
| 307 | depends on MWINCHIP3D || MWINCHIP2 || MWINCHIPC6 || MCYRIXIII || X86_ELAN || MK6 || M586MMX || M586TSC || M586 || M486 || MVIAC3_2 || MGEODEGX1 |
| 308 | default y |
| 309 | |
| 310 | config X86_GOOD_APIC |
| 311 | bool |
Simon Arlott | 0949be3 | 2007-05-02 19:27:05 +0200 | [diff] [blame] | 312 | depends on MK7 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || MK8 || MEFFICEON || MCORE2 || MVIAC7 |
Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 313 | default y |
| 314 | |
| 315 | config X86_INTEL_USERCOPY |
| 316 | bool |
Andi Kleen | c55d92d | 2006-12-07 02:14:09 +0100 | [diff] [blame] | 317 | depends on MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M586MMX || X86_GENERIC || MK8 || MK7 || MEFFICEON || MCORE2 |
Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 318 | default y |
| 319 | |
| 320 | config X86_USE_PPRO_CHECKSUM |
| 321 | bool |
Andi Kleen | c55d92d | 2006-12-07 02:14:09 +0100 | [diff] [blame] | 322 | depends on MWINCHIP3D || MWINCHIP2 || MWINCHIPC6 || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MK8 || MVIAC3_2 || MEFFICEON || MGEODE_LX || MCORE2 |
Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 323 | default y |
| 324 | |
| 325 | config X86_USE_3DNOW |
| 326 | bool |
Paolo 'Blaisorblade' Giarrusso | 1b4ad24 | 2006-10-11 01:21:35 -0700 | [diff] [blame] | 327 | depends on (MCYRIXIII || MK7 || MGEODE_LX) && !UML |
Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 328 | default y |
| 329 | |
| 330 | config X86_OOSTORE |
| 331 | bool |
| 332 | depends on (MWINCHIP3D || MWINCHIP2 || MWINCHIPC6) && MTRR |
| 333 | default y |
| 334 | |
| 335 | config X86_TSC |
| 336 | bool |
Simon Arlott | 0949be3 | 2007-05-02 19:27:05 +0200 | [diff] [blame] | 337 | depends on (MWINCHIP3D || MWINCHIP2 || MCRUSOE || MEFFICEON || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || MK8 || MVIAC3_2 || MVIAC7 || MGEODEGX1 || MGEODE_LX || MCORE2) && !X86_NUMAQ |
Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 338 | default y |
Andi Kleen | c7f81c9 | 2007-05-02 19:27:20 +0200 | [diff] [blame] | 339 | |
| 340 | # this should be set for all -march=.. options where the compiler |
| 341 | # generates cmov. |
| 342 | config X86_CMOV |
| 343 | bool |
| 344 | depends on (MK7 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MVIAC3_2 || MVIAC7) |
| 345 | default y |
| 346 | |
| 347 | config X86_MINIMUM_CPU_MODEL |
| 348 | int |
| 349 | default "4" if X86_XADD || X86_CMPXCHG || X86_BSWAP |
| 350 | default "0" |
| 351 | |