Sarah Sharp | 74c6874 | 2009-04-27 19:52:22 -0700 | [diff] [blame] | 1 | /* |
| 2 | * xHCI host controller driver |
| 3 | * |
| 4 | * Copyright (C) 2008 Intel Corp. |
| 5 | * |
| 6 | * Author: Sarah Sharp |
| 7 | * Some code borrowed from the Linux EHCI driver. |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License version 2 as |
| 11 | * published by the Free Software Foundation. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, but |
| 14 | * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY |
| 15 | * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
| 16 | * for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software Foundation, |
| 20 | * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
| 21 | */ |
| 22 | |
| 23 | #ifndef __LINUX_XHCI_HCD_H |
| 24 | #define __LINUX_XHCI_HCD_H |
| 25 | |
| 26 | #include <linux/usb.h> |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 27 | #include <linux/timer.h> |
Sarah Sharp | 8e595a5 | 2009-07-27 12:03:31 -0700 | [diff] [blame] | 28 | #include <linux/kernel.h> |
Eric Lescouet | 27729aa | 2010-04-24 23:21:52 +0200 | [diff] [blame] | 29 | #include <linux/usb/hcd.h> |
Sarah Sharp | 74c6874 | 2009-04-27 19:52:22 -0700 | [diff] [blame] | 30 | |
Sarah Sharp | 74c6874 | 2009-04-27 19:52:22 -0700 | [diff] [blame] | 31 | /* Code sharing between pci-quirks and xhci hcd */ |
| 32 | #include "xhci-ext-caps.h" |
| 33 | |
| 34 | /* xHCI PCI Configuration Registers */ |
| 35 | #define XHCI_SBRN_OFFSET (0x60) |
| 36 | |
Sarah Sharp | 66d4ead | 2009-04-27 19:52:28 -0700 | [diff] [blame] | 37 | /* Max number of USB devices for any host controller - limit in section 6.1 */ |
| 38 | #define MAX_HC_SLOTS 256 |
Sarah Sharp | 0f2a793 | 2009-04-27 19:57:12 -0700 | [diff] [blame] | 39 | /* Section 5.3.3 - MaxPorts */ |
| 40 | #define MAX_HC_PORTS 127 |
Sarah Sharp | 66d4ead | 2009-04-27 19:52:28 -0700 | [diff] [blame] | 41 | |
Sarah Sharp | 74c6874 | 2009-04-27 19:52:22 -0700 | [diff] [blame] | 42 | /* |
| 43 | * xHCI register interface. |
| 44 | * This corresponds to the eXtensible Host Controller Interface (xHCI) |
| 45 | * Revision 0.95 specification |
Sarah Sharp | 74c6874 | 2009-04-27 19:52:22 -0700 | [diff] [blame] | 46 | */ |
| 47 | |
| 48 | /** |
| 49 | * struct xhci_cap_regs - xHCI Host Controller Capability Registers. |
| 50 | * @hc_capbase: length of the capabilities register and HC version number |
| 51 | * @hcs_params1: HCSPARAMS1 - Structural Parameters 1 |
| 52 | * @hcs_params2: HCSPARAMS2 - Structural Parameters 2 |
| 53 | * @hcs_params3: HCSPARAMS3 - Structural Parameters 3 |
| 54 | * @hcc_params: HCCPARAMS - Capability Parameters |
| 55 | * @db_off: DBOFF - Doorbell array offset |
| 56 | * @run_regs_off: RTSOFF - Runtime register space offset |
| 57 | */ |
| 58 | struct xhci_cap_regs { |
| 59 | u32 hc_capbase; |
| 60 | u32 hcs_params1; |
| 61 | u32 hcs_params2; |
| 62 | u32 hcs_params3; |
| 63 | u32 hcc_params; |
| 64 | u32 db_off; |
| 65 | u32 run_regs_off; |
| 66 | /* Reserved up to (CAPLENGTH - 0x1C) */ |
Sarah Sharp | 9844197 | 2009-05-14 11:44:18 -0700 | [diff] [blame] | 67 | }; |
Sarah Sharp | 74c6874 | 2009-04-27 19:52:22 -0700 | [diff] [blame] | 68 | |
| 69 | /* hc_capbase bitmasks */ |
| 70 | /* bits 7:0 - how long is the Capabilities register */ |
| 71 | #define HC_LENGTH(p) XHCI_HC_LENGTH(p) |
| 72 | /* bits 31:16 */ |
| 73 | #define HC_VERSION(p) (((p) >> 16) & 0xffff) |
| 74 | |
| 75 | /* HCSPARAMS1 - hcs_params1 - bitmasks */ |
| 76 | /* bits 0:7, Max Device Slots */ |
| 77 | #define HCS_MAX_SLOTS(p) (((p) >> 0) & 0xff) |
| 78 | #define HCS_SLOTS_MASK 0xff |
| 79 | /* bits 8:18, Max Interrupters */ |
| 80 | #define HCS_MAX_INTRS(p) (((p) >> 8) & 0x7ff) |
| 81 | /* bits 24:31, Max Ports - max value is 0x7F = 127 ports */ |
| 82 | #define HCS_MAX_PORTS(p) (((p) >> 24) & 0x7f) |
| 83 | |
| 84 | /* HCSPARAMS2 - hcs_params2 - bitmasks */ |
| 85 | /* bits 0:3, frames or uframes that SW needs to queue transactions |
| 86 | * ahead of the HW to meet periodic deadlines */ |
| 87 | #define HCS_IST(p) (((p) >> 0) & 0xf) |
| 88 | /* bits 4:7, max number of Event Ring segments */ |
| 89 | #define HCS_ERST_MAX(p) (((p) >> 4) & 0xf) |
| 90 | /* bit 26 Scratchpad restore - for save/restore HW state - not used yet */ |
| 91 | /* bits 27:31 number of Scratchpad buffers SW must allocate for the HW */ |
John Youn | 254c80a | 2009-07-27 12:05:03 -0700 | [diff] [blame] | 92 | #define HCS_MAX_SCRATCHPAD(p) (((p) >> 27) & 0x1f) |
Sarah Sharp | 74c6874 | 2009-04-27 19:52:22 -0700 | [diff] [blame] | 93 | |
| 94 | /* HCSPARAMS3 - hcs_params3 - bitmasks */ |
| 95 | /* bits 0:7, Max U1 to U0 latency for the roothub ports */ |
| 96 | #define HCS_U1_LATENCY(p) (((p) >> 0) & 0xff) |
| 97 | /* bits 16:31, Max U2 to U0 latency for the roothub ports */ |
| 98 | #define HCS_U2_LATENCY(p) (((p) >> 16) & 0xffff) |
| 99 | |
| 100 | /* HCCPARAMS - hcc_params - bitmasks */ |
| 101 | /* true: HC can use 64-bit address pointers */ |
| 102 | #define HCC_64BIT_ADDR(p) ((p) & (1 << 0)) |
| 103 | /* true: HC can do bandwidth negotiation */ |
| 104 | #define HCC_BANDWIDTH_NEG(p) ((p) & (1 << 1)) |
| 105 | /* true: HC uses 64-byte Device Context structures |
| 106 | * FIXME 64-byte context structures aren't supported yet. |
| 107 | */ |
| 108 | #define HCC_64BYTE_CONTEXT(p) ((p) & (1 << 2)) |
| 109 | /* true: HC has port power switches */ |
| 110 | #define HCC_PPC(p) ((p) & (1 << 3)) |
| 111 | /* true: HC has port indicators */ |
| 112 | #define HCS_INDICATOR(p) ((p) & (1 << 4)) |
| 113 | /* true: HC has Light HC Reset Capability */ |
| 114 | #define HCC_LIGHT_RESET(p) ((p) & (1 << 5)) |
| 115 | /* true: HC supports latency tolerance messaging */ |
| 116 | #define HCC_LTC(p) ((p) & (1 << 6)) |
| 117 | /* true: no secondary Stream ID Support */ |
| 118 | #define HCC_NSS(p) ((p) & (1 << 7)) |
| 119 | /* Max size for Primary Stream Arrays - 2^(n+1), where n is bits 12:15 */ |
Sarah Sharp | 8df75f4 | 2010-04-02 15:34:16 -0700 | [diff] [blame] | 120 | #define HCC_MAX_PSA(p) (1 << ((((p) >> 12) & 0xf) + 1)) |
Sarah Sharp | 74c6874 | 2009-04-27 19:52:22 -0700 | [diff] [blame] | 121 | /* Extended Capabilities pointer from PCI base - section 5.3.6 */ |
| 122 | #define HCC_EXT_CAPS(p) XHCI_HCC_EXT_CAPS(p) |
| 123 | |
| 124 | /* db_off bitmask - bits 0:1 reserved */ |
| 125 | #define DBOFF_MASK (~0x3) |
| 126 | |
| 127 | /* run_regs_off bitmask - bits 0:4 reserved */ |
| 128 | #define RTSOFF_MASK (~0x1f) |
| 129 | |
| 130 | |
| 131 | /* Number of registers per port */ |
| 132 | #define NUM_PORT_REGS 4 |
| 133 | |
| 134 | /** |
| 135 | * struct xhci_op_regs - xHCI Host Controller Operational Registers. |
| 136 | * @command: USBCMD - xHC command register |
| 137 | * @status: USBSTS - xHC status register |
| 138 | * @page_size: This indicates the page size that the host controller |
| 139 | * supports. If bit n is set, the HC supports a page size |
| 140 | * of 2^(n+12), up to a 128MB page size. |
| 141 | * 4K is the minimum page size. |
| 142 | * @cmd_ring: CRP - 64-bit Command Ring Pointer |
| 143 | * @dcbaa_ptr: DCBAAP - 64-bit Device Context Base Address Array Pointer |
| 144 | * @config_reg: CONFIG - Configure Register |
| 145 | * @port_status_base: PORTSCn - base address for Port Status and Control |
| 146 | * Each port has a Port Status and Control register, |
| 147 | * followed by a Port Power Management Status and Control |
| 148 | * register, a Port Link Info register, and a reserved |
| 149 | * register. |
| 150 | * @port_power_base: PORTPMSCn - base address for |
| 151 | * Port Power Management Status and Control |
| 152 | * @port_link_base: PORTLIn - base address for Port Link Info (current |
| 153 | * Link PM state and control) for USB 2.1 and USB 3.0 |
| 154 | * devices. |
| 155 | */ |
| 156 | struct xhci_op_regs { |
| 157 | u32 command; |
| 158 | u32 status; |
| 159 | u32 page_size; |
| 160 | u32 reserved1; |
| 161 | u32 reserved2; |
| 162 | u32 dev_notification; |
Sarah Sharp | 8e595a5 | 2009-07-27 12:03:31 -0700 | [diff] [blame] | 163 | u64 cmd_ring; |
Sarah Sharp | 74c6874 | 2009-04-27 19:52:22 -0700 | [diff] [blame] | 164 | /* rsvd: offset 0x20-2F */ |
| 165 | u32 reserved3[4]; |
Sarah Sharp | 8e595a5 | 2009-07-27 12:03:31 -0700 | [diff] [blame] | 166 | u64 dcbaa_ptr; |
Sarah Sharp | 74c6874 | 2009-04-27 19:52:22 -0700 | [diff] [blame] | 167 | u32 config_reg; |
| 168 | /* rsvd: offset 0x3C-3FF */ |
| 169 | u32 reserved4[241]; |
| 170 | /* port 1 registers, which serve as a base address for other ports */ |
| 171 | u32 port_status_base; |
| 172 | u32 port_power_base; |
| 173 | u32 port_link_base; |
| 174 | u32 reserved5; |
| 175 | /* registers for ports 2-255 */ |
| 176 | u32 reserved6[NUM_PORT_REGS*254]; |
Sarah Sharp | 9844197 | 2009-05-14 11:44:18 -0700 | [diff] [blame] | 177 | }; |
Sarah Sharp | 74c6874 | 2009-04-27 19:52:22 -0700 | [diff] [blame] | 178 | |
| 179 | /* USBCMD - USB command - command bitmasks */ |
| 180 | /* start/stop HC execution - do not write unless HC is halted*/ |
| 181 | #define CMD_RUN XHCI_CMD_RUN |
| 182 | /* Reset HC - resets internal HC state machine and all registers (except |
| 183 | * PCI config regs). HC does NOT drive a USB reset on the downstream ports. |
| 184 | * The xHCI driver must reinitialize the xHC after setting this bit. |
| 185 | */ |
| 186 | #define CMD_RESET (1 << 1) |
| 187 | /* Event Interrupt Enable - a '1' allows interrupts from the host controller */ |
| 188 | #define CMD_EIE XHCI_CMD_EIE |
| 189 | /* Host System Error Interrupt Enable - get out-of-band signal for HC errors */ |
| 190 | #define CMD_HSEIE XHCI_CMD_HSEIE |
| 191 | /* bits 4:6 are reserved (and should be preserved on writes). */ |
| 192 | /* light reset (port status stays unchanged) - reset completed when this is 0 */ |
| 193 | #define CMD_LRESET (1 << 7) |
Andiry Xu | 5535b1d | 2010-10-14 07:23:06 -0700 | [diff] [blame] | 194 | /* host controller save/restore state. */ |
Sarah Sharp | 74c6874 | 2009-04-27 19:52:22 -0700 | [diff] [blame] | 195 | #define CMD_CSS (1 << 8) |
| 196 | #define CMD_CRS (1 << 9) |
| 197 | /* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */ |
| 198 | #define CMD_EWE XHCI_CMD_EWE |
| 199 | /* MFINDEX power management - '1' means xHC can stop MFINDEX counter if all root |
| 200 | * hubs are in U3 (selective suspend), disconnect, disabled, or powered-off. |
| 201 | * '0' means the xHC can power it off if all ports are in the disconnect, |
| 202 | * disabled, or powered-off state. |
| 203 | */ |
| 204 | #define CMD_PM_INDEX (1 << 11) |
| 205 | /* bits 12:31 are reserved (and should be preserved on writes). */ |
| 206 | |
| 207 | /* USBSTS - USB status - status bitmasks */ |
| 208 | /* HC not running - set to 1 when run/stop bit is cleared. */ |
| 209 | #define STS_HALT XHCI_STS_HALT |
| 210 | /* serious error, e.g. PCI parity error. The HC will clear the run/stop bit. */ |
| 211 | #define STS_FATAL (1 << 2) |
| 212 | /* event interrupt - clear this prior to clearing any IP flags in IR set*/ |
| 213 | #define STS_EINT (1 << 3) |
| 214 | /* port change detect */ |
| 215 | #define STS_PORT (1 << 4) |
| 216 | /* bits 5:7 reserved and zeroed */ |
| 217 | /* save state status - '1' means xHC is saving state */ |
| 218 | #define STS_SAVE (1 << 8) |
| 219 | /* restore state status - '1' means xHC is restoring state */ |
| 220 | #define STS_RESTORE (1 << 9) |
| 221 | /* true: save or restore error */ |
| 222 | #define STS_SRE (1 << 10) |
| 223 | /* true: Controller Not Ready to accept doorbell or op reg writes after reset */ |
| 224 | #define STS_CNR XHCI_STS_CNR |
| 225 | /* true: internal Host Controller Error - SW needs to reset and reinitialize */ |
| 226 | #define STS_HCE (1 << 12) |
| 227 | /* bits 13:31 reserved and should be preserved */ |
| 228 | |
| 229 | /* |
| 230 | * DNCTRL - Device Notification Control Register - dev_notification bitmasks |
| 231 | * Generate a device notification event when the HC sees a transaction with a |
| 232 | * notification type that matches a bit set in this bit field. |
| 233 | */ |
| 234 | #define DEV_NOTE_MASK (0xffff) |
| 235 | #define ENABLE_DEV_NOTE(x) (1 << x) |
| 236 | /* Most of the device notification types should only be used for debug. |
| 237 | * SW does need to pay attention to function wake notifications. |
| 238 | */ |
| 239 | #define DEV_NOTE_FWAKE ENABLE_DEV_NOTE(1) |
| 240 | |
Sarah Sharp | 0ebbab3 | 2009-04-27 19:52:34 -0700 | [diff] [blame] | 241 | /* CRCR - Command Ring Control Register - cmd_ring bitmasks */ |
| 242 | /* bit 0 is the command ring cycle state */ |
| 243 | /* stop ring operation after completion of the currently executing command */ |
| 244 | #define CMD_RING_PAUSE (1 << 1) |
| 245 | /* stop ring immediately - abort the currently executing command */ |
| 246 | #define CMD_RING_ABORT (1 << 2) |
| 247 | /* true: command ring is running */ |
| 248 | #define CMD_RING_RUNNING (1 << 3) |
| 249 | /* bits 4:5 reserved and should be preserved */ |
| 250 | /* Command Ring pointer - bit mask for the lower 32 bits. */ |
Sarah Sharp | 8e595a5 | 2009-07-27 12:03:31 -0700 | [diff] [blame] | 251 | #define CMD_RING_RSVD_BITS (0x3f) |
Sarah Sharp | 0ebbab3 | 2009-04-27 19:52:34 -0700 | [diff] [blame] | 252 | |
Sarah Sharp | 74c6874 | 2009-04-27 19:52:22 -0700 | [diff] [blame] | 253 | /* CONFIG - Configure Register - config_reg bitmasks */ |
| 254 | /* bits 0:7 - maximum number of device slots enabled (NumSlotsEn) */ |
| 255 | #define MAX_DEVS(p) ((p) & 0xff) |
| 256 | /* bits 8:31 - reserved and should be preserved */ |
| 257 | |
| 258 | /* PORTSC - Port Status and Control Register - port_status_base bitmasks */ |
| 259 | /* true: device connected */ |
| 260 | #define PORT_CONNECT (1 << 0) |
| 261 | /* true: port enabled */ |
| 262 | #define PORT_PE (1 << 1) |
| 263 | /* bit 2 reserved and zeroed */ |
| 264 | /* true: port has an over-current condition */ |
| 265 | #define PORT_OC (1 << 3) |
| 266 | /* true: port reset signaling asserted */ |
| 267 | #define PORT_RESET (1 << 4) |
| 268 | /* Port Link State - bits 5:8 |
| 269 | * A read gives the current link PM state of the port, |
| 270 | * a write with Link State Write Strobe set sets the link state. |
| 271 | */ |
Andiry Xu | be88fe4 | 2010-10-14 07:22:57 -0700 | [diff] [blame] | 272 | #define PORT_PLS_MASK (0xf << 5) |
| 273 | #define XDEV_U0 (0x0 << 5) |
| 274 | #define XDEV_U3 (0x3 << 5) |
| 275 | #define XDEV_RESUME (0xf << 5) |
Sarah Sharp | 74c6874 | 2009-04-27 19:52:22 -0700 | [diff] [blame] | 276 | /* true: port has power (see HCC_PPC) */ |
| 277 | #define PORT_POWER (1 << 9) |
| 278 | /* bits 10:13 indicate device speed: |
| 279 | * 0 - undefined speed - port hasn't be initialized by a reset yet |
| 280 | * 1 - full speed |
| 281 | * 2 - low speed |
| 282 | * 3 - high speed |
| 283 | * 4 - super speed |
| 284 | * 5-15 reserved |
| 285 | */ |
Sarah Sharp | 3ffbba9 | 2009-04-27 19:57:38 -0700 | [diff] [blame] | 286 | #define DEV_SPEED_MASK (0xf << 10) |
| 287 | #define XDEV_FS (0x1 << 10) |
| 288 | #define XDEV_LS (0x2 << 10) |
| 289 | #define XDEV_HS (0x3 << 10) |
| 290 | #define XDEV_SS (0x4 << 10) |
Sarah Sharp | 74c6874 | 2009-04-27 19:52:22 -0700 | [diff] [blame] | 291 | #define DEV_UNDEFSPEED(p) (((p) & DEV_SPEED_MASK) == (0x0<<10)) |
Sarah Sharp | 3ffbba9 | 2009-04-27 19:57:38 -0700 | [diff] [blame] | 292 | #define DEV_FULLSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_FS) |
| 293 | #define DEV_LOWSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_LS) |
| 294 | #define DEV_HIGHSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_HS) |
| 295 | #define DEV_SUPERSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_SS) |
| 296 | /* Bits 20:23 in the Slot Context are the speed for the device */ |
| 297 | #define SLOT_SPEED_FS (XDEV_FS << 10) |
| 298 | #define SLOT_SPEED_LS (XDEV_LS << 10) |
| 299 | #define SLOT_SPEED_HS (XDEV_HS << 10) |
| 300 | #define SLOT_SPEED_SS (XDEV_SS << 10) |
Sarah Sharp | 74c6874 | 2009-04-27 19:52:22 -0700 | [diff] [blame] | 301 | /* Port Indicator Control */ |
| 302 | #define PORT_LED_OFF (0 << 14) |
| 303 | #define PORT_LED_AMBER (1 << 14) |
| 304 | #define PORT_LED_GREEN (2 << 14) |
| 305 | #define PORT_LED_MASK (3 << 14) |
| 306 | /* Port Link State Write Strobe - set this when changing link state */ |
| 307 | #define PORT_LINK_STROBE (1 << 16) |
| 308 | /* true: connect status change */ |
| 309 | #define PORT_CSC (1 << 17) |
| 310 | /* true: port enable change */ |
| 311 | #define PORT_PEC (1 << 18) |
| 312 | /* true: warm reset for a USB 3.0 device is done. A "hot" reset puts the port |
| 313 | * into an enabled state, and the device into the default state. A "warm" reset |
| 314 | * also resets the link, forcing the device through the link training sequence. |
| 315 | * SW can also look at the Port Reset register to see when warm reset is done. |
| 316 | */ |
| 317 | #define PORT_WRC (1 << 19) |
| 318 | /* true: over-current change */ |
| 319 | #define PORT_OCC (1 << 20) |
| 320 | /* true: reset change - 1 to 0 transition of PORT_RESET */ |
| 321 | #define PORT_RC (1 << 21) |
| 322 | /* port link status change - set on some port link state transitions: |
| 323 | * Transition Reason |
| 324 | * ------------------------------------------------------------------------------ |
| 325 | * - U3 to Resume Wakeup signaling from a device |
| 326 | * - Resume to Recovery to U0 USB 3.0 device resume |
| 327 | * - Resume to U0 USB 2.0 device resume |
| 328 | * - U3 to Recovery to U0 Software resume of USB 3.0 device complete |
| 329 | * - U3 to U0 Software resume of USB 2.0 device complete |
| 330 | * - U2 to U0 L1 resume of USB 2.1 device complete |
| 331 | * - U0 to U0 (???) L1 entry rejection by USB 2.1 device |
| 332 | * - U0 to disabled L1 entry error with USB 2.1 device |
| 333 | * - Any state to inactive Error on USB 3.0 port |
| 334 | */ |
| 335 | #define PORT_PLC (1 << 22) |
| 336 | /* port configure error change - port failed to configure its link partner */ |
| 337 | #define PORT_CEC (1 << 23) |
| 338 | /* bit 24 reserved */ |
| 339 | /* wake on connect (enable) */ |
| 340 | #define PORT_WKCONN_E (1 << 25) |
| 341 | /* wake on disconnect (enable) */ |
| 342 | #define PORT_WKDISC_E (1 << 26) |
| 343 | /* wake on over-current (enable) */ |
| 344 | #define PORT_WKOC_E (1 << 27) |
| 345 | /* bits 28:29 reserved */ |
| 346 | /* true: device is removable - for USB 3.0 roothub emulation */ |
| 347 | #define PORT_DEV_REMOVE (1 << 30) |
| 348 | /* Initiate a warm port reset - complete when PORT_WRC is '1' */ |
| 349 | #define PORT_WR (1 << 31) |
| 350 | |
| 351 | /* Port Power Management Status and Control - port_power_base bitmasks */ |
| 352 | /* Inactivity timer value for transitions into U1, in microseconds. |
| 353 | * Timeout can be up to 127us. 0xFF means an infinite timeout. |
| 354 | */ |
| 355 | #define PORT_U1_TIMEOUT(p) ((p) & 0xff) |
| 356 | /* Inactivity timer value for transitions into U2 */ |
| 357 | #define PORT_U2_TIMEOUT(p) (((p) & 0xff) << 8) |
| 358 | /* Bits 24:31 for port testing */ |
| 359 | |
Andiry Xu | 9777e3c | 2010-10-14 07:23:03 -0700 | [diff] [blame] | 360 | /* USB2 Protocol PORTSPMSC */ |
| 361 | #define PORT_RWE (1 << 0x3) |
Sarah Sharp | 74c6874 | 2009-04-27 19:52:22 -0700 | [diff] [blame] | 362 | |
| 363 | /** |
Sarah Sharp | 9844197 | 2009-05-14 11:44:18 -0700 | [diff] [blame] | 364 | * struct xhci_intr_reg - Interrupt Register Set |
Sarah Sharp | 74c6874 | 2009-04-27 19:52:22 -0700 | [diff] [blame] | 365 | * @irq_pending: IMAN - Interrupt Management Register. Used to enable |
| 366 | * interrupts and check for pending interrupts. |
| 367 | * @irq_control: IMOD - Interrupt Moderation Register. |
| 368 | * Used to throttle interrupts. |
| 369 | * @erst_size: Number of segments in the Event Ring Segment Table (ERST). |
| 370 | * @erst_base: ERST base address. |
| 371 | * @erst_dequeue: Event ring dequeue pointer. |
| 372 | * |
| 373 | * Each interrupter (defined by a MSI-X vector) has an event ring and an Event |
| 374 | * Ring Segment Table (ERST) associated with it. The event ring is comprised of |
| 375 | * multiple segments of the same size. The HC places events on the ring and |
| 376 | * "updates the Cycle bit in the TRBs to indicate to software the current |
| 377 | * position of the Enqueue Pointer." The HCD (Linux) processes those events and |
| 378 | * updates the dequeue pointer. |
| 379 | */ |
Sarah Sharp | 9844197 | 2009-05-14 11:44:18 -0700 | [diff] [blame] | 380 | struct xhci_intr_reg { |
Sarah Sharp | 74c6874 | 2009-04-27 19:52:22 -0700 | [diff] [blame] | 381 | u32 irq_pending; |
| 382 | u32 irq_control; |
| 383 | u32 erst_size; |
| 384 | u32 rsvd; |
Sarah Sharp | 8e595a5 | 2009-07-27 12:03:31 -0700 | [diff] [blame] | 385 | u64 erst_base; |
| 386 | u64 erst_dequeue; |
Sarah Sharp | 9844197 | 2009-05-14 11:44:18 -0700 | [diff] [blame] | 387 | }; |
Sarah Sharp | 74c6874 | 2009-04-27 19:52:22 -0700 | [diff] [blame] | 388 | |
Sarah Sharp | 66d4ead | 2009-04-27 19:52:28 -0700 | [diff] [blame] | 389 | /* irq_pending bitmasks */ |
Sarah Sharp | 74c6874 | 2009-04-27 19:52:22 -0700 | [diff] [blame] | 390 | #define ER_IRQ_PENDING(p) ((p) & 0x1) |
Sarah Sharp | 66d4ead | 2009-04-27 19:52:28 -0700 | [diff] [blame] | 391 | /* bits 2:31 need to be preserved */ |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 392 | /* THIS IS BUGGY - FIXME - IP IS WRITE 1 TO CLEAR */ |
Sarah Sharp | 66d4ead | 2009-04-27 19:52:28 -0700 | [diff] [blame] | 393 | #define ER_IRQ_CLEAR(p) ((p) & 0xfffffffe) |
| 394 | #define ER_IRQ_ENABLE(p) ((ER_IRQ_CLEAR(p)) | 0x2) |
| 395 | #define ER_IRQ_DISABLE(p) ((ER_IRQ_CLEAR(p)) & ~(0x2)) |
| 396 | |
| 397 | /* irq_control bitmasks */ |
| 398 | /* Minimum interval between interrupts (in 250ns intervals). The interval |
| 399 | * between interrupts will be longer if there are no events on the event ring. |
| 400 | * Default is 4000 (1 ms). |
| 401 | */ |
| 402 | #define ER_IRQ_INTERVAL_MASK (0xffff) |
| 403 | /* Counter used to count down the time to the next interrupt - HW use only */ |
| 404 | #define ER_IRQ_COUNTER_MASK (0xffff << 16) |
| 405 | |
| 406 | /* erst_size bitmasks */ |
Sarah Sharp | 74c6874 | 2009-04-27 19:52:22 -0700 | [diff] [blame] | 407 | /* Preserve bits 16:31 of erst_size */ |
Sarah Sharp | 66d4ead | 2009-04-27 19:52:28 -0700 | [diff] [blame] | 408 | #define ERST_SIZE_MASK (0xffff << 16) |
| 409 | |
| 410 | /* erst_dequeue bitmasks */ |
| 411 | /* Dequeue ERST Segment Index (DESI) - Segment number (or alias) |
| 412 | * where the current dequeue pointer lies. This is an optional HW hint. |
| 413 | */ |
| 414 | #define ERST_DESI_MASK (0x7) |
| 415 | /* Event Handler Busy (EHB) - is the event ring scheduled to be serviced by |
| 416 | * a work queue (or delayed service routine)? |
| 417 | */ |
| 418 | #define ERST_EHB (1 << 3) |
Sarah Sharp | 0ebbab3 | 2009-04-27 19:52:34 -0700 | [diff] [blame] | 419 | #define ERST_PTR_MASK (0xf) |
Sarah Sharp | 74c6874 | 2009-04-27 19:52:22 -0700 | [diff] [blame] | 420 | |
| 421 | /** |
| 422 | * struct xhci_run_regs |
| 423 | * @microframe_index: |
| 424 | * MFINDEX - current microframe number |
| 425 | * |
| 426 | * Section 5.5 Host Controller Runtime Registers: |
| 427 | * "Software should read and write these registers using only Dword (32 bit) |
| 428 | * or larger accesses" |
| 429 | */ |
| 430 | struct xhci_run_regs { |
Sarah Sharp | 9844197 | 2009-05-14 11:44:18 -0700 | [diff] [blame] | 431 | u32 microframe_index; |
| 432 | u32 rsvd[7]; |
| 433 | struct xhci_intr_reg ir_set[128]; |
| 434 | }; |
Sarah Sharp | 74c6874 | 2009-04-27 19:52:22 -0700 | [diff] [blame] | 435 | |
Sarah Sharp | 0ebbab3 | 2009-04-27 19:52:34 -0700 | [diff] [blame] | 436 | /** |
| 437 | * struct doorbell_array |
| 438 | * |
| 439 | * Section 5.6 |
| 440 | */ |
| 441 | struct xhci_doorbell_array { |
| 442 | u32 doorbell[256]; |
Sarah Sharp | 9844197 | 2009-05-14 11:44:18 -0700 | [diff] [blame] | 443 | }; |
Sarah Sharp | 0ebbab3 | 2009-04-27 19:52:34 -0700 | [diff] [blame] | 444 | |
| 445 | #define DB_TARGET_MASK 0xFFFFFF00 |
| 446 | #define DB_STREAM_ID_MASK 0x0000FFFF |
| 447 | #define DB_TARGET_HOST 0x0 |
| 448 | #define DB_STREAM_ID_HOST 0x0 |
| 449 | #define DB_MASK (0xff << 8) |
| 450 | |
Sarah Sharp | d0e96f5 | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 451 | /* Endpoint Target - bits 0:7 */ |
| 452 | #define EPI_TO_DB(p) (((p) + 1) & 0xff) |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 453 | #define STREAM_ID_TO_DB(p) (((p) & 0xffff) << 16) |
Sarah Sharp | d0e96f5 | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 454 | |
Sarah Sharp | 0ebbab3 | 2009-04-27 19:52:34 -0700 | [diff] [blame] | 455 | |
Sarah Sharp | a74588f | 2009-04-27 19:53:42 -0700 | [diff] [blame] | 456 | /** |
John Youn | d115b04 | 2009-07-27 12:05:15 -0700 | [diff] [blame] | 457 | * struct xhci_container_ctx |
| 458 | * @type: Type of context. Used to calculated offsets to contained contexts. |
| 459 | * @size: Size of the context data |
| 460 | * @bytes: The raw context data given to HW |
| 461 | * @dma: dma address of the bytes |
| 462 | * |
| 463 | * Represents either a Device or Input context. Holds a pointer to the raw |
| 464 | * memory used for the context (bytes) and dma address of it (dma). |
| 465 | */ |
| 466 | struct xhci_container_ctx { |
| 467 | unsigned type; |
| 468 | #define XHCI_CTX_TYPE_DEVICE 0x1 |
| 469 | #define XHCI_CTX_TYPE_INPUT 0x2 |
| 470 | |
| 471 | int size; |
| 472 | |
| 473 | u8 *bytes; |
| 474 | dma_addr_t dma; |
| 475 | }; |
| 476 | |
| 477 | /** |
Sarah Sharp | a74588f | 2009-04-27 19:53:42 -0700 | [diff] [blame] | 478 | * struct xhci_slot_ctx |
| 479 | * @dev_info: Route string, device speed, hub info, and last valid endpoint |
| 480 | * @dev_info2: Max exit latency for device number, root hub port number |
| 481 | * @tt_info: tt_info is used to construct split transaction tokens |
| 482 | * @dev_state: slot state and device address |
| 483 | * |
| 484 | * Slot Context - section 6.2.1.1. This assumes the HC uses 32-byte context |
| 485 | * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes |
| 486 | * reserved at the end of the slot context for HC internal use. |
| 487 | */ |
| 488 | struct xhci_slot_ctx { |
| 489 | u32 dev_info; |
| 490 | u32 dev_info2; |
| 491 | u32 tt_info; |
| 492 | u32 dev_state; |
| 493 | /* offset 0x10 to 0x1f reserved for HC internal use */ |
| 494 | u32 reserved[4]; |
Sarah Sharp | 9844197 | 2009-05-14 11:44:18 -0700 | [diff] [blame] | 495 | }; |
Sarah Sharp | a74588f | 2009-04-27 19:53:42 -0700 | [diff] [blame] | 496 | |
| 497 | /* dev_info bitmasks */ |
| 498 | /* Route String - 0:19 */ |
| 499 | #define ROUTE_STRING_MASK (0xfffff) |
| 500 | /* Device speed - values defined by PORTSC Device Speed field - 20:23 */ |
| 501 | #define DEV_SPEED (0xf << 20) |
| 502 | /* bit 24 reserved */ |
| 503 | /* Is this LS/FS device connected through a HS hub? - bit 25 */ |
| 504 | #define DEV_MTT (0x1 << 25) |
| 505 | /* Set if the device is a hub - bit 26 */ |
| 506 | #define DEV_HUB (0x1 << 26) |
| 507 | /* Index of the last valid endpoint context in this device context - 27:31 */ |
Sarah Sharp | 3ffbba9 | 2009-04-27 19:57:38 -0700 | [diff] [blame] | 508 | #define LAST_CTX_MASK (0x1f << 27) |
| 509 | #define LAST_CTX(p) ((p) << 27) |
| 510 | #define LAST_CTX_TO_EP_NUM(p) (((p) >> 27) - 1) |
Sarah Sharp | 3ffbba9 | 2009-04-27 19:57:38 -0700 | [diff] [blame] | 511 | #define SLOT_FLAG (1 << 0) |
| 512 | #define EP0_FLAG (1 << 1) |
Sarah Sharp | a74588f | 2009-04-27 19:53:42 -0700 | [diff] [blame] | 513 | |
| 514 | /* dev_info2 bitmasks */ |
| 515 | /* Max Exit Latency (ms) - worst case time to wake up all links in dev path */ |
| 516 | #define MAX_EXIT (0xffff) |
| 517 | /* Root hub port number that is needed to access the USB device */ |
Sarah Sharp | 3ffbba9 | 2009-04-27 19:57:38 -0700 | [diff] [blame] | 518 | #define ROOT_HUB_PORT(p) (((p) & 0xff) << 16) |
Andiry Xu | be88fe4 | 2010-10-14 07:22:57 -0700 | [diff] [blame] | 519 | #define DEVINFO_TO_ROOT_HUB_PORT(p) (((p) >> 16) & 0xff) |
Sarah Sharp | ac1c1b7 | 2009-09-04 10:53:20 -0700 | [diff] [blame] | 520 | /* Maximum number of ports under a hub device */ |
| 521 | #define XHCI_MAX_PORTS(p) (((p) & 0xff) << 24) |
Sarah Sharp | a74588f | 2009-04-27 19:53:42 -0700 | [diff] [blame] | 522 | |
| 523 | /* tt_info bitmasks */ |
| 524 | /* |
| 525 | * TT Hub Slot ID - for low or full speed devices attached to a high-speed hub |
| 526 | * The Slot ID of the hub that isolates the high speed signaling from |
| 527 | * this low or full-speed device. '0' if attached to root hub port. |
| 528 | */ |
| 529 | #define TT_SLOT (0xff) |
| 530 | /* |
| 531 | * The number of the downstream facing port of the high-speed hub |
| 532 | * '0' if the device is not low or full speed. |
| 533 | */ |
| 534 | #define TT_PORT (0xff << 8) |
Sarah Sharp | ac1c1b7 | 2009-09-04 10:53:20 -0700 | [diff] [blame] | 535 | #define TT_THINK_TIME(p) (((p) & 0x3) << 16) |
Sarah Sharp | a74588f | 2009-04-27 19:53:42 -0700 | [diff] [blame] | 536 | |
| 537 | /* dev_state bitmasks */ |
| 538 | /* USB device address - assigned by the HC */ |
Sarah Sharp | 3ffbba9 | 2009-04-27 19:57:38 -0700 | [diff] [blame] | 539 | #define DEV_ADDR_MASK (0xff) |
Sarah Sharp | a74588f | 2009-04-27 19:53:42 -0700 | [diff] [blame] | 540 | /* bits 8:26 reserved */ |
| 541 | /* Slot state */ |
| 542 | #define SLOT_STATE (0x1f << 27) |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 543 | #define GET_SLOT_STATE(p) (((p) & (0x1f << 27)) >> 27) |
Sarah Sharp | a74588f | 2009-04-27 19:53:42 -0700 | [diff] [blame] | 544 | |
| 545 | |
| 546 | /** |
| 547 | * struct xhci_ep_ctx |
| 548 | * @ep_info: endpoint state, streams, mult, and interval information. |
| 549 | * @ep_info2: information on endpoint type, max packet size, max burst size, |
| 550 | * error count, and whether the HC will force an event for all |
| 551 | * transactions. |
Sarah Sharp | 3ffbba9 | 2009-04-27 19:57:38 -0700 | [diff] [blame] | 552 | * @deq: 64-bit ring dequeue pointer address. If the endpoint only |
| 553 | * defines one stream, this points to the endpoint transfer ring. |
| 554 | * Otherwise, it points to a stream context array, which has a |
| 555 | * ring pointer for each flow. |
| 556 | * @tx_info: |
| 557 | * Average TRB lengths for the endpoint ring and |
| 558 | * max payload within an Endpoint Service Interval Time (ESIT). |
Sarah Sharp | a74588f | 2009-04-27 19:53:42 -0700 | [diff] [blame] | 559 | * |
| 560 | * Endpoint Context - section 6.2.1.2. This assumes the HC uses 32-byte context |
| 561 | * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes |
| 562 | * reserved at the end of the endpoint context for HC internal use. |
| 563 | */ |
| 564 | struct xhci_ep_ctx { |
| 565 | u32 ep_info; |
| 566 | u32 ep_info2; |
Sarah Sharp | 8e595a5 | 2009-07-27 12:03:31 -0700 | [diff] [blame] | 567 | u64 deq; |
Sarah Sharp | 3ffbba9 | 2009-04-27 19:57:38 -0700 | [diff] [blame] | 568 | u32 tx_info; |
Sarah Sharp | a74588f | 2009-04-27 19:53:42 -0700 | [diff] [blame] | 569 | /* offset 0x14 - 0x1f reserved for HC internal use */ |
Sarah Sharp | 3ffbba9 | 2009-04-27 19:57:38 -0700 | [diff] [blame] | 570 | u32 reserved[3]; |
Sarah Sharp | 9844197 | 2009-05-14 11:44:18 -0700 | [diff] [blame] | 571 | }; |
Sarah Sharp | a74588f | 2009-04-27 19:53:42 -0700 | [diff] [blame] | 572 | |
| 573 | /* ep_info bitmasks */ |
| 574 | /* |
| 575 | * Endpoint State - bits 0:2 |
| 576 | * 0 - disabled |
| 577 | * 1 - running |
| 578 | * 2 - halted due to halt condition - ok to manipulate endpoint ring |
| 579 | * 3 - stopped |
| 580 | * 4 - TRB error |
| 581 | * 5-7 - reserved |
| 582 | */ |
Sarah Sharp | d0e96f5 | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 583 | #define EP_STATE_MASK (0xf) |
| 584 | #define EP_STATE_DISABLED 0 |
| 585 | #define EP_STATE_RUNNING 1 |
| 586 | #define EP_STATE_HALTED 2 |
| 587 | #define EP_STATE_STOPPED 3 |
| 588 | #define EP_STATE_ERROR 4 |
Sarah Sharp | a74588f | 2009-04-27 19:53:42 -0700 | [diff] [blame] | 589 | /* Mult - Max number of burtst within an interval, in EP companion desc. */ |
| 590 | #define EP_MULT(p) ((p & 0x3) << 8) |
| 591 | /* bits 10:14 are Max Primary Streams */ |
| 592 | /* bit 15 is Linear Stream Array */ |
| 593 | /* Interval - period between requests to an endpoint - 125u increments. */ |
Sarah Sharp | f94e0186 | 2009-04-27 19:58:38 -0700 | [diff] [blame] | 594 | #define EP_INTERVAL(p) ((p & 0xff) << 16) |
Sarah Sharp | 624defa | 2009-09-02 12:14:28 -0700 | [diff] [blame] | 595 | #define EP_INTERVAL_TO_UFRAMES(p) (1 << (((p) >> 16) & 0xff)) |
Sarah Sharp | 8df75f4 | 2010-04-02 15:34:16 -0700 | [diff] [blame] | 596 | #define EP_MAXPSTREAMS_MASK (0x1f << 10) |
| 597 | #define EP_MAXPSTREAMS(p) (((p) << 10) & EP_MAXPSTREAMS_MASK) |
| 598 | /* Endpoint is set up with a Linear Stream Array (vs. Secondary Stream Array) */ |
| 599 | #define EP_HAS_LSA (1 << 15) |
Sarah Sharp | a74588f | 2009-04-27 19:53:42 -0700 | [diff] [blame] | 600 | |
| 601 | /* ep_info2 bitmasks */ |
| 602 | /* |
| 603 | * Force Event - generate transfer events for all TRBs for this endpoint |
| 604 | * This will tell the HC to ignore the IOC and ISP flags (for debugging only). |
| 605 | */ |
| 606 | #define FORCE_EVENT (0x1) |
| 607 | #define ERROR_COUNT(p) (((p) & 0x3) << 1) |
Sarah Sharp | 82d1009 | 2009-08-07 14:04:52 -0700 | [diff] [blame] | 608 | #define CTX_TO_EP_TYPE(p) (((p) >> 3) & 0x7) |
Sarah Sharp | a74588f | 2009-04-27 19:53:42 -0700 | [diff] [blame] | 609 | #define EP_TYPE(p) ((p) << 3) |
| 610 | #define ISOC_OUT_EP 1 |
| 611 | #define BULK_OUT_EP 2 |
| 612 | #define INT_OUT_EP 3 |
| 613 | #define CTRL_EP 4 |
| 614 | #define ISOC_IN_EP 5 |
| 615 | #define BULK_IN_EP 6 |
| 616 | #define INT_IN_EP 7 |
| 617 | /* bit 6 reserved */ |
| 618 | /* bit 7 is Host Initiate Disable - for disabling stream selection */ |
| 619 | #define MAX_BURST(p) (((p)&0xff) << 8) |
| 620 | #define MAX_PACKET(p) (((p)&0xffff) << 16) |
Sarah Sharp | 2d3f1fa | 2009-08-07 14:04:49 -0700 | [diff] [blame] | 621 | #define MAX_PACKET_MASK (0xffff << 16) |
| 622 | #define MAX_PACKET_DECODED(p) (((p) >> 16) & 0xffff) |
Sarah Sharp | a74588f | 2009-04-27 19:53:42 -0700 | [diff] [blame] | 623 | |
Sarah Sharp | 9238f25 | 2010-04-16 08:07:27 -0700 | [diff] [blame] | 624 | /* tx_info bitmasks */ |
| 625 | #define AVG_TRB_LENGTH_FOR_EP(p) ((p) & 0xffff) |
| 626 | #define MAX_ESIT_PAYLOAD_FOR_EP(p) (((p) & 0xffff) << 16) |
| 627 | |
Sarah Sharp | a74588f | 2009-04-27 19:53:42 -0700 | [diff] [blame] | 628 | |
| 629 | /** |
John Youn | d115b04 | 2009-07-27 12:05:15 -0700 | [diff] [blame] | 630 | * struct xhci_input_control_context |
| 631 | * Input control context; see section 6.2.5. |
Sarah Sharp | a74588f | 2009-04-27 19:53:42 -0700 | [diff] [blame] | 632 | * |
| 633 | * @drop_context: set the bit of the endpoint context you want to disable |
| 634 | * @add_context: set the bit of the endpoint context you want to enable |
| 635 | */ |
John Youn | d115b04 | 2009-07-27 12:05:15 -0700 | [diff] [blame] | 636 | struct xhci_input_control_ctx { |
Sarah Sharp | a74588f | 2009-04-27 19:53:42 -0700 | [diff] [blame] | 637 | u32 drop_flags; |
| 638 | u32 add_flags; |
John Youn | d115b04 | 2009-07-27 12:05:15 -0700 | [diff] [blame] | 639 | u32 rsvd2[6]; |
Sarah Sharp | 9844197 | 2009-05-14 11:44:18 -0700 | [diff] [blame] | 640 | }; |
Sarah Sharp | a74588f | 2009-04-27 19:53:42 -0700 | [diff] [blame] | 641 | |
Sarah Sharp | 913a8a3 | 2009-09-04 10:53:13 -0700 | [diff] [blame] | 642 | /* Represents everything that is needed to issue a command on the command ring. |
| 643 | * It's useful to pre-allocate these for commands that cannot fail due to |
| 644 | * out-of-memory errors, like freeing streams. |
| 645 | */ |
| 646 | struct xhci_command { |
| 647 | /* Input context for changing device state */ |
| 648 | struct xhci_container_ctx *in_ctx; |
| 649 | u32 status; |
| 650 | /* If completion is null, no one is waiting on this command |
| 651 | * and the structure can be freed after the command completes. |
| 652 | */ |
| 653 | struct completion *completion; |
| 654 | union xhci_trb *command_trb; |
| 655 | struct list_head cmd_list; |
| 656 | }; |
| 657 | |
Sarah Sharp | a74588f | 2009-04-27 19:53:42 -0700 | [diff] [blame] | 658 | /* drop context bitmasks */ |
| 659 | #define DROP_EP(x) (0x1 << x) |
| 660 | /* add context bitmasks */ |
| 661 | #define ADD_EP(x) (0x1 << x) |
| 662 | |
Sarah Sharp | 8df75f4 | 2010-04-02 15:34:16 -0700 | [diff] [blame] | 663 | struct xhci_stream_ctx { |
| 664 | /* 64-bit stream ring address, cycle state, and stream type */ |
| 665 | u64 stream_ring; |
| 666 | /* offset 0x14 - 0x1f reserved for HC internal use */ |
| 667 | u32 reserved[2]; |
| 668 | }; |
| 669 | |
| 670 | /* Stream Context Types (section 6.4.1) - bits 3:1 of stream ctx deq ptr */ |
| 671 | #define SCT_FOR_CTX(p) (((p) << 1) & 0x7) |
| 672 | /* Secondary stream array type, dequeue pointer is to a transfer ring */ |
| 673 | #define SCT_SEC_TR 0 |
| 674 | /* Primary stream array type, dequeue pointer is to a transfer ring */ |
| 675 | #define SCT_PRI_TR 1 |
| 676 | /* Dequeue pointer is for a secondary stream array (SSA) with 8 entries */ |
| 677 | #define SCT_SSA_8 2 |
| 678 | #define SCT_SSA_16 3 |
| 679 | #define SCT_SSA_32 4 |
| 680 | #define SCT_SSA_64 5 |
| 681 | #define SCT_SSA_128 6 |
| 682 | #define SCT_SSA_256 7 |
| 683 | |
| 684 | /* Assume no secondary streams for now */ |
| 685 | struct xhci_stream_info { |
| 686 | struct xhci_ring **stream_rings; |
| 687 | /* Number of streams, including stream 0 (which drivers can't use) */ |
| 688 | unsigned int num_streams; |
| 689 | /* The stream context array may be bigger than |
| 690 | * the number of streams the driver asked for |
| 691 | */ |
| 692 | struct xhci_stream_ctx *stream_ctx_array; |
| 693 | unsigned int num_stream_ctxs; |
| 694 | dma_addr_t ctx_array_dma; |
| 695 | /* For mapping physical TRB addresses to segments in stream rings */ |
| 696 | struct radix_tree_root trb_address_map; |
| 697 | struct xhci_command *free_streams_command; |
| 698 | }; |
| 699 | |
| 700 | #define SMALL_STREAM_ARRAY_SIZE 256 |
| 701 | #define MEDIUM_STREAM_ARRAY_SIZE 1024 |
| 702 | |
Sarah Sharp | 63a0d9a | 2009-09-04 10:53:09 -0700 | [diff] [blame] | 703 | struct xhci_virt_ep { |
| 704 | struct xhci_ring *ring; |
Sarah Sharp | 8df75f4 | 2010-04-02 15:34:16 -0700 | [diff] [blame] | 705 | /* Related to endpoints that are configured to use stream IDs only */ |
| 706 | struct xhci_stream_info *stream_info; |
Sarah Sharp | 63a0d9a | 2009-09-04 10:53:09 -0700 | [diff] [blame] | 707 | /* Temporary storage in case the configure endpoint command fails and we |
| 708 | * have to restore the device state to the previous state |
| 709 | */ |
| 710 | struct xhci_ring *new_ring; |
| 711 | unsigned int ep_state; |
| 712 | #define SET_DEQ_PENDING (1 << 0) |
Sarah Sharp | 678539c | 2009-10-27 10:55:52 -0700 | [diff] [blame] | 713 | #define EP_HALTED (1 << 1) /* For stall handling */ |
| 714 | #define EP_HALT_PENDING (1 << 2) /* For URB cancellation */ |
Sarah Sharp | 8df75f4 | 2010-04-02 15:34:16 -0700 | [diff] [blame] | 715 | /* Transitioning the endpoint to using streams, don't enqueue URBs */ |
| 716 | #define EP_GETTING_STREAMS (1 << 3) |
| 717 | #define EP_HAS_STREAMS (1 << 4) |
| 718 | /* Transitioning the endpoint to not using streams, don't enqueue URBs */ |
| 719 | #define EP_GETTING_NO_STREAMS (1 << 5) |
Sarah Sharp | 63a0d9a | 2009-09-04 10:53:09 -0700 | [diff] [blame] | 720 | /* ---- Related to URB cancellation ---- */ |
| 721 | struct list_head cancelled_td_list; |
Sarah Sharp | 63a0d9a | 2009-09-04 10:53:09 -0700 | [diff] [blame] | 722 | /* The TRB that was last reported in a stopped endpoint ring */ |
| 723 | union xhci_trb *stopped_trb; |
| 724 | struct xhci_td *stopped_td; |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 725 | unsigned int stopped_stream; |
Sarah Sharp | 6f5165c | 2009-10-27 10:57:01 -0700 | [diff] [blame] | 726 | /* Watchdog timer for stop endpoint command to cancel URBs */ |
| 727 | struct timer_list stop_cmd_timer; |
| 728 | int stop_cmds_pending; |
| 729 | struct xhci_hcd *xhci; |
Andiry Xu | d18240d | 2010-07-22 15:23:25 -0700 | [diff] [blame] | 730 | /* |
| 731 | * Sometimes the xHC can not process isochronous endpoint ring quickly |
| 732 | * enough, and it will miss some isoc tds on the ring and generate |
| 733 | * a Missed Service Error Event. |
| 734 | * Set skip flag when receive a Missed Service Error Event and |
| 735 | * process the missed tds on the endpoint ring. |
| 736 | */ |
| 737 | bool skip; |
Sarah Sharp | 63a0d9a | 2009-09-04 10:53:09 -0700 | [diff] [blame] | 738 | }; |
| 739 | |
Sarah Sharp | 3ffbba9 | 2009-04-27 19:57:38 -0700 | [diff] [blame] | 740 | struct xhci_virt_device { |
Andiry Xu | 6492773 | 2010-10-14 07:22:45 -0700 | [diff] [blame] | 741 | struct usb_device *udev; |
Sarah Sharp | 3ffbba9 | 2009-04-27 19:57:38 -0700 | [diff] [blame] | 742 | /* |
| 743 | * Commands to the hardware are passed an "input context" that |
| 744 | * tells the hardware what to change in its data structures. |
| 745 | * The hardware will return changes in an "output context" that |
| 746 | * software must allocate for the hardware. We need to keep |
| 747 | * track of input and output contexts separately because |
| 748 | * these commands might fail and we don't trust the hardware. |
| 749 | */ |
John Youn | d115b04 | 2009-07-27 12:05:15 -0700 | [diff] [blame] | 750 | struct xhci_container_ctx *out_ctx; |
Sarah Sharp | 3ffbba9 | 2009-04-27 19:57:38 -0700 | [diff] [blame] | 751 | /* Used for addressing devices and configuration changes */ |
John Youn | d115b04 | 2009-07-27 12:05:15 -0700 | [diff] [blame] | 752 | struct xhci_container_ctx *in_ctx; |
Sarah Sharp | 74f9fe2 | 2009-12-03 09:44:29 -0800 | [diff] [blame] | 753 | /* Rings saved to ensure old alt settings can be re-instated */ |
| 754 | struct xhci_ring **ring_cache; |
| 755 | int num_rings_cached; |
Andiry Xu | c8d4af8 | 2010-10-14 07:22:51 -0700 | [diff] [blame] | 756 | /* Store xHC assigned device address */ |
| 757 | int address; |
Sarah Sharp | 74f9fe2 | 2009-12-03 09:44:29 -0800 | [diff] [blame] | 758 | #define XHCI_MAX_RINGS_CACHED 31 |
Sarah Sharp | 63a0d9a | 2009-09-04 10:53:09 -0700 | [diff] [blame] | 759 | struct xhci_virt_ep eps[31]; |
Sarah Sharp | f94e0186 | 2009-04-27 19:58:38 -0700 | [diff] [blame] | 760 | struct completion cmd_completion; |
Sarah Sharp | 3ffbba9 | 2009-04-27 19:57:38 -0700 | [diff] [blame] | 761 | /* Status of the last command issued for this device */ |
| 762 | u32 cmd_status; |
Sarah Sharp | 913a8a3 | 2009-09-04 10:53:13 -0700 | [diff] [blame] | 763 | struct list_head cmd_list; |
Andiry Xu | be88fe4 | 2010-10-14 07:22:57 -0700 | [diff] [blame] | 764 | u8 port; |
Sarah Sharp | 3ffbba9 | 2009-04-27 19:57:38 -0700 | [diff] [blame] | 765 | }; |
| 766 | |
| 767 | |
Sarah Sharp | a74588f | 2009-04-27 19:53:42 -0700 | [diff] [blame] | 768 | /** |
| 769 | * struct xhci_device_context_array |
| 770 | * @dev_context_ptr array of 64-bit DMA addresses for device contexts |
| 771 | */ |
| 772 | struct xhci_device_context_array { |
| 773 | /* 64-bit device addresses; we only write 32-bit addresses */ |
Sarah Sharp | 8e595a5 | 2009-07-27 12:03:31 -0700 | [diff] [blame] | 774 | u64 dev_context_ptrs[MAX_HC_SLOTS]; |
Sarah Sharp | a74588f | 2009-04-27 19:53:42 -0700 | [diff] [blame] | 775 | /* private xHCD pointers */ |
| 776 | dma_addr_t dma; |
Sarah Sharp | 9844197 | 2009-05-14 11:44:18 -0700 | [diff] [blame] | 777 | }; |
Sarah Sharp | a74588f | 2009-04-27 19:53:42 -0700 | [diff] [blame] | 778 | /* TODO: write function to set the 64-bit device DMA address */ |
| 779 | /* |
| 780 | * TODO: change this to be dynamically sized at HC mem init time since the HC |
| 781 | * might not be able to handle the maximum number of devices possible. |
| 782 | */ |
| 783 | |
| 784 | |
Sarah Sharp | 0ebbab3 | 2009-04-27 19:52:34 -0700 | [diff] [blame] | 785 | struct xhci_transfer_event { |
| 786 | /* 64-bit buffer address, or immediate data */ |
Sarah Sharp | 8e595a5 | 2009-07-27 12:03:31 -0700 | [diff] [blame] | 787 | u64 buffer; |
Sarah Sharp | 0ebbab3 | 2009-04-27 19:52:34 -0700 | [diff] [blame] | 788 | u32 transfer_len; |
| 789 | /* This field is interpreted differently based on the type of TRB */ |
| 790 | u32 flags; |
Sarah Sharp | 9844197 | 2009-05-14 11:44:18 -0700 | [diff] [blame] | 791 | }; |
Sarah Sharp | 0ebbab3 | 2009-04-27 19:52:34 -0700 | [diff] [blame] | 792 | |
Sarah Sharp | d0e96f5 | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 793 | /** Transfer Event bit fields **/ |
| 794 | #define TRB_TO_EP_ID(p) (((p) >> 16) & 0x1f) |
| 795 | |
Sarah Sharp | 0ebbab3 | 2009-04-27 19:52:34 -0700 | [diff] [blame] | 796 | /* Completion Code - only applicable for some types of TRBs */ |
| 797 | #define COMP_CODE_MASK (0xff << 24) |
| 798 | #define GET_COMP_CODE(p) (((p) & COMP_CODE_MASK) >> 24) |
| 799 | #define COMP_SUCCESS 1 |
| 800 | /* Data Buffer Error */ |
| 801 | #define COMP_DB_ERR 2 |
| 802 | /* Babble Detected Error */ |
| 803 | #define COMP_BABBLE 3 |
| 804 | /* USB Transaction Error */ |
| 805 | #define COMP_TX_ERR 4 |
| 806 | /* TRB Error - some TRB field is invalid */ |
| 807 | #define COMP_TRB_ERR 5 |
| 808 | /* Stall Error - USB device is stalled */ |
| 809 | #define COMP_STALL 6 |
| 810 | /* Resource Error - HC doesn't have memory for that device configuration */ |
| 811 | #define COMP_ENOMEM 7 |
| 812 | /* Bandwidth Error - not enough room in schedule for this dev config */ |
| 813 | #define COMP_BW_ERR 8 |
| 814 | /* No Slots Available Error - HC ran out of device slots */ |
| 815 | #define COMP_ENOSLOTS 9 |
| 816 | /* Invalid Stream Type Error */ |
| 817 | #define COMP_STREAM_ERR 10 |
| 818 | /* Slot Not Enabled Error - doorbell rung for disabled device slot */ |
| 819 | #define COMP_EBADSLT 11 |
| 820 | /* Endpoint Not Enabled Error */ |
| 821 | #define COMP_EBADEP 12 |
| 822 | /* Short Packet */ |
| 823 | #define COMP_SHORT_TX 13 |
| 824 | /* Ring Underrun - doorbell rung for an empty isoc OUT ep ring */ |
| 825 | #define COMP_UNDERRUN 14 |
| 826 | /* Ring Overrun - isoc IN ep ring is empty when ep is scheduled to RX */ |
| 827 | #define COMP_OVERRUN 15 |
| 828 | /* Virtual Function Event Ring Full Error */ |
| 829 | #define COMP_VF_FULL 16 |
| 830 | /* Parameter Error - Context parameter is invalid */ |
| 831 | #define COMP_EINVAL 17 |
| 832 | /* Bandwidth Overrun Error - isoc ep exceeded its allocated bandwidth */ |
| 833 | #define COMP_BW_OVER 18 |
| 834 | /* Context State Error - illegal context state transition requested */ |
| 835 | #define COMP_CTX_STATE 19 |
| 836 | /* No Ping Response Error - HC didn't get PING_RESPONSE in time to TX */ |
| 837 | #define COMP_PING_ERR 20 |
| 838 | /* Event Ring is full */ |
| 839 | #define COMP_ER_FULL 21 |
| 840 | /* Missed Service Error - HC couldn't service an isoc ep within interval */ |
| 841 | #define COMP_MISSED_INT 23 |
| 842 | /* Successfully stopped command ring */ |
| 843 | #define COMP_CMD_STOP 24 |
| 844 | /* Successfully aborted current command and stopped command ring */ |
| 845 | #define COMP_CMD_ABORT 25 |
| 846 | /* Stopped - transfer was terminated by a stop endpoint command */ |
| 847 | #define COMP_STOP 26 |
| 848 | /* Same as COMP_EP_STOPPED, but the transfered length in the event is invalid */ |
| 849 | #define COMP_STOP_INVAL 27 |
| 850 | /* Control Abort Error - Debug Capability - control pipe aborted */ |
| 851 | #define COMP_DBG_ABORT 28 |
| 852 | /* TRB type 29 and 30 reserved */ |
| 853 | /* Isoc Buffer Overrun - an isoc IN ep sent more data than could fit in TD */ |
| 854 | #define COMP_BUFF_OVER 31 |
| 855 | /* Event Lost Error - xHC has an "internal event overrun condition" */ |
| 856 | #define COMP_ISSUES 32 |
| 857 | /* Undefined Error - reported when other error codes don't apply */ |
| 858 | #define COMP_UNKNOWN 33 |
| 859 | /* Invalid Stream ID Error */ |
| 860 | #define COMP_STRID_ERR 34 |
| 861 | /* Secondary Bandwidth Error - may be returned by a Configure Endpoint cmd */ |
| 862 | /* FIXME - check for this */ |
| 863 | #define COMP_2ND_BW_ERR 35 |
| 864 | /* Split Transaction Error */ |
| 865 | #define COMP_SPLIT_ERR 36 |
| 866 | |
| 867 | struct xhci_link_trb { |
| 868 | /* 64-bit segment pointer*/ |
Sarah Sharp | 8e595a5 | 2009-07-27 12:03:31 -0700 | [diff] [blame] | 869 | u64 segment_ptr; |
Sarah Sharp | 0ebbab3 | 2009-04-27 19:52:34 -0700 | [diff] [blame] | 870 | u32 intr_target; |
| 871 | u32 control; |
Sarah Sharp | 9844197 | 2009-05-14 11:44:18 -0700 | [diff] [blame] | 872 | }; |
Sarah Sharp | 0ebbab3 | 2009-04-27 19:52:34 -0700 | [diff] [blame] | 873 | |
| 874 | /* control bitfields */ |
| 875 | #define LINK_TOGGLE (0x1<<1) |
| 876 | |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 877 | /* Command completion event TRB */ |
| 878 | struct xhci_event_cmd { |
| 879 | /* Pointer to command TRB, or the value passed by the event data trb */ |
Sarah Sharp | 8e595a5 | 2009-07-27 12:03:31 -0700 | [diff] [blame] | 880 | u64 cmd_trb; |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 881 | u32 status; |
| 882 | u32 flags; |
Sarah Sharp | 9844197 | 2009-05-14 11:44:18 -0700 | [diff] [blame] | 883 | }; |
Sarah Sharp | 0ebbab3 | 2009-04-27 19:52:34 -0700 | [diff] [blame] | 884 | |
Sarah Sharp | 3ffbba9 | 2009-04-27 19:57:38 -0700 | [diff] [blame] | 885 | /* flags bitmasks */ |
| 886 | /* bits 16:23 are the virtual function ID */ |
| 887 | /* bits 24:31 are the slot ID */ |
| 888 | #define TRB_TO_SLOT_ID(p) (((p) & (0xff<<24)) >> 24) |
| 889 | #define SLOT_ID_FOR_TRB(p) (((p) & 0xff) << 24) |
Sarah Sharp | 0ebbab3 | 2009-04-27 19:52:34 -0700 | [diff] [blame] | 890 | |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 891 | /* Stop Endpoint TRB - ep_index to endpoint ID for this TRB */ |
| 892 | #define TRB_TO_EP_INDEX(p) ((((p) & (0x1f << 16)) >> 16) - 1) |
| 893 | #define EP_ID_FOR_TRB(p) ((((p) + 1) & 0x1f) << 16) |
| 894 | |
Andiry Xu | be88fe4 | 2010-10-14 07:22:57 -0700 | [diff] [blame] | 895 | #define SUSPEND_PORT_FOR_TRB(p) (((p) & 1) << 23) |
| 896 | #define TRB_TO_SUSPEND_PORT(p) (((p) & (1 << 23)) >> 23) |
| 897 | #define LAST_EP_INDEX 30 |
| 898 | |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 899 | /* Set TR Dequeue Pointer command TRB fields */ |
| 900 | #define TRB_TO_STREAM_ID(p) ((((p) & (0xffff << 16)) >> 16)) |
| 901 | #define STREAM_ID_FOR_TRB(p) ((((p)) & 0xffff) << 16) |
| 902 | |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 903 | |
Sarah Sharp | 0f2a793 | 2009-04-27 19:57:12 -0700 | [diff] [blame] | 904 | /* Port Status Change Event TRB fields */ |
| 905 | /* Port ID - bits 31:24 */ |
| 906 | #define GET_PORT_ID(p) (((p) & (0xff << 24)) >> 24) |
| 907 | |
Sarah Sharp | 0ebbab3 | 2009-04-27 19:52:34 -0700 | [diff] [blame] | 908 | /* Normal TRB fields */ |
| 909 | /* transfer_len bitmasks - bits 0:16 */ |
| 910 | #define TRB_LEN(p) ((p) & 0x1ffff) |
Sarah Sharp | 0ebbab3 | 2009-04-27 19:52:34 -0700 | [diff] [blame] | 911 | /* Interrupter Target - which MSI-X vector to target the completion event at */ |
| 912 | #define TRB_INTR_TARGET(p) (((p) & 0x3ff) << 22) |
| 913 | #define GET_INTR_TARGET(p) (((p) >> 22) & 0x3ff) |
| 914 | |
| 915 | /* Cycle bit - indicates TRB ownership by HC or HCD */ |
| 916 | #define TRB_CYCLE (1<<0) |
| 917 | /* |
| 918 | * Force next event data TRB to be evaluated before task switch. |
| 919 | * Used to pass OS data back after a TD completes. |
| 920 | */ |
| 921 | #define TRB_ENT (1<<1) |
| 922 | /* Interrupt on short packet */ |
| 923 | #define TRB_ISP (1<<2) |
| 924 | /* Set PCIe no snoop attribute */ |
| 925 | #define TRB_NO_SNOOP (1<<3) |
| 926 | /* Chain multiple TRBs into a TD */ |
| 927 | #define TRB_CHAIN (1<<4) |
| 928 | /* Interrupt on completion */ |
| 929 | #define TRB_IOC (1<<5) |
| 930 | /* The buffer pointer contains immediate data */ |
| 931 | #define TRB_IDT (1<<6) |
| 932 | |
| 933 | |
| 934 | /* Control transfer TRB specific fields */ |
| 935 | #define TRB_DIR_IN (1<<16) |
| 936 | |
Andiry Xu | 04e5190 | 2010-07-22 15:23:39 -0700 | [diff] [blame] | 937 | /* Isochronous TRB specific fields */ |
| 938 | #define TRB_SIA (1<<31) |
| 939 | |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 940 | struct xhci_generic_trb { |
| 941 | u32 field[4]; |
Sarah Sharp | 9844197 | 2009-05-14 11:44:18 -0700 | [diff] [blame] | 942 | }; |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 943 | |
| 944 | union xhci_trb { |
| 945 | struct xhci_link_trb link; |
| 946 | struct xhci_transfer_event trans_event; |
| 947 | struct xhci_event_cmd event_cmd; |
| 948 | struct xhci_generic_trb generic; |
| 949 | }; |
| 950 | |
Sarah Sharp | 0ebbab3 | 2009-04-27 19:52:34 -0700 | [diff] [blame] | 951 | /* TRB bit mask */ |
| 952 | #define TRB_TYPE_BITMASK (0xfc00) |
| 953 | #define TRB_TYPE(p) ((p) << 10) |
Sarah Sharp | 0238634 | 2010-05-24 13:25:28 -0700 | [diff] [blame] | 954 | #define TRB_FIELD_TO_TYPE(p) (((p) & TRB_TYPE_BITMASK) >> 10) |
Sarah Sharp | 0ebbab3 | 2009-04-27 19:52:34 -0700 | [diff] [blame] | 955 | /* TRB type IDs */ |
| 956 | /* bulk, interrupt, isoc scatter/gather, and control data stage */ |
| 957 | #define TRB_NORMAL 1 |
| 958 | /* setup stage for control transfers */ |
| 959 | #define TRB_SETUP 2 |
| 960 | /* data stage for control transfers */ |
| 961 | #define TRB_DATA 3 |
| 962 | /* status stage for control transfers */ |
| 963 | #define TRB_STATUS 4 |
| 964 | /* isoc transfers */ |
| 965 | #define TRB_ISOC 5 |
| 966 | /* TRB for linking ring segments */ |
| 967 | #define TRB_LINK 6 |
| 968 | #define TRB_EVENT_DATA 7 |
| 969 | /* Transfer Ring No-op (not for the command ring) */ |
| 970 | #define TRB_TR_NOOP 8 |
| 971 | /* Command TRBs */ |
| 972 | /* Enable Slot Command */ |
| 973 | #define TRB_ENABLE_SLOT 9 |
| 974 | /* Disable Slot Command */ |
| 975 | #define TRB_DISABLE_SLOT 10 |
| 976 | /* Address Device Command */ |
| 977 | #define TRB_ADDR_DEV 11 |
| 978 | /* Configure Endpoint Command */ |
| 979 | #define TRB_CONFIG_EP 12 |
| 980 | /* Evaluate Context Command */ |
| 981 | #define TRB_EVAL_CONTEXT 13 |
Sarah Sharp | a1587d9 | 2009-07-27 12:03:15 -0700 | [diff] [blame] | 982 | /* Reset Endpoint Command */ |
| 983 | #define TRB_RESET_EP 14 |
Sarah Sharp | 0ebbab3 | 2009-04-27 19:52:34 -0700 | [diff] [blame] | 984 | /* Stop Transfer Ring Command */ |
| 985 | #define TRB_STOP_RING 15 |
| 986 | /* Set Transfer Ring Dequeue Pointer Command */ |
| 987 | #define TRB_SET_DEQ 16 |
| 988 | /* Reset Device Command */ |
| 989 | #define TRB_RESET_DEV 17 |
| 990 | /* Force Event Command (opt) */ |
| 991 | #define TRB_FORCE_EVENT 18 |
| 992 | /* Negotiate Bandwidth Command (opt) */ |
| 993 | #define TRB_NEG_BANDWIDTH 19 |
| 994 | /* Set Latency Tolerance Value Command (opt) */ |
| 995 | #define TRB_SET_LT 20 |
| 996 | /* Get port bandwidth Command */ |
| 997 | #define TRB_GET_BW 21 |
| 998 | /* Force Header Command - generate a transaction or link management packet */ |
| 999 | #define TRB_FORCE_HEADER 22 |
| 1000 | /* No-op Command - not for transfer rings */ |
| 1001 | #define TRB_CMD_NOOP 23 |
| 1002 | /* TRB IDs 24-31 reserved */ |
| 1003 | /* Event TRBS */ |
| 1004 | /* Transfer Event */ |
| 1005 | #define TRB_TRANSFER 32 |
| 1006 | /* Command Completion Event */ |
| 1007 | #define TRB_COMPLETION 33 |
| 1008 | /* Port Status Change Event */ |
| 1009 | #define TRB_PORT_STATUS 34 |
| 1010 | /* Bandwidth Request Event (opt) */ |
| 1011 | #define TRB_BANDWIDTH_EVENT 35 |
| 1012 | /* Doorbell Event (opt) */ |
| 1013 | #define TRB_DOORBELL 36 |
| 1014 | /* Host Controller Event */ |
| 1015 | #define TRB_HC_EVENT 37 |
| 1016 | /* Device Notification Event - device sent function wake notification */ |
| 1017 | #define TRB_DEV_NOTE 38 |
| 1018 | /* MFINDEX Wrap Event - microframe counter wrapped */ |
| 1019 | #define TRB_MFINDEX_WRAP 39 |
| 1020 | /* TRB IDs 40-47 reserved, 48-63 is vendor-defined */ |
| 1021 | |
Sarah Sharp | 0238634 | 2010-05-24 13:25:28 -0700 | [diff] [blame] | 1022 | /* Nec vendor-specific command completion event. */ |
| 1023 | #define TRB_NEC_CMD_COMP 48 |
| 1024 | /* Get NEC firmware revision. */ |
| 1025 | #define TRB_NEC_GET_FW 49 |
| 1026 | |
| 1027 | #define NEC_FW_MINOR(p) (((p) >> 0) & 0xff) |
| 1028 | #define NEC_FW_MAJOR(p) (((p) >> 8) & 0xff) |
| 1029 | |
Sarah Sharp | 0ebbab3 | 2009-04-27 19:52:34 -0700 | [diff] [blame] | 1030 | /* |
| 1031 | * TRBS_PER_SEGMENT must be a multiple of 4, |
| 1032 | * since the command ring is 64-byte aligned. |
| 1033 | * It must also be greater than 16. |
| 1034 | */ |
| 1035 | #define TRBS_PER_SEGMENT 64 |
Sarah Sharp | 913a8a3 | 2009-09-04 10:53:13 -0700 | [diff] [blame] | 1036 | /* Allow two commands + a link TRB, along with any reserved command TRBs */ |
| 1037 | #define MAX_RSVD_CMD_TRBS (TRBS_PER_SEGMENT - 3) |
Sarah Sharp | 0ebbab3 | 2009-04-27 19:52:34 -0700 | [diff] [blame] | 1038 | #define SEGMENT_SIZE (TRBS_PER_SEGMENT*16) |
Sarah Sharp | 8df75f4 | 2010-04-02 15:34:16 -0700 | [diff] [blame] | 1039 | /* SEGMENT_SHIFT should be log2(SEGMENT_SIZE). |
| 1040 | * Change this if you change TRBS_PER_SEGMENT! |
| 1041 | */ |
| 1042 | #define SEGMENT_SHIFT 10 |
Sarah Sharp | b10de14 | 2009-04-27 19:58:50 -0700 | [diff] [blame] | 1043 | /* TRB buffer pointers can't cross 64KB boundaries */ |
| 1044 | #define TRB_MAX_BUFF_SHIFT 16 |
| 1045 | #define TRB_MAX_BUFF_SIZE (1 << TRB_MAX_BUFF_SHIFT) |
Sarah Sharp | 0ebbab3 | 2009-04-27 19:52:34 -0700 | [diff] [blame] | 1046 | |
| 1047 | struct xhci_segment { |
| 1048 | union xhci_trb *trbs; |
| 1049 | /* private to HCD */ |
| 1050 | struct xhci_segment *next; |
| 1051 | dma_addr_t dma; |
Sarah Sharp | 9844197 | 2009-05-14 11:44:18 -0700 | [diff] [blame] | 1052 | }; |
Sarah Sharp | 0ebbab3 | 2009-04-27 19:52:34 -0700 | [diff] [blame] | 1053 | |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 1054 | struct xhci_td { |
| 1055 | struct list_head td_list; |
| 1056 | struct list_head cancelled_td_list; |
| 1057 | struct urb *urb; |
| 1058 | struct xhci_segment *start_seg; |
| 1059 | union xhci_trb *first_trb; |
| 1060 | union xhci_trb *last_trb; |
| 1061 | }; |
| 1062 | |
Sarah Sharp | ac9d8fe | 2009-08-07 14:04:55 -0700 | [diff] [blame] | 1063 | struct xhci_dequeue_state { |
| 1064 | struct xhci_segment *new_deq_seg; |
| 1065 | union xhci_trb *new_deq_ptr; |
| 1066 | int new_cycle_state; |
| 1067 | }; |
| 1068 | |
Sarah Sharp | 0ebbab3 | 2009-04-27 19:52:34 -0700 | [diff] [blame] | 1069 | struct xhci_ring { |
| 1070 | struct xhci_segment *first_seg; |
| 1071 | union xhci_trb *enqueue; |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 1072 | struct xhci_segment *enq_seg; |
| 1073 | unsigned int enq_updates; |
Sarah Sharp | 0ebbab3 | 2009-04-27 19:52:34 -0700 | [diff] [blame] | 1074 | union xhci_trb *dequeue; |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 1075 | struct xhci_segment *deq_seg; |
| 1076 | unsigned int deq_updates; |
Sarah Sharp | d0e96f5 | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 1077 | struct list_head td_list; |
Sarah Sharp | 0ebbab3 | 2009-04-27 19:52:34 -0700 | [diff] [blame] | 1078 | /* |
| 1079 | * Write the cycle state into the TRB cycle field to give ownership of |
| 1080 | * the TRB to the host controller (if we are the producer), or to check |
| 1081 | * if we own the TRB (if we are the consumer). See section 4.9.1. |
| 1082 | */ |
| 1083 | u32 cycle_state; |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 1084 | unsigned int stream_id; |
Sarah Sharp | 0ebbab3 | 2009-04-27 19:52:34 -0700 | [diff] [blame] | 1085 | }; |
| 1086 | |
| 1087 | struct xhci_erst_entry { |
| 1088 | /* 64-bit event ring segment address */ |
Sarah Sharp | 8e595a5 | 2009-07-27 12:03:31 -0700 | [diff] [blame] | 1089 | u64 seg_addr; |
Sarah Sharp | 0ebbab3 | 2009-04-27 19:52:34 -0700 | [diff] [blame] | 1090 | u32 seg_size; |
| 1091 | /* Set to zero */ |
| 1092 | u32 rsvd; |
Sarah Sharp | 9844197 | 2009-05-14 11:44:18 -0700 | [diff] [blame] | 1093 | }; |
Sarah Sharp | 0ebbab3 | 2009-04-27 19:52:34 -0700 | [diff] [blame] | 1094 | |
| 1095 | struct xhci_erst { |
| 1096 | struct xhci_erst_entry *entries; |
| 1097 | unsigned int num_entries; |
| 1098 | /* xhci->event_ring keeps track of segment dma addresses */ |
| 1099 | dma_addr_t erst_dma_addr; |
| 1100 | /* Num entries the ERST can contain */ |
| 1101 | unsigned int erst_size; |
| 1102 | }; |
| 1103 | |
John Youn | 254c80a | 2009-07-27 12:05:03 -0700 | [diff] [blame] | 1104 | struct xhci_scratchpad { |
| 1105 | u64 *sp_array; |
| 1106 | dma_addr_t sp_dma; |
| 1107 | void **sp_buffers; |
| 1108 | dma_addr_t *sp_dma_buffers; |
| 1109 | }; |
| 1110 | |
Andiry Xu | 8e51adc | 2010-07-22 15:23:31 -0700 | [diff] [blame] | 1111 | struct urb_priv { |
| 1112 | int length; |
| 1113 | int td_cnt; |
| 1114 | struct xhci_td *td[0]; |
| 1115 | }; |
| 1116 | |
Sarah Sharp | 0ebbab3 | 2009-04-27 19:52:34 -0700 | [diff] [blame] | 1117 | /* |
| 1118 | * Each segment table entry is 4*32bits long. 1K seems like an ok size: |
| 1119 | * (1K bytes * 8bytes/bit) / (4*32 bits) = 64 segment entries in the table, |
| 1120 | * meaning 64 ring segments. |
| 1121 | * Initial allocated size of the ERST, in number of entries */ |
| 1122 | #define ERST_NUM_SEGS 1 |
| 1123 | /* Initial allocated size of the ERST, in number of entries */ |
| 1124 | #define ERST_SIZE 64 |
| 1125 | /* Initial number of event segment rings allocated */ |
| 1126 | #define ERST_ENTRIES 1 |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 1127 | /* Poll every 60 seconds */ |
| 1128 | #define POLL_TIMEOUT 60 |
Sarah Sharp | 6f5165c | 2009-10-27 10:57:01 -0700 | [diff] [blame] | 1129 | /* Stop endpoint command timeout (secs) for URB cancellation watchdog timer */ |
| 1130 | #define XHCI_STOP_EP_CMD_TIMEOUT 5 |
Sarah Sharp | 0ebbab3 | 2009-04-27 19:52:34 -0700 | [diff] [blame] | 1131 | /* XXX: Make these module parameters */ |
| 1132 | |
Andiry Xu | 5535b1d | 2010-10-14 07:23:06 -0700 | [diff] [blame] | 1133 | struct s3_save { |
| 1134 | u32 command; |
| 1135 | u32 dev_nt; |
| 1136 | u64 dcbaa_ptr; |
| 1137 | u32 config_reg; |
| 1138 | u32 irq_pending; |
| 1139 | u32 irq_control; |
| 1140 | u32 erst_size; |
| 1141 | u64 erst_base; |
| 1142 | u64 erst_dequeue; |
| 1143 | }; |
Sarah Sharp | 74c6874 | 2009-04-27 19:52:22 -0700 | [diff] [blame] | 1144 | |
| 1145 | /* There is one ehci_hci structure per controller */ |
| 1146 | struct xhci_hcd { |
| 1147 | /* glue to PCI and HCD framework */ |
| 1148 | struct xhci_cap_regs __iomem *cap_regs; |
| 1149 | struct xhci_op_regs __iomem *op_regs; |
| 1150 | struct xhci_run_regs __iomem *run_regs; |
Sarah Sharp | 0ebbab3 | 2009-04-27 19:52:34 -0700 | [diff] [blame] | 1151 | struct xhci_doorbell_array __iomem *dba; |
Sarah Sharp | 66d4ead | 2009-04-27 19:52:28 -0700 | [diff] [blame] | 1152 | /* Our HCD's current interrupter register set */ |
Sarah Sharp | 9844197 | 2009-05-14 11:44:18 -0700 | [diff] [blame] | 1153 | struct xhci_intr_reg __iomem *ir_set; |
Sarah Sharp | 74c6874 | 2009-04-27 19:52:22 -0700 | [diff] [blame] | 1154 | |
| 1155 | /* Cached register copies of read-only HC data */ |
| 1156 | __u32 hcs_params1; |
| 1157 | __u32 hcs_params2; |
| 1158 | __u32 hcs_params3; |
| 1159 | __u32 hcc_params; |
| 1160 | |
| 1161 | spinlock_t lock; |
| 1162 | |
| 1163 | /* packed release number */ |
| 1164 | u8 sbrn; |
| 1165 | u16 hci_version; |
| 1166 | u8 max_slots; |
| 1167 | u8 max_interrupters; |
| 1168 | u8 max_ports; |
| 1169 | u8 isoc_threshold; |
| 1170 | int event_ring_max; |
| 1171 | int addr_64; |
Sarah Sharp | 66d4ead | 2009-04-27 19:52:28 -0700 | [diff] [blame] | 1172 | /* 4KB min, 128MB max */ |
Sarah Sharp | 74c6874 | 2009-04-27 19:52:22 -0700 | [diff] [blame] | 1173 | int page_size; |
Sarah Sharp | 66d4ead | 2009-04-27 19:52:28 -0700 | [diff] [blame] | 1174 | /* Valid values are 12 to 20, inclusive */ |
| 1175 | int page_shift; |
Dong Nguyen | 43b86af | 2010-07-21 16:56:08 -0700 | [diff] [blame] | 1176 | /* msi-x vectors */ |
Sarah Sharp | 66d4ead | 2009-04-27 19:52:28 -0700 | [diff] [blame] | 1177 | int msix_count; |
| 1178 | struct msix_entry *msix_entries; |
Sarah Sharp | 0ebbab3 | 2009-04-27 19:52:34 -0700 | [diff] [blame] | 1179 | /* data structures */ |
Sarah Sharp | a74588f | 2009-04-27 19:53:42 -0700 | [diff] [blame] | 1180 | struct xhci_device_context_array *dcbaa; |
Sarah Sharp | 0ebbab3 | 2009-04-27 19:52:34 -0700 | [diff] [blame] | 1181 | struct xhci_ring *cmd_ring; |
Sarah Sharp | 913a8a3 | 2009-09-04 10:53:13 -0700 | [diff] [blame] | 1182 | unsigned int cmd_ring_reserved_trbs; |
Sarah Sharp | 0ebbab3 | 2009-04-27 19:52:34 -0700 | [diff] [blame] | 1183 | struct xhci_ring *event_ring; |
| 1184 | struct xhci_erst erst; |
John Youn | 254c80a | 2009-07-27 12:05:03 -0700 | [diff] [blame] | 1185 | /* Scratchpad */ |
| 1186 | struct xhci_scratchpad *scratchpad; |
| 1187 | |
Sarah Sharp | 3ffbba9 | 2009-04-27 19:57:38 -0700 | [diff] [blame] | 1188 | /* slot enabling and address device helpers */ |
| 1189 | struct completion addr_dev; |
| 1190 | int slot_id; |
| 1191 | /* Internal mirror of the HW's dcbaa */ |
| 1192 | struct xhci_virt_device *devs[MAX_HC_SLOTS]; |
Sarah Sharp | 0ebbab3 | 2009-04-27 19:52:34 -0700 | [diff] [blame] | 1193 | |
| 1194 | /* DMA pools */ |
| 1195 | struct dma_pool *device_pool; |
| 1196 | struct dma_pool *segment_pool; |
Sarah Sharp | 8df75f4 | 2010-04-02 15:34:16 -0700 | [diff] [blame] | 1197 | struct dma_pool *small_streams_pool; |
| 1198 | struct dma_pool *medium_streams_pool; |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 1199 | |
| 1200 | #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING |
| 1201 | /* Poll the rings - for debugging */ |
| 1202 | struct timer_list event_ring_timer; |
| 1203 | int zombie; |
| 1204 | #endif |
Sarah Sharp | 6f5165c | 2009-10-27 10:57:01 -0700 | [diff] [blame] | 1205 | /* Host controller watchdog timer structures */ |
| 1206 | unsigned int xhc_state; |
Andiry Xu | 9777e3c | 2010-10-14 07:23:03 -0700 | [diff] [blame] | 1207 | |
| 1208 | unsigned long bus_suspended; |
| 1209 | unsigned long next_statechange; |
| 1210 | |
| 1211 | u32 command; |
Andiry Xu | 5535b1d | 2010-10-14 07:23:06 -0700 | [diff] [blame] | 1212 | struct s3_save s3; |
Sarah Sharp | 6f5165c | 2009-10-27 10:57:01 -0700 | [diff] [blame] | 1213 | /* Host controller is dying - not responding to commands. "I'm not dead yet!" |
| 1214 | * |
| 1215 | * xHC interrupts have been disabled and a watchdog timer will (or has already) |
| 1216 | * halt the xHCI host, and complete all URBs with an -ESHUTDOWN code. Any code |
| 1217 | * that sees this status (other than the timer that set it) should stop touching |
| 1218 | * hardware immediately. Interrupt handlers should return immediately when |
| 1219 | * they see this status (any time they drop and re-acquire xhci->lock). |
| 1220 | * xhci_urb_dequeue() should call usb_hcd_check_unlink_urb() and return without |
| 1221 | * putting the TD on the canceled list, etc. |
| 1222 | * |
| 1223 | * There are no reports of xHCI host controllers that display this issue. |
| 1224 | */ |
| 1225 | #define XHCI_STATE_DYING (1 << 0) |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 1226 | /* Statistics */ |
| 1227 | int noops_submitted; |
| 1228 | int noops_handled; |
| 1229 | int error_bitmask; |
Sarah Sharp | b0567b3 | 2009-08-07 14:04:36 -0700 | [diff] [blame] | 1230 | unsigned int quirks; |
| 1231 | #define XHCI_LINK_TRB_QUIRK (1 << 0) |
Sarah Sharp | ac9d8fe | 2009-08-07 14:04:55 -0700 | [diff] [blame] | 1232 | #define XHCI_RESET_EP_QUIRK (1 << 1) |
Sarah Sharp | 0238634 | 2010-05-24 13:25:28 -0700 | [diff] [blame] | 1233 | #define XHCI_NEC_HOST (1 << 2) |
Andiry Xu | be88fe4 | 2010-10-14 07:22:57 -0700 | [diff] [blame] | 1234 | u32 port_c_suspend[8]; /* port suspend change*/ |
| 1235 | u32 suspended_ports[8]; /* which ports are |
| 1236 | suspended */ |
Andiry Xu | 5619253 | 2010-10-14 07:23:00 -0700 | [diff] [blame] | 1237 | unsigned long resume_done[MAX_HC_PORTS]; |
Sarah Sharp | 74c6874 | 2009-04-27 19:52:22 -0700 | [diff] [blame] | 1238 | }; |
| 1239 | |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 1240 | /* For testing purposes */ |
| 1241 | #define NUM_TEST_NOOPS 0 |
| 1242 | |
Sarah Sharp | 74c6874 | 2009-04-27 19:52:22 -0700 | [diff] [blame] | 1243 | /* convert between an HCD pointer and the corresponding EHCI_HCD */ |
| 1244 | static inline struct xhci_hcd *hcd_to_xhci(struct usb_hcd *hcd) |
| 1245 | { |
| 1246 | return (struct xhci_hcd *) (hcd->hcd_priv); |
| 1247 | } |
| 1248 | |
| 1249 | static inline struct usb_hcd *xhci_to_hcd(struct xhci_hcd *xhci) |
| 1250 | { |
| 1251 | return container_of((void *) xhci, struct usb_hcd, hcd_priv); |
| 1252 | } |
| 1253 | |
| 1254 | #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING |
| 1255 | #define XHCI_DEBUG 1 |
| 1256 | #else |
| 1257 | #define XHCI_DEBUG 0 |
| 1258 | #endif |
| 1259 | |
| 1260 | #define xhci_dbg(xhci, fmt, args...) \ |
| 1261 | do { if (XHCI_DEBUG) dev_dbg(xhci_to_hcd(xhci)->self.controller , fmt , ## args); } while (0) |
| 1262 | #define xhci_info(xhci, fmt, args...) \ |
| 1263 | do { if (XHCI_DEBUG) dev_info(xhci_to_hcd(xhci)->self.controller , fmt , ## args); } while (0) |
| 1264 | #define xhci_err(xhci, fmt, args...) \ |
| 1265 | dev_err(xhci_to_hcd(xhci)->self.controller , fmt , ## args) |
| 1266 | #define xhci_warn(xhci, fmt, args...) \ |
| 1267 | dev_warn(xhci_to_hcd(xhci)->self.controller , fmt , ## args) |
| 1268 | |
| 1269 | /* TODO: copied from ehci.h - can be refactored? */ |
| 1270 | /* xHCI spec says all registers are little endian */ |
| 1271 | static inline unsigned int xhci_readl(const struct xhci_hcd *xhci, |
| 1272 | __u32 __iomem *regs) |
| 1273 | { |
| 1274 | return readl(regs); |
| 1275 | } |
Greg Kroah-Hartman | 045f123 | 2009-04-29 19:12:44 -0700 | [diff] [blame] | 1276 | static inline void xhci_writel(struct xhci_hcd *xhci, |
Sarah Sharp | 74c6874 | 2009-04-27 19:52:22 -0700 | [diff] [blame] | 1277 | const unsigned int val, __u32 __iomem *regs) |
| 1278 | { |
Sarah Sharp | 66e49d8 | 2009-07-27 12:03:46 -0700 | [diff] [blame] | 1279 | xhci_dbg(xhci, |
| 1280 | "`MEM_WRITE_DWORD(3'b000, 32'h%p, 32'h%0x, 4'hf);\n", |
| 1281 | regs, val); |
Sarah Sharp | 74c6874 | 2009-04-27 19:52:22 -0700 | [diff] [blame] | 1282 | writel(val, regs); |
| 1283 | } |
| 1284 | |
Sarah Sharp | 8e595a5 | 2009-07-27 12:03:31 -0700 | [diff] [blame] | 1285 | /* |
| 1286 | * Registers should always be accessed with double word or quad word accesses. |
| 1287 | * |
| 1288 | * Some xHCI implementations may support 64-bit address pointers. Registers |
| 1289 | * with 64-bit address pointers should be written to with dword accesses by |
| 1290 | * writing the low dword first (ptr[0]), then the high dword (ptr[1]) second. |
| 1291 | * xHCI implementations that do not support 64-bit address pointers will ignore |
| 1292 | * the high dword, and write order is irrelevant. |
| 1293 | */ |
| 1294 | static inline u64 xhci_read_64(const struct xhci_hcd *xhci, |
| 1295 | __u64 __iomem *regs) |
| 1296 | { |
| 1297 | __u32 __iomem *ptr = (__u32 __iomem *) regs; |
| 1298 | u64 val_lo = readl(ptr); |
| 1299 | u64 val_hi = readl(ptr + 1); |
| 1300 | return val_lo + (val_hi << 32); |
| 1301 | } |
| 1302 | static inline void xhci_write_64(struct xhci_hcd *xhci, |
| 1303 | const u64 val, __u64 __iomem *regs) |
| 1304 | { |
| 1305 | __u32 __iomem *ptr = (__u32 __iomem *) regs; |
| 1306 | u32 val_lo = lower_32_bits(val); |
| 1307 | u32 val_hi = upper_32_bits(val); |
| 1308 | |
Sarah Sharp | 66e49d8 | 2009-07-27 12:03:46 -0700 | [diff] [blame] | 1309 | xhci_dbg(xhci, |
| 1310 | "`MEM_WRITE_DWORD(3'b000, 64'h%p, 64'h%0lx, 4'hf);\n", |
| 1311 | regs, (long unsigned int) val); |
Sarah Sharp | 8e595a5 | 2009-07-27 12:03:31 -0700 | [diff] [blame] | 1312 | writel(val_lo, ptr); |
| 1313 | writel(val_hi, ptr + 1); |
| 1314 | } |
| 1315 | |
Sarah Sharp | b0567b3 | 2009-08-07 14:04:36 -0700 | [diff] [blame] | 1316 | static inline int xhci_link_trb_quirk(struct xhci_hcd *xhci) |
| 1317 | { |
| 1318 | u32 temp = xhci_readl(xhci, &xhci->cap_regs->hc_capbase); |
| 1319 | return ((HC_VERSION(temp) == 0x95) && |
| 1320 | (xhci->quirks & XHCI_LINK_TRB_QUIRK)); |
| 1321 | } |
| 1322 | |
Sarah Sharp | 66d4ead | 2009-04-27 19:52:28 -0700 | [diff] [blame] | 1323 | /* xHCI debugging */ |
Sarah Sharp | 9844197 | 2009-05-14 11:44:18 -0700 | [diff] [blame] | 1324 | void xhci_print_ir_set(struct xhci_hcd *xhci, struct xhci_intr_reg *ir_set, int set_num); |
Sarah Sharp | 66d4ead | 2009-04-27 19:52:28 -0700 | [diff] [blame] | 1325 | void xhci_print_registers(struct xhci_hcd *xhci); |
Sarah Sharp | 0ebbab3 | 2009-04-27 19:52:34 -0700 | [diff] [blame] | 1326 | void xhci_dbg_regs(struct xhci_hcd *xhci); |
| 1327 | void xhci_print_run_regs(struct xhci_hcd *xhci); |
Sarah Sharp | d0e96f5 | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 1328 | void xhci_print_trb_offsets(struct xhci_hcd *xhci, union xhci_trb *trb); |
| 1329 | void xhci_debug_trb(struct xhci_hcd *xhci, union xhci_trb *trb); |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 1330 | void xhci_debug_segment(struct xhci_hcd *xhci, struct xhci_segment *seg); |
Sarah Sharp | 0ebbab3 | 2009-04-27 19:52:34 -0700 | [diff] [blame] | 1331 | void xhci_debug_ring(struct xhci_hcd *xhci, struct xhci_ring *ring); |
| 1332 | void xhci_dbg_erst(struct xhci_hcd *xhci, struct xhci_erst *erst); |
| 1333 | void xhci_dbg_cmd_ptrs(struct xhci_hcd *xhci); |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 1334 | void xhci_dbg_ring_ptrs(struct xhci_hcd *xhci, struct xhci_ring *ring); |
John Youn | d115b04 | 2009-07-27 12:05:15 -0700 | [diff] [blame] | 1335 | void xhci_dbg_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int last_ep); |
Sarah Sharp | 9c9a7db | 2010-01-04 12:20:17 -0800 | [diff] [blame] | 1336 | char *xhci_get_slot_state(struct xhci_hcd *xhci, |
Sarah Sharp | 2a8f82c | 2009-12-09 15:59:13 -0800 | [diff] [blame] | 1337 | struct xhci_container_ctx *ctx); |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 1338 | void xhci_dbg_ep_rings(struct xhci_hcd *xhci, |
| 1339 | unsigned int slot_id, unsigned int ep_index, |
| 1340 | struct xhci_virt_ep *ep); |
Sarah Sharp | 66d4ead | 2009-04-27 19:52:28 -0700 | [diff] [blame] | 1341 | |
Uwe Kleine-Koenig | 3dbda77 | 2009-07-23 08:31:31 +0200 | [diff] [blame] | 1342 | /* xHCI memory management */ |
Sarah Sharp | 66d4ead | 2009-04-27 19:52:28 -0700 | [diff] [blame] | 1343 | void xhci_mem_cleanup(struct xhci_hcd *xhci); |
| 1344 | int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags); |
Sarah Sharp | 3ffbba9 | 2009-04-27 19:57:38 -0700 | [diff] [blame] | 1345 | void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id); |
| 1346 | int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id, struct usb_device *udev, gfp_t flags); |
| 1347 | int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev); |
Sarah Sharp | 2d1ee59 | 2010-07-09 17:08:54 +0200 | [diff] [blame] | 1348 | void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci, |
| 1349 | struct usb_device *udev); |
Sarah Sharp | d0e96f5 | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 1350 | unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc); |
Sarah Sharp | f94e0186 | 2009-04-27 19:58:38 -0700 | [diff] [blame] | 1351 | unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc); |
Sarah Sharp | ac9d8fe | 2009-08-07 14:04:55 -0700 | [diff] [blame] | 1352 | unsigned int xhci_get_endpoint_flag_from_index(unsigned int ep_index); |
| 1353 | unsigned int xhci_last_valid_endpoint(u32 added_ctxs); |
Sarah Sharp | f94e0186 | 2009-04-27 19:58:38 -0700 | [diff] [blame] | 1354 | void xhci_endpoint_zero(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, struct usb_host_endpoint *ep); |
Sarah Sharp | f2217e8 | 2009-08-07 14:04:43 -0700 | [diff] [blame] | 1355 | void xhci_endpoint_copy(struct xhci_hcd *xhci, |
Sarah Sharp | 913a8a3 | 2009-09-04 10:53:13 -0700 | [diff] [blame] | 1356 | struct xhci_container_ctx *in_ctx, |
| 1357 | struct xhci_container_ctx *out_ctx, |
| 1358 | unsigned int ep_index); |
| 1359 | void xhci_slot_copy(struct xhci_hcd *xhci, |
| 1360 | struct xhci_container_ctx *in_ctx, |
| 1361 | struct xhci_container_ctx *out_ctx); |
Sarah Sharp | f88ba78 | 2009-05-14 11:44:22 -0700 | [diff] [blame] | 1362 | int xhci_endpoint_init(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, |
| 1363 | struct usb_device *udev, struct usb_host_endpoint *ep, |
| 1364 | gfp_t mem_flags); |
Sarah Sharp | f94e0186 | 2009-04-27 19:58:38 -0700 | [diff] [blame] | 1365 | void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring); |
Sarah Sharp | 412566b | 2009-12-09 15:59:01 -0800 | [diff] [blame] | 1366 | void xhci_free_or_cache_endpoint_ring(struct xhci_hcd *xhci, |
| 1367 | struct xhci_virt_device *virt_dev, |
| 1368 | unsigned int ep_index); |
Sarah Sharp | 8df75f4 | 2010-04-02 15:34:16 -0700 | [diff] [blame] | 1369 | struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci, |
| 1370 | unsigned int num_stream_ctxs, |
| 1371 | unsigned int num_streams, gfp_t flags); |
| 1372 | void xhci_free_stream_info(struct xhci_hcd *xhci, |
| 1373 | struct xhci_stream_info *stream_info); |
| 1374 | void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci, |
| 1375 | struct xhci_ep_ctx *ep_ctx, |
| 1376 | struct xhci_stream_info *stream_info); |
| 1377 | void xhci_setup_no_streams_ep_input_ctx(struct xhci_hcd *xhci, |
| 1378 | struct xhci_ep_ctx *ep_ctx, |
| 1379 | struct xhci_virt_ep *ep); |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 1380 | struct xhci_ring *xhci_dma_to_transfer_ring( |
| 1381 | struct xhci_virt_ep *ep, |
| 1382 | u64 address); |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 1383 | struct xhci_ring *xhci_stream_id_to_ring( |
| 1384 | struct xhci_virt_device *dev, |
| 1385 | unsigned int ep_index, |
| 1386 | unsigned int stream_id); |
Sarah Sharp | 913a8a3 | 2009-09-04 10:53:13 -0700 | [diff] [blame] | 1387 | struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci, |
Sarah Sharp | a1d78c1 | 2009-12-09 15:59:03 -0800 | [diff] [blame] | 1388 | bool allocate_in_ctx, bool allocate_completion, |
| 1389 | gfp_t mem_flags); |
Andiry Xu | 8e51adc | 2010-07-22 15:23:31 -0700 | [diff] [blame] | 1390 | void xhci_urb_free_priv(struct xhci_hcd *xhci, struct urb_priv *urb_priv); |
Sarah Sharp | 913a8a3 | 2009-09-04 10:53:13 -0700 | [diff] [blame] | 1391 | void xhci_free_command(struct xhci_hcd *xhci, |
| 1392 | struct xhci_command *command); |
Sarah Sharp | 66d4ead | 2009-04-27 19:52:28 -0700 | [diff] [blame] | 1393 | |
| 1394 | #ifdef CONFIG_PCI |
| 1395 | /* xHCI PCI glue */ |
| 1396 | int xhci_register_pci(void); |
| 1397 | void xhci_unregister_pci(void); |
| 1398 | #endif |
| 1399 | |
| 1400 | /* xHCI host controller glue */ |
Sarah Sharp | 4f0f0ba | 2009-10-27 10:56:33 -0700 | [diff] [blame] | 1401 | void xhci_quiesce(struct xhci_hcd *xhci); |
Sarah Sharp | 66d4ead | 2009-04-27 19:52:28 -0700 | [diff] [blame] | 1402 | int xhci_halt(struct xhci_hcd *xhci); |
| 1403 | int xhci_reset(struct xhci_hcd *xhci); |
| 1404 | int xhci_init(struct usb_hcd *hcd); |
| 1405 | int xhci_run(struct usb_hcd *hcd); |
| 1406 | void xhci_stop(struct usb_hcd *hcd); |
| 1407 | void xhci_shutdown(struct usb_hcd *hcd); |
Sarah Sharp | 436a389 | 2010-10-15 14:59:15 -0700 | [diff] [blame] | 1408 | |
| 1409 | #ifdef CONFIG_PM |
Andiry Xu | 5535b1d | 2010-10-14 07:23:06 -0700 | [diff] [blame] | 1410 | int xhci_suspend(struct xhci_hcd *xhci); |
| 1411 | int xhci_resume(struct xhci_hcd *xhci, bool hibernated); |
Sarah Sharp | 436a389 | 2010-10-15 14:59:15 -0700 | [diff] [blame] | 1412 | #else |
| 1413 | #define xhci_suspend NULL |
| 1414 | #define xhci_resume NULL |
| 1415 | #endif |
| 1416 | |
Sarah Sharp | 66d4ead | 2009-04-27 19:52:28 -0700 | [diff] [blame] | 1417 | int xhci_get_frame(struct usb_hcd *hcd); |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 1418 | irqreturn_t xhci_irq(struct usb_hcd *hcd); |
Sarah Sharp | 9032cd5 | 2010-07-29 22:12:29 -0700 | [diff] [blame] | 1419 | irqreturn_t xhci_msi_irq(int irq, struct usb_hcd *hcd); |
Sarah Sharp | 3ffbba9 | 2009-04-27 19:57:38 -0700 | [diff] [blame] | 1420 | int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev); |
| 1421 | void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev); |
Sarah Sharp | 8df75f4 | 2010-04-02 15:34:16 -0700 | [diff] [blame] | 1422 | int xhci_alloc_streams(struct usb_hcd *hcd, struct usb_device *udev, |
| 1423 | struct usb_host_endpoint **eps, unsigned int num_eps, |
| 1424 | unsigned int num_streams, gfp_t mem_flags); |
| 1425 | int xhci_free_streams(struct usb_hcd *hcd, struct usb_device *udev, |
| 1426 | struct usb_host_endpoint **eps, unsigned int num_eps, |
| 1427 | gfp_t mem_flags); |
Sarah Sharp | 3ffbba9 | 2009-04-27 19:57:38 -0700 | [diff] [blame] | 1428 | int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev); |
Sarah Sharp | ac1c1b7 | 2009-09-04 10:53:20 -0700 | [diff] [blame] | 1429 | int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev, |
| 1430 | struct usb_tt *tt, gfp_t mem_flags); |
Sarah Sharp | d0e96f5 | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 1431 | int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags); |
| 1432 | int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status); |
Sarah Sharp | f94e0186 | 2009-04-27 19:58:38 -0700 | [diff] [blame] | 1433 | int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev, struct usb_host_endpoint *ep); |
| 1434 | int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev, struct usb_host_endpoint *ep); |
Sarah Sharp | a1587d9 | 2009-07-27 12:03:15 -0700 | [diff] [blame] | 1435 | void xhci_endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep); |
Andiry Xu | f0615c4 | 2010-10-14 07:22:48 -0700 | [diff] [blame] | 1436 | int xhci_discover_or_reset_device(struct usb_hcd *hcd, struct usb_device *udev); |
Sarah Sharp | f94e0186 | 2009-04-27 19:58:38 -0700 | [diff] [blame] | 1437 | int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev); |
| 1438 | void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev); |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 1439 | |
| 1440 | /* xHCI ring, segment, TRB, and TD functions */ |
Sarah Sharp | 23e3be1 | 2009-04-29 19:05:20 -0700 | [diff] [blame] | 1441 | dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, union xhci_trb *trb); |
Sarah Sharp | 6648f29 | 2009-11-09 13:35:23 -0800 | [diff] [blame] | 1442 | struct xhci_segment *trb_in_td(struct xhci_segment *start_seg, |
| 1443 | union xhci_trb *start_trb, union xhci_trb *end_trb, |
| 1444 | dma_addr_t suspect_dma); |
Sarah Sharp | b45b506 | 2009-12-09 15:59:06 -0800 | [diff] [blame] | 1445 | int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code); |
Sarah Sharp | 23e3be1 | 2009-04-29 19:05:20 -0700 | [diff] [blame] | 1446 | void xhci_ring_cmd_db(struct xhci_hcd *xhci); |
| 1447 | void *xhci_setup_one_noop(struct xhci_hcd *xhci); |
Sarah Sharp | 23e3be1 | 2009-04-29 19:05:20 -0700 | [diff] [blame] | 1448 | int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id); |
| 1449 | int xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr, |
| 1450 | u32 slot_id); |
Sarah Sharp | 0238634 | 2010-05-24 13:25:28 -0700 | [diff] [blame] | 1451 | int xhci_queue_vendor_command(struct xhci_hcd *xhci, |
| 1452 | u32 field1, u32 field2, u32 field3, u32 field4); |
Sarah Sharp | 23e3be1 | 2009-04-29 19:05:20 -0700 | [diff] [blame] | 1453 | int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id, |
Andiry Xu | be88fe4 | 2010-10-14 07:22:57 -0700 | [diff] [blame] | 1454 | unsigned int ep_index, int suspend); |
Sarah Sharp | 23e3be1 | 2009-04-29 19:05:20 -0700 | [diff] [blame] | 1455 | int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb, |
| 1456 | int slot_id, unsigned int ep_index); |
| 1457 | int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb, |
| 1458 | int slot_id, unsigned int ep_index); |
Sarah Sharp | 624defa | 2009-09-02 12:14:28 -0700 | [diff] [blame] | 1459 | int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb, |
| 1460 | int slot_id, unsigned int ep_index); |
Andiry Xu | 04e5190 | 2010-07-22 15:23:39 -0700 | [diff] [blame] | 1461 | int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags, |
| 1462 | struct urb *urb, int slot_id, unsigned int ep_index); |
Sarah Sharp | 23e3be1 | 2009-04-29 19:05:20 -0700 | [diff] [blame] | 1463 | int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr, |
Sarah Sharp | 913a8a3 | 2009-09-04 10:53:13 -0700 | [diff] [blame] | 1464 | u32 slot_id, bool command_must_succeed); |
Sarah Sharp | f2217e8 | 2009-08-07 14:04:43 -0700 | [diff] [blame] | 1465 | int xhci_queue_evaluate_context(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr, |
| 1466 | u32 slot_id); |
Sarah Sharp | a1587d9 | 2009-07-27 12:03:15 -0700 | [diff] [blame] | 1467 | int xhci_queue_reset_ep(struct xhci_hcd *xhci, int slot_id, |
| 1468 | unsigned int ep_index); |
Sarah Sharp | 2a8f82c | 2009-12-09 15:59:13 -0800 | [diff] [blame] | 1469 | int xhci_queue_reset_device(struct xhci_hcd *xhci, u32 slot_id); |
Sarah Sharp | c92bcfa | 2009-07-27 12:05:21 -0700 | [diff] [blame] | 1470 | void xhci_find_new_dequeue_state(struct xhci_hcd *xhci, |
| 1471 | unsigned int slot_id, unsigned int ep_index, |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 1472 | unsigned int stream_id, struct xhci_td *cur_td, |
| 1473 | struct xhci_dequeue_state *state); |
Sarah Sharp | c92bcfa | 2009-07-27 12:05:21 -0700 | [diff] [blame] | 1474 | void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci, |
Sarah Sharp | 63a0d9a | 2009-09-04 10:53:09 -0700 | [diff] [blame] | 1475 | unsigned int slot_id, unsigned int ep_index, |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 1476 | unsigned int stream_id, |
Sarah Sharp | 63a0d9a | 2009-09-04 10:53:09 -0700 | [diff] [blame] | 1477 | struct xhci_dequeue_state *deq_state); |
Sarah Sharp | 82d1009 | 2009-08-07 14:04:52 -0700 | [diff] [blame] | 1478 | void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci, |
Sarah Sharp | 63a0d9a | 2009-09-04 10:53:09 -0700 | [diff] [blame] | 1479 | struct usb_device *udev, unsigned int ep_index); |
Sarah Sharp | ac9d8fe | 2009-08-07 14:04:55 -0700 | [diff] [blame] | 1480 | void xhci_queue_config_ep_quirk(struct xhci_hcd *xhci, |
| 1481 | unsigned int slot_id, unsigned int ep_index, |
| 1482 | struct xhci_dequeue_state *deq_state); |
Sarah Sharp | 6f5165c | 2009-10-27 10:57:01 -0700 | [diff] [blame] | 1483 | void xhci_stop_endpoint_command_watchdog(unsigned long arg); |
Andiry Xu | be88fe4 | 2010-10-14 07:22:57 -0700 | [diff] [blame] | 1484 | void xhci_ring_ep_doorbell(struct xhci_hcd *xhci, unsigned int slot_id, |
| 1485 | unsigned int ep_index, unsigned int stream_id); |
Sarah Sharp | 66d4ead | 2009-04-27 19:52:28 -0700 | [diff] [blame] | 1486 | |
Sarah Sharp | 0f2a793 | 2009-04-27 19:57:12 -0700 | [diff] [blame] | 1487 | /* xHCI roothub code */ |
| 1488 | int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, u16 wIndex, |
| 1489 | char *buf, u16 wLength); |
| 1490 | int xhci_hub_status_data(struct usb_hcd *hcd, char *buf); |
Sarah Sharp | 436a389 | 2010-10-15 14:59:15 -0700 | [diff] [blame] | 1491 | |
| 1492 | #ifdef CONFIG_PM |
Andiry Xu | 9777e3c | 2010-10-14 07:23:03 -0700 | [diff] [blame] | 1493 | int xhci_bus_suspend(struct usb_hcd *hcd); |
| 1494 | int xhci_bus_resume(struct usb_hcd *hcd); |
Sarah Sharp | 436a389 | 2010-10-15 14:59:15 -0700 | [diff] [blame] | 1495 | #else |
| 1496 | #define xhci_bus_suspend NULL |
| 1497 | #define xhci_bus_resume NULL |
| 1498 | #endif /* CONFIG_PM */ |
| 1499 | |
Andiry Xu | 5619253 | 2010-10-14 07:23:00 -0700 | [diff] [blame] | 1500 | u32 xhci_port_state_to_neutral(u32 state); |
| 1501 | int xhci_find_slot_id_by_port(struct xhci_hcd *xhci, u16 port); |
| 1502 | void xhci_ring_device(struct xhci_hcd *xhci, int slot_id); |
Sarah Sharp | 0f2a793 | 2009-04-27 19:57:12 -0700 | [diff] [blame] | 1503 | |
John Youn | d115b04 | 2009-07-27 12:05:15 -0700 | [diff] [blame] | 1504 | /* xHCI contexts */ |
| 1505 | struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx); |
| 1506 | struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx); |
| 1507 | struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int ep_index); |
| 1508 | |
Sarah Sharp | 74c6874 | 2009-04-27 19:52:22 -0700 | [diff] [blame] | 1509 | #endif /* __LINUX_XHCI_HCD_H */ |