blob: bde8f78551f9dbf5a9b5bce736385f863c60ae70 [file] [log] [blame]
Doug Thompsoncfe40fd2009-05-04 19:25:34 +02001/*
2 * AMD64 class Memory Controller kernel module
3 *
4 * Copyright (c) 2009 SoftwareBitMaker.
5 * Copyright (c) 2009 Advanced Micro Devices, Inc.
6 *
7 * This file may be distributed under the terms of the
8 * GNU General Public License.
9 *
10 * Originally Written by Thayne Harbaugh
11 *
12 * Changes by Douglas "norsk" Thompson <dougthompson@xmission.com>:
13 * - K8 CPU Revision D and greater support
14 *
15 * Changes by Dave Peterson <dsp@llnl.gov> <dave_peterson@pobox.com>:
16 * - Module largely rewritten, with new (and hopefully correct)
17 * code for dealing with node and chip select interleaving,
18 * various code cleanup, and bug fixes
19 * - Added support for memory hoisting using DRAM hole address
20 * register
21 *
22 * Changes by Douglas "norsk" Thompson <dougthompson@xmission.com>:
23 * -K8 Rev (1207) revision support added, required Revision
24 * specific mini-driver code to support Rev F as well as
25 * prior revisions
26 *
27 * Changes by Douglas "norsk" Thompson <dougthompson@xmission.com>:
28 * -Family 10h revision support added. New PCI Device IDs,
29 * indicating new changes. Actual registers modified
30 * were slight, less than the Rev E to Rev F transition
31 * but changing the PCI Device ID was the proper thing to
32 * do, as it provides for almost automactic family
33 * detection. The mods to Rev F required more family
34 * information detection.
35 *
36 * Changes/Fixes by Borislav Petkov <borislav.petkov@amd.com>:
37 * - misc fixes and code cleanups
38 *
39 * This module is based on the following documents
40 * (available from http://www.amd.com/):
41 *
42 * Title: BIOS and Kernel Developer's Guide for AMD Athlon 64 and AMD
43 * Opteron Processors
44 * AMD publication #: 26094
45 *` Revision: 3.26
46 *
47 * Title: BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh
48 * Processors
49 * AMD publication #: 32559
50 * Revision: 3.00
51 * Issue Date: May 2006
52 *
53 * Title: BIOS and Kernel Developer's Guide (BKDG) For AMD Family 10h
54 * Processors
55 * AMD publication #: 31116
56 * Revision: 3.00
57 * Issue Date: September 07, 2007
58 *
59 * Sections in the first 2 documents are no longer in sync with each other.
60 * The Family 10h BKDG was totally re-written from scratch with a new
61 * presentation model.
62 * Therefore, comments that refer to a Document section might be off.
63 */
64
65#include <linux/module.h>
66#include <linux/ctype.h>
67#include <linux/init.h>
68#include <linux/pci.h>
69#include <linux/pci_ids.h>
70#include <linux/slab.h>
71#include <linux/mmzone.h>
72#include <linux/edac.h>
Doug Thompsonf9431992009-04-27 19:46:08 +020073#include <asm/msr.h>
Doug Thompsoncfe40fd2009-05-04 19:25:34 +020074#include "edac_core.h"
Borislav Petkovb70ef012009-06-25 19:32:38 +020075#include "edac_mce_amd.h"
Doug Thompsoncfe40fd2009-05-04 19:25:34 +020076
77#define amd64_printk(level, fmt, arg...) \
78 edac_printk(level, "amd64", fmt, ##arg)
79
80#define amd64_mc_printk(mci, level, fmt, arg...) \
81 edac_mc_chipset_printk(mci, level, "amd64", fmt, ##arg)
82
83/*
84 * Throughout the comments in this code, the following terms are used:
85 *
86 * SysAddr, DramAddr, and InputAddr
87 *
88 * These terms come directly from the amd64 documentation
89 * (AMD publication #26094). They are defined as follows:
90 *
91 * SysAddr:
92 * This is a physical address generated by a CPU core or a device
93 * doing DMA. If generated by a CPU core, a SysAddr is the result of
94 * a virtual to physical address translation by the CPU core's address
95 * translation mechanism (MMU).
96 *
97 * DramAddr:
98 * A DramAddr is derived from a SysAddr by subtracting an offset that
99 * depends on which node the SysAddr maps to and whether the SysAddr
100 * is within a range affected by memory hoisting. The DRAM Base
101 * (section 3.4.4.1) and DRAM Limit (section 3.4.4.2) registers
102 * determine which node a SysAddr maps to.
103 *
104 * If the DRAM Hole Address Register (DHAR) is enabled and the SysAddr
105 * is within the range of addresses specified by this register, then
106 * a value x from the DHAR is subtracted from the SysAddr to produce a
107 * DramAddr. Here, x represents the base address for the node that
108 * the SysAddr maps to plus an offset due to memory hoisting. See
109 * section 3.4.8 and the comments in amd64_get_dram_hole_info() and
110 * sys_addr_to_dram_addr() below for more information.
111 *
112 * If the SysAddr is not affected by the DHAR then a value y is
113 * subtracted from the SysAddr to produce a DramAddr. Here, y is the
114 * base address for the node that the SysAddr maps to. See section
115 * 3.4.4 and the comments in sys_addr_to_dram_addr() below for more
116 * information.
117 *
118 * InputAddr:
119 * A DramAddr is translated to an InputAddr before being passed to the
120 * memory controller for the node that the DramAddr is associated
121 * with. The memory controller then maps the InputAddr to a csrow.
122 * If node interleaving is not in use, then the InputAddr has the same
123 * value as the DramAddr. Otherwise, the InputAddr is produced by
124 * discarding the bits used for node interleaving from the DramAddr.
125 * See section 3.4.4 for more information.
126 *
127 * The memory controller for a given node uses its DRAM CS Base and
128 * DRAM CS Mask registers to map an InputAddr to a csrow. See
129 * sections 3.5.4 and 3.5.5 for more information.
130 */
131
132#define EDAC_AMD64_VERSION " Ver: 3.2.0 " __DATE__
133#define EDAC_MOD_STR "amd64_edac"
134
135/* Extended Model from CPUID, for CPU Revision numbers */
136#define OPTERON_CPU_LE_REV_C 0
137#define OPTERON_CPU_REV_D 1
138#define OPTERON_CPU_REV_E 2
139
140/* NPT processors have the following Extended Models */
141#define OPTERON_CPU_REV_F 4
142#define OPTERON_CPU_REV_FA 5
143
144/* Hardware limit on ChipSelect rows per MC and processors per system */
145#define CHIPSELECT_COUNT 8
146#define DRAM_REG_COUNT 8
147
148
149/*
150 * PCI-defined configuration space registers
151 */
152
153
154/*
155 * Function 1 - Address Map
156 */
157#define K8_DRAM_BASE_LOW 0x40
158#define K8_DRAM_LIMIT_LOW 0x44
159#define K8_DHAR 0xf0
160
161#define DHAR_VALID BIT(0)
162#define F10_DRAM_MEM_HOIST_VALID BIT(1)
163
164#define DHAR_BASE_MASK 0xff000000
165#define dhar_base(dhar) (dhar & DHAR_BASE_MASK)
166
167#define K8_DHAR_OFFSET_MASK 0x0000ff00
168#define k8_dhar_offset(dhar) ((dhar & K8_DHAR_OFFSET_MASK) << 16)
169
170#define F10_DHAR_OFFSET_MASK 0x0000ff80
171 /* NOTE: Extra mask bit vs K8 */
172#define f10_dhar_offset(dhar) ((dhar & F10_DHAR_OFFSET_MASK) << 16)
173
174
175/* F10 High BASE/LIMIT registers */
176#define F10_DRAM_BASE_HIGH 0x140
177#define F10_DRAM_LIMIT_HIGH 0x144
178
179
180/*
181 * Function 2 - DRAM controller
182 */
183#define K8_DCSB0 0x40
184#define F10_DCSB1 0x140
185
186#define K8_DCSB_CS_ENABLE BIT(0)
187#define K8_DCSB_NPT_SPARE BIT(1)
188#define K8_DCSB_NPT_TESTFAIL BIT(2)
189
190/*
191 * REV E: select [31:21] and [15:9] from DCSB and the shift amount to form
192 * the address
193 */
194#define REV_E_DCSB_BASE_BITS (0xFFE0FE00ULL)
195#define REV_E_DCS_SHIFT 4
196#define REV_E_DCSM_COUNT 8
197
198#define REV_F_F1Xh_DCSB_BASE_BITS (0x1FF83FE0ULL)
199#define REV_F_F1Xh_DCS_SHIFT 8
200
201/*
202 * REV F and later: selects [28:19] and [13:5] from DCSB and the shift amount
203 * to form the address
204 */
205#define REV_F_DCSB_BASE_BITS (0x1FF83FE0ULL)
206#define REV_F_DCS_SHIFT 8
207#define REV_F_DCSM_COUNT 4
208#define F10_DCSM_COUNT 4
209#define F11_DCSM_COUNT 2
210
211/* DRAM CS Mask Registers */
212#define K8_DCSM0 0x60
213#define F10_DCSM1 0x160
214
215/* REV E: select [29:21] and [15:9] from DCSM */
216#define REV_E_DCSM_MASK_BITS 0x3FE0FE00
217
218/* unused bits [24:20] and [12:0] */
219#define REV_E_DCS_NOTUSED_BITS 0x01F01FFF
220
221/* REV F and later: select [28:19] and [13:5] from DCSM */
222#define REV_F_F1Xh_DCSM_MASK_BITS 0x1FF83FE0
223
224/* unused bits [26:22] and [12:0] */
225#define REV_F_F1Xh_DCS_NOTUSED_BITS 0x07C01FFF
226
227#define DBAM0 0x80
228#define DBAM1 0x180
229
230/* Extract the DIMM 'type' on the i'th DIMM from the DBAM reg value passed */
231#define DBAM_DIMM(i, reg) ((((reg) >> (4*i))) & 0xF)
232
233#define DBAM_MAX_VALUE 11
234
235
236#define F10_DCLR_0 0x90
237#define F10_DCLR_1 0x190
238#define REVE_WIDTH_128 BIT(16)
239#define F10_WIDTH_128 BIT(11)
240
241
242#define F10_DCHR_0 0x94
243#define F10_DCHR_1 0x194
244
245#define F10_DCHR_FOUR_RANK_DIMM BIT(18)
246#define F10_DCHR_Ddr3Mode BIT(8)
247#define F10_DCHR_MblMode BIT(6)
248
249
250#define F10_DCTL_SEL_LOW 0x110
251
252#define dct_sel_baseaddr(pvt) \
253 ((pvt->dram_ctl_select_low) & 0xFFFFF800)
254
255#define dct_sel_interleave_addr(pvt) \
256 (((pvt->dram_ctl_select_low) >> 6) & 0x3)
257
258enum {
259 F10_DCTL_SEL_LOW_DctSelHiRngEn = BIT(0),
260 F10_DCTL_SEL_LOW_DctSelIntLvEn = BIT(2),
261 F10_DCTL_SEL_LOW_DctGangEn = BIT(4),
262 F10_DCTL_SEL_LOW_DctDatIntLv = BIT(5),
263 F10_DCTL_SEL_LOW_DramEnable = BIT(8),
264 F10_DCTL_SEL_LOW_MemCleared = BIT(10),
265};
266
267#define dct_high_range_enabled(pvt) \
268 (pvt->dram_ctl_select_low & F10_DCTL_SEL_LOW_DctSelHiRngEn)
269
270#define dct_interleave_enabled(pvt) \
271 (pvt->dram_ctl_select_low & F10_DCTL_SEL_LOW_DctSelIntLvEn)
272
273#define dct_ganging_enabled(pvt) \
274 (pvt->dram_ctl_select_low & F10_DCTL_SEL_LOW_DctGangEn)
275
276#define dct_data_intlv_enabled(pvt) \
277 (pvt->dram_ctl_select_low & F10_DCTL_SEL_LOW_DctDatIntLv)
278
279#define dct_dram_enabled(pvt) \
280 (pvt->dram_ctl_select_low & F10_DCTL_SEL_LOW_DramEnable)
281
282#define dct_memory_cleared(pvt) \
283 (pvt->dram_ctl_select_low & F10_DCTL_SEL_LOW_MemCleared)
284
285
286#define F10_DCTL_SEL_HIGH 0x114
287
288
289/*
290 * Function 3 - Misc Control
291 */
292#define K8_NBCTL 0x40
293
294/* Correctable ECC error reporting enable */
295#define K8_NBCTL_CECCEn BIT(0)
296
297/* UnCorrectable ECC error reporting enable */
298#define K8_NBCTL_UECCEn BIT(1)
299
300#define K8_NBCFG 0x44
301#define K8_NBCFG_CHIPKILL BIT(23)
302#define K8_NBCFG_ECC_ENABLE BIT(22)
303
304#define K8_NBSL 0x48
305
306
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200307/* Family F10h: Normalized Extended Error Codes */
308#define F10_NBSL_EXT_ERR_RES 0x0
309#define F10_NBSL_EXT_ERR_CRC 0x1
310#define F10_NBSL_EXT_ERR_SYNC 0x2
311#define F10_NBSL_EXT_ERR_MST 0x3
312#define F10_NBSL_EXT_ERR_TGT 0x4
313#define F10_NBSL_EXT_ERR_GART 0x5
314#define F10_NBSL_EXT_ERR_RMW 0x6
315#define F10_NBSL_EXT_ERR_WDT 0x7
316#define F10_NBSL_EXT_ERR_ECC 0x8
317#define F10_NBSL_EXT_ERR_DEV 0x9
318#define F10_NBSL_EXT_ERR_LINK_DATA 0xA
319
320/* Next two are overloaded values */
321#define F10_NBSL_EXT_ERR_LINK_PROTO 0xB
322#define F10_NBSL_EXT_ERR_L3_PROTO 0xB
323
324#define F10_NBSL_EXT_ERR_NB_ARRAY 0xC
325#define F10_NBSL_EXT_ERR_DRAM_PARITY 0xD
326#define F10_NBSL_EXT_ERR_LINK_RETRY 0xE
327
328/* Next two are overloaded values */
329#define F10_NBSL_EXT_ERR_GART_WALK 0xF
330#define F10_NBSL_EXT_ERR_DEV_WALK 0xF
331
332/* 0x10 to 0x1B: Reserved */
333#define F10_NBSL_EXT_ERR_L3_DATA 0x1C
334#define F10_NBSL_EXT_ERR_L3_TAG 0x1D
335#define F10_NBSL_EXT_ERR_L3_LRU 0x1E
336
337/* K8: Normalized Extended Error Codes */
338#define K8_NBSL_EXT_ERR_ECC 0x0
339#define K8_NBSL_EXT_ERR_CRC 0x1
340#define K8_NBSL_EXT_ERR_SYNC 0x2
341#define K8_NBSL_EXT_ERR_MST 0x3
342#define K8_NBSL_EXT_ERR_TGT 0x4
343#define K8_NBSL_EXT_ERR_GART 0x5
344#define K8_NBSL_EXT_ERR_RMW 0x6
345#define K8_NBSL_EXT_ERR_WDT 0x7
346#define K8_NBSL_EXT_ERR_CHIPKILL_ECC 0x8
347#define K8_NBSL_EXT_ERR_DRAM_PARITY 0xD
348
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200349/*
350 * The following are for BUS type errors AFTER values have been normalized by
351 * shifting right
352 */
353#define K8_NBSL_PP_SRC 0x0
354#define K8_NBSL_PP_RES 0x1
355#define K8_NBSL_PP_OBS 0x2
356#define K8_NBSL_PP_GENERIC 0x3
357
358
359#define K8_NBSH 0x4C
360
361#define K8_NBSH_VALID_BIT BIT(31)
362#define K8_NBSH_OVERFLOW BIT(30)
363#define K8_NBSH_UNCORRECTED_ERR BIT(29)
364#define K8_NBSH_ERR_ENABLE BIT(28)
365#define K8_NBSH_MISC_ERR_VALID BIT(27)
366#define K8_NBSH_VALID_ERROR_ADDR BIT(26)
367#define K8_NBSH_PCC BIT(25)
368#define K8_NBSH_CECC BIT(14)
369#define K8_NBSH_UECC BIT(13)
370#define K8_NBSH_ERR_SCRUBER BIT(8)
371#define K8_NBSH_CORE3 BIT(3)
372#define K8_NBSH_CORE2 BIT(2)
373#define K8_NBSH_CORE1 BIT(1)
374#define K8_NBSH_CORE0 BIT(0)
375
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200376#define EXTRACT_ERR_CPU_MAP(x) ((x) & 0xF)
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200377
378
379#define K8_NBEAL 0x50
380#define K8_NBEAH 0x54
381#define K8_SCRCTRL 0x58
382
383#define F10_NB_CFG_LOW 0x88
384#define F10_NB_CFG_LOW_ENABLE_EXT_CFG BIT(14)
385
386#define F10_NB_CFG_HIGH 0x8C
387
388#define F10_ONLINE_SPARE 0xB0
389#define F10_ONLINE_SPARE_SWAPDONE0(x) ((x) & BIT(1))
390#define F10_ONLINE_SPARE_SWAPDONE1(x) ((x) & BIT(3))
391#define F10_ONLINE_SPARE_BADDRAM_CS0(x) (((x) >> 4) & 0x00000007)
392#define F10_ONLINE_SPARE_BADDRAM_CS1(x) (((x) >> 8) & 0x00000007)
393
394#define F10_NB_ARRAY_ADDR 0xB8
395
396#define F10_NB_ARRAY_DRAM_ECC 0x80000000
397
398/* Bits [2:1] are used to select 16-byte section within a 64-byte cacheline */
399#define SET_NB_ARRAY_ADDRESS(section) (((section) & 0x3) << 1)
400
401#define F10_NB_ARRAY_DATA 0xBC
402
403#define SET_NB_DRAM_INJECTION_WRITE(word, bits) \
404 (BIT(((word) & 0xF) + 20) | \
405 BIT(17) | \
406 ((bits) & 0xF))
407
408#define SET_NB_DRAM_INJECTION_READ(word, bits) \
409 (BIT(((word) & 0xF) + 20) | \
410 BIT(16) | \
411 ((bits) & 0xF))
412
413#define K8_NBCAP 0xE8
414#define K8_NBCAP_CORES (BIT(12)|BIT(13))
415#define K8_NBCAP_CHIPKILL BIT(4)
416#define K8_NBCAP_SECDED BIT(3)
417#define K8_NBCAP_8_NODE BIT(2)
418#define K8_NBCAP_DUAL_NODE BIT(1)
419#define K8_NBCAP_DCT_DUAL BIT(0)
420
421/*
422 * MSR Regs
423 */
424#define K8_MSR_MCGCTL 0x017b
425#define K8_MSR_MCGCTL_NBE BIT(4)
426
427#define K8_MSR_MC4CTL 0x0410
428#define K8_MSR_MC4STAT 0x0411
429#define K8_MSR_MC4ADDR 0x0412
430
431/* AMD sets the first MC device at device ID 0x18. */
Borislav Petkov37da0452009-06-10 17:36:57 +0200432static inline int get_node_id(struct pci_dev *pdev)
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200433{
434 return PCI_SLOT(pdev->devfn) - 0x18;
435}
436
437enum amd64_chipset_families {
438 K8_CPUS = 0,
439 F10_CPUS,
440 F11_CPUS,
441};
442
443/*
444 * Structure to hold:
445 *
446 * 1) dynamically read status and error address HW registers
447 * 2) sysfs entered values
448 * 3) MCE values
449 *
450 * Depends on entry into the modules
451 */
Borislav Petkovef44cc42009-07-23 14:45:48 +0200452struct err_regs {
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200453 u32 nbcfg;
454 u32 nbsh;
455 u32 nbsl;
456 u32 nbeah;
457 u32 nbeal;
458};
459
460/* Error injection control structure */
461struct error_injection {
462 u32 section;
463 u32 word;
464 u32 bit_map;
465};
466
467struct amd64_pvt {
468 /* pci_device handles which we utilize */
469 struct pci_dev *addr_f1_ctl;
470 struct pci_dev *dram_f2_ctl;
471 struct pci_dev *misc_f3_ctl;
472
473 int mc_node_id; /* MC index of this MC node */
474 int ext_model; /* extended model value of this node */
475
476 struct low_ops *ops; /* pointer to per PCI Device ID func table */
477
478 int channel_count;
479
480 /* Raw registers */
481 u32 dclr0; /* DRAM Configuration Low DCT0 reg */
482 u32 dclr1; /* DRAM Configuration Low DCT1 reg */
483 u32 dchr0; /* DRAM Configuration High DCT0 reg */
484 u32 dchr1; /* DRAM Configuration High DCT1 reg */
485 u32 nbcap; /* North Bridge Capabilities */
486 u32 nbcfg; /* F10 North Bridge Configuration */
487 u32 ext_nbcfg; /* Extended F10 North Bridge Configuration */
488 u32 dhar; /* DRAM Hoist reg */
489 u32 dbam0; /* DRAM Base Address Mapping reg for DCT0 */
490 u32 dbam1; /* DRAM Base Address Mapping reg for DCT1 */
491
492 /* DRAM CS Base Address Registers F2x[1,0][5C:40] */
493 u32 dcsb0[CHIPSELECT_COUNT];
494 u32 dcsb1[CHIPSELECT_COUNT];
495
496 /* DRAM CS Mask Registers F2x[1,0][6C:60] */
497 u32 dcsm0[CHIPSELECT_COUNT];
498 u32 dcsm1[CHIPSELECT_COUNT];
499
500 /*
501 * Decoded parts of DRAM BASE and LIMIT Registers
502 * F1x[78,70,68,60,58,50,48,40]
503 */
504 u64 dram_base[DRAM_REG_COUNT];
505 u64 dram_limit[DRAM_REG_COUNT];
506 u8 dram_IntlvSel[DRAM_REG_COUNT];
507 u8 dram_IntlvEn[DRAM_REG_COUNT];
508 u8 dram_DstNode[DRAM_REG_COUNT];
509 u8 dram_rw_en[DRAM_REG_COUNT];
510
511 /*
512 * The following fields are set at (load) run time, after CPU revision
513 * has been determined, since the dct_base and dct_mask registers vary
514 * based on revision
515 */
516 u32 dcsb_base; /* DCSB base bits */
517 u32 dcsm_mask; /* DCSM mask bits */
518 u32 num_dcsm; /* Number of DCSM registers */
519 u32 dcs_mask_notused; /* DCSM notused mask bits */
520 u32 dcs_shift; /* DCSB and DCSM shift value */
521
522 u64 top_mem; /* top of memory below 4GB */
523 u64 top_mem2; /* top of memory above 4GB */
524
525 u32 dram_ctl_select_low; /* DRAM Controller Select Low Reg */
526 u32 dram_ctl_select_high; /* DRAM Controller Select High Reg */
527 u32 online_spare; /* On-Line spare Reg */
528
529 /* temp storage for when input is received from sysfs */
Borislav Petkovef44cc42009-07-23 14:45:48 +0200530 struct err_regs ctl_error_info;
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200531
532 /* place to store error injection parameters prior to issue */
533 struct error_injection injection;
534
535 /* Save old hw registers' values before we modified them */
536 u32 nbctl_mcgctl_saved; /* When true, following 2 are valid */
537 u32 old_nbctl;
Doug Thompsonf9431992009-04-27 19:46:08 +0200538 unsigned long old_mcgctl; /* per core on this node */
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200539
540 /* MC Type Index value: socket F vs Family 10h */
541 u32 mc_type_index;
542
543 /* misc settings */
544 struct flags {
545 unsigned long cf8_extcfg:1;
546 } flags;
547};
548
549struct scrubrate {
550 u32 scrubval; /* bit pattern for scrub rate */
551 u32 bandwidth; /* bandwidth consumed (bytes/sec) */
552};
553
554extern struct scrubrate scrubrates[23];
555extern u32 revf_quad_ddr2_shift[16];
556extern const char *tt_msgs[4];
557extern const char *ll_msgs[4];
558extern const char *rrrr_msgs[16];
559extern const char *to_msgs[2];
560extern const char *pp_msgs[4];
561extern const char *ii_msgs[4];
562extern const char *ext_msgs[32];
563extern const char *htlink_msgs[8];
564
Doug Thompson7d6034d2009-04-27 20:01:01 +0200565#ifdef CONFIG_EDAC_DEBUG
566#define NUM_DBG_ATTRS 9
567#else
568#define NUM_DBG_ATTRS 0
569#endif
570
571#ifdef CONFIG_EDAC_AMD64_ERROR_INJECTION
572#define NUM_INJ_ATTRS 5
573#else
574#define NUM_INJ_ATTRS 0
575#endif
576
577extern struct mcidev_sysfs_attribute amd64_dbg_attrs[NUM_DBG_ATTRS],
578 amd64_inj_attrs[NUM_INJ_ATTRS];
579
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200580/*
581 * Each of the PCI Device IDs types have their own set of hardware accessor
582 * functions and per device encoding/decoding logic.
583 */
584struct low_ops {
585 int (*probe_valid_hardware)(struct amd64_pvt *pvt);
586 int (*early_channel_count)(struct amd64_pvt *pvt);
587
588 u64 (*get_error_address)(struct mem_ctl_info *mci,
Borislav Petkovef44cc42009-07-23 14:45:48 +0200589 struct err_regs *info);
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200590 void (*read_dram_base_limit)(struct amd64_pvt *pvt, int dram);
591 void (*read_dram_ctl_register)(struct amd64_pvt *pvt);
592 void (*map_sysaddr_to_csrow)(struct mem_ctl_info *mci,
Borislav Petkovef44cc42009-07-23 14:45:48 +0200593 struct err_regs *info,
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200594 u64 SystemAddr);
595 int (*dbam_map_to_pages)(struct amd64_pvt *pvt, int dram_map);
596};
597
598struct amd64_family_type {
599 const char *ctl_name;
600 u16 addr_f1_ctl;
601 u16 misc_f3_ctl;
602 struct low_ops ops;
603};
604
605static struct amd64_family_type amd64_family_types[];
606
607static inline const char *get_amd_family_name(int index)
608{
609 return amd64_family_types[index].ctl_name;
610}
611
612static inline struct low_ops *family_ops(int index)
613{
614 return &amd64_family_types[index].ops;
615}
616
617/*
618 * For future CPU versions, verify the following as new 'slow' rates appear and
619 * modify the necessary skip values for the supported CPU.
620 */
621#define K8_MIN_SCRUB_RATE_BITS 0x0
622#define F10_MIN_SCRUB_RATE_BITS 0x5
623#define F11_MIN_SCRUB_RATE_BITS 0x6
624
625int amd64_process_error_info(struct mem_ctl_info *mci,
Borislav Petkovef44cc42009-07-23 14:45:48 +0200626 struct err_regs *info,
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200627 int handle_errors);
628int amd64_get_dram_hole_info(struct mem_ctl_info *mci, u64 *hole_base,
629 u64 *hole_offset, u64 *hole_size);