Syed Mohammed, Khasim | cc26b3b | 2008-10-09 17:51:41 +0300 | [diff] [blame] | 1 | /* |
| 2 | * linux/arch/arm/mach-omap3/sram.S |
| 3 | * |
| 4 | * Omap3 specific functions that need to be run in internal SRAM |
| 5 | * |
Paul Walmsley | 4267b5d | 2009-06-19 19:08:27 -0600 | [diff] [blame] | 6 | * Copyright (C) 2004, 2007, 2008 Texas Instruments, Inc. |
| 7 | * Copyright (C) 2008 Nokia Corporation |
Syed Mohammed, Khasim | cc26b3b | 2008-10-09 17:51:41 +0300 | [diff] [blame] | 8 | * |
Paul Walmsley | 4267b5d | 2009-06-19 19:08:27 -0600 | [diff] [blame] | 9 | * Rajendra Nayak <rnayak@ti.com> |
Syed Mohammed, Khasim | cc26b3b | 2008-10-09 17:51:41 +0300 | [diff] [blame] | 10 | * Richard Woodruff <r-woodruff2@ti.com> |
Paul Walmsley | 4267b5d | 2009-06-19 19:08:27 -0600 | [diff] [blame] | 11 | * Paul Walmsley |
Syed Mohammed, Khasim | cc26b3b | 2008-10-09 17:51:41 +0300 | [diff] [blame] | 12 | * |
| 13 | * This program is free software; you can redistribute it and/or |
| 14 | * modify it under the terms of the GNU General Public License as |
| 15 | * published by the Free Software Foundation; either version 2 of |
| 16 | * the License, or (at your option) any later version. |
| 17 | * |
| 18 | * This program is distributed in the hope that it will be useful, |
| 19 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 20 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the |
| 21 | * GNU General Public License for more details. |
| 22 | * |
| 23 | * You should have received a copy of the GNU General Public License |
| 24 | * along with this program; if not, write to the Free Software |
| 25 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 26 | * MA 02111-1307 USA |
| 27 | */ |
| 28 | #include <linux/linkage.h> |
| 29 | #include <asm/assembler.h> |
| 30 | #include <mach/hardware.h> |
| 31 | |
| 32 | #include <mach/io.h> |
| 33 | |
| 34 | #include "sdrc.h" |
Paul Walmsley | 59fb659 | 2010-12-21 15:30:55 -0700 | [diff] [blame] | 35 | #include "cm2xxx_3xxx.h" |
Syed Mohammed, Khasim | cc26b3b | 2008-10-09 17:51:41 +0300 | [diff] [blame] | 36 | |
Dave Martin | ef7a87d | 2011-03-04 15:33:56 +0000 | [diff] [blame^] | 37 | /* |
| 38 | * This file needs be built unconditionally as ARM to interoperate correctly |
| 39 | * with non-Thumb-2-capable firmware. |
| 40 | */ |
| 41 | .arm |
| 42 | |
Syed Mohammed, Khasim | cc26b3b | 2008-10-09 17:51:41 +0300 | [diff] [blame] | 43 | .text |
| 44 | |
Jean Pihet | 58cda88 | 2009-07-24 19:43:25 -0600 | [diff] [blame] | 45 | /* r1 parameters */ |
Paul Walmsley | df14e47 | 2009-06-19 19:08:28 -0600 | [diff] [blame] | 46 | #define SDRC_NO_UNLOCK_DLL 0x0 |
| 47 | #define SDRC_UNLOCK_DLL 0x1 |
| 48 | |
| 49 | /* SDRC_DLLA_CTRL bit settings */ |
Paul Walmsley | 7b7bcef | 2009-06-19 19:08:29 -0600 | [diff] [blame] | 50 | #define FIXEDDELAY_SHIFT 24 |
| 51 | #define FIXEDDELAY_MASK (0xff << FIXEDDELAY_SHIFT) |
Paul Walmsley | df14e47 | 2009-06-19 19:08:28 -0600 | [diff] [blame] | 52 | #define DLLIDLE_MASK 0x4 |
| 53 | |
Paul Walmsley | 7b7bcef | 2009-06-19 19:08:29 -0600 | [diff] [blame] | 54 | /* |
| 55 | * SDRC_DLLA_CTRL default values: TI hardware team indicates that |
| 56 | * FIXEDDELAY should be initialized to 0xf. This apparently was |
| 57 | * empirically determined during process testing, so no derivation |
| 58 | * was provided. |
| 59 | */ |
| 60 | #define FIXEDDELAY_DEFAULT (0x0f << FIXEDDELAY_SHIFT) |
| 61 | |
Paul Walmsley | df14e47 | 2009-06-19 19:08:28 -0600 | [diff] [blame] | 62 | /* SDRC_DLLA_STATUS bit settings */ |
| 63 | #define LOCKSTATUS_MASK 0x4 |
| 64 | |
| 65 | /* SDRC_POWER bit settings */ |
| 66 | #define SRFRONIDLEREQ_MASK 0x40 |
Paul Walmsley | df14e47 | 2009-06-19 19:08:28 -0600 | [diff] [blame] | 67 | |
| 68 | /* CM_IDLEST1_CORE bit settings */ |
| 69 | #define ST_SDRC_MASK 0x2 |
| 70 | |
| 71 | /* CM_ICLKEN1_CORE bit settings */ |
| 72 | #define EN_SDRC_MASK 0x2 |
| 73 | |
| 74 | /* CM_CLKSEL1_PLL bit settings */ |
| 75 | #define CORE_DPLL_CLKOUT_DIV_SHIFT 0x1b |
| 76 | |
Syed Mohammed, Khasim | cc26b3b | 2008-10-09 17:51:41 +0300 | [diff] [blame] | 77 | /* |
Paul Walmsley | 4267b5d | 2009-06-19 19:08:27 -0600 | [diff] [blame] | 78 | * omap3_sram_configure_core_dpll - change DPLL3 M2 divider |
Paul Walmsley | c9812d0 | 2009-06-19 19:08:26 -0600 | [diff] [blame] | 79 | * |
Jean Pihet | 58cda88 | 2009-07-24 19:43:25 -0600 | [diff] [blame] | 80 | * Params passed in registers: |
| 81 | * r0 = new M2 divider setting (only 1 and 2 supported right now) |
| 82 | * r1 = unlock SDRC DLL? (1 = yes, 0 = no). Only unlock DLL for |
| 83 | * SDRC rates < 83MHz |
| 84 | * r2 = number of MPU cycles to wait for SDRC to stabilize after |
| 85 | * reprogramming the SDRC when switching to a slower MPU speed |
| 86 | * r3 = increasing SDRC rate? (1 = yes, 0 = no) |
| 87 | * |
| 88 | * Params passed via the stack. The needed params will be copied in SRAM |
| 89 | * before use by the code in SRAM (SDRAM is not accessible during SDRC |
| 90 | * reconfiguration): |
| 91 | * new SDRC_RFR_CTRL_0 register contents |
| 92 | * new SDRC_ACTIM_CTRL_A_0 register contents |
| 93 | * new SDRC_ACTIM_CTRL_B_0 register contents |
| 94 | * new SDRC_MR_0 register value |
| 95 | * new SDRC_RFR_CTRL_1 register contents |
| 96 | * new SDRC_ACTIM_CTRL_A_1 register contents |
| 97 | * new SDRC_ACTIM_CTRL_B_1 register contents |
| 98 | * new SDRC_MR_1 register value |
| 99 | * |
Paul Walmsley | 18862cb | 2009-12-08 16:33:14 -0700 | [diff] [blame] | 100 | * If the param SDRC_RFR_CTRL_1 is 0, the parameters are not programmed into |
| 101 | * the SDRC CS1 registers |
| 102 | * |
| 103 | * NOTE: This code no longer attempts to program the SDRC AC timing and MR |
| 104 | * registers. This is because the code currently cannot ensure that all |
| 105 | * L3 initiators (e.g., sDMA, IVA, DSS DISPC, etc.) are not accessing the |
| 106 | * SDRAM when the registers are written. If the registers are changed while |
| 107 | * an initiator is accessing SDRAM, memory can be corrupted and/or the SDRC |
| 108 | * may enter an unpredictable state. In the future, the intent is to |
| 109 | * re-enable this code in cases where we can ensure that no initiators are |
| 110 | * touching the SDRAM. Until that time, users who know that their use case |
| 111 | * can satisfy the above requirement can enable the CONFIG_OMAP3_SDRC_AC_TIMING |
| 112 | * option. |
Paul Walmsley | 1124d2f | 2010-12-21 21:08:14 -0700 | [diff] [blame] | 113 | * |
| 114 | * Richard Woodruff notes that any changes to this code must be carefully |
| 115 | * audited and tested to ensure that they don't cause a TLB miss while |
| 116 | * the SDRAM is inaccessible. Such a situation will crash the system |
| 117 | * since it will cause the ARM MMU to attempt to walk the page tables. |
| 118 | * These crashes may be intermittent. |
Syed Mohammed, Khasim | cc26b3b | 2008-10-09 17:51:41 +0300 | [diff] [blame] | 119 | */ |
| 120 | ENTRY(omap3_sram_configure_core_dpll) |
| 121 | stmfd sp!, {r1-r12, lr} @ store regs to stack |
Jean Pihet | 58cda88 | 2009-07-24 19:43:25 -0600 | [diff] [blame] | 122 | |
| 123 | @ pull the extra args off the stack |
| 124 | @ and store them in SRAM |
Dave Martin | ef7a87d | 2011-03-04 15:33:56 +0000 | [diff] [blame^] | 125 | |
| 126 | /* |
| 127 | * PC-relative stores are deprecated in ARMv7 and lead to undefined behaviour |
| 128 | * in Thumb-2: use a r7 as a base instead. |
| 129 | * Be careful not to clobber r7 when maintaing this file. |
| 130 | */ |
| 131 | THUMB( adr r7, omap3_sram_configure_core_dpll ) |
| 132 | .macro strtext Rt:req, label:req |
| 133 | ARM( str \Rt, \label ) |
| 134 | THUMB( str \Rt, [r7, \label - omap3_sram_configure_core_dpll] ) |
| 135 | .endm |
| 136 | |
Jean Pihet | 58cda88 | 2009-07-24 19:43:25 -0600 | [diff] [blame] | 137 | ldr r4, [sp, #52] |
Dave Martin | ef7a87d | 2011-03-04 15:33:56 +0000 | [diff] [blame^] | 138 | strtext r4, omap_sdrc_rfr_ctrl_0_val |
Jean Pihet | 58cda88 | 2009-07-24 19:43:25 -0600 | [diff] [blame] | 139 | ldr r4, [sp, #56] |
Dave Martin | ef7a87d | 2011-03-04 15:33:56 +0000 | [diff] [blame^] | 140 | strtext r4, omap_sdrc_actim_ctrl_a_0_val |
Jean Pihet | 58cda88 | 2009-07-24 19:43:25 -0600 | [diff] [blame] | 141 | ldr r4, [sp, #60] |
Dave Martin | ef7a87d | 2011-03-04 15:33:56 +0000 | [diff] [blame^] | 142 | strtext r4, omap_sdrc_actim_ctrl_b_0_val |
Jean Pihet | 58cda88 | 2009-07-24 19:43:25 -0600 | [diff] [blame] | 143 | ldr r4, [sp, #64] |
Dave Martin | ef7a87d | 2011-03-04 15:33:56 +0000 | [diff] [blame^] | 144 | strtext r4, omap_sdrc_mr_0_val |
Jean Pihet | 58cda88 | 2009-07-24 19:43:25 -0600 | [diff] [blame] | 145 | ldr r4, [sp, #68] |
Dave Martin | ef7a87d | 2011-03-04 15:33:56 +0000 | [diff] [blame^] | 146 | strtext r4, omap_sdrc_rfr_ctrl_1_val |
Jean Pihet | 58cda88 | 2009-07-24 19:43:25 -0600 | [diff] [blame] | 147 | cmp r4, #0 @ if SDRC_RFR_CTRL_1 is 0, |
| 148 | beq skip_cs1_params @ do not use cs1 params |
| 149 | ldr r4, [sp, #72] |
Dave Martin | ef7a87d | 2011-03-04 15:33:56 +0000 | [diff] [blame^] | 150 | strtext r4, omap_sdrc_actim_ctrl_a_1_val |
Jean Pihet | 58cda88 | 2009-07-24 19:43:25 -0600 | [diff] [blame] | 151 | ldr r4, [sp, #76] |
Dave Martin | ef7a87d | 2011-03-04 15:33:56 +0000 | [diff] [blame^] | 152 | strtext r4, omap_sdrc_actim_ctrl_b_1_val |
Jean Pihet | 58cda88 | 2009-07-24 19:43:25 -0600 | [diff] [blame] | 153 | ldr r4, [sp, #80] |
Dave Martin | ef7a87d | 2011-03-04 15:33:56 +0000 | [diff] [blame^] | 154 | strtext r4, omap_sdrc_mr_1_val |
Jean Pihet | 58cda88 | 2009-07-24 19:43:25 -0600 | [diff] [blame] | 155 | skip_cs1_params: |
Jon Hunter | a3fed9b | 2010-09-27 14:02:59 -0600 | [diff] [blame] | 156 | mrc p15, 0, r8, c1, c0, 0 @ read ctrl register |
| 157 | bic r10, r8, #0x800 @ clear Z-bit, disable branch prediction |
| 158 | mcr p15, 0, r10, c1, c0, 0 @ write ctrl register |
Paul Walmsley | 69d4255 | 2009-05-12 17:27:09 -0600 | [diff] [blame] | 159 | dsb @ flush buffered writes to interconnect |
Jon Hunter | a3fed9b | 2010-09-27 14:02:59 -0600 | [diff] [blame] | 160 | isb @ prevent speculative exec past here |
Jean Pihet | 58cda88 | 2009-07-24 19:43:25 -0600 | [diff] [blame] | 161 | cmp r3, #1 @ if increasing SDRC clk rate, |
Tero Kristo | 3afec63 | 2009-06-19 19:08:29 -0600 | [diff] [blame] | 162 | bleq configure_sdrc @ program the SDRC regs early (for RFR) |
Jean Pihet | 58cda88 | 2009-07-24 19:43:25 -0600 | [diff] [blame] | 163 | cmp r1, #SDRC_UNLOCK_DLL @ set the intended DLL state |
Paul Walmsley | 4519c2b | 2009-05-12 17:26:32 -0600 | [diff] [blame] | 164 | bleq unlock_dll |
Syed Mohammed, Khasim | cc26b3b | 2008-10-09 17:51:41 +0300 | [diff] [blame] | 165 | blne lock_dll |
Paul Walmsley | 4267b5d | 2009-06-19 19:08:27 -0600 | [diff] [blame] | 166 | bl sdram_in_selfrefresh @ put SDRAM in self refresh, idle SDRC |
| 167 | bl configure_core_dpll @ change the DPLL3 M2 divider |
Rajendra Nayak | df56556 | 2009-07-24 19:44:02 -0600 | [diff] [blame] | 168 | mov r12, r2 |
| 169 | bl wait_clk_stable @ wait for SDRC to stabilize |
Paul Walmsley | 4267b5d | 2009-06-19 19:08:27 -0600 | [diff] [blame] | 170 | bl enable_sdrc @ take SDRC out of idle |
Jean Pihet | 58cda88 | 2009-07-24 19:43:25 -0600 | [diff] [blame] | 171 | cmp r1, #SDRC_UNLOCK_DLL @ wait for DLL status to change |
Paul Walmsley | 4519c2b | 2009-05-12 17:26:32 -0600 | [diff] [blame] | 172 | bleq wait_dll_unlock |
Syed Mohammed, Khasim | cc26b3b | 2008-10-09 17:51:41 +0300 | [diff] [blame] | 173 | blne wait_dll_lock |
Jean Pihet | 58cda88 | 2009-07-24 19:43:25 -0600 | [diff] [blame] | 174 | cmp r3, #1 @ if increasing SDRC clk rate, |
Paul Walmsley | 4267b5d | 2009-06-19 19:08:27 -0600 | [diff] [blame] | 175 | beq return_to_sdram @ return to SDRAM code, otherwise, |
| 176 | bl configure_sdrc @ reprogram SDRC regs now |
Paul Walmsley | c9812d0 | 2009-06-19 19:08:26 -0600 | [diff] [blame] | 177 | return_to_sdram: |
Jon Hunter | a3fed9b | 2010-09-27 14:02:59 -0600 | [diff] [blame] | 178 | mcr p15, 0, r8, c1, c0, 0 @ restore ctrl register |
Paul Walmsley | 69d4255 | 2009-05-12 17:27:09 -0600 | [diff] [blame] | 179 | isb @ prevent speculative exec past here |
Syed Mohammed, Khasim | cc26b3b | 2008-10-09 17:51:41 +0300 | [diff] [blame] | 180 | mov r0, #0 @ return value |
| 181 | ldmfd sp!, {r1-r12, pc} @ restore regs and return |
| 182 | unlock_dll: |
Paul Walmsley | b2abb27 | 2009-05-12 17:27:10 -0600 | [diff] [blame] | 183 | ldr r11, omap3_sdrc_dlla_ctrl |
| 184 | ldr r12, [r11] |
Rajendra Nayak | 8ff120e | 2009-07-24 19:44:01 -0600 | [diff] [blame] | 185 | bic r12, r12, #FIXEDDELAY_MASK |
Paul Walmsley | 7b7bcef | 2009-06-19 19:08:29 -0600 | [diff] [blame] | 186 | orr r12, r12, #FIXEDDELAY_DEFAULT |
Paul Walmsley | df14e47 | 2009-06-19 19:08:28 -0600 | [diff] [blame] | 187 | orr r12, r12, #DLLIDLE_MASK |
Paul Walmsley | b2abb27 | 2009-05-12 17:27:10 -0600 | [diff] [blame] | 188 | str r12, [r11] @ (no OCP barrier needed) |
Syed Mohammed, Khasim | cc26b3b | 2008-10-09 17:51:41 +0300 | [diff] [blame] | 189 | bx lr |
| 190 | lock_dll: |
Paul Walmsley | b2abb27 | 2009-05-12 17:27:10 -0600 | [diff] [blame] | 191 | ldr r11, omap3_sdrc_dlla_ctrl |
| 192 | ldr r12, [r11] |
Paul Walmsley | df14e47 | 2009-06-19 19:08:28 -0600 | [diff] [blame] | 193 | bic r12, r12, #DLLIDLE_MASK |
Paul Walmsley | b2abb27 | 2009-05-12 17:27:10 -0600 | [diff] [blame] | 194 | str r12, [r11] @ (no OCP barrier needed) |
Syed Mohammed, Khasim | cc26b3b | 2008-10-09 17:51:41 +0300 | [diff] [blame] | 195 | bx lr |
| 196 | sdram_in_selfrefresh: |
Paul Walmsley | b2abb27 | 2009-05-12 17:27:10 -0600 | [diff] [blame] | 197 | ldr r11, omap3_sdrc_power @ read the SDRC_POWER register |
| 198 | ldr r12, [r11] @ read the contents of SDRC_POWER |
| 199 | mov r9, r12 @ keep a copy of SDRC_POWER bits |
Paul Walmsley | df14e47 | 2009-06-19 19:08:28 -0600 | [diff] [blame] | 200 | orr r12, r12, #SRFRONIDLEREQ_MASK @ enable self refresh on idle |
Paul Walmsley | b2abb27 | 2009-05-12 17:27:10 -0600 | [diff] [blame] | 201 | str r12, [r11] @ write back to SDRC_POWER register |
| 202 | ldr r12, [r11] @ posted-write barrier for SDRC |
Paul Walmsley | 4267b5d | 2009-06-19 19:08:27 -0600 | [diff] [blame] | 203 | idle_sdrc: |
Paul Walmsley | b2abb27 | 2009-05-12 17:27:10 -0600 | [diff] [blame] | 204 | ldr r11, omap3_cm_iclken1_core @ read the CM_ICLKEN1_CORE reg |
| 205 | ldr r12, [r11] |
Paul Walmsley | df14e47 | 2009-06-19 19:08:28 -0600 | [diff] [blame] | 206 | bic r12, r12, #EN_SDRC_MASK @ disable iclk bit for SDRC |
Paul Walmsley | b2abb27 | 2009-05-12 17:27:10 -0600 | [diff] [blame] | 207 | str r12, [r11] |
Syed Mohammed, Khasim | cc26b3b | 2008-10-09 17:51:41 +0300 | [diff] [blame] | 208 | wait_sdrc_idle: |
Paul Walmsley | b2abb27 | 2009-05-12 17:27:10 -0600 | [diff] [blame] | 209 | ldr r11, omap3_cm_idlest1_core |
| 210 | ldr r12, [r11] |
Paul Walmsley | df14e47 | 2009-06-19 19:08:28 -0600 | [diff] [blame] | 211 | and r12, r12, #ST_SDRC_MASK @ check for SDRC idle |
| 212 | cmp r12, #ST_SDRC_MASK |
Syed Mohammed, Khasim | cc26b3b | 2008-10-09 17:51:41 +0300 | [diff] [blame] | 213 | bne wait_sdrc_idle |
| 214 | bx lr |
| 215 | configure_core_dpll: |
Paul Walmsley | b2abb27 | 2009-05-12 17:27:10 -0600 | [diff] [blame] | 216 | ldr r11, omap3_cm_clksel1_pll |
| 217 | ldr r12, [r11] |
| 218 | ldr r10, core_m2_mask_val @ modify m2 for core dpll |
| 219 | and r12, r12, r10 |
Jean Pihet | 58cda88 | 2009-07-24 19:43:25 -0600 | [diff] [blame] | 220 | orr r12, r12, r0, lsl #CORE_DPLL_CLKOUT_DIV_SHIFT |
Paul Walmsley | b2abb27 | 2009-05-12 17:27:10 -0600 | [diff] [blame] | 221 | str r12, [r11] |
| 222 | ldr r12, [r11] @ posted-write barrier for CM |
Syed Mohammed, Khasim | cc26b3b | 2008-10-09 17:51:41 +0300 | [diff] [blame] | 223 | bx lr |
| 224 | wait_clk_stable: |
Paul Walmsley | b2abb27 | 2009-05-12 17:27:10 -0600 | [diff] [blame] | 225 | subs r12, r12, #1 |
Syed Mohammed, Khasim | cc26b3b | 2008-10-09 17:51:41 +0300 | [diff] [blame] | 226 | bne wait_clk_stable |
Syed Mohammed, Khasim | cc26b3b | 2008-10-09 17:51:41 +0300 | [diff] [blame] | 227 | bx lr |
| 228 | enable_sdrc: |
Paul Walmsley | b2abb27 | 2009-05-12 17:27:10 -0600 | [diff] [blame] | 229 | ldr r11, omap3_cm_iclken1_core |
| 230 | ldr r12, [r11] |
Paul Walmsley | df14e47 | 2009-06-19 19:08:28 -0600 | [diff] [blame] | 231 | orr r12, r12, #EN_SDRC_MASK @ enable iclk bit for SDRC |
Paul Walmsley | b2abb27 | 2009-05-12 17:27:10 -0600 | [diff] [blame] | 232 | str r12, [r11] |
Syed Mohammed, Khasim | cc26b3b | 2008-10-09 17:51:41 +0300 | [diff] [blame] | 233 | wait_sdrc_idle1: |
Paul Walmsley | b2abb27 | 2009-05-12 17:27:10 -0600 | [diff] [blame] | 234 | ldr r11, omap3_cm_idlest1_core |
| 235 | ldr r12, [r11] |
Paul Walmsley | df14e47 | 2009-06-19 19:08:28 -0600 | [diff] [blame] | 236 | and r12, r12, #ST_SDRC_MASK |
Paul Walmsley | b2abb27 | 2009-05-12 17:27:10 -0600 | [diff] [blame] | 237 | cmp r12, #0 |
Syed Mohammed, Khasim | cc26b3b | 2008-10-09 17:51:41 +0300 | [diff] [blame] | 238 | bne wait_sdrc_idle1 |
Paul Walmsley | fa0406a | 2009-05-12 17:27:09 -0600 | [diff] [blame] | 239 | restore_sdrc_power_val: |
Paul Walmsley | b2abb27 | 2009-05-12 17:27:10 -0600 | [diff] [blame] | 240 | ldr r11, omap3_sdrc_power |
| 241 | str r9, [r11] @ restore SDRC_POWER, no barrier needed |
Syed Mohammed, Khasim | cc26b3b | 2008-10-09 17:51:41 +0300 | [diff] [blame] | 242 | bx lr |
| 243 | wait_dll_lock: |
Paul Walmsley | b2abb27 | 2009-05-12 17:27:10 -0600 | [diff] [blame] | 244 | ldr r11, omap3_sdrc_dlla_status |
| 245 | ldr r12, [r11] |
Paul Walmsley | df14e47 | 2009-06-19 19:08:28 -0600 | [diff] [blame] | 246 | and r12, r12, #LOCKSTATUS_MASK |
| 247 | cmp r12, #LOCKSTATUS_MASK |
Syed Mohammed, Khasim | cc26b3b | 2008-10-09 17:51:41 +0300 | [diff] [blame] | 248 | bne wait_dll_lock |
| 249 | bx lr |
| 250 | wait_dll_unlock: |
Paul Walmsley | b2abb27 | 2009-05-12 17:27:10 -0600 | [diff] [blame] | 251 | ldr r11, omap3_sdrc_dlla_status |
| 252 | ldr r12, [r11] |
Paul Walmsley | df14e47 | 2009-06-19 19:08:28 -0600 | [diff] [blame] | 253 | and r12, r12, #LOCKSTATUS_MASK |
Paul Walmsley | b2abb27 | 2009-05-12 17:27:10 -0600 | [diff] [blame] | 254 | cmp r12, #0x0 |
Syed Mohammed, Khasim | cc26b3b | 2008-10-09 17:51:41 +0300 | [diff] [blame] | 255 | bne wait_dll_unlock |
| 256 | bx lr |
| 257 | configure_sdrc: |
Jean Pihet | 58cda88 | 2009-07-24 19:43:25 -0600 | [diff] [blame] | 258 | ldr r12, omap_sdrc_rfr_ctrl_0_val @ fetch value from SRAM |
| 259 | ldr r11, omap3_sdrc_rfr_ctrl_0 @ fetch addr from SRAM |
| 260 | str r12, [r11] @ store |
Paul Walmsley | 18862cb | 2009-12-08 16:33:14 -0700 | [diff] [blame] | 261 | #ifdef CONFIG_OMAP3_SDRC_AC_TIMING |
Jean Pihet | 58cda88 | 2009-07-24 19:43:25 -0600 | [diff] [blame] | 262 | ldr r12, omap_sdrc_actim_ctrl_a_0_val |
| 263 | ldr r11, omap3_sdrc_actim_ctrl_a_0 |
| 264 | str r12, [r11] |
| 265 | ldr r12, omap_sdrc_actim_ctrl_b_0_val |
| 266 | ldr r11, omap3_sdrc_actim_ctrl_b_0 |
| 267 | str r12, [r11] |
| 268 | ldr r12, omap_sdrc_mr_0_val |
Paul Walmsley | d0ba392 | 2009-06-19 19:08:27 -0600 | [diff] [blame] | 269 | ldr r11, omap3_sdrc_mr_0 |
Jean Pihet | 58cda88 | 2009-07-24 19:43:25 -0600 | [diff] [blame] | 270 | str r12, [r11] |
Paul Walmsley | 18862cb | 2009-12-08 16:33:14 -0700 | [diff] [blame] | 271 | #endif |
Jean Pihet | 58cda88 | 2009-07-24 19:43:25 -0600 | [diff] [blame] | 272 | ldr r12, omap_sdrc_rfr_ctrl_1_val |
| 273 | cmp r12, #0 @ if SDRC_RFR_CTRL_1 is 0, |
| 274 | beq skip_cs1_prog @ do not program cs1 params |
| 275 | ldr r11, omap3_sdrc_rfr_ctrl_1 |
| 276 | str r12, [r11] |
Paul Walmsley | 18862cb | 2009-12-08 16:33:14 -0700 | [diff] [blame] | 277 | #ifdef CONFIG_OMAP3_SDRC_AC_TIMING |
Jean Pihet | 58cda88 | 2009-07-24 19:43:25 -0600 | [diff] [blame] | 278 | ldr r12, omap_sdrc_actim_ctrl_a_1_val |
| 279 | ldr r11, omap3_sdrc_actim_ctrl_a_1 |
| 280 | str r12, [r11] |
| 281 | ldr r12, omap_sdrc_actim_ctrl_b_1_val |
| 282 | ldr r11, omap3_sdrc_actim_ctrl_b_1 |
| 283 | str r12, [r11] |
| 284 | ldr r12, omap_sdrc_mr_1_val |
| 285 | ldr r11, omap3_sdrc_mr_1 |
| 286 | str r12, [r11] |
Paul Walmsley | 18862cb | 2009-12-08 16:33:14 -0700 | [diff] [blame] | 287 | #endif |
Jean Pihet | 58cda88 | 2009-07-24 19:43:25 -0600 | [diff] [blame] | 288 | skip_cs1_prog: |
| 289 | ldr r12, [r11] @ posted-write barrier for SDRC |
Syed Mohammed, Khasim | cc26b3b | 2008-10-09 17:51:41 +0300 | [diff] [blame] | 290 | bx lr |
| 291 | |
Dave Martin | ef7a87d | 2011-03-04 15:33:56 +0000 | [diff] [blame^] | 292 | .align |
Syed Mohammed, Khasim | cc26b3b | 2008-10-09 17:51:41 +0300 | [diff] [blame] | 293 | omap3_sdrc_power: |
| 294 | .word OMAP34XX_SDRC_REGADDR(SDRC_POWER) |
| 295 | omap3_cm_clksel1_pll: |
| 296 | .word OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1) |
| 297 | omap3_cm_idlest1_core: |
| 298 | .word OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST) |
| 299 | omap3_cm_iclken1_core: |
| 300 | .word OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1) |
Jean Pihet | 58cda88 | 2009-07-24 19:43:25 -0600 | [diff] [blame] | 301 | |
| 302 | omap3_sdrc_rfr_ctrl_0: |
Syed Mohammed, Khasim | cc26b3b | 2008-10-09 17:51:41 +0300 | [diff] [blame] | 303 | .word OMAP34XX_SDRC_REGADDR(SDRC_RFR_CTRL_0) |
Jean Pihet | 58cda88 | 2009-07-24 19:43:25 -0600 | [diff] [blame] | 304 | omap3_sdrc_rfr_ctrl_1: |
| 305 | .word OMAP34XX_SDRC_REGADDR(SDRC_RFR_CTRL_1) |
| 306 | omap3_sdrc_actim_ctrl_a_0: |
Syed Mohammed, Khasim | cc26b3b | 2008-10-09 17:51:41 +0300 | [diff] [blame] | 307 | .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_0) |
Jean Pihet | 58cda88 | 2009-07-24 19:43:25 -0600 | [diff] [blame] | 308 | omap3_sdrc_actim_ctrl_a_1: |
| 309 | .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_1) |
| 310 | omap3_sdrc_actim_ctrl_b_0: |
Syed Mohammed, Khasim | cc26b3b | 2008-10-09 17:51:41 +0300 | [diff] [blame] | 311 | .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_0) |
Jean Pihet | 58cda88 | 2009-07-24 19:43:25 -0600 | [diff] [blame] | 312 | omap3_sdrc_actim_ctrl_b_1: |
| 313 | .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_1) |
Paul Walmsley | d0ba392 | 2009-06-19 19:08:27 -0600 | [diff] [blame] | 314 | omap3_sdrc_mr_0: |
| 315 | .word OMAP34XX_SDRC_REGADDR(SDRC_MR_0) |
Jean Pihet | 58cda88 | 2009-07-24 19:43:25 -0600 | [diff] [blame] | 316 | omap3_sdrc_mr_1: |
| 317 | .word OMAP34XX_SDRC_REGADDR(SDRC_MR_1) |
| 318 | omap_sdrc_rfr_ctrl_0_val: |
| 319 | .word 0xDEADBEEF |
| 320 | omap_sdrc_rfr_ctrl_1_val: |
| 321 | .word 0xDEADBEEF |
| 322 | omap_sdrc_actim_ctrl_a_0_val: |
| 323 | .word 0xDEADBEEF |
| 324 | omap_sdrc_actim_ctrl_a_1_val: |
| 325 | .word 0xDEADBEEF |
| 326 | omap_sdrc_actim_ctrl_b_0_val: |
| 327 | .word 0xDEADBEEF |
| 328 | omap_sdrc_actim_ctrl_b_1_val: |
| 329 | .word 0xDEADBEEF |
| 330 | omap_sdrc_mr_0_val: |
| 331 | .word 0xDEADBEEF |
| 332 | omap_sdrc_mr_1_val: |
| 333 | .word 0xDEADBEEF |
| 334 | |
Syed Mohammed, Khasim | cc26b3b | 2008-10-09 17:51:41 +0300 | [diff] [blame] | 335 | omap3_sdrc_dlla_status: |
| 336 | .word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS) |
| 337 | omap3_sdrc_dlla_ctrl: |
| 338 | .word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL) |
| 339 | core_m2_mask_val: |
| 340 | .word 0x07FFFFFF |
Dave Martin | ef7a87d | 2011-03-04 15:33:56 +0000 | [diff] [blame^] | 341 | ENDPROC(omap3_sram_configure_core_dpll) |
Syed Mohammed, Khasim | cc26b3b | 2008-10-09 17:51:41 +0300 | [diff] [blame] | 342 | |
| 343 | ENTRY(omap3_sram_configure_core_dpll_sz) |
| 344 | .word . - omap3_sram_configure_core_dpll |
Jean Pihet | 58cda88 | 2009-07-24 19:43:25 -0600 | [diff] [blame] | 345 | |