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Kevin Chan1d5fd4a2013-01-11 14:08:14 -08001#ifndef MSM_CAM_ISPIF_H
2#define MSM_CAM_ISPIF_H
3
Lokesh Kumar Aakulu329a3472013-06-03 06:08:17 -07004#define CSID_VERSION_V20 0x02000011
5#define CSID_VERSION_V22 0x02001000
6#define CSID_VERSION_V30 0x30000000
7#define CSID_VERSION_V3 0x30000000
Kevin Chan1d5fd4a2013-01-11 14:08:14 -08008
9enum msm_ispif_vfe_intf {
10 VFE0,
11 VFE1,
12 VFE_MAX
13};
14#define VFE0_MASK (1 << VFE0)
15#define VFE1_MASK (1 << VFE1)
16
17enum msm_ispif_intftype {
18 PIX0,
19 RDI0,
20 PIX1,
21 RDI1,
22 RDI2,
23 INTF_MAX
24};
Mingcheng Zhu8d117332013-04-01 12:05:56 -070025#define MAX_PARAM_ENTRIES (INTF_MAX * 2)
Lakshmi Narayana Kalavala1d1cb7b2013-07-16 15:57:03 -070026#define MAX_CID_CH 8
Mingcheng Zhu8d117332013-04-01 12:05:56 -070027
Kevin Chan1d5fd4a2013-01-11 14:08:14 -080028#define PIX0_MASK (1 << PIX0)
29#define PIX1_MASK (1 << PIX1)
30#define RDI0_MASK (1 << RDI0)
31#define RDI1_MASK (1 << RDI1)
32#define RDI2_MASK (1 << RDI2)
33
34
35enum msm_ispif_vc {
36 VC0,
37 VC1,
38 VC2,
39 VC3,
40 VC_MAX
41};
42
43enum msm_ispif_cid {
44 CID0,
45 CID1,
46 CID2,
47 CID3,
48 CID4,
49 CID5,
50 CID6,
51 CID7,
52 CID8,
53 CID9,
54 CID10,
55 CID11,
56 CID12,
57 CID13,
58 CID14,
59 CID15,
60 CID_MAX
61};
62
63enum msm_ispif_csid {
64 CSID0,
65 CSID1,
66 CSID2,
67 CSID3,
68 CSID_MAX
69};
70
71struct msm_ispif_params_entry {
Mingcheng Zhu1329a6c2013-03-29 18:09:49 -070072 enum msm_ispif_vfe_intf vfe_intf;
Kevin Chan1d5fd4a2013-01-11 14:08:14 -080073 enum msm_ispif_intftype intftype;
74 int num_cids;
75 enum msm_ispif_cid cids[3];
76 enum msm_ispif_csid csid;
Mingcheng Zhu43fe0982013-03-29 18:11:08 -070077 int crop_enable;
78 uint16_t crop_start_pixel;
79 uint16_t crop_end_pixel;
Kevin Chan1d5fd4a2013-01-11 14:08:14 -080080};
81
82struct msm_ispif_param_data {
Kevin Chan1d5fd4a2013-01-11 14:08:14 -080083 uint32_t num;
Mingcheng Zhu8d117332013-04-01 12:05:56 -070084 struct msm_ispif_params_entry entries[MAX_PARAM_ENTRIES];
Kevin Chan1d5fd4a2013-01-11 14:08:14 -080085};
86
Vladislav Hristovb9a0b332013-03-18 10:11:46 -070087struct msm_isp_info {
88 uint32_t max_resolution;
89 uint32_t id;
90 uint32_t ver;
91};
92
93struct msm_ispif_vfe_info {
94 int num_vfe;
95 struct msm_isp_info info[VFE_MAX];
96};
97
Kevin Chan1d5fd4a2013-01-11 14:08:14 -080098enum ispif_cfg_type_t {
99 ISPIF_CLK_ENABLE,
100 ISPIF_CLK_DISABLE,
101 ISPIF_INIT,
102 ISPIF_CFG,
103 ISPIF_START_FRAME_BOUNDARY,
104 ISPIF_STOP_FRAME_BOUNDARY,
105 ISPIF_STOP_IMMEDIATELY,
106 ISPIF_RELEASE,
107 ISPIF_ENABLE_REG_DUMP,
Vladislav Hristovb9a0b332013-03-18 10:11:46 -0700108 ISPIF_SET_VFE_INFO,
Kevin Chan1d5fd4a2013-01-11 14:08:14 -0800109};
110
111struct ispif_cfg_data {
112 enum ispif_cfg_type_t cfg_type;
113 union {
114 int reg_dump; /* ISPIF_ENABLE_REG_DUMP */
115 uint32_t csid_version; /* ISPIF_INIT */
Vladislav Hristovb9a0b332013-03-18 10:11:46 -0700116 struct msm_ispif_vfe_info vfe_info; /* ISPIF_SET_VFE_INFO */
Kevin Chan1d5fd4a2013-01-11 14:08:14 -0800117 struct msm_ispif_param_data params; /* CFG, START, STOP */
118 };
119};
120
121#define VIDIOC_MSM_ISPIF_CFG \
122 _IOWR('V', BASE_VIDIOC_PRIVATE, struct ispif_cfg_data)
123
124#endif /* MSM_CAM_ISPIF_H */