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Praveen Chidambaramf27a5152013-02-01 11:44:53 -07001/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
Praveen Chidambaram78499012011-11-01 17:15:17 -06002 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 */
13
14#include <linux/kernel.h>
15#include <linux/platform_device.h>
Steve Mucklef132c6c2012-06-06 18:30:57 -070016#include <asm/io.h>
Mitchel Humpherys0cc2bce2012-09-06 11:35:55 -070017#include <linux/msm_ion.h>
Praveen Chidambaram78499012011-11-01 17:15:17 -060018#include <mach/msm_iomap.h>
19#include <mach/irqs-8930.h>
20#include <mach/rpm.h>
Arun Menonaabf2632012-02-24 15:30:47 -080021#include <mach/msm_bus.h>
Gagan Maccd5b3272012-02-09 18:13:10 -070022#include <mach/msm_bus_board.h>
Arun Menonaabf2632012-02-24 15:30:47 -080023#include <mach/board.h>
24#include <mach/socinfo.h>
Laura Abbott0577d7b2012-04-17 11:14:30 -070025#include <mach/iommu_domains.h>
Laura Abbott532b2df2012-04-12 10:53:48 -070026#include <mach/msm_rtb.h>
Laura Abbottf3173042012-05-29 15:23:18 -070027#include <mach/msm_cache_dump.h>
Praveen Chidambaram78499012011-11-01 17:15:17 -060028
29#include "devices.h"
30#include "rpm_log.h"
31#include "rpm_stats.h"
Girish Mahadevan898c56d2012-06-05 16:09:19 -060032#include "rpm_rbcpr_stats.h"
Matt Wagantall1f65d9d2012-04-25 14:24:20 -070033#include "footswitch.h"
Patrick Dalyc1227cb2012-08-28 13:39:17 -070034#include "acpuclock-krait.h"
Praveen Chidambaramf27a5152013-02-01 11:44:53 -070035#include "pm.h"
Praveen Chidambaram78499012011-11-01 17:15:17 -060036
37#ifdef CONFIG_MSM_MPM
Subhash Jadavani909e04f2012-04-12 10:52:50 +053038#include <mach/mpm.h>
Praveen Chidambaram78499012011-11-01 17:15:17 -060039#endif
Anji Jonnala6c2b6852012-09-21 13:34:44 +053040#define MSM8930_PC_CNTR_PHYS (MSM8930_IMEM_PHYS + 0x664)
41#define MSM8930_PC_CNTR_SIZE 0x40
Anji Jonnala93129922012-10-09 20:57:53 +053042#define MSM8930_RPM_MASTER_STATS_BASE 0x10B100
Anji Jonnala6c2b6852012-09-21 13:34:44 +053043
44static struct resource msm8930_resources_pccntr[] = {
45 {
46 .start = MSM8930_PC_CNTR_PHYS,
47 .end = MSM8930_PC_CNTR_PHYS + MSM8930_PC_CNTR_SIZE,
48 .flags = IORESOURCE_MEM,
49 },
50};
51
Praveen Chidambaramf27a5152013-02-01 11:44:53 -070052static struct msm_pm_init_data_type msm_pm_data = {
53 .retention_calls_tz = true,
54};
55
56struct platform_device msm8930_pm_8x60 = {
57 .name = "pm-8x60",
Anji Jonnala6c2b6852012-09-21 13:34:44 +053058 .id = -1,
59 .num_resources = ARRAY_SIZE(msm8930_resources_pccntr),
60 .resource = msm8930_resources_pccntr,
Praveen Chidambaramf27a5152013-02-01 11:44:53 -070061 .dev = {
62 .platform_data = &msm_pm_data,
63 },
Anji Jonnala6c2b6852012-09-21 13:34:44 +053064};
Praveen Chidambaram78499012011-11-01 17:15:17 -060065
66struct msm_rpm_platform_data msm8930_rpm_data __initdata = {
67 .reg_base_addrs = {
68 [MSM_RPM_PAGE_STATUS] = MSM_RPM_BASE,
69 [MSM_RPM_PAGE_CTRL] = MSM_RPM_BASE + 0x400,
70 [MSM_RPM_PAGE_REQ] = MSM_RPM_BASE + 0x600,
71 [MSM_RPM_PAGE_ACK] = MSM_RPM_BASE + 0xa00,
72 },
73 .irq_ack = RPM_APCC_CPU0_GP_HIGH_IRQ,
Stephen Boydf61255e2012-02-24 14:31:09 -080074 .irq_err = RPM_APCC_CPU0_GP_LOW_IRQ,
Praveen Chidambarame396ce62012-03-30 11:15:57 -060075 .irq_wakeup = RPM_APCC_CPU0_WAKE_UP_IRQ,
Praveen Chidambaram78499012011-11-01 17:15:17 -060076 .ipc_rpm_reg = MSM_APCS_GCC_BASE + 0x008,
77 .ipc_rpm_val = 4,
78 .target_id = {
79 MSM_RPM_MAP(8930, NOTIFICATION_CONFIGURED_0, NOTIFICATION, 4),
80 MSM_RPM_MAP(8930, NOTIFICATION_REGISTERED_0, NOTIFICATION, 4),
81 MSM_RPM_MAP(8930, INVALIDATE_0, INVALIDATE, 8),
Mahesh Sivasubramanianef2a0fa2012-01-24 15:57:01 -070082 MSM_RPM_MAP(8960, TRIGGER_TIMED_TO, TRIGGER_TIMED, 1),
83 MSM_RPM_MAP(8960, TRIGGER_TIMED_SCLK_COUNT, TRIGGER_TIMED, 1),
Praveen Chidambaram78499012011-11-01 17:15:17 -060084 MSM_RPM_MAP(8930, RPM_CTL, RPM_CTL, 1),
85 MSM_RPM_MAP(8930, CXO_CLK, CXO_CLK, 1),
86 MSM_RPM_MAP(8930, PXO_CLK, PXO_CLK, 1),
87 MSM_RPM_MAP(8930, APPS_FABRIC_CLK, APPS_FABRIC_CLK, 1),
88 MSM_RPM_MAP(8930, SYSTEM_FABRIC_CLK, SYSTEM_FABRIC_CLK, 1),
89 MSM_RPM_MAP(8930, MM_FABRIC_CLK, MM_FABRIC_CLK, 1),
90 MSM_RPM_MAP(8930, DAYTONA_FABRIC_CLK, DAYTONA_FABRIC_CLK, 1),
91 MSM_RPM_MAP(8930, SFPB_CLK, SFPB_CLK, 1),
92 MSM_RPM_MAP(8930, CFPB_CLK, CFPB_CLK, 1),
93 MSM_RPM_MAP(8930, MMFPB_CLK, MMFPB_CLK, 1),
94 MSM_RPM_MAP(8930, EBI1_CLK, EBI1_CLK, 1),
95 MSM_RPM_MAP(8930, APPS_FABRIC_CFG_HALT_0,
96 APPS_FABRIC_CFG_HALT, 2),
97 MSM_RPM_MAP(8930, APPS_FABRIC_CFG_CLKMOD_0,
98 APPS_FABRIC_CFG_CLKMOD, 3),
99 MSM_RPM_MAP(8930, APPS_FABRIC_CFG_IOCTL,
100 APPS_FABRIC_CFG_IOCTL, 1),
Mahesh Sivasubramanian2d2c70592012-03-20 17:07:24 -0600101 MSM_RPM_MAP(8930, APPS_FABRIC_ARB_0, APPS_FABRIC_ARB, 6),
Praveen Chidambaram78499012011-11-01 17:15:17 -0600102 MSM_RPM_MAP(8930, SYS_FABRIC_CFG_HALT_0,
103 SYS_FABRIC_CFG_HALT, 2),
104 MSM_RPM_MAP(8930, SYS_FABRIC_CFG_CLKMOD_0,
105 SYS_FABRIC_CFG_CLKMOD, 3),
106 MSM_RPM_MAP(8930, SYS_FABRIC_CFG_IOCTL,
107 SYS_FABRIC_CFG_IOCTL, 1),
108 MSM_RPM_MAP(8930, SYSTEM_FABRIC_ARB_0,
Mahesh Sivasubramanian2d2c70592012-03-20 17:07:24 -0600109 SYSTEM_FABRIC_ARB, 20),
Praveen Chidambaram78499012011-11-01 17:15:17 -0600110 MSM_RPM_MAP(8930, MMSS_FABRIC_CFG_HALT_0,
111 MMSS_FABRIC_CFG_HALT, 2),
112 MSM_RPM_MAP(8930, MMSS_FABRIC_CFG_CLKMOD_0,
113 MMSS_FABRIC_CFG_CLKMOD, 3),
114 MSM_RPM_MAP(8930, MMSS_FABRIC_CFG_IOCTL,
115 MMSS_FABRIC_CFG_IOCTL, 1),
Mahesh Sivasubramanian2d2c70592012-03-20 17:07:24 -0600116 MSM_RPM_MAP(8930, MM_FABRIC_ARB_0, MM_FABRIC_ARB, 11),
Praveen Chidambaram78499012011-11-01 17:15:17 -0600117 MSM_RPM_MAP(8930, PM8038_S1_0, PM8038_S1, 2),
118 MSM_RPM_MAP(8930, PM8038_S2_0, PM8038_S2, 2),
119 MSM_RPM_MAP(8930, PM8038_S3_0, PM8038_S3, 2),
120 MSM_RPM_MAP(8930, PM8038_S4_0, PM8038_S4, 2),
121 MSM_RPM_MAP(8930, PM8038_S5_0, PM8038_S5, 2),
122 MSM_RPM_MAP(8930, PM8038_S6_0, PM8038_S6, 2),
123 MSM_RPM_MAP(8930, PM8038_L1_0, PM8038_L1, 2),
124 MSM_RPM_MAP(8930, PM8038_L2_0, PM8038_L2, 2),
125 MSM_RPM_MAP(8930, PM8038_L3_0, PM8038_L3, 2),
126 MSM_RPM_MAP(8930, PM8038_L4_0, PM8038_L4, 2),
127 MSM_RPM_MAP(8930, PM8038_L5_0, PM8038_L5, 2),
128 MSM_RPM_MAP(8930, PM8038_L6_0, PM8038_L6, 2),
129 MSM_RPM_MAP(8930, PM8038_L7_0, PM8038_L7, 2),
130 MSM_RPM_MAP(8930, PM8038_L8_0, PM8038_L8, 2),
131 MSM_RPM_MAP(8930, PM8038_L9_0, PM8038_L9, 2),
132 MSM_RPM_MAP(8930, PM8038_L10_0, PM8038_L10, 2),
133 MSM_RPM_MAP(8930, PM8038_L11_0, PM8038_L11, 2),
134 MSM_RPM_MAP(8930, PM8038_L12_0, PM8038_L12, 2),
135 MSM_RPM_MAP(8930, PM8038_L13_0, PM8038_L13, 2),
136 MSM_RPM_MAP(8930, PM8038_L14_0, PM8038_L14, 2),
137 MSM_RPM_MAP(8930, PM8038_L15_0, PM8038_L15, 2),
138 MSM_RPM_MAP(8930, PM8038_L16_0, PM8038_L16, 2),
139 MSM_RPM_MAP(8930, PM8038_L17_0, PM8038_L17, 2),
140 MSM_RPM_MAP(8930, PM8038_L18_0, PM8038_L18, 2),
141 MSM_RPM_MAP(8930, PM8038_L19_0, PM8038_L19, 2),
142 MSM_RPM_MAP(8930, PM8038_L20_0, PM8038_L20, 2),
143 MSM_RPM_MAP(8930, PM8038_L21_0, PM8038_L21, 2),
144 MSM_RPM_MAP(8930, PM8038_L22_0, PM8038_L22, 2),
145 MSM_RPM_MAP(8930, PM8038_L23_0, PM8038_L23, 2),
146 MSM_RPM_MAP(8930, PM8038_L24_0, PM8038_L24, 2),
147 MSM_RPM_MAP(8930, PM8038_L25_0, PM8038_L25, 2),
148 MSM_RPM_MAP(8930, PM8038_L26_0, PM8038_L26, 2),
149 MSM_RPM_MAP(8930, PM8038_L27_0, PM8038_L27, 2),
150 MSM_RPM_MAP(8930, PM8038_CLK1_0, PM8038_CLK1, 2),
151 MSM_RPM_MAP(8930, PM8038_CLK2_0, PM8038_CLK2, 2),
152 MSM_RPM_MAP(8930, PM8038_LVS1, PM8038_LVS1, 1),
153 MSM_RPM_MAP(8930, PM8038_LVS2, PM8038_LVS2, 1),
David Collins64c86fb2012-11-29 17:31:39 -0800154 MSM_RPM_MAP_PMIC(8930, 8038, NCP_0, NCP, 2),
155 MSM_RPM_MAP_PMIC(8930, 8038, CXO_BUFFERS, CXO_BUFFERS, 1),
156 MSM_RPM_MAP_PMIC(8930, 8038, USB_OTG_SWITCH, USB_OTG_SWITCH, 1),
157 MSM_RPM_MAP_PMIC(8930, 8038, HDMI_SWITCH, HDMI_SWITCH, 1),
158 MSM_RPM_MAP_PMIC(8930, 8038, QDSS_CLK, QDSS_CLK, 1),
159 MSM_RPM_MAP_PMIC(8930, 8038, VOLTAGE_CORNER, VOLTAGE_CORNER, 1),
Praveen Chidambaram78499012011-11-01 17:15:17 -0600160 },
161 .target_status = {
162 MSM_RPM_STATUS_ID_MAP(8930, VERSION_MAJOR),
163 MSM_RPM_STATUS_ID_MAP(8930, VERSION_MINOR),
164 MSM_RPM_STATUS_ID_MAP(8930, VERSION_BUILD),
165 MSM_RPM_STATUS_ID_MAP(8930, SUPPORTED_RESOURCES_0),
166 MSM_RPM_STATUS_ID_MAP(8930, SUPPORTED_RESOURCES_1),
167 MSM_RPM_STATUS_ID_MAP(8930, SUPPORTED_RESOURCES_2),
168 MSM_RPM_STATUS_ID_MAP(8930, RESERVED_SUPPORTED_RESOURCES_0),
169 MSM_RPM_STATUS_ID_MAP(8930, SEQUENCE),
170 MSM_RPM_STATUS_ID_MAP(8930, RPM_CTL),
171 MSM_RPM_STATUS_ID_MAP(8930, CXO_CLK),
172 MSM_RPM_STATUS_ID_MAP(8930, PXO_CLK),
173 MSM_RPM_STATUS_ID_MAP(8930, APPS_FABRIC_CLK),
174 MSM_RPM_STATUS_ID_MAP(8930, SYSTEM_FABRIC_CLK),
175 MSM_RPM_STATUS_ID_MAP(8930, MM_FABRIC_CLK),
176 MSM_RPM_STATUS_ID_MAP(8930, DAYTONA_FABRIC_CLK),
177 MSM_RPM_STATUS_ID_MAP(8930, SFPB_CLK),
178 MSM_RPM_STATUS_ID_MAP(8930, CFPB_CLK),
179 MSM_RPM_STATUS_ID_MAP(8930, MMFPB_CLK),
180 MSM_RPM_STATUS_ID_MAP(8930, EBI1_CLK),
181 MSM_RPM_STATUS_ID_MAP(8930, APPS_FABRIC_CFG_HALT),
182 MSM_RPM_STATUS_ID_MAP(8930, APPS_FABRIC_CFG_CLKMOD),
183 MSM_RPM_STATUS_ID_MAP(8930, APPS_FABRIC_CFG_IOCTL),
184 MSM_RPM_STATUS_ID_MAP(8930, APPS_FABRIC_ARB),
185 MSM_RPM_STATUS_ID_MAP(8930, SYS_FABRIC_CFG_HALT),
186 MSM_RPM_STATUS_ID_MAP(8930, SYS_FABRIC_CFG_CLKMOD),
187 MSM_RPM_STATUS_ID_MAP(8930, SYS_FABRIC_CFG_IOCTL),
188 MSM_RPM_STATUS_ID_MAP(8930, SYSTEM_FABRIC_ARB),
189 MSM_RPM_STATUS_ID_MAP(8930, MMSS_FABRIC_CFG_HALT),
190 MSM_RPM_STATUS_ID_MAP(8930, MMSS_FABRIC_CFG_CLKMOD),
191 MSM_RPM_STATUS_ID_MAP(8930, MMSS_FABRIC_CFG_IOCTL),
192 MSM_RPM_STATUS_ID_MAP(8930, MM_FABRIC_ARB),
193 MSM_RPM_STATUS_ID_MAP(8930, PM8038_S1_0),
194 MSM_RPM_STATUS_ID_MAP(8930, PM8038_S1_1),
195 MSM_RPM_STATUS_ID_MAP(8930, PM8038_S2_0),
196 MSM_RPM_STATUS_ID_MAP(8930, PM8038_S2_1),
197 MSM_RPM_STATUS_ID_MAP(8930, PM8038_S3_0),
198 MSM_RPM_STATUS_ID_MAP(8930, PM8038_S3_1),
199 MSM_RPM_STATUS_ID_MAP(8930, PM8038_S4_0),
200 MSM_RPM_STATUS_ID_MAP(8930, PM8038_S4_1),
201 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L1_0),
202 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L1_1),
203 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L2_0),
204 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L2_1),
205 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L3_0),
206 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L3_1),
207 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L4_0),
208 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L4_1),
209 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L5_0),
210 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L5_1),
211 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L6_0),
212 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L6_1),
213 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L7_0),
214 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L7_1),
215 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L8_0),
216 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L8_1),
217 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L9_0),
218 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L9_1),
219 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L10_0),
220 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L10_1),
221 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L11_0),
222 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L11_1),
223 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L12_0),
224 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L12_1),
225 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L13_0),
226 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L13_1),
227 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L14_0),
228 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L14_1),
229 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L15_0),
230 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L15_1),
231 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L16_0),
232 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L16_1),
233 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L17_0),
234 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L17_1),
235 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L18_0),
236 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L18_1),
237 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L19_0),
238 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L19_1),
239 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L20_0),
240 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L20_1),
241 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L21_0),
242 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L21_1),
243 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L22_0),
244 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L22_1),
245 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L23_0),
246 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L23_1),
247 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L24_0),
248 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L24_1),
249 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L25_0),
250 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L25_1),
251 MSM_RPM_STATUS_ID_MAP(8930, PM8038_CLK1_0),
252 MSM_RPM_STATUS_ID_MAP(8930, PM8038_CLK1_1),
253 MSM_RPM_STATUS_ID_MAP(8930, PM8038_CLK2_0),
254 MSM_RPM_STATUS_ID_MAP(8930, PM8038_CLK2_1),
255 MSM_RPM_STATUS_ID_MAP(8930, PM8038_LVS1),
256 MSM_RPM_STATUS_ID_MAP(8930, PM8038_LVS2),
Praveen Chidambaram75b8c812012-08-10 16:26:37 -0600257 MSM_RPM_STATUS_ID_MAP(8930, PM8038_NCP_0),
258 MSM_RPM_STATUS_ID_MAP(8930, PM8038_NCP_1),
259 MSM_RPM_STATUS_ID_MAP(8930, PM8038_CXO_BUFFERS),
260 MSM_RPM_STATUS_ID_MAP(8930, PM8038_USB_OTG_SWITCH),
261 MSM_RPM_STATUS_ID_MAP(8930, PM8038_HDMI_SWITCH),
262 MSM_RPM_STATUS_ID_MAP(8930, PM8038_QDSS_CLK),
263 MSM_RPM_STATUS_ID_MAP(8930, PM8038_VOLTAGE_CORNER),
Praveen Chidambaram78499012011-11-01 17:15:17 -0600264 },
265 .target_ctrl_id = {
266 MSM_RPM_CTRL_MAP(8930, VERSION_MAJOR),
267 MSM_RPM_CTRL_MAP(8930, VERSION_MINOR),
268 MSM_RPM_CTRL_MAP(8930, VERSION_BUILD),
269 MSM_RPM_CTRL_MAP(8930, REQ_CTX_0),
270 MSM_RPM_CTRL_MAP(8930, REQ_SEL_0),
271 MSM_RPM_CTRL_MAP(8930, ACK_CTX_0),
272 MSM_RPM_CTRL_MAP(8930, ACK_SEL_0),
273 },
274 .sel_invalidate = MSM_RPM_8930_SEL_INVALIDATE,
275 .sel_notification = MSM_RPM_8930_SEL_NOTIFICATION,
276 .sel_last = MSM_RPM_8930_SEL_LAST,
277 .ver = {3, 0, 0},
278};
279
Praveen Chidambaram75b8c812012-08-10 16:26:37 -0600280struct msm_rpm_platform_data msm8930_rpm_data_pm8917 __initdata = {
281 .reg_base_addrs = {
282 [MSM_RPM_PAGE_STATUS] = MSM_RPM_BASE,
283 [MSM_RPM_PAGE_CTRL] = MSM_RPM_BASE + 0x400,
284 [MSM_RPM_PAGE_REQ] = MSM_RPM_BASE + 0x600,
285 [MSM_RPM_PAGE_ACK] = MSM_RPM_BASE + 0xa00,
286 },
287 .irq_ack = RPM_APCC_CPU0_GP_HIGH_IRQ,
288 .irq_err = RPM_APCC_CPU0_GP_LOW_IRQ,
289 .irq_wakeup = RPM_APCC_CPU0_WAKE_UP_IRQ,
290 .ipc_rpm_reg = MSM_APCS_GCC_BASE + 0x008,
291 .ipc_rpm_val = 4,
292 .target_id = {
293 MSM_RPM_MAP(8930, NOTIFICATION_CONFIGURED_0, NOTIFICATION, 4),
294 MSM_RPM_MAP(8930, NOTIFICATION_REGISTERED_0, NOTIFICATION, 4),
295 MSM_RPM_MAP(8930, INVALIDATE_0, INVALIDATE, 8),
296 MSM_RPM_MAP(8960, TRIGGER_TIMED_TO, TRIGGER_TIMED, 1),
297 MSM_RPM_MAP(8960, TRIGGER_TIMED_SCLK_COUNT, TRIGGER_TIMED, 1),
298 MSM_RPM_MAP(8930, RPM_CTL, RPM_CTL, 1),
299 MSM_RPM_MAP(8930, CXO_CLK, CXO_CLK, 1),
300 MSM_RPM_MAP(8930, PXO_CLK, PXO_CLK, 1),
301 MSM_RPM_MAP(8930, APPS_FABRIC_CLK, APPS_FABRIC_CLK, 1),
302 MSM_RPM_MAP(8930, SYSTEM_FABRIC_CLK, SYSTEM_FABRIC_CLK, 1),
303 MSM_RPM_MAP(8930, MM_FABRIC_CLK, MM_FABRIC_CLK, 1),
304 MSM_RPM_MAP(8930, DAYTONA_FABRIC_CLK, DAYTONA_FABRIC_CLK, 1),
305 MSM_RPM_MAP(8930, SFPB_CLK, SFPB_CLK, 1),
306 MSM_RPM_MAP(8930, CFPB_CLK, CFPB_CLK, 1),
307 MSM_RPM_MAP(8930, MMFPB_CLK, MMFPB_CLK, 1),
308 MSM_RPM_MAP(8930, EBI1_CLK, EBI1_CLK, 1),
309 MSM_RPM_MAP(8930, APPS_FABRIC_CFG_HALT_0,
310 APPS_FABRIC_CFG_HALT, 2),
311 MSM_RPM_MAP(8930, APPS_FABRIC_CFG_CLKMOD_0,
312 APPS_FABRIC_CFG_CLKMOD, 3),
313 MSM_RPM_MAP(8930, APPS_FABRIC_CFG_IOCTL,
314 APPS_FABRIC_CFG_IOCTL, 1),
315 MSM_RPM_MAP(8930, APPS_FABRIC_ARB_0, APPS_FABRIC_ARB, 6),
316 MSM_RPM_MAP(8930, SYS_FABRIC_CFG_HALT_0,
317 SYS_FABRIC_CFG_HALT, 2),
318 MSM_RPM_MAP(8930, SYS_FABRIC_CFG_CLKMOD_0,
319 SYS_FABRIC_CFG_CLKMOD, 3),
320 MSM_RPM_MAP(8930, SYS_FABRIC_CFG_IOCTL,
321 SYS_FABRIC_CFG_IOCTL, 1),
322 MSM_RPM_MAP(8930, SYSTEM_FABRIC_ARB_0,
323 SYSTEM_FABRIC_ARB, 20),
324 MSM_RPM_MAP(8930, MMSS_FABRIC_CFG_HALT_0,
325 MMSS_FABRIC_CFG_HALT, 2),
326 MSM_RPM_MAP(8930, MMSS_FABRIC_CFG_CLKMOD_0,
327 MMSS_FABRIC_CFG_CLKMOD, 3),
328 MSM_RPM_MAP(8930, MMSS_FABRIC_CFG_IOCTL,
329 MMSS_FABRIC_CFG_IOCTL, 1),
330 MSM_RPM_MAP(8930, MM_FABRIC_ARB_0, MM_FABRIC_ARB, 11),
331 MSM_RPM_MAP(8930, PM8917_S1_0, PM8917_S1, 2),
332 MSM_RPM_MAP(8930, PM8917_S2_0, PM8917_S2, 2),
333 MSM_RPM_MAP(8930, PM8917_S3_0, PM8917_S3, 2),
334 MSM_RPM_MAP(8930, PM8917_S4_0, PM8917_S4, 2),
335 MSM_RPM_MAP(8930, PM8917_S5_0, PM8917_S5, 2),
336 MSM_RPM_MAP(8930, PM8917_S6_0, PM8917_S6, 2),
337 MSM_RPM_MAP(8930, PM8917_S7_0, PM8917_S7, 2),
338 MSM_RPM_MAP(8930, PM8917_S8_0, PM8917_S8, 2),
339 MSM_RPM_MAP(8930, PM8917_L1_0, PM8917_L1, 2),
340 MSM_RPM_MAP(8930, PM8917_L2_0, PM8917_L2, 2),
341 MSM_RPM_MAP(8930, PM8917_L3_0, PM8917_L3, 2),
342 MSM_RPM_MAP(8930, PM8917_L4_0, PM8917_L4, 2),
343 MSM_RPM_MAP(8930, PM8917_L5_0, PM8917_L5, 2),
344 MSM_RPM_MAP(8930, PM8917_L6_0, PM8917_L6, 2),
345 MSM_RPM_MAP(8930, PM8917_L7_0, PM8917_L7, 2),
346 MSM_RPM_MAP(8930, PM8917_L8_0, PM8917_L8, 2),
347 MSM_RPM_MAP(8930, PM8917_L9_0, PM8917_L9, 2),
348 MSM_RPM_MAP(8930, PM8917_L10_0, PM8917_L10, 2),
349 MSM_RPM_MAP(8930, PM8917_L11_0, PM8917_L11, 2),
350 MSM_RPM_MAP(8930, PM8917_L12_0, PM8917_L12, 2),
351 MSM_RPM_MAP(8930, PM8917_L14_0, PM8917_L14, 2),
352 MSM_RPM_MAP(8930, PM8917_L15_0, PM8917_L15, 2),
353 MSM_RPM_MAP(8930, PM8917_L16_0, PM8917_L16, 2),
354 MSM_RPM_MAP(8930, PM8917_L17_0, PM8917_L17, 2),
355 MSM_RPM_MAP(8930, PM8917_L18_0, PM8917_L18, 2),
356 MSM_RPM_MAP(8930, PM8917_L21_0, PM8917_L21, 2),
357 MSM_RPM_MAP(8930, PM8917_L22_0, PM8917_L22, 2),
358 MSM_RPM_MAP(8930, PM8917_L23_0, PM8917_L23, 2),
359 MSM_RPM_MAP(8930, PM8917_L24_0, PM8917_L24, 2),
360 MSM_RPM_MAP(8930, PM8917_L25_0, PM8917_L25, 2),
361 MSM_RPM_MAP(8930, PM8917_L26_0, PM8917_L26, 2),
362 MSM_RPM_MAP(8930, PM8917_L27_0, PM8917_L27, 2),
363 MSM_RPM_MAP(8930, PM8917_L28_0, PM8917_L28, 2),
364 MSM_RPM_MAP(8930, PM8917_L29_0, PM8917_L29, 2),
365 MSM_RPM_MAP(8930, PM8917_L30_0, PM8917_L30, 2),
366 MSM_RPM_MAP(8930, PM8917_L31_0, PM8917_L31, 2),
367 MSM_RPM_MAP(8930, PM8917_L32_0, PM8917_L32, 2),
368 MSM_RPM_MAP(8930, PM8917_L33_0, PM8917_L33, 2),
369 MSM_RPM_MAP(8930, PM8917_L34_0, PM8917_L34, 2),
370 MSM_RPM_MAP(8930, PM8917_L35_0, PM8917_L35, 2),
371 MSM_RPM_MAP(8930, PM8917_L36_0, PM8917_L36, 2),
372 MSM_RPM_MAP(8930, PM8917_CLK1_0, PM8917_CLK1, 2),
373 MSM_RPM_MAP(8930, PM8917_CLK2_0, PM8917_CLK2, 2),
374 MSM_RPM_MAP(8930, PM8917_LVS1, PM8917_LVS1, 1),
375 MSM_RPM_MAP(8930, PM8917_LVS3, PM8917_LVS3, 1),
376 MSM_RPM_MAP(8930, PM8917_LVS4, PM8917_LVS4, 1),
377 MSM_RPM_MAP(8930, PM8917_LVS5, PM8917_LVS5, 1),
378 MSM_RPM_MAP(8930, PM8917_LVS6, PM8917_LVS6, 1),
379 MSM_RPM_MAP(8930, PM8917_LVS7, PM8917_LVS7, 1),
David Collins64c86fb2012-11-29 17:31:39 -0800380 MSM_RPM_MAP_PMIC(8930, 8917, NCP_0, NCP, 2),
381 MSM_RPM_MAP_PMIC(8930, 8917, CXO_BUFFERS, CXO_BUFFERS, 1),
382 MSM_RPM_MAP_PMIC(8930, 8917, USB_OTG_SWITCH, USB_OTG_SWITCH, 1),
383 MSM_RPM_MAP_PMIC(8930, 8917, HDMI_SWITCH, HDMI_SWITCH, 1),
384 MSM_RPM_MAP_PMIC(8930, 8917, QDSS_CLK, QDSS_CLK, 1),
385 MSM_RPM_MAP_PMIC(8930, 8917, VOLTAGE_CORNER, VOLTAGE_CORNER, 1),
Praveen Chidambaram75b8c812012-08-10 16:26:37 -0600386 },
387 .target_status = {
388 MSM_RPM_STATUS_ID_MAP(8930, VERSION_MAJOR),
389 MSM_RPM_STATUS_ID_MAP(8930, VERSION_MINOR),
390 MSM_RPM_STATUS_ID_MAP(8930, VERSION_BUILD),
391 MSM_RPM_STATUS_ID_MAP(8930, SUPPORTED_RESOURCES_0),
392 MSM_RPM_STATUS_ID_MAP(8930, SUPPORTED_RESOURCES_1),
393 MSM_RPM_STATUS_ID_MAP(8930, SUPPORTED_RESOURCES_2),
394 MSM_RPM_STATUS_ID_MAP(8930, RESERVED_SUPPORTED_RESOURCES_0),
395 MSM_RPM_STATUS_ID_MAP(8930, SEQUENCE),
396 MSM_RPM_STATUS_ID_MAP(8930, RPM_CTL),
397 MSM_RPM_STATUS_ID_MAP(8930, CXO_CLK),
398 MSM_RPM_STATUS_ID_MAP(8930, PXO_CLK),
399 MSM_RPM_STATUS_ID_MAP(8930, APPS_FABRIC_CLK),
400 MSM_RPM_STATUS_ID_MAP(8930, SYSTEM_FABRIC_CLK),
401 MSM_RPM_STATUS_ID_MAP(8930, MM_FABRIC_CLK),
402 MSM_RPM_STATUS_ID_MAP(8930, DAYTONA_FABRIC_CLK),
403 MSM_RPM_STATUS_ID_MAP(8930, SFPB_CLK),
404 MSM_RPM_STATUS_ID_MAP(8930, CFPB_CLK),
405 MSM_RPM_STATUS_ID_MAP(8930, MMFPB_CLK),
406 MSM_RPM_STATUS_ID_MAP(8930, EBI1_CLK),
407 MSM_RPM_STATUS_ID_MAP(8930, APPS_FABRIC_CFG_HALT),
408 MSM_RPM_STATUS_ID_MAP(8930, APPS_FABRIC_CFG_CLKMOD),
409 MSM_RPM_STATUS_ID_MAP(8930, APPS_FABRIC_CFG_IOCTL),
410 MSM_RPM_STATUS_ID_MAP(8930, APPS_FABRIC_ARB),
411 MSM_RPM_STATUS_ID_MAP(8930, SYS_FABRIC_CFG_HALT),
412 MSM_RPM_STATUS_ID_MAP(8930, SYS_FABRIC_CFG_CLKMOD),
413 MSM_RPM_STATUS_ID_MAP(8930, SYS_FABRIC_CFG_IOCTL),
414 MSM_RPM_STATUS_ID_MAP(8930, SYSTEM_FABRIC_ARB),
415 MSM_RPM_STATUS_ID_MAP(8930, MMSS_FABRIC_CFG_HALT),
416 MSM_RPM_STATUS_ID_MAP(8930, MMSS_FABRIC_CFG_CLKMOD),
417 MSM_RPM_STATUS_ID_MAP(8930, MMSS_FABRIC_CFG_IOCTL),
418 MSM_RPM_STATUS_ID_MAP(8930, MM_FABRIC_ARB),
419 MSM_RPM_STATUS_ID_MAP(8930, PM8917_S1_0),
420 MSM_RPM_STATUS_ID_MAP(8930, PM8917_S1_1),
421 MSM_RPM_STATUS_ID_MAP(8930, PM8917_S2_0),
422 MSM_RPM_STATUS_ID_MAP(8930, PM8917_S2_1),
423 MSM_RPM_STATUS_ID_MAP(8930, PM8917_S3_0),
424 MSM_RPM_STATUS_ID_MAP(8930, PM8917_S3_1),
425 MSM_RPM_STATUS_ID_MAP(8930, PM8917_S4_0),
426 MSM_RPM_STATUS_ID_MAP(8930, PM8917_S4_1),
427 MSM_RPM_STATUS_ID_MAP(8930, PM8917_S5_0),
428 MSM_RPM_STATUS_ID_MAP(8930, PM8917_S5_1),
429 MSM_RPM_STATUS_ID_MAP(8930, PM8917_S6_0),
430 MSM_RPM_STATUS_ID_MAP(8930, PM8917_S6_1),
431 MSM_RPM_STATUS_ID_MAP(8930, PM8917_S7_0),
432 MSM_RPM_STATUS_ID_MAP(8930, PM8917_S7_1),
433 MSM_RPM_STATUS_ID_MAP(8930, PM8917_S8_0),
434 MSM_RPM_STATUS_ID_MAP(8930, PM8917_S8_1),
435 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L1_0),
436 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L1_1),
437 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L2_0),
438 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L2_1),
439 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L3_0),
440 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L3_1),
441 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L4_0),
442 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L4_1),
443 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L5_0),
444 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L5_1),
445 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L6_0),
446 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L6_1),
447 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L7_0),
448 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L7_1),
449 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L8_0),
450 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L8_1),
451 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L9_0),
452 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L9_1),
453 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L10_0),
454 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L10_1),
455 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L11_0),
456 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L11_1),
457 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L12_0),
458 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L12_1),
459 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L14_0),
460 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L14_1),
461 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L15_0),
462 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L15_1),
463 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L16_0),
464 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L16_1),
465 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L17_0),
466 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L17_1),
467 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L18_0),
468 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L18_1),
469 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L21_0),
470 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L21_1),
471 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L22_0),
472 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L22_1),
473 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L23_0),
474 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L23_1),
475 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L24_0),
476 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L24_1),
477 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L25_0),
478 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L25_1),
479 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L26_0),
480 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L26_1),
481 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L27_0),
482 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L27_1),
483 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L28_0),
484 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L28_1),
485 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L29_0),
486 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L29_1),
487 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L30_0),
488 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L30_1),
489 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L31_0),
490 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L31_1),
491 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L32_0),
492 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L32_1),
493 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L33_0),
494 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L33_1),
495 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L34_0),
496 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L34_1),
497 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L35_0),
498 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L35_1),
499 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L36_0),
500 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L36_1),
501 MSM_RPM_STATUS_ID_MAP(8930, PM8917_CLK1_0),
502 MSM_RPM_STATUS_ID_MAP(8930, PM8917_CLK1_1),
503 MSM_RPM_STATUS_ID_MAP(8930, PM8917_CLK2_0),
504 MSM_RPM_STATUS_ID_MAP(8930, PM8917_CLK2_1),
505 MSM_RPM_STATUS_ID_MAP(8930, PM8917_LVS1),
506 MSM_RPM_STATUS_ID_MAP(8930, PM8917_LVS3),
507 MSM_RPM_STATUS_ID_MAP(8930, PM8917_LVS4),
508 MSM_RPM_STATUS_ID_MAP(8930, PM8917_LVS5),
509 MSM_RPM_STATUS_ID_MAP(8930, PM8917_LVS6),
510 MSM_RPM_STATUS_ID_MAP(8930, PM8917_LVS7),
511 MSM_RPM_STATUS_ID_MAP(8930, PM8917_NCP_0),
512 MSM_RPM_STATUS_ID_MAP(8930, PM8917_NCP_1),
513 MSM_RPM_STATUS_ID_MAP(8930, PM8917_CXO_BUFFERS),
514 MSM_RPM_STATUS_ID_MAP(8930, PM8917_USB_OTG_SWITCH),
515 MSM_RPM_STATUS_ID_MAP(8930, PM8917_HDMI_SWITCH),
516 MSM_RPM_STATUS_ID_MAP(8930, PM8917_QDSS_CLK),
517 MSM_RPM_STATUS_ID_MAP(8930, PM8917_VOLTAGE_CORNER),
518 },
519 .target_ctrl_id = {
520 MSM_RPM_CTRL_MAP(8930, VERSION_MAJOR),
521 MSM_RPM_CTRL_MAP(8930, VERSION_MINOR),
522 MSM_RPM_CTRL_MAP(8930, VERSION_BUILD),
523 MSM_RPM_CTRL_MAP(8930, REQ_CTX_0),
524 MSM_RPM_CTRL_MAP(8930, REQ_SEL_0),
525 MSM_RPM_CTRL_MAP(8930, ACK_CTX_0),
526 MSM_RPM_CTRL_MAP(8930, ACK_SEL_0),
527 },
528 .sel_invalidate = MSM_RPM_8930_SEL_INVALIDATE,
529 .sel_notification = MSM_RPM_8930_SEL_NOTIFICATION,
530 .sel_last = MSM_RPM_8930_SEL_LAST,
531 .ver = {3, 0, 0},
532};
Praveen Chidambaram78499012011-11-01 17:15:17 -0600533struct platform_device msm8930_rpm_device = {
534 .name = "msm_rpm",
535 .id = -1,
536};
537
538static struct msm_rpm_log_platform_data msm_rpm_log_pdata = {
539 .phys_addr_base = 0x0010C000,
540 .reg_offsets = {
541 [MSM_RPM_LOG_PAGE_INDICES] = 0x00000080,
542 [MSM_RPM_LOG_PAGE_BUFFER] = 0x000000A0,
543 },
544 .phys_size = SZ_8K,
545 .log_len = 4096, /* log's buffer length in bytes */
546 .log_len_mask = (4096 >> 2) - 1, /* length mask in units of u32 */
547};
548
549struct platform_device msm8930_rpm_log_device = {
550 .name = "msm_rpm_log",
551 .id = -1,
552 .dev = {
553 .platform_data = &msm_rpm_log_pdata,
554 },
555};
556
557static struct msm_rpmstats_platform_data msm_rpm_stat_pdata = {
Priyanka Mathur71859f42012-10-17 10:54:35 -0700558 .version = 1,
Praveen Chidambaram78499012011-11-01 17:15:17 -0600559};
560
Priyanka Mathur71859f42012-10-17 10:54:35 -0700561static struct resource msm_rpm_stat_resource[] = {
562 {
563 .start = 0x0010D204,
564 .end = 0x0010D204 + SZ_8K,
565 .flags = IORESOURCE_MEM,
566 .name = "phys_addr_base"
567
568 },
569};
570
571
Praveen Chidambaram78499012011-11-01 17:15:17 -0600572struct platform_device msm8930_rpm_stat_device = {
573 .name = "msm_rpm_stat",
574 .id = -1,
Priyanka Mathur71859f42012-10-17 10:54:35 -0700575 .resource = msm_rpm_stat_resource,
576 .num_resources = ARRAY_SIZE(msm_rpm_stat_resource),
577 .dev = {
Praveen Chidambaram78499012011-11-01 17:15:17 -0600578 .platform_data = &msm_rpm_stat_pdata,
Priyanka Mathur71859f42012-10-17 10:54:35 -0700579 }
Praveen Chidambaram78499012011-11-01 17:15:17 -0600580};
581
Anji Jonnala93129922012-10-09 20:57:53 +0530582static struct resource resources_rpm_master_stats[] = {
583 {
584 .start = MSM8930_RPM_MASTER_STATS_BASE,
585 .end = MSM8930_RPM_MASTER_STATS_BASE + SZ_256,
586 .flags = IORESOURCE_MEM,
587 },
588};
589
590static char *master_names[] = {
591 "KPSS",
592 "MPSS",
593 "LPASS",
594 "RIVA",
595};
596
597static struct msm_rpm_master_stats_platform_data msm_rpm_master_stat_pdata = {
598 .masters = master_names,
599 .nomasters = ARRAY_SIZE(master_names),
600};
601
602struct platform_device msm8930_rpm_master_stat_device = {
603 .name = "msm_rpm_master_stat",
604 .id = -1,
605 .num_resources = ARRAY_SIZE(resources_rpm_master_stats),
606 .resource = resources_rpm_master_stats,
607 .dev = {
608 .platform_data = &msm_rpm_master_stat_pdata,
609 },
610};
611
Girish Mahadevan898c56d2012-06-05 16:09:19 -0600612static struct resource msm_rpm_rbcpr_resource = {
Girish Mahadevanea1a1d72012-09-10 12:43:26 -0600613 .start = 0x0010DB00,
614 .end = 0x0010DB00 + SZ_8K - 1,
Girish Mahadevan898c56d2012-06-05 16:09:19 -0600615 .flags = IORESOURCE_MEM,
616};
617
618static struct msm_rpmrbcpr_platform_data msm_rpm_rbcpr_pdata = {
619 .rbcpr_data = {
620 .upside_steps = 1,
621 .downside_steps = 2,
622 .svs_voltage = 1050000,
623 .nominal_voltage = 1162500,
624 .turbo_voltage = 1287500,
625 },
626};
627
628struct platform_device msm8930_rpm_rbcpr_device = {
629 .name = "msm_rpm_rbcpr",
630 .id = -1,
631 .dev = {
632 .platform_data = &msm_rpm_rbcpr_pdata,
633 },
634 .resource = &msm_rpm_rbcpr_resource,
635};
636
Gagan Maccd5b3272012-02-09 18:13:10 -0700637struct platform_device msm_bus_8930_sys_fabric = {
638 .name = "msm_bus_fabric",
639 .id = MSM_BUS_FAB_SYSTEM,
640};
641struct platform_device msm_bus_8930_apps_fabric = {
642 .name = "msm_bus_fabric",
643 .id = MSM_BUS_FAB_APPSS,
644};
645struct platform_device msm_bus_8930_mm_fabric = {
646 .name = "msm_bus_fabric",
647 .id = MSM_BUS_FAB_MMSS,
648};
649struct platform_device msm_bus_8930_sys_fpb = {
650 .name = "msm_bus_fabric",
651 .id = MSM_BUS_FAB_SYSTEM_FPB,
652};
653struct platform_device msm_bus_8930_cpss_fpb = {
654 .name = "msm_bus_fabric",
655 .id = MSM_BUS_FAB_CPSS_FPB,
656};
657
Matt Wagantallab730bd2012-06-07 20:13:51 -0700658struct platform_device msm8627_device_acpuclk = {
659 .name = "acpuclk-8627",
660 .id = -1,
661};
662
Patrick Dalyc1227cb2012-08-28 13:39:17 -0700663static struct acpuclk_platform_data acpuclk_8930_pdata = {
664 .uses_pm8917 = false,
665};
666
Matt Wagantall6dcfa922012-06-07 20:13:51 -0700667struct platform_device msm8930_device_acpuclk = {
668 .name = "acpuclk-8930",
669 .id = -1,
Patrick Dalyc1227cb2012-08-28 13:39:17 -0700670 .dev = {
671 .platform_data = &acpuclk_8930_pdata,
672 },
Matt Wagantall6dcfa922012-06-07 20:13:51 -0700673};
674
Tianyi Gou12370f12012-07-23 19:13:57 -0700675struct platform_device msm8930aa_device_acpuclk = {
676 .name = "acpuclk-8930aa",
677 .id = -1,
678};
679
Tianyi Gou2520b6e2012-10-29 19:13:53 -0700680static struct acpuclk_platform_data acpuclk_8930ab_pdata = {
681 .uses_pm8917 = false,
682};
683
684struct platform_device msm8930ab_device_acpuclk = {
685 .name = "acpuclk-8930ab",
686 .id = -1,
687 .dev = {
688 .platform_data = &acpuclk_8930ab_pdata,
689 },
690};
691
Matt Wagantall1f65d9d2012-04-25 14:24:20 -0700692static struct fs_driver_data gfx3d_fs_data = {
693 .clks = (struct fs_clk_data[]){
694 { .name = "core_clk", .reset_rate = 27000000 },
695 { .name = "iface_clk" },
696 { .name = "bus_clk" },
697 { 0 }
698 },
699 .bus_port0 = MSM_BUS_MASTER_GRAPHICS_3D,
700};
701
702static struct fs_driver_data ijpeg_fs_data = {
703 .clks = (struct fs_clk_data[]){
704 { .name = "core_clk" },
705 { .name = "iface_clk" },
706 { .name = "bus_clk" },
707 { 0 }
708 },
709 .bus_port0 = MSM_BUS_MASTER_JPEG_ENC,
710};
711
Tianyi Gou723843b2012-06-13 15:24:56 -0700712static struct fs_driver_data mdp_fs_data_8930 = {
Matt Wagantall1f65d9d2012-04-25 14:24:20 -0700713 .clks = (struct fs_clk_data[]){
714 { .name = "core_clk" },
715 { .name = "iface_clk" },
716 { .name = "bus_clk" },
717 { .name = "vsync_clk" },
718 { .name = "lut_clk" },
719 { .name = "tv_src_clk" },
720 { .name = "tv_clk" },
Matt Wagantallc33c1ed2012-07-23 17:19:08 -0700721 { .name = "reset1_clk" },
Matt Wagantall1f65d9d2012-04-25 14:24:20 -0700722 { 0 }
723 },
724 .bus_port0 = MSM_BUS_MASTER_MDP_PORT0,
725 .bus_port1 = MSM_BUS_MASTER_MDP_PORT1,
726};
727
Aravind Venkateswaran896d2f92012-10-29 17:54:55 -0700728static struct fs_driver_data mdp_fs_data_8930_pm8917 = {
729 .clks = (struct fs_clk_data[]){
730 { .name = "core_clk" },
731 { .name = "iface_clk" },
732 { .name = "bus_clk" },
733 { .name = "vsync_clk" },
734 { .name = "lut_clk" },
735 { .name = "reset1_clk" },
736 { 0 }
737 },
738 .bus_port0 = MSM_BUS_MASTER_MDP_PORT0,
739 .bus_port1 = MSM_BUS_MASTER_MDP_PORT1,
740};
741
Tianyi Gou723843b2012-06-13 15:24:56 -0700742static struct fs_driver_data mdp_fs_data_8627 = {
743 .clks = (struct fs_clk_data[]){
744 { .name = "core_clk" },
745 { .name = "iface_clk" },
746 { .name = "bus_clk" },
747 { .name = "vsync_clk" },
748 { .name = "lut_clk" },
749 { .name = "reset1_clk" },
750 { 0 }
751 },
752 .bus_port0 = MSM_BUS_MASTER_MDP_PORT0,
753 .bus_port1 = MSM_BUS_MASTER_MDP_PORT1,
754};
755
Matt Wagantall1f65d9d2012-04-25 14:24:20 -0700756static struct fs_driver_data rot_fs_data = {
757 .clks = (struct fs_clk_data[]){
758 { .name = "core_clk" },
759 { .name = "iface_clk" },
760 { .name = "bus_clk" },
761 { 0 }
762 },
763 .bus_port0 = MSM_BUS_MASTER_ROTATOR,
764};
765
766static struct fs_driver_data ved_fs_data = {
767 .clks = (struct fs_clk_data[]){
768 { .name = "core_clk" },
769 { .name = "iface_clk" },
770 { .name = "bus_clk" },
771 { 0 }
772 },
773 .bus_port0 = MSM_BUS_MASTER_HD_CODEC_PORT0,
774 .bus_port1 = MSM_BUS_MASTER_HD_CODEC_PORT1,
775};
776
777static struct fs_driver_data vfe_fs_data = {
778 .clks = (struct fs_clk_data[]){
779 { .name = "core_clk" },
780 { .name = "iface_clk" },
781 { .name = "bus_clk" },
782 { 0 }
783 },
784 .bus_port0 = MSM_BUS_MASTER_VFE,
785};
786
787static struct fs_driver_data vpe_fs_data = {
788 .clks = (struct fs_clk_data[]){
789 { .name = "core_clk" },
790 { .name = "iface_clk" },
791 { .name = "bus_clk" },
792 { 0 }
793 },
794 .bus_port0 = MSM_BUS_MASTER_VPE,
795};
796
797struct platform_device *msm8930_footswitch[] __initdata = {
Tianyi Gou723843b2012-06-13 15:24:56 -0700798 FS_8X60(FS_MDP, "vdd", "mdp.0", &mdp_fs_data_8930),
Matt Wagantall316f2fc2012-05-03 20:41:42 -0700799 FS_8X60(FS_ROT, "vdd", "msm_rotator.0", &rot_fs_data),
Matt Wagantalle4454b82012-05-03 20:48:01 -0700800 FS_8X60(FS_IJPEG, "vdd", "msm_gemini.0", &ijpeg_fs_data),
Kiran Kumar H Nfa18a032012-06-25 14:34:18 -0700801 FS_8X60(FS_VFE, "vdd", "msm_vfe.0", &vfe_fs_data),
802 FS_8X60(FS_VPE, "vdd", "msm_vpe.0", &vpe_fs_data),
Matt Wagantalld6fbf232012-05-03 20:09:28 -0700803 FS_8X60(FS_GFX3D, "vdd", "kgsl-3d0.0", &gfx3d_fs_data),
Matt Wagantall5e46aac2012-05-03 20:20:18 -0700804 FS_8X60(FS_VED, "vdd", "msm_vidc.0", &ved_fs_data),
Matt Wagantall1f65d9d2012-04-25 14:24:20 -0700805};
806unsigned msm8930_num_footswitch __initdata = ARRAY_SIZE(msm8930_footswitch);
807
Aravind Venkateswaran896d2f92012-10-29 17:54:55 -0700808struct platform_device *msm8930_pm8917_footswitch[] __initdata = {
809 FS_8X60(FS_MDP, "vdd", "mdp.0", &mdp_fs_data_8930_pm8917),
810 FS_8X60(FS_ROT, "vdd", "msm_rotator.0", &rot_fs_data),
811 FS_8X60(FS_IJPEG, "vdd", "msm_gemini.0", &ijpeg_fs_data),
812 FS_8X60(FS_VFE, "vdd", "msm_vfe.0", &vfe_fs_data),
813 FS_8X60(FS_VPE, "vdd", "msm_vpe.0", &vpe_fs_data),
814 FS_8X60(FS_GFX3D, "vdd", "kgsl-3d0.0", &gfx3d_fs_data),
815 FS_8X60(FS_VED, "vdd", "msm_vidc.0", &ved_fs_data),
816};
817unsigned msm8930_pm8917_num_footswitch __initdata =
818 ARRAY_SIZE(msm8930_pm8917_footswitch);
819
Tianyi Gou723843b2012-06-13 15:24:56 -0700820struct platform_device *msm8627_footswitch[] __initdata = {
821 FS_8X60(FS_MDP, "vdd", "mdp.0", &mdp_fs_data_8627),
822 FS_8X60(FS_ROT, "vdd", "msm_rotator.0", &rot_fs_data),
823 FS_8X60(FS_IJPEG, "vdd", "msm_gemini.0", &ijpeg_fs_data),
824 FS_8X60(FS_VFE, "vdd", "msm_vfe.0", &vfe_fs_data),
825 FS_8X60(FS_VPE, "vdd", "msm_vpe.0", &vpe_fs_data),
826 FS_8X60(FS_GFX3D, "vdd", "kgsl-3d0.0", &gfx3d_fs_data),
827 FS_8X60(FS_VED, "vdd", "msm_vidc.0", &ved_fs_data),
828};
829unsigned msm8627_num_footswitch __initdata = ARRAY_SIZE(msm8627_footswitch);
830
Arun Menonaabf2632012-02-24 15:30:47 -0800831/* MSM Video core device */
832#ifdef CONFIG_MSM_BUS_SCALING
833static struct msm_bus_vectors vidc_init_vectors[] = {
834 {
835 .src = MSM_BUS_MASTER_HD_CODEC_PORT0,
836 .dst = MSM_BUS_SLAVE_EBI_CH0,
837 .ab = 0,
838 .ib = 0,
839 },
840 {
841 .src = MSM_BUS_MASTER_HD_CODEC_PORT1,
842 .dst = MSM_BUS_SLAVE_EBI_CH0,
843 .ab = 0,
844 .ib = 0,
845 },
846 {
847 .src = MSM_BUS_MASTER_AMPSS_M0,
848 .dst = MSM_BUS_SLAVE_EBI_CH0,
849 .ab = 0,
850 .ib = 0,
851 },
852 {
853 .src = MSM_BUS_MASTER_AMPSS_M0,
854 .dst = MSM_BUS_SLAVE_EBI_CH0,
855 .ab = 0,
856 .ib = 0,
857 },
858};
859static struct msm_bus_vectors vidc_venc_vga_vectors[] = {
860 {
861 .src = MSM_BUS_MASTER_HD_CODEC_PORT0,
862 .dst = MSM_BUS_SLAVE_EBI_CH0,
863 .ab = 54525952,
864 .ib = 436207616,
865 },
866 {
867 .src = MSM_BUS_MASTER_HD_CODEC_PORT1,
868 .dst = MSM_BUS_SLAVE_EBI_CH0,
869 .ab = 72351744,
870 .ib = 289406976,
871 },
872 {
873 .src = MSM_BUS_MASTER_AMPSS_M0,
874 .dst = MSM_BUS_SLAVE_EBI_CH0,
875 .ab = 500000,
876 .ib = 1000000,
877 },
878 {
879 .src = MSM_BUS_MASTER_AMPSS_M0,
880 .dst = MSM_BUS_SLAVE_EBI_CH0,
881 .ab = 500000,
882 .ib = 1000000,
883 },
884};
885static struct msm_bus_vectors vidc_vdec_vga_vectors[] = {
886 {
887 .src = MSM_BUS_MASTER_HD_CODEC_PORT0,
888 .dst = MSM_BUS_SLAVE_EBI_CH0,
889 .ab = 40894464,
890 .ib = 327155712,
891 },
892 {
893 .src = MSM_BUS_MASTER_HD_CODEC_PORT1,
894 .dst = MSM_BUS_SLAVE_EBI_CH0,
895 .ab = 48234496,
896 .ib = 192937984,
897 },
898 {
899 .src = MSM_BUS_MASTER_AMPSS_M0,
900 .dst = MSM_BUS_SLAVE_EBI_CH0,
901 .ab = 500000,
902 .ib = 2000000,
903 },
904 {
905 .src = MSM_BUS_MASTER_AMPSS_M0,
906 .dst = MSM_BUS_SLAVE_EBI_CH0,
907 .ab = 500000,
908 .ib = 2000000,
909 },
910};
911static struct msm_bus_vectors vidc_venc_720p_vectors[] = {
912 {
913 .src = MSM_BUS_MASTER_HD_CODEC_PORT0,
914 .dst = MSM_BUS_SLAVE_EBI_CH0,
915 .ab = 163577856,
916 .ib = 1308622848,
917 },
918 {
919 .src = MSM_BUS_MASTER_HD_CODEC_PORT1,
920 .dst = MSM_BUS_SLAVE_EBI_CH0,
921 .ab = 219152384,
922 .ib = 876609536,
923 },
924 {
925 .src = MSM_BUS_MASTER_AMPSS_M0,
926 .dst = MSM_BUS_SLAVE_EBI_CH0,
927 .ab = 1750000,
928 .ib = 3500000,
929 },
930 {
931 .src = MSM_BUS_MASTER_AMPSS_M0,
932 .dst = MSM_BUS_SLAVE_EBI_CH0,
933 .ab = 1750000,
934 .ib = 3500000,
935 },
936};
937static struct msm_bus_vectors vidc_vdec_720p_vectors[] = {
938 {
939 .src = MSM_BUS_MASTER_HD_CODEC_PORT0,
940 .dst = MSM_BUS_SLAVE_EBI_CH0,
941 .ab = 121634816,
942 .ib = 973078528,
943 },
944 {
945 .src = MSM_BUS_MASTER_HD_CODEC_PORT1,
946 .dst = MSM_BUS_SLAVE_EBI_CH0,
947 .ab = 155189248,
948 .ib = 620756992,
949 },
950 {
951 .src = MSM_BUS_MASTER_AMPSS_M0,
952 .dst = MSM_BUS_SLAVE_EBI_CH0,
953 .ab = 1750000,
954 .ib = 7000000,
955 },
956 {
957 .src = MSM_BUS_MASTER_AMPSS_M0,
958 .dst = MSM_BUS_SLAVE_EBI_CH0,
959 .ab = 1750000,
960 .ib = 7000000,
961 },
962};
963static struct msm_bus_vectors vidc_venc_1080p_vectors[] = {
964 {
965 .src = MSM_BUS_MASTER_HD_CODEC_PORT0,
966 .dst = MSM_BUS_SLAVE_EBI_CH0,
967 .ab = 372244480,
968 .ib = 2560000000U,
969 },
970 {
971 .src = MSM_BUS_MASTER_HD_CODEC_PORT1,
972 .dst = MSM_BUS_SLAVE_EBI_CH0,
973 .ab = 501219328,
974 .ib = 2560000000U,
975 },
976 {
977 .src = MSM_BUS_MASTER_AMPSS_M0,
978 .dst = MSM_BUS_SLAVE_EBI_CH0,
979 .ab = 2500000,
980 .ib = 5000000,
981 },
982 {
983 .src = MSM_BUS_MASTER_AMPSS_M0,
984 .dst = MSM_BUS_SLAVE_EBI_CH0,
985 .ab = 2500000,
986 .ib = 5000000,
987 },
988};
989static struct msm_bus_vectors vidc_vdec_1080p_vectors[] = {
990 {
991 .src = MSM_BUS_MASTER_HD_CODEC_PORT0,
992 .dst = MSM_BUS_SLAVE_EBI_CH0,
993 .ab = 222298112,
994 .ib = 2560000000U,
995 },
996 {
997 .src = MSM_BUS_MASTER_HD_CODEC_PORT1,
998 .dst = MSM_BUS_SLAVE_EBI_CH0,
999 .ab = 330301440,
1000 .ib = 2560000000U,
1001 },
1002 {
1003 .src = MSM_BUS_MASTER_AMPSS_M0,
1004 .dst = MSM_BUS_SLAVE_EBI_CH0,
1005 .ab = 2500000,
1006 .ib = 700000000,
1007 },
1008 {
1009 .src = MSM_BUS_MASTER_AMPSS_M0,
1010 .dst = MSM_BUS_SLAVE_EBI_CH0,
1011 .ab = 2500000,
1012 .ib = 10000000,
1013 },
1014};
Arun Menonb31fefd2012-07-19 14:02:13 -07001015static struct msm_bus_vectors vidc_venc_1080p_turbo_vectors[] = {
1016 {
1017 .src = MSM_BUS_MASTER_HD_CODEC_PORT0,
1018 .dst = MSM_BUS_SLAVE_EBI_CH0,
1019 .ab = 222298112,
1020 .ib = 3522000000U,
1021 },
1022 {
1023 .src = MSM_BUS_MASTER_HD_CODEC_PORT1,
1024 .dst = MSM_BUS_SLAVE_EBI_CH0,
1025 .ab = 330301440,
1026 .ib = 3522000000U,
1027 },
1028 {
1029 .src = MSM_BUS_MASTER_AMPSS_M0,
1030 .dst = MSM_BUS_SLAVE_EBI_CH0,
1031 .ab = 2500000,
1032 .ib = 700000000,
1033 },
1034 {
1035 .src = MSM_BUS_MASTER_AMPSS_M0,
1036 .dst = MSM_BUS_SLAVE_EBI_CH0,
1037 .ab = 2500000,
1038 .ib = 10000000,
1039 },
1040};
1041static struct msm_bus_vectors vidc_vdec_1080p_turbo_vectors[] = {
1042 {
1043 .src = MSM_BUS_MASTER_HD_CODEC_PORT0,
1044 .dst = MSM_BUS_SLAVE_EBI_CH0,
1045 .ab = 222298112,
1046 .ib = 3522000000U,
1047 },
1048 {
1049 .src = MSM_BUS_MASTER_HD_CODEC_PORT1,
1050 .dst = MSM_BUS_SLAVE_EBI_CH0,
1051 .ab = 330301440,
1052 .ib = 3522000000U,
1053 },
1054 {
1055 .src = MSM_BUS_MASTER_AMPSS_M0,
1056 .dst = MSM_BUS_SLAVE_EBI_CH0,
1057 .ab = 2500000,
1058 .ib = 700000000,
1059 },
1060 {
1061 .src = MSM_BUS_MASTER_AMPSS_M0,
1062 .dst = MSM_BUS_SLAVE_EBI_CH0,
1063 .ab = 2500000,
1064 .ib = 10000000,
1065 },
1066};
Arun Menonaabf2632012-02-24 15:30:47 -08001067
1068static struct msm_bus_paths vidc_bus_client_config[] = {
1069 {
1070 ARRAY_SIZE(vidc_init_vectors),
1071 vidc_init_vectors,
1072 },
1073 {
1074 ARRAY_SIZE(vidc_venc_vga_vectors),
1075 vidc_venc_vga_vectors,
1076 },
1077 {
1078 ARRAY_SIZE(vidc_vdec_vga_vectors),
1079 vidc_vdec_vga_vectors,
1080 },
1081 {
1082 ARRAY_SIZE(vidc_venc_720p_vectors),
1083 vidc_venc_720p_vectors,
1084 },
1085 {
1086 ARRAY_SIZE(vidc_vdec_720p_vectors),
1087 vidc_vdec_720p_vectors,
1088 },
1089 {
1090 ARRAY_SIZE(vidc_venc_1080p_vectors),
1091 vidc_venc_1080p_vectors,
1092 },
1093 {
1094 ARRAY_SIZE(vidc_vdec_1080p_vectors),
1095 vidc_vdec_1080p_vectors,
1096 },
Arun Menonb31fefd2012-07-19 14:02:13 -07001097 {
1098 ARRAY_SIZE(vidc_venc_1080p_turbo_vectors),
1099 vidc_vdec_1080p_turbo_vectors,
1100 },
1101 {
1102 ARRAY_SIZE(vidc_vdec_1080p_turbo_vectors),
1103 vidc_vdec_1080p_turbo_vectors,
1104 },
Arun Menonaabf2632012-02-24 15:30:47 -08001105};
1106
1107static struct msm_bus_scale_pdata vidc_bus_client_data = {
1108 vidc_bus_client_config,
1109 ARRAY_SIZE(vidc_bus_client_config),
1110 .name = "vidc",
1111};
1112#endif
1113
1114#define MSM_VIDC_BASE_PHYS 0x04400000
1115#define MSM_VIDC_BASE_SIZE 0x00100000
1116
1117static struct resource apq8930_device_vidc_resources[] = {
1118 {
1119 .start = MSM_VIDC_BASE_PHYS,
1120 .end = MSM_VIDC_BASE_PHYS + MSM_VIDC_BASE_SIZE - 1,
1121 .flags = IORESOURCE_MEM,
1122 },
1123 {
1124 .start = VCODEC_IRQ,
1125 .end = VCODEC_IRQ,
1126 .flags = IORESOURCE_IRQ,
1127 },
1128};
1129
1130struct msm_vidc_platform_data apq8930_vidc_platform_data = {
1131#ifdef CONFIG_MSM_BUS_SCALING
1132 .vidc_bus_client_pdata = &vidc_bus_client_data,
1133#endif
1134#ifdef CONFIG_MSM_MULTIMEDIA_USE_ION
1135 .memtype = ION_CP_MM_HEAP_ID,
1136 .enable_ion = 1,
Deepak Kotur8097f782012-05-14 14:13:06 -07001137 .cp_enabled = 1,
Arun Menonaabf2632012-02-24 15:30:47 -08001138#else
1139 .memtype = MEMTYPE_EBI1,
1140 .enable_ion = 0,
1141#endif
Anil Gahlotd0ce26d2012-05-08 17:58:46 -07001142 .disable_dmx = 1,
Arun Menonaabf2632012-02-24 15:30:47 -08001143 .disable_fullhd = 0,
Mohan Kumar Gubbihalli Lachma Naik885fcc52012-10-26 17:55:27 -07001144 .cont_mode_dpb_count = 18,
Riaz Rahaman84f8c682012-05-30 13:32:10 +05301145 .fw_addr = 0x9fe00000,
Arun Menonaabf2632012-02-24 15:30:47 -08001146};
1147
1148struct platform_device apq8930_msm_device_vidc = {
1149 .name = "msm_vidc",
1150 .id = 0,
1151 .num_resources = ARRAY_SIZE(apq8930_device_vidc_resources),
1152 .resource = apq8930_device_vidc_resources,
1153 .dev = {
1154 .platform_data = &apq8930_vidc_platform_data,
1155 },
1156};
1157
1158struct platform_device *vidc_device[] __initdata = {
1159 &apq8930_msm_device_vidc
1160};
1161
1162void __init msm8930_add_vidc_device(void)
1163{
1164 if (cpu_is_msm8627()) {
1165 struct msm_vidc_platform_data *pdata;
1166 pdata = (struct msm_vidc_platform_data *)
1167 apq8930_msm_device_vidc.dev.platform_data;
1168 pdata->disable_fullhd = 1;
1169 }
1170 platform_add_devices(vidc_device, ARRAY_SIZE(vidc_device));
1171}
Laura Abbott0577d7b2012-04-17 11:14:30 -07001172
1173struct msm_iommu_domain_name msm8930_iommu_ctx_names[] = {
1174 /* Camera */
1175 {
Laura Abbott0577d7b2012-04-17 11:14:30 -07001176 .name = "ijpeg_src",
1177 .domain = CAMERA_DOMAIN,
1178 },
1179 /* Camera */
1180 {
1181 .name = "ijpeg_dst",
1182 .domain = CAMERA_DOMAIN,
1183 },
1184 /* Camera */
1185 {
1186 .name = "jpegd_src",
1187 .domain = CAMERA_DOMAIN,
1188 },
1189 /* Camera */
1190 {
1191 .name = "jpegd_dst",
1192 .domain = CAMERA_DOMAIN,
1193 },
1194 /* Rotator */
1195 {
1196 .name = "rot_src",
Olav Hauganef95ae32012-05-15 09:50:30 -07001197 .domain = ROTATOR_SRC_DOMAIN,
Laura Abbott0577d7b2012-04-17 11:14:30 -07001198 },
1199 /* Rotator */
1200 {
1201 .name = "rot_dst",
Olav Hauganef95ae32012-05-15 09:50:30 -07001202 .domain = ROTATOR_SRC_DOMAIN,
Laura Abbott0577d7b2012-04-17 11:14:30 -07001203 },
1204 /* Video */
1205 {
1206 .name = "vcodec_a_mm1",
1207 .domain = VIDEO_DOMAIN,
1208 },
1209 /* Video */
1210 {
1211 .name = "vcodec_b_mm2",
1212 .domain = VIDEO_DOMAIN,
1213 },
1214 /* Video */
1215 {
1216 .name = "vcodec_a_stream",
1217 .domain = VIDEO_DOMAIN,
1218 },
1219};
1220
1221static struct mem_pool msm8930_video_pools[] = {
1222 /*
1223 * Video hardware has the following requirements:
1224 * 1. All video addresses used by the video hardware must be at a higher
1225 * address than video firmware address.
1226 * 2. Video hardware can only access a range of 256MB from the base of
1227 * the video firmware.
1228 */
1229 [VIDEO_FIRMWARE_POOL] =
1230 /* Low addresses, intended for video firmware */
1231 {
1232 .paddr = SZ_128K,
1233 .size = SZ_16M - SZ_128K,
1234 },
1235 [VIDEO_MAIN_POOL] =
1236 /* Main video pool */
1237 {
1238 .paddr = SZ_16M,
1239 .size = SZ_256M - SZ_16M,
1240 },
1241 [GEN_POOL] =
1242 /* Remaining address space up to 2G */
1243 {
1244 .paddr = SZ_256M,
1245 .size = SZ_2G - SZ_256M,
1246 },
1247};
1248
1249static struct mem_pool msm8930_camera_pools[] = {
1250 [GEN_POOL] =
1251 /* One address space for camera */
1252 {
1253 .paddr = SZ_128K,
1254 .size = SZ_2G - SZ_128K,
1255 },
1256};
1257
Olav Hauganef95ae32012-05-15 09:50:30 -07001258static struct mem_pool msm8930_display_read_pools[] = {
Laura Abbott0577d7b2012-04-17 11:14:30 -07001259 [GEN_POOL] =
Olav Hauganef95ae32012-05-15 09:50:30 -07001260 /* One address space for display reads */
Laura Abbott0577d7b2012-04-17 11:14:30 -07001261 {
1262 .paddr = SZ_128K,
1263 .size = SZ_2G - SZ_128K,
1264 },
1265};
1266
Olav Hauganef95ae32012-05-15 09:50:30 -07001267static struct mem_pool msm8930_rotator_src_pools[] = {
Laura Abbott0577d7b2012-04-17 11:14:30 -07001268 [GEN_POOL] =
Olav Hauganef95ae32012-05-15 09:50:30 -07001269 /* One address space for rotator src */
Laura Abbott0577d7b2012-04-17 11:14:30 -07001270 {
1271 .paddr = SZ_128K,
1272 .size = SZ_2G - SZ_128K,
1273 },
1274};
1275
1276static struct msm_iommu_domain msm8930_iommu_domains[] = {
1277 [VIDEO_DOMAIN] = {
1278 .iova_pools = msm8930_video_pools,
1279 .npools = ARRAY_SIZE(msm8930_video_pools),
1280 },
1281 [CAMERA_DOMAIN] = {
1282 .iova_pools = msm8930_camera_pools,
1283 .npools = ARRAY_SIZE(msm8930_camera_pools),
1284 },
Olav Hauganef95ae32012-05-15 09:50:30 -07001285 [DISPLAY_READ_DOMAIN] = {
1286 .iova_pools = msm8930_display_read_pools,
1287 .npools = ARRAY_SIZE(msm8930_display_read_pools),
Laura Abbott0577d7b2012-04-17 11:14:30 -07001288 },
Olav Hauganef95ae32012-05-15 09:50:30 -07001289 [ROTATOR_SRC_DOMAIN] = {
1290 .iova_pools = msm8930_rotator_src_pools,
1291 .npools = ARRAY_SIZE(msm8930_rotator_src_pools),
Laura Abbott0577d7b2012-04-17 11:14:30 -07001292 },
1293};
1294
1295struct iommu_domains_pdata msm8930_iommu_domain_pdata = {
1296 .domains = msm8930_iommu_domains,
1297 .ndomains = ARRAY_SIZE(msm8930_iommu_domains),
1298 .domain_names = msm8930_iommu_ctx_names,
1299 .nnames = ARRAY_SIZE(msm8930_iommu_ctx_names),
1300 .domain_alloc_flags = 0,
1301};
1302
1303struct platform_device msm8930_iommu_domain_device = {
1304 .name = "iommu_domains",
1305 .id = -1,
1306 .dev = {
1307 .platform_data = &msm8930_iommu_domain_pdata,
Laura Abbott532b2df2012-04-12 10:53:48 -07001308 }
1309};
1310
1311struct msm_rtb_platform_data msm8930_rtb_pdata = {
1312 .size = SZ_1M,
1313};
1314
1315static int __init msm_rtb_set_buffer_size(char *p)
1316{
1317 int s;
1318
1319 s = memparse(p, NULL);
1320 msm8930_rtb_pdata.size = ALIGN(s, SZ_4K);
1321 return 0;
1322}
1323early_param("msm_rtb_size", msm_rtb_set_buffer_size);
1324
1325
1326struct platform_device msm8930_rtb_device = {
1327 .name = "msm_rtb",
1328 .id = -1,
1329 .dev = {
1330 .platform_data = &msm8930_rtb_pdata,
Laura Abbott0577d7b2012-04-17 11:14:30 -07001331 },
1332};
Laura Abbottf3173042012-05-29 15:23:18 -07001333
1334#define MSM8930_L1_SIZE SZ_1M
1335/*
1336 * The actual L2 size is smaller but we need a larger buffer
1337 * size to store other dump information
1338 */
1339#define MSM8930_L2_SIZE SZ_4M
1340
1341struct msm_cache_dump_platform_data msm8930_cache_dump_pdata = {
1342 .l2_size = MSM8930_L2_SIZE,
1343 .l1_size = MSM8930_L1_SIZE,
1344};
1345
1346struct platform_device msm8930_cache_dump_device = {
1347 .name = "msm_cache_dump",
1348 .id = -1,
1349 .dev = {
1350 .platform_data = &msm8930_cache_dump_pdata,
1351 },
1352};