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gerrit-public.fairphone.software / kernel / msm / 50d5c60634673a79f8d88564e10345b50fca7378 / . / drivers / scsi / mpt2sas / mpi / mpi2_cnfg.h
blob: 1611c57a6fdff2a64b868d1fcede2f958b1018d5 [file] [log] [blame]
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]1/*
2 * Copyright (c) 2000-2009 LSI Corporation.
3 *
4 *
5 * Name: mpi2_cnfg.h
6 * Title: MPI Configuration messages and pages
7 * Creation Date: November 10, 2006
8 *
Kashyap, Desai9fec5f92009-09-23 17:26:20 +0530[diff] [blame]9 * mpi2_cnfg.h Version: 02.00.12
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]10 *
11 * Version History
12 * ---------------
13 *
14 * Date Version Description
15 * -------- -------- ------------------------------------------------------
16 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A.
17 * 06-04-07 02.00.01 Added defines for SAS IO Unit Page 2 PhyFlags.
18 * Added Manufacturing Page 11.
19 * Added MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE
20 * define.
21 * 06-26-07 02.00.02 Adding generic structure for product-specific
22 * Manufacturing pages: MPI2_CONFIG_PAGE_MANUFACTURING_PS.
23 * Rework of BIOS Page 2 configuration page.
24 * Fixed MPI2_BIOSPAGE2_BOOT_DEVICE to be a union of the
25 * forms.
26 * Added configuration pages IOC Page 8 and Driver
27 * Persistent Mapping Page 0.
28 * 08-31-07 02.00.03 Modified configuration pages dealing with Integrated
29 * RAID (Manufacturing Page 4, RAID Volume Pages 0 and 1,
30 * RAID Physical Disk Pages 0 and 1, RAID Configuration
31 * Page 0).
32 * Added new value for AccessStatus field of SAS Device
33 * Page 0 (_SATA_NEEDS_INITIALIZATION).
34 * 10-31-07 02.00.04 Added missing SEPDevHandle field to
35 * MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0.
36 * 12-18-07 02.00.05 Modified IO Unit Page 0 to use 32-bit version fields for
37 * NVDATA.
38 * Modified IOC Page 7 to use masks and added field for
39 * SASBroadcastPrimitiveMasks.
40 * Added MPI2_CONFIG_PAGE_BIOS_4.
41 * Added MPI2_CONFIG_PAGE_LOG_0.
42 * 02-29-08 02.00.06 Modified various names to make them 32-character unique.
43 * Added SAS Device IDs.
44 * Updated Integrated RAID configuration pages including
45 * Manufacturing Page 4, IOC Page 6, and RAID Configuration
46 * Page 0.
47 * 05-21-08 02.00.07 Added define MPI2_MANPAGE4_MIX_SSD_SAS_SATA.
48 * Added define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION.
49 * Fixed define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING.
50 * Added missing MaxNumRoutedSasAddresses field to
51 * MPI2_CONFIG_PAGE_EXPANDER_0.
52 * Added SAS Port Page 0.
53 * Modified structure layout for
54 * MPI2_CONFIG_PAGE_DRIVER_MAPPING_0.
55 * 06-27-08 02.00.08 Changed MPI2_CONFIG_PAGE_RD_PDISK_1 to use
56 * MPI2_RAID_PHYS_DISK1_PATH_MAX to size the array.
57 * 10-02-08 02.00.09 Changed MPI2_RAID_PGAD_CONFIGNUM_MASK from 0x0000FFFF
58 * to 0x000000FF.
59 * Added two new values for the Physical Disk Coercion Size
60 * bits in the Flags field of Manufacturing Page 4.
61 * Added product-specific Manufacturing pages 16 to 31.
62 * Modified Flags bits for controlling write cache on SATA
63 * drives in IO Unit Page 1.
64 * Added new bit to AdditionalControlFlags of SAS IO Unit
65 * Page 1 to control Invalid Topology Correction.
66 * Added additional defines for RAID Volume Page 0
67 * VolumeStatusFlags field.
68 * Modified meaning of RAID Volume Page 0 VolumeSettings
69 * define for auto-configure of hot-swap drives.
70 * Added SupportedPhysDisks field to RAID Volume Page 1 and
71 * added related defines.
72 * Added PhysDiskAttributes field (and related defines) to
73 * RAID Physical Disk Page 0.
74 * Added MPI2_SAS_PHYINFO_PHY_VACANT define.
75 * Added three new DiscoveryStatus bits for SAS IO Unit
76 * Page 0 and SAS Expander Page 0.
77 * Removed multiplexing information from SAS IO Unit pages.
78 * Added BootDeviceWaitTime field to SAS IO Unit Page 4.
79 * Removed Zone Address Resolved bit from PhyInfo and from
80 * Expander Page 0 Flags field.
81 * Added two new AccessStatus values to SAS Device Page 0
82 * for indicating routing problems. Added 3 reserved words
83 * to this page.
84 * 01-19-09 02.00.10 Fixed defines for GPIOVal field of IO Unit Page 3.
85 * Inserted missing reserved field into structure for IOC
86 * Page 6.
87 * Added more pending task bits to RAID Volume Page 0
88 * VolumeStatusFlags defines.
89 * Added MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED define.
90 * Added a new DiscoveryStatus bit for SAS IO Unit Page 0
91 * and SAS Expander Page 0 to flag a downstream initiator
92 * when in simplified routing mode.
93 * Removed SATA Init Failure defines for DiscoveryStatus
94 * fields of SAS IO Unit Page 0 and SAS Expander Page 0.
95 * Added MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED define.
96 * Added PortGroups, DmaGroup, and ControlGroup fields to
97 * SAS Device Page 0.
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]98 * 05-06-09 02.00.11 Added structures and defines for IO Unit Page 5 and IO
99 * Unit Page 6.
100 * Added expander reduced functionality data to SAS
101 * Expander Page 0.
102 * Added SAS PHY Page 2 and SAS PHY Page 3.
Kashyap, Desai9fec5f92009-09-23 17:26:20 +0530[diff] [blame]103 * 07-30-09 02.00.12 Added IO Unit Page 7.
104 * Added new device ids.
105 * Added SAS IO Unit Page 5.
106 * Added partial and slumber power management capable flags
107 * to SAS Device Page 0 Flags field.
108 * Added PhyInfo defines for power condition.
109 * Added Ethernet configuration pages.
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]110 * --------------------------------------------------------------------------
111 */
112
113#ifndef MPI2_CNFG_H
114#define MPI2_CNFG_H
115
116/*****************************************************************************
117* Configuration Page Header and defines
118*****************************************************************************/
119
120/* Config Page Header */
121typedef struct _MPI2_CONFIG_PAGE_HEADER
122{
123 U8 PageVersion; /* 0x00 */
124 U8 PageLength; /* 0x01 */
125 U8 PageNumber; /* 0x02 */
126 U8 PageType; /* 0x03 */
127} MPI2_CONFIG_PAGE_HEADER, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_HEADER,
128 Mpi2ConfigPageHeader_t, MPI2_POINTER pMpi2ConfigPageHeader_t;
129
130typedef union _MPI2_CONFIG_PAGE_HEADER_UNION
131{
132 MPI2_CONFIG_PAGE_HEADER Struct;
133 U8 Bytes[4];
134 U16 Word16[2];
135 U32 Word32;
136} MPI2_CONFIG_PAGE_HEADER_UNION, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_HEADER_UNION,
137 Mpi2ConfigPageHeaderUnion, MPI2_POINTER pMpi2ConfigPageHeaderUnion;
138
139/* Extended Config Page Header */
140typedef struct _MPI2_CONFIG_EXTENDED_PAGE_HEADER
141{
142 U8 PageVersion; /* 0x00 */
143 U8 Reserved1; /* 0x01 */
144 U8 PageNumber; /* 0x02 */
145 U8 PageType; /* 0x03 */
146 U16 ExtPageLength; /* 0x04 */
147 U8 ExtPageType; /* 0x06 */
148 U8 Reserved2; /* 0x07 */
149} MPI2_CONFIG_EXTENDED_PAGE_HEADER,
150 MPI2_POINTER PTR_MPI2_CONFIG_EXTENDED_PAGE_HEADER,
151 Mpi2ConfigExtendedPageHeader_t, MPI2_POINTER pMpi2ConfigExtendedPageHeader_t;
152
153typedef union _MPI2_CONFIG_EXT_PAGE_HEADER_UNION
154{
155 MPI2_CONFIG_PAGE_HEADER Struct;
156 MPI2_CONFIG_EXTENDED_PAGE_HEADER Ext;
157 U8 Bytes[8];
158 U16 Word16[4];
159 U32 Word32[2];
160} MPI2_CONFIG_EXT_PAGE_HEADER_UNION, MPI2_POINTER PTR_MPI2_CONFIG_EXT_PAGE_HEADER_UNION,
161 Mpi2ConfigPageExtendedHeaderUnion, MPI2_POINTER pMpi2ConfigPageExtendedHeaderUnion;
162
163
164/* PageType field values */
165#define MPI2_CONFIG_PAGEATTR_READ_ONLY (0x00)
166#define MPI2_CONFIG_PAGEATTR_CHANGEABLE (0x10)
167#define MPI2_CONFIG_PAGEATTR_PERSISTENT (0x20)
168#define MPI2_CONFIG_PAGEATTR_MASK (0xF0)
169
170#define MPI2_CONFIG_PAGETYPE_IO_UNIT (0x00)
171#define MPI2_CONFIG_PAGETYPE_IOC (0x01)
172#define MPI2_CONFIG_PAGETYPE_BIOS (0x02)
173#define MPI2_CONFIG_PAGETYPE_RAID_VOLUME (0x08)
174#define MPI2_CONFIG_PAGETYPE_MANUFACTURING (0x09)
175#define MPI2_CONFIG_PAGETYPE_RAID_PHYSDISK (0x0A)
176#define MPI2_CONFIG_PAGETYPE_EXTENDED (0x0F)
177#define MPI2_CONFIG_PAGETYPE_MASK (0x0F)
178
179#define MPI2_CONFIG_TYPENUM_MASK (0x0FFF)
180
181
182/* ExtPageType field values */
183#define MPI2_CONFIG_EXTPAGETYPE_SAS_IO_UNIT (0x10)
184#define MPI2_CONFIG_EXTPAGETYPE_SAS_EXPANDER (0x11)
185#define MPI2_CONFIG_EXTPAGETYPE_SAS_DEVICE (0x12)
186#define MPI2_CONFIG_EXTPAGETYPE_SAS_PHY (0x13)
187#define MPI2_CONFIG_EXTPAGETYPE_LOG (0x14)
188#define MPI2_CONFIG_EXTPAGETYPE_ENCLOSURE (0x15)
189#define MPI2_CONFIG_EXTPAGETYPE_RAID_CONFIG (0x16)
190#define MPI2_CONFIG_EXTPAGETYPE_DRIVER_MAPPING (0x17)
191#define MPI2_CONFIG_EXTPAGETYPE_SAS_PORT (0x18)
Kashyap, Desai9fec5f92009-09-23 17:26:20 +0530[diff] [blame]192#define MPI2_CONFIG_EXTPAGETYPE_ETHERNET (0x19)
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]193
194
195/*****************************************************************************
196* PageAddress defines
197*****************************************************************************/
198
199/* RAID Volume PageAddress format */
200#define MPI2_RAID_VOLUME_PGAD_FORM_MASK (0xF0000000)
201#define MPI2_RAID_VOLUME_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
202#define MPI2_RAID_VOLUME_PGAD_FORM_HANDLE (0x10000000)
203
204#define MPI2_RAID_VOLUME_PGAD_HANDLE_MASK (0x0000FFFF)
205
206
207/* RAID Physical Disk PageAddress format */
208#define MPI2_PHYSDISK_PGAD_FORM_MASK (0xF0000000)
209#define MPI2_PHYSDISK_PGAD_FORM_GET_NEXT_PHYSDISKNUM (0x00000000)
210#define MPI2_PHYSDISK_PGAD_FORM_PHYSDISKNUM (0x10000000)
211#define MPI2_PHYSDISK_PGAD_FORM_DEVHANDLE (0x20000000)
212
213#define MPI2_PHYSDISK_PGAD_PHYSDISKNUM_MASK (0x000000FF)
214#define MPI2_PHYSDISK_PGAD_DEVHANDLE_MASK (0x0000FFFF)
215
216
217/* SAS Expander PageAddress format */
218#define MPI2_SAS_EXPAND_PGAD_FORM_MASK (0xF0000000)
219#define MPI2_SAS_EXPAND_PGAD_FORM_GET_NEXT_HNDL (0x00000000)
220#define MPI2_SAS_EXPAND_PGAD_FORM_HNDL_PHY_NUM (0x10000000)
221#define MPI2_SAS_EXPAND_PGAD_FORM_HNDL (0x20000000)
222
223#define MPI2_SAS_EXPAND_PGAD_HANDLE_MASK (0x0000FFFF)
224#define MPI2_SAS_EXPAND_PGAD_PHYNUM_MASK (0x00FF0000)
225#define MPI2_SAS_EXPAND_PGAD_PHYNUM_SHIFT (16)
226
227
228/* SAS Device PageAddress format */
229#define MPI2_SAS_DEVICE_PGAD_FORM_MASK (0xF0000000)
230#define MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
231#define MPI2_SAS_DEVICE_PGAD_FORM_HANDLE (0x20000000)
232
233#define MPI2_SAS_DEVICE_PGAD_HANDLE_MASK (0x0000FFFF)
234
235
236/* SAS PHY PageAddress format */
237#define MPI2_SAS_PHY_PGAD_FORM_MASK (0xF0000000)
238#define MPI2_SAS_PHY_PGAD_FORM_PHY_NUMBER (0x00000000)
239#define MPI2_SAS_PHY_PGAD_FORM_PHY_TBL_INDEX (0x10000000)
240
241#define MPI2_SAS_PHY_PGAD_PHY_NUMBER_MASK (0x000000FF)
242#define MPI2_SAS_PHY_PGAD_PHY_TBL_INDEX_MASK (0x0000FFFF)
243
244
245/* SAS Port PageAddress format */
246#define MPI2_SASPORT_PGAD_FORM_MASK (0xF0000000)
247#define MPI2_SASPORT_PGAD_FORM_GET_NEXT_PORT (0x00000000)
248#define MPI2_SASPORT_PGAD_FORM_PORT_NUM (0x10000000)
249
250#define MPI2_SASPORT_PGAD_PORTNUMBER_MASK (0x00000FFF)
251
252
253/* SAS Enclosure PageAddress format */
254#define MPI2_SAS_ENCLOS_PGAD_FORM_MASK (0xF0000000)
255#define MPI2_SAS_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
256#define MPI2_SAS_ENCLOS_PGAD_FORM_HANDLE (0x10000000)
257
258#define MPI2_SAS_ENCLOS_PGAD_HANDLE_MASK (0x0000FFFF)
259
260
261/* RAID Configuration PageAddress format */
262#define MPI2_RAID_PGAD_FORM_MASK (0xF0000000)
263#define MPI2_RAID_PGAD_FORM_GET_NEXT_CONFIGNUM (0x00000000)
264#define MPI2_RAID_PGAD_FORM_CONFIGNUM (0x10000000)
265#define MPI2_RAID_PGAD_FORM_ACTIVE_CONFIG (0x20000000)
266
267#define MPI2_RAID_PGAD_CONFIGNUM_MASK (0x000000FF)
268
269
270/* Driver Persistent Mapping PageAddress format */
271#define MPI2_DPM_PGAD_FORM_MASK (0xF0000000)
272#define MPI2_DPM_PGAD_FORM_ENTRY_RANGE (0x00000000)
273
274#define MPI2_DPM_PGAD_ENTRY_COUNT_MASK (0x0FFF0000)
275#define MPI2_DPM_PGAD_ENTRY_COUNT_SHIFT (16)
276#define MPI2_DPM_PGAD_START_ENTRY_MASK (0x0000FFFF)
277
278
Kashyap, Desai9fec5f92009-09-23 17:26:20 +0530[diff] [blame]279/* Ethernet PageAddress format */
280#define MPI2_ETHERNET_PGAD_FORM_MASK (0xF0000000)
281#define MPI2_ETHERNET_PGAD_FORM_IF_NUM (0x00000000)
282
283#define MPI2_ETHERNET_PGAD_IF_NUMBER_MASK (0x000000FF)
284
285
286
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]287/****************************************************************************
288* Configuration messages
289****************************************************************************/
290
291/* Configuration Request Message */
292typedef struct _MPI2_CONFIG_REQUEST
293{
294 U8 Action; /* 0x00 */
295 U8 SGLFlags; /* 0x01 */
296 U8 ChainOffset; /* 0x02 */
297 U8 Function; /* 0x03 */
298 U16 ExtPageLength; /* 0x04 */
299 U8 ExtPageType; /* 0x06 */
300 U8 MsgFlags; /* 0x07 */
301 U8 VP_ID; /* 0x08 */
302 U8 VF_ID; /* 0x09 */
303 U16 Reserved1; /* 0x0A */
304 U32 Reserved2; /* 0x0C */
305 U32 Reserved3; /* 0x10 */
306 MPI2_CONFIG_PAGE_HEADER Header; /* 0x14 */
307 U32 PageAddress; /* 0x18 */
308 MPI2_SGE_IO_UNION PageBufferSGE; /* 0x1C */
309} MPI2_CONFIG_REQUEST, MPI2_POINTER PTR_MPI2_CONFIG_REQUEST,
310 Mpi2ConfigRequest_t, MPI2_POINTER pMpi2ConfigRequest_t;
311
312/* values for the Action field */
313#define MPI2_CONFIG_ACTION_PAGE_HEADER (0x00)
314#define MPI2_CONFIG_ACTION_PAGE_READ_CURRENT (0x01)
315#define MPI2_CONFIG_ACTION_PAGE_WRITE_CURRENT (0x02)
316#define MPI2_CONFIG_ACTION_PAGE_DEFAULT (0x03)
317#define MPI2_CONFIG_ACTION_PAGE_WRITE_NVRAM (0x04)
318#define MPI2_CONFIG_ACTION_PAGE_READ_DEFAULT (0x05)
319#define MPI2_CONFIG_ACTION_PAGE_READ_NVRAM (0x06)
320#define MPI2_CONFIG_ACTION_PAGE_GET_CHANGEABLE (0x07)
321
322/* values for SGLFlags field are in the SGL section of mpi2.h */
323
324
325/* Config Reply Message */
326typedef struct _MPI2_CONFIG_REPLY
327{
328 U8 Action; /* 0x00 */
329 U8 SGLFlags; /* 0x01 */
330 U8 MsgLength; /* 0x02 */
331 U8 Function; /* 0x03 */
332 U16 ExtPageLength; /* 0x04 */
333 U8 ExtPageType; /* 0x06 */
334 U8 MsgFlags; /* 0x07 */
335 U8 VP_ID; /* 0x08 */
336 U8 VF_ID; /* 0x09 */
337 U16 Reserved1; /* 0x0A */
338 U16 Reserved2; /* 0x0C */
339 U16 IOCStatus; /* 0x0E */
340 U32 IOCLogInfo; /* 0x10 */
341 MPI2_CONFIG_PAGE_HEADER Header; /* 0x14 */
342} MPI2_CONFIG_REPLY, MPI2_POINTER PTR_MPI2_CONFIG_REPLY,
343 Mpi2ConfigReply_t, MPI2_POINTER pMpi2ConfigReply_t;
344
345
346
347/*****************************************************************************
348*
349* C o n f i g u r a t i o n P a g e s
350*
351*****************************************************************************/
352
353/****************************************************************************
354* Manufacturing Config pages
355****************************************************************************/
356
357#define MPI2_MFGPAGE_VENDORID_LSI (0x1000)
358
359/* SAS */
360#define MPI2_MFGPAGE_DEVID_SAS2004 (0x0070)
361#define MPI2_MFGPAGE_DEVID_SAS2008 (0x0072)
362#define MPI2_MFGPAGE_DEVID_SAS2108_1 (0x0074)
363#define MPI2_MFGPAGE_DEVID_SAS2108_2 (0x0076)
364#define MPI2_MFGPAGE_DEVID_SAS2108_3 (0x0077)
365#define MPI2_MFGPAGE_DEVID_SAS2116_1 (0x0064)
366#define MPI2_MFGPAGE_DEVID_SAS2116_2 (0x0065)
Kashyap, Desai9fec5f92009-09-23 17:26:20 +0530[diff] [blame]367
Kashyap, Desaidb271362009-09-23 17:24:27 +0530[diff] [blame]368#define MPI2_MFGPAGE_DEVID_SAS2208_1 (0x0080)
369#define MPI2_MFGPAGE_DEVID_SAS2208_2 (0x0081)
370#define MPI2_MFGPAGE_DEVID_SAS2208_3 (0x0082)
371#define MPI2_MFGPAGE_DEVID_SAS2208_4 (0x0083)
372#define MPI2_MFGPAGE_DEVID_SAS2208_5 (0x0084)
373#define MPI2_MFGPAGE_DEVID_SAS2208_6 (0x0085)
374#define MPI2_MFGPAGE_DEVID_SAS2208_7 (0x0086)
375#define MPI2_MFGPAGE_DEVID_SAS2208_8 (0x0087)
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]376
377
378/* Manufacturing Page 0 */
379
380typedef struct _MPI2_CONFIG_PAGE_MAN_0
381{
382 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
383 U8 ChipName[16]; /* 0x04 */
384 U8 ChipRevision[8]; /* 0x14 */
385 U8 BoardName[16]; /* 0x1C */
386 U8 BoardAssembly[16]; /* 0x2C */
387 U8 BoardTracerNumber[16]; /* 0x3C */
388} MPI2_CONFIG_PAGE_MAN_0,
389 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_0,
390 Mpi2ManufacturingPage0_t, MPI2_POINTER pMpi2ManufacturingPage0_t;
391
392#define MPI2_MANUFACTURING0_PAGEVERSION (0x00)
393
394
395/* Manufacturing Page 1 */
396
397typedef struct _MPI2_CONFIG_PAGE_MAN_1
398{
399 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
400 U8 VPD[256]; /* 0x04 */
401} MPI2_CONFIG_PAGE_MAN_1,
402 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_1,
403 Mpi2ManufacturingPage1_t, MPI2_POINTER pMpi2ManufacturingPage1_t;
404
405#define MPI2_MANUFACTURING1_PAGEVERSION (0x00)
406
407
408typedef struct _MPI2_CHIP_REVISION_ID
409{
410 U16 DeviceID; /* 0x00 */
411 U8 PCIRevisionID; /* 0x02 */
412 U8 Reserved; /* 0x03 */
413} MPI2_CHIP_REVISION_ID, MPI2_POINTER PTR_MPI2_CHIP_REVISION_ID,
414 Mpi2ChipRevisionId_t, MPI2_POINTER pMpi2ChipRevisionId_t;
415
416
417/* Manufacturing Page 2 */
418
419/*
420 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
421 * one and check Header.PageLength at runtime.
422 */
423#ifndef MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS
424#define MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS (1)
425#endif
426
427typedef struct _MPI2_CONFIG_PAGE_MAN_2
428{
429 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
430 MPI2_CHIP_REVISION_ID ChipId; /* 0x04 */
431 U32 HwSettings[MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS];/* 0x08 */
432} MPI2_CONFIG_PAGE_MAN_2,
433 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_2,
434 Mpi2ManufacturingPage2_t, MPI2_POINTER pMpi2ManufacturingPage2_t;
435
436#define MPI2_MANUFACTURING2_PAGEVERSION (0x00)
437
438
439/* Manufacturing Page 3 */
440
441/*
442 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
443 * one and check Header.PageLength at runtime.
444 */
445#ifndef MPI2_MAN_PAGE_3_INFO_WORDS
446#define MPI2_MAN_PAGE_3_INFO_WORDS (1)
447#endif
448
449typedef struct _MPI2_CONFIG_PAGE_MAN_3
450{
451 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
452 MPI2_CHIP_REVISION_ID ChipId; /* 0x04 */
453 U32 Info[MPI2_MAN_PAGE_3_INFO_WORDS];/* 0x08 */
454} MPI2_CONFIG_PAGE_MAN_3,
455 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_3,
456 Mpi2ManufacturingPage3_t, MPI2_POINTER pMpi2ManufacturingPage3_t;
457
458#define MPI2_MANUFACTURING3_PAGEVERSION (0x00)
459
460
461/* Manufacturing Page 4 */
462
463typedef struct _MPI2_MANPAGE4_PWR_SAVE_SETTINGS
464{
465 U8 PowerSaveFlags; /* 0x00 */
466 U8 InternalOperationsSleepTime; /* 0x01 */
467 U8 InternalOperationsRunTime; /* 0x02 */
468 U8 HostIdleTime; /* 0x03 */
469} MPI2_MANPAGE4_PWR_SAVE_SETTINGS,
470 MPI2_POINTER PTR_MPI2_MANPAGE4_PWR_SAVE_SETTINGS,
471 Mpi2ManPage4PwrSaveSettings_t, MPI2_POINTER pMpi2ManPage4PwrSaveSettings_t;
472
473/* defines for the PowerSaveFlags field */
474#define MPI2_MANPAGE4_MASK_POWERSAVE_MODE (0x03)
475#define MPI2_MANPAGE4_POWERSAVE_MODE_DISABLED (0x00)
476#define MPI2_MANPAGE4_CUSTOM_POWERSAVE_MODE (0x01)
477#define MPI2_MANPAGE4_FULL_POWERSAVE_MODE (0x02)
478
479typedef struct _MPI2_CONFIG_PAGE_MAN_4
480{
481 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
482 U32 Reserved1; /* 0x04 */
483 U32 Flags; /* 0x08 */
484 U8 InquirySize; /* 0x0C */
485 U8 Reserved2; /* 0x0D */
486 U16 Reserved3; /* 0x0E */
487 U8 InquiryData[56]; /* 0x10 */
488 U32 RAID0VolumeSettings; /* 0x48 */
489 U32 RAID1EVolumeSettings; /* 0x4C */
490 U32 RAID1VolumeSettings; /* 0x50 */
491 U32 RAID10VolumeSettings; /* 0x54 */
492 U32 Reserved4; /* 0x58 */
493 U32 Reserved5; /* 0x5C */
494 MPI2_MANPAGE4_PWR_SAVE_SETTINGS PowerSaveSettings; /* 0x60 */
495 U8 MaxOCEDisks; /* 0x64 */
496 U8 ResyncRate; /* 0x65 */
497 U16 DataScrubDuration; /* 0x66 */
498 U8 MaxHotSpares; /* 0x68 */
499 U8 MaxPhysDisksPerVol; /* 0x69 */
500 U8 MaxPhysDisks; /* 0x6A */
501 U8 MaxVolumes; /* 0x6B */
502} MPI2_CONFIG_PAGE_MAN_4,
503 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_4,
504 Mpi2ManufacturingPage4_t, MPI2_POINTER pMpi2ManufacturingPage4_t;
505
506#define MPI2_MANUFACTURING4_PAGEVERSION (0x0A)
507
508/* Manufacturing Page 4 Flags field */
509#define MPI2_MANPAGE4_METADATA_SIZE_MASK (0x00030000)
510#define MPI2_MANPAGE4_METADATA_512MB (0x00000000)
511
512#define MPI2_MANPAGE4_MIX_SSD_SAS_SATA (0x00008000)
513#define MPI2_MANPAGE4_MIX_SSD_AND_NON_SSD (0x00004000)
514#define MPI2_MANPAGE4_HIDE_PHYSDISK_NON_IR (0x00002000)
515
516#define MPI2_MANPAGE4_MASK_PHYSDISK_COERCION (0x00001C00)
517#define MPI2_MANPAGE4_PHYSDISK_COERCION_1GB (0x00000000)
518#define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION (0x00000400)
519#define MPI2_MANPAGE4_PHYSDISK_ADAPTIVE_COERCION (0x00000800)
520#define MPI2_MANPAGE4_PHYSDISK_ZERO_COERCION (0x00000C00)
521
522#define MPI2_MANPAGE4_MASK_BAD_BLOCK_MARKING (0x00000300)
523#define MPI2_MANPAGE4_DEFAULT_BAD_BLOCK_MARKING (0x00000000)
524#define MPI2_MANPAGE4_TABLE_BAD_BLOCK_MARKING (0x00000100)
525#define MPI2_MANPAGE4_WRITE_LONG_BAD_BLOCK_MARKING (0x00000200)
526
527#define MPI2_MANPAGE4_FORCE_OFFLINE_FAILOVER (0x00000080)
528#define MPI2_MANPAGE4_RAID10_DISABLE (0x00000040)
529#define MPI2_MANPAGE4_RAID1E_DISABLE (0x00000020)
530#define MPI2_MANPAGE4_RAID1_DISABLE (0x00000010)
531#define MPI2_MANPAGE4_RAID0_DISABLE (0x00000008)
532#define MPI2_MANPAGE4_IR_MODEPAGE8_DISABLE (0x00000004)
533#define MPI2_MANPAGE4_IM_RESYNC_CACHE_ENABLE (0x00000002)
534#define MPI2_MANPAGE4_IR_NO_MIX_SAS_SATA (0x00000001)
535
536
537/* Manufacturing Page 5 */
538
539/*
540 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
541 * one and check Header.PageLength or NumPhys at runtime.
542 */
543#ifndef MPI2_MAN_PAGE_5_PHY_ENTRIES
544#define MPI2_MAN_PAGE_5_PHY_ENTRIES (1)
545#endif
546
547typedef struct _MPI2_MANUFACTURING5_ENTRY
548{
549 U64 WWID; /* 0x00 */
550 U64 DeviceName; /* 0x08 */
551} MPI2_MANUFACTURING5_ENTRY, MPI2_POINTER PTR_MPI2_MANUFACTURING5_ENTRY,
552 Mpi2Manufacturing5Entry_t, MPI2_POINTER pMpi2Manufacturing5Entry_t;
553
554typedef struct _MPI2_CONFIG_PAGE_MAN_5
555{
556 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
557 U8 NumPhys; /* 0x04 */
558 U8 Reserved1; /* 0x05 */
559 U16 Reserved2; /* 0x06 */
560 U32 Reserved3; /* 0x08 */
561 U32 Reserved4; /* 0x0C */
562 MPI2_MANUFACTURING5_ENTRY Phy[MPI2_MAN_PAGE_5_PHY_ENTRIES];/* 0x08 */
563} MPI2_CONFIG_PAGE_MAN_5,
564 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_5,
565 Mpi2ManufacturingPage5_t, MPI2_POINTER pMpi2ManufacturingPage5_t;
566
567#define MPI2_MANUFACTURING5_PAGEVERSION (0x03)
568
569
570/* Manufacturing Page 6 */
571
572typedef struct _MPI2_CONFIG_PAGE_MAN_6
573{
574 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
575 U32 ProductSpecificInfo;/* 0x04 */
576} MPI2_CONFIG_PAGE_MAN_6,
577 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_6,
578 Mpi2ManufacturingPage6_t, MPI2_POINTER pMpi2ManufacturingPage6_t;
579
580#define MPI2_MANUFACTURING6_PAGEVERSION (0x00)
581
582
583/* Manufacturing Page 7 */
584
585typedef struct _MPI2_MANPAGE7_CONNECTOR_INFO
586{
587 U32 Pinout; /* 0x00 */
588 U8 Connector[16]; /* 0x04 */
589 U8 Location; /* 0x14 */
590 U8 Reserved1; /* 0x15 */
591 U16 Slot; /* 0x16 */
592 U32 Reserved2; /* 0x18 */
593} MPI2_MANPAGE7_CONNECTOR_INFO, MPI2_POINTER PTR_MPI2_MANPAGE7_CONNECTOR_INFO,
594 Mpi2ManPage7ConnectorInfo_t, MPI2_POINTER pMpi2ManPage7ConnectorInfo_t;
595
596/* defines for the Pinout field */
597#define MPI2_MANPAGE7_PINOUT_SFF_8484_L4 (0x00080000)
598#define MPI2_MANPAGE7_PINOUT_SFF_8484_L3 (0x00040000)
599#define MPI2_MANPAGE7_PINOUT_SFF_8484_L2 (0x00020000)
600#define MPI2_MANPAGE7_PINOUT_SFF_8484_L1 (0x00010000)
601#define MPI2_MANPAGE7_PINOUT_SFF_8470_L4 (0x00000800)
602#define MPI2_MANPAGE7_PINOUT_SFF_8470_L3 (0x00000400)
603#define MPI2_MANPAGE7_PINOUT_SFF_8470_L2 (0x00000200)
604#define MPI2_MANPAGE7_PINOUT_SFF_8470_L1 (0x00000100)
605#define MPI2_MANPAGE7_PINOUT_SFF_8482 (0x00000002)
606#define MPI2_MANPAGE7_PINOUT_CONNECTION_UNKNOWN (0x00000001)
607
608/* defines for the Location field */
609#define MPI2_MANPAGE7_LOCATION_UNKNOWN (0x01)
610#define MPI2_MANPAGE7_LOCATION_INTERNAL (0x02)
611#define MPI2_MANPAGE7_LOCATION_EXTERNAL (0x04)
612#define MPI2_MANPAGE7_LOCATION_SWITCHABLE (0x08)
613#define MPI2_MANPAGE7_LOCATION_AUTO (0x10)
614#define MPI2_MANPAGE7_LOCATION_NOT_PRESENT (0x20)
615#define MPI2_MANPAGE7_LOCATION_NOT_CONNECTED (0x80)
616
617/*
618 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
619 * one and check NumPhys at runtime.
620 */
621#ifndef MPI2_MANPAGE7_CONNECTOR_INFO_MAX
622#define MPI2_MANPAGE7_CONNECTOR_INFO_MAX (1)
623#endif
624
625typedef struct _MPI2_CONFIG_PAGE_MAN_7
626{
627 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
628 U32 Reserved1; /* 0x04 */
629 U32 Reserved2; /* 0x08 */
630 U32 Flags; /* 0x0C */
631 U8 EnclosureName[16]; /* 0x10 */
632 U8 NumPhys; /* 0x20 */
633 U8 Reserved3; /* 0x21 */
634 U16 Reserved4; /* 0x22 */
635 MPI2_MANPAGE7_CONNECTOR_INFO ConnectorInfo[MPI2_MANPAGE7_CONNECTOR_INFO_MAX]; /* 0x24 */
636} MPI2_CONFIG_PAGE_MAN_7,
637 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_7,
638 Mpi2ManufacturingPage7_t, MPI2_POINTER pMpi2ManufacturingPage7_t;
639
640#define MPI2_MANUFACTURING7_PAGEVERSION (0x00)
641
642/* defines for the Flags field */
643#define MPI2_MANPAGE7_FLAG_USE_SLOT_INFO (0x00000001)
644
645
646/*
647 * Generic structure to use for product-specific manufacturing pages
648 * (currently Manufacturing Page 8 through Manufacturing Page 31).
649 */
650
651typedef struct _MPI2_CONFIG_PAGE_MAN_PS
652{
653 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
654 U32 ProductSpecificInfo;/* 0x04 */
655} MPI2_CONFIG_PAGE_MAN_PS,
656 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_PS,
657 Mpi2ManufacturingPagePS_t, MPI2_POINTER pMpi2ManufacturingPagePS_t;
658
659#define MPI2_MANUFACTURING8_PAGEVERSION (0x00)
660#define MPI2_MANUFACTURING9_PAGEVERSION (0x00)
661#define MPI2_MANUFACTURING10_PAGEVERSION (0x00)
662#define MPI2_MANUFACTURING11_PAGEVERSION (0x00)
663#define MPI2_MANUFACTURING12_PAGEVERSION (0x00)
664#define MPI2_MANUFACTURING13_PAGEVERSION (0x00)
665#define MPI2_MANUFACTURING14_PAGEVERSION (0x00)
666#define MPI2_MANUFACTURING15_PAGEVERSION (0x00)
667#define MPI2_MANUFACTURING16_PAGEVERSION (0x00)
668#define MPI2_MANUFACTURING17_PAGEVERSION (0x00)
669#define MPI2_MANUFACTURING18_PAGEVERSION (0x00)
670#define MPI2_MANUFACTURING19_PAGEVERSION (0x00)
671#define MPI2_MANUFACTURING20_PAGEVERSION (0x00)
672#define MPI2_MANUFACTURING21_PAGEVERSION (0x00)
673#define MPI2_MANUFACTURING22_PAGEVERSION (0x00)
674#define MPI2_MANUFACTURING23_PAGEVERSION (0x00)
675#define MPI2_MANUFACTURING24_PAGEVERSION (0x00)
676#define MPI2_MANUFACTURING25_PAGEVERSION (0x00)
677#define MPI2_MANUFACTURING26_PAGEVERSION (0x00)
678#define MPI2_MANUFACTURING27_PAGEVERSION (0x00)
679#define MPI2_MANUFACTURING28_PAGEVERSION (0x00)
680#define MPI2_MANUFACTURING29_PAGEVERSION (0x00)
681#define MPI2_MANUFACTURING30_PAGEVERSION (0x00)
682#define MPI2_MANUFACTURING31_PAGEVERSION (0x00)
683
684
685/****************************************************************************
686* IO Unit Config Pages
687****************************************************************************/
688
689/* IO Unit Page 0 */
690
691typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_0
692{
693 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
694 U64 UniqueValue; /* 0x04 */
695 MPI2_VERSION_UNION NvdataVersionDefault; /* 0x08 */
696 MPI2_VERSION_UNION NvdataVersionPersistent; /* 0x0A */
697} MPI2_CONFIG_PAGE_IO_UNIT_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_0,
698 Mpi2IOUnitPage0_t, MPI2_POINTER pMpi2IOUnitPage0_t;
699
700#define MPI2_IOUNITPAGE0_PAGEVERSION (0x02)
701
702
703/* IO Unit Page 1 */
704
705typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_1
706{
707 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
708 U32 Flags; /* 0x04 */
709} MPI2_CONFIG_PAGE_IO_UNIT_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_1,
710 Mpi2IOUnitPage1_t, MPI2_POINTER pMpi2IOUnitPage1_t;
711
712#define MPI2_IOUNITPAGE1_PAGEVERSION (0x04)
713
714/* IO Unit Page 1 Flags defines */
715#define MPI2_IOUNITPAGE1_MASK_SATA_WRITE_CACHE (0x00000600)
716#define MPI2_IOUNITPAGE1_ENABLE_SATA_WRITE_CACHE (0x00000000)
717#define MPI2_IOUNITPAGE1_DISABLE_SATA_WRITE_CACHE (0x00000200)
718#define MPI2_IOUNITPAGE1_UNCHANGED_SATA_WRITE_CACHE (0x00000400)
719#define MPI2_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE (0x00000100)
720#define MPI2_IOUNITPAGE1_DISABLE_IR (0x00000040)
721#define MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING (0x00000020)
722#define MPI2_IOUNITPAGE1_IR_USE_STATIC_VOLUME_ID (0x00000004)
723#define MPI2_IOUNITPAGE1_MULTI_PATHING (0x00000002)
724#define MPI2_IOUNITPAGE1_SINGLE_PATHING (0x00000000)
725
726
727/* IO Unit Page 3 */
728
729/*
730 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
731 * one and check Header.PageLength at runtime.
732 */
733#ifndef MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX
734#define MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX (1)
735#endif
736
737typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_3
738{
739 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
740 U8 GPIOCount; /* 0x04 */
741 U8 Reserved1; /* 0x05 */
742 U16 Reserved2; /* 0x06 */
743 U16 GPIOVal[MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX];/* 0x08 */
744} MPI2_CONFIG_PAGE_IO_UNIT_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_3,
745 Mpi2IOUnitPage3_t, MPI2_POINTER pMpi2IOUnitPage3_t;
746
747#define MPI2_IOUNITPAGE3_PAGEVERSION (0x01)
748
749/* defines for IO Unit Page 3 GPIOVal field */
750#define MPI2_IOUNITPAGE3_GPIO_FUNCTION_MASK (0xFFFC)
751#define MPI2_IOUNITPAGE3_GPIO_FUNCTION_SHIFT (2)
752#define MPI2_IOUNITPAGE3_GPIO_SETTING_OFF (0x0000)
753#define MPI2_IOUNITPAGE3_GPIO_SETTING_ON (0x0001)
754
755
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]756/* IO Unit Page 5 */
757
758/*
759 * Upper layer code (drivers, utilities, etc.) should leave this define set to
760 * one and check Header.PageLength or NumDmaEngines at runtime.
761 */
762#ifndef MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES
763#define MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES (1)
764#endif
765
766typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_5 {
767 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
768 U64 RaidAcceleratorBufferBaseAddress; /* 0x04 */
769 U64 RaidAcceleratorBufferSize; /* 0x0C */
770 U64 RaidAcceleratorControlBaseAddress; /* 0x14 */
771 U8 RAControlSize; /* 0x1C */
772 U8 NumDmaEngines; /* 0x1D */
773 U8 RAMinControlSize; /* 0x1E */
774 U8 RAMaxControlSize; /* 0x1F */
775 U32 Reserved1; /* 0x20 */
776 U32 Reserved2; /* 0x24 */
777 U32 Reserved3; /* 0x28 */
778 U32 DmaEngineCapabilities
779 [MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES]; /* 0x2C */
780} MPI2_CONFIG_PAGE_IO_UNIT_5, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_5,
781 Mpi2IOUnitPage5_t, MPI2_POINTER pMpi2IOUnitPage5_t;
782
783#define MPI2_IOUNITPAGE5_PAGEVERSION (0x00)
784
785/* defines for IO Unit Page 5 DmaEngineCapabilities field */
786#define MPI2_IOUNITPAGE5_DMA_CAP_MASK_MAX_REQUESTS (0xFF00)
787#define MPI2_IOUNITPAGE5_DMA_CAP_SHIFT_MAX_REQUESTS (16)
788
789#define MPI2_IOUNITPAGE5_DMA_CAP_EEDP (0x0008)
790#define MPI2_IOUNITPAGE5_DMA_CAP_PARITY_GENERATION (0x0004)
791#define MPI2_IOUNITPAGE5_DMA_CAP_HASHING (0x0002)
792#define MPI2_IOUNITPAGE5_DMA_CAP_ENCRYPTION (0x0001)
793
794
795/* IO Unit Page 6 */
796
797typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_6 {
798 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
799 U16 Flags; /* 0x04 */
800 U8 RAHostControlSize; /* 0x06 */
801 U8 Reserved0; /* 0x07 */
802 U64 RaidAcceleratorHostControlBaseAddress; /* 0x08 */
803 U32 Reserved1; /* 0x10 */
804 U32 Reserved2; /* 0x14 */
805 U32 Reserved3; /* 0x18 */
806} MPI2_CONFIG_PAGE_IO_UNIT_6, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_6,
807 Mpi2IOUnitPage6_t, MPI2_POINTER pMpi2IOUnitPage6_t;
808
809#define MPI2_IOUNITPAGE6_PAGEVERSION (0x00)
810
811/* defines for IO Unit Page 6 Flags field */
812#define MPI2_IOUNITPAGE6_FLAGS_ENABLE_RAID_ACCELERATOR (0x0001)
813
814
Kashyap, Desai9fec5f92009-09-23 17:26:20 +0530[diff] [blame]815/* IO Unit Page 7 */
816
817typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_7 {
818 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
819 U16 Reserved1; /* 0x04 */
820 U8 PCIeWidth; /* 0x06 */
821 U8 PCIeSpeed; /* 0x07 */
822 U32 ProcessorState; /* 0x08 */
823 U32 Reserved2; /* 0x0C */
824 U16 IOCTemperature; /* 0x10 */
825 U8 IOCTemperatureUnits; /* 0x12 */
826 U8 IOCSpeed; /* 0x13 */
827 U32 Reserved3; /* 0x14 */
828} MPI2_CONFIG_PAGE_IO_UNIT_7, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_7,
829 Mpi2IOUnitPage7_t, MPI2_POINTER pMpi2IOUnitPage7_t;
830
831#define MPI2_IOUNITPAGE7_PAGEVERSION (0x00)
832
833/* defines for IO Unit Page 7 PCIeWidth field */
834#define MPI2_IOUNITPAGE7_PCIE_WIDTH_X1 (0x01)
835#define MPI2_IOUNITPAGE7_PCIE_WIDTH_X2 (0x02)
836#define MPI2_IOUNITPAGE7_PCIE_WIDTH_X4 (0x04)
837#define MPI2_IOUNITPAGE7_PCIE_WIDTH_X8 (0x08)
838
839/* defines for IO Unit Page 7 PCIeSpeed field */
840#define MPI2_IOUNITPAGE7_PCIE_SPEED_2_5_GBPS (0x00)
841#define MPI2_IOUNITPAGE7_PCIE_SPEED_5_0_GBPS (0x01)
842#define MPI2_IOUNITPAGE7_PCIE_SPEED_8_0_GBPS (0x02)
843
844/* defines for IO Unit Page 7 ProcessorState field */
845#define MPI2_IOUNITPAGE7_PSTATE_MASK_SECOND (0x0000000F)
846#define MPI2_IOUNITPAGE7_PSTATE_SHIFT_SECOND (0)
847
848#define MPI2_IOUNITPAGE7_PSTATE_NOT_PRESENT (0x00)
849#define MPI2_IOUNITPAGE7_PSTATE_DISABLED (0x01)
850#define MPI2_IOUNITPAGE7_PSTATE_ENABLED (0x02)
851
852/* defines for IO Unit Page 7 IOCTemperatureUnits field */
853#define MPI2_IOUNITPAGE7_IOC_TEMP_NOT_PRESENT (0x00)
854#define MPI2_IOUNITPAGE7_IOC_TEMP_FAHRENHEIT (0x01)
855#define MPI2_IOUNITPAGE7_IOC_TEMP_CELSIUS (0x02)
856
857/* defines for IO Unit Page 7 IOCSpeed field */
858#define MPI2_IOUNITPAGE7_IOC_SPEED_FULL (0x01)
859#define MPI2_IOUNITPAGE7_IOC_SPEED_HALF (0x02)
860#define MPI2_IOUNITPAGE7_IOC_SPEED_QUARTER (0x04)
861#define MPI2_IOUNITPAGE7_IOC_SPEED_EIGHTH (0x08)
862
863
864
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]865/****************************************************************************
866* IOC Config Pages
867****************************************************************************/
868
869/* IOC Page 0 */
870
871typedef struct _MPI2_CONFIG_PAGE_IOC_0
872{
873 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
874 U32 Reserved1; /* 0x04 */
875 U32 Reserved2; /* 0x08 */
876 U16 VendorID; /* 0x0C */
877 U16 DeviceID; /* 0x0E */
878 U8 RevisionID; /* 0x10 */
879 U8 Reserved3; /* 0x11 */
880 U16 Reserved4; /* 0x12 */
881 U32 ClassCode; /* 0x14 */
882 U16 SubsystemVendorID; /* 0x18 */
883 U16 SubsystemID; /* 0x1A */
884} MPI2_CONFIG_PAGE_IOC_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_0,
885 Mpi2IOCPage0_t, MPI2_POINTER pMpi2IOCPage0_t;
886
887#define MPI2_IOCPAGE0_PAGEVERSION (0x02)
888
889
890/* IOC Page 1 */
891
892typedef struct _MPI2_CONFIG_PAGE_IOC_1
893{
894 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
895 U32 Flags; /* 0x04 */
896 U32 CoalescingTimeout; /* 0x08 */
897 U8 CoalescingDepth; /* 0x0C */
898 U8 PCISlotNum; /* 0x0D */
899 U8 PCIBusNum; /* 0x0E */
900 U8 PCIDomainSegment; /* 0x0F */
901 U32 Reserved1; /* 0x10 */
902 U32 Reserved2; /* 0x14 */
903} MPI2_CONFIG_PAGE_IOC_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_1,
904 Mpi2IOCPage1_t, MPI2_POINTER pMpi2IOCPage1_t;
905
906#define MPI2_IOCPAGE1_PAGEVERSION (0x05)
907
908/* defines for IOC Page 1 Flags field */
909#define MPI2_IOCPAGE1_REPLY_COALESCING (0x00000001)
910
911#define MPI2_IOCPAGE1_PCISLOTNUM_UNKNOWN (0xFF)
912#define MPI2_IOCPAGE1_PCIBUSNUM_UNKNOWN (0xFF)
913#define MPI2_IOCPAGE1_PCIDOMAIN_UNKNOWN (0xFF)
914
915/* IOC Page 6 */
916
917typedef struct _MPI2_CONFIG_PAGE_IOC_6
918{
919 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
920 U32 CapabilitiesFlags; /* 0x04 */
921 U8 MaxDrivesRAID0; /* 0x08 */
922 U8 MaxDrivesRAID1; /* 0x09 */
923 U8 MaxDrivesRAID1E; /* 0x0A */
924 U8 MaxDrivesRAID10; /* 0x0B */
925 U8 MinDrivesRAID0; /* 0x0C */
926 U8 MinDrivesRAID1; /* 0x0D */
927 U8 MinDrivesRAID1E; /* 0x0E */
928 U8 MinDrivesRAID10; /* 0x0F */
929 U32 Reserved1; /* 0x10 */
930 U8 MaxGlobalHotSpares; /* 0x14 */
931 U8 MaxPhysDisks; /* 0x15 */
932 U8 MaxVolumes; /* 0x16 */
933 U8 MaxConfigs; /* 0x17 */
934 U8 MaxOCEDisks; /* 0x18 */
935 U8 Reserved2; /* 0x19 */
936 U16 Reserved3; /* 0x1A */
937 U32 SupportedStripeSizeMapRAID0; /* 0x1C */
938 U32 SupportedStripeSizeMapRAID1E; /* 0x20 */
939 U32 SupportedStripeSizeMapRAID10; /* 0x24 */
940 U32 Reserved4; /* 0x28 */
941 U32 Reserved5; /* 0x2C */
942 U16 DefaultMetadataSize; /* 0x30 */
943 U16 Reserved6; /* 0x32 */
944 U16 MaxBadBlockTableEntries; /* 0x34 */
945 U16 Reserved7; /* 0x36 */
946 U32 IRNvsramVersion; /* 0x38 */
947} MPI2_CONFIG_PAGE_IOC_6, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_6,
948 Mpi2IOCPage6_t, MPI2_POINTER pMpi2IOCPage6_t;
949
950#define MPI2_IOCPAGE6_PAGEVERSION (0x04)
951
952/* defines for IOC Page 6 CapabilitiesFlags */
953#define MPI2_IOCPAGE6_CAP_FLAGS_RAID10_SUPPORT (0x00000010)
954#define MPI2_IOCPAGE6_CAP_FLAGS_RAID1_SUPPORT (0x00000008)
955#define MPI2_IOCPAGE6_CAP_FLAGS_RAID1E_SUPPORT (0x00000004)
956#define MPI2_IOCPAGE6_CAP_FLAGS_RAID0_SUPPORT (0x00000002)
957#define MPI2_IOCPAGE6_CAP_FLAGS_GLOBAL_HOT_SPARE (0x00000001)
958
959
960/* IOC Page 7 */
961
962#define MPI2_IOCPAGE7_EVENTMASK_WORDS (4)
963
964typedef struct _MPI2_CONFIG_PAGE_IOC_7
965{
966 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
967 U32 Reserved1; /* 0x04 */
968 U32 EventMasks[MPI2_IOCPAGE7_EVENTMASK_WORDS];/* 0x08 */
969 U16 SASBroadcastPrimitiveMasks; /* 0x18 */
970 U16 Reserved2; /* 0x1A */
971 U32 Reserved3; /* 0x1C */
972} MPI2_CONFIG_PAGE_IOC_7, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_7,
973 Mpi2IOCPage7_t, MPI2_POINTER pMpi2IOCPage7_t;
974
975#define MPI2_IOCPAGE7_PAGEVERSION (0x01)
976
977
978/* IOC Page 8 */
979
980typedef struct _MPI2_CONFIG_PAGE_IOC_8
981{
982 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
983 U8 NumDevsPerEnclosure; /* 0x04 */
984 U8 Reserved1; /* 0x05 */
985 U16 Reserved2; /* 0x06 */
986 U16 MaxPersistentEntries; /* 0x08 */
987 U16 MaxNumPhysicalMappedIDs; /* 0x0A */
988 U16 Flags; /* 0x0C */
989 U16 Reserved3; /* 0x0E */
990 U16 IRVolumeMappingFlags; /* 0x10 */
991 U16 Reserved4; /* 0x12 */
992 U32 Reserved5; /* 0x14 */
993} MPI2_CONFIG_PAGE_IOC_8, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_8,
994 Mpi2IOCPage8_t, MPI2_POINTER pMpi2IOCPage8_t;
995
996#define MPI2_IOCPAGE8_PAGEVERSION (0x00)
997
998/* defines for IOC Page 8 Flags field */
999#define MPI2_IOCPAGE8_FLAGS_DA_START_SLOT_1 (0x00000020)
1000#define MPI2_IOCPAGE8_FLAGS_RESERVED_TARGETID_0 (0x00000010)
1001
1002#define MPI2_IOCPAGE8_FLAGS_MASK_MAPPING_MODE (0x0000000E)
1003#define MPI2_IOCPAGE8_FLAGS_DEVICE_PERSISTENCE_MAPPING (0x00000000)
1004#define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING (0x00000002)
1005
1006#define MPI2_IOCPAGE8_FLAGS_DISABLE_PERSISTENT_MAPPING (0x00000001)
1007#define MPI2_IOCPAGE8_FLAGS_ENABLE_PERSISTENT_MAPPING (0x00000000)
1008
1009/* defines for IOC Page 8 IRVolumeMappingFlags */
1010#define MPI2_IOCPAGE8_IRFLAGS_MASK_VOLUME_MAPPING_MODE (0x00000003)
1011#define MPI2_IOCPAGE8_IRFLAGS_LOW_VOLUME_MAPPING (0x00000000)
1012#define MPI2_IOCPAGE8_IRFLAGS_HIGH_VOLUME_MAPPING (0x00000001)
1013
1014
1015/****************************************************************************
1016* BIOS Config Pages
1017****************************************************************************/
1018
1019/* BIOS Page 1 */
1020
1021typedef struct _MPI2_CONFIG_PAGE_BIOS_1
1022{
1023 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1024 U32 BiosOptions; /* 0x04 */
1025 U32 IOCSettings; /* 0x08 */
1026 U32 Reserved1; /* 0x0C */
1027 U32 DeviceSettings; /* 0x10 */
1028 U16 NumberOfDevices; /* 0x14 */
1029 U16 Reserved2; /* 0x16 */
1030 U16 IOTimeoutBlockDevicesNonRM; /* 0x18 */
1031 U16 IOTimeoutSequential; /* 0x1A */
1032 U16 IOTimeoutOther; /* 0x1C */
1033 U16 IOTimeoutBlockDevicesRM; /* 0x1E */
1034} MPI2_CONFIG_PAGE_BIOS_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_1,
1035 Mpi2BiosPage1_t, MPI2_POINTER pMpi2BiosPage1_t;
1036
1037#define MPI2_BIOSPAGE1_PAGEVERSION (0x04)
1038
1039/* values for BIOS Page 1 BiosOptions field */
1040#define MPI2_BIOSPAGE1_OPTIONS_DISABLE_BIOS (0x00000001)
1041
1042/* values for BIOS Page 1 IOCSettings field */
1043#define MPI2_BIOSPAGE1_IOCSET_MASK_BOOT_PREFERENCE (0x00030000)
1044#define MPI2_BIOSPAGE1_IOCSET_ENCLOSURE_SLOT_BOOT (0x00000000)
1045#define MPI2_BIOSPAGE1_IOCSET_SAS_ADDRESS_BOOT (0x00010000)
1046
1047#define MPI2_BIOSPAGE1_IOCSET_MASK_RM_SETTING (0x000000C0)
1048#define MPI2_BIOSPAGE1_IOCSET_NONE_RM_SETTING (0x00000000)
1049#define MPI2_BIOSPAGE1_IOCSET_BOOT_RM_SETTING (0x00000040)
1050#define MPI2_BIOSPAGE1_IOCSET_MEDIA_RM_SETTING (0x00000080)
1051
1052#define MPI2_BIOSPAGE1_IOCSET_MASK_ADAPTER_SUPPORT (0x00000030)
1053#define MPI2_BIOSPAGE1_IOCSET_NO_SUPPORT (0x00000000)
1054#define MPI2_BIOSPAGE1_IOCSET_BIOS_SUPPORT (0x00000010)
1055#define MPI2_BIOSPAGE1_IOCSET_OS_SUPPORT (0x00000020)
1056#define MPI2_BIOSPAGE1_IOCSET_ALL_SUPPORT (0x00000030)
1057
1058#define MPI2_BIOSPAGE1_IOCSET_ALTERNATE_CHS (0x00000008)
1059
1060/* values for BIOS Page 1 DeviceSettings field */
1061#define MPI2_BIOSPAGE1_DEVSET_DISABLE_SMART_POLLING (0x00000010)
1062#define MPI2_BIOSPAGE1_DEVSET_DISABLE_SEQ_LUN (0x00000008)
1063#define MPI2_BIOSPAGE1_DEVSET_DISABLE_RM_LUN (0x00000004)
1064#define MPI2_BIOSPAGE1_DEVSET_DISABLE_NON_RM_LUN (0x00000002)
1065#define MPI2_BIOSPAGE1_DEVSET_DISABLE_OTHER_LUN (0x00000001)
1066
1067
1068/* BIOS Page 2 */
1069
1070typedef struct _MPI2_BOOT_DEVICE_ADAPTER_ORDER
1071{
1072 U32 Reserved1; /* 0x00 */
1073 U32 Reserved2; /* 0x04 */
1074 U32 Reserved3; /* 0x08 */
1075 U32 Reserved4; /* 0x0C */
1076 U32 Reserved5; /* 0x10 */
1077 U32 Reserved6; /* 0x14 */
1078} MPI2_BOOT_DEVICE_ADAPTER_ORDER,
1079 MPI2_POINTER PTR_MPI2_BOOT_DEVICE_ADAPTER_ORDER,
1080 Mpi2BootDeviceAdapterOrder_t, MPI2_POINTER pMpi2BootDeviceAdapterOrder_t;
1081
1082typedef struct _MPI2_BOOT_DEVICE_SAS_WWID
1083{
1084 U64 SASAddress; /* 0x00 */
1085 U8 LUN[8]; /* 0x08 */
1086 U32 Reserved1; /* 0x10 */
1087 U32 Reserved2; /* 0x14 */
1088} MPI2_BOOT_DEVICE_SAS_WWID, MPI2_POINTER PTR_MPI2_BOOT_DEVICE_SAS_WWID,
1089 Mpi2BootDeviceSasWwid_t, MPI2_POINTER pMpi2BootDeviceSasWwid_t;
1090
1091typedef struct _MPI2_BOOT_DEVICE_ENCLOSURE_SLOT
1092{
1093 U64 EnclosureLogicalID; /* 0x00 */
1094 U32 Reserved1; /* 0x08 */
1095 U32 Reserved2; /* 0x0C */
1096 U16 SlotNumber; /* 0x10 */
1097 U16 Reserved3; /* 0x12 */
1098 U32 Reserved4; /* 0x14 */
1099} MPI2_BOOT_DEVICE_ENCLOSURE_SLOT,
1100 MPI2_POINTER PTR_MPI2_BOOT_DEVICE_ENCLOSURE_SLOT,
1101 Mpi2BootDeviceEnclosureSlot_t, MPI2_POINTER pMpi2BootDeviceEnclosureSlot_t;
1102
1103typedef struct _MPI2_BOOT_DEVICE_DEVICE_NAME
1104{
1105 U64 DeviceName; /* 0x00 */
1106 U8 LUN[8]; /* 0x08 */
1107 U32 Reserved1; /* 0x10 */
1108 U32 Reserved2; /* 0x14 */
1109} MPI2_BOOT_DEVICE_DEVICE_NAME, MPI2_POINTER PTR_MPI2_BOOT_DEVICE_DEVICE_NAME,
1110 Mpi2BootDeviceDeviceName_t, MPI2_POINTER pMpi2BootDeviceDeviceName_t;
1111
1112typedef union _MPI2_MPI2_BIOSPAGE2_BOOT_DEVICE
1113{
1114 MPI2_BOOT_DEVICE_ADAPTER_ORDER AdapterOrder;
1115 MPI2_BOOT_DEVICE_SAS_WWID SasWwid;
1116 MPI2_BOOT_DEVICE_ENCLOSURE_SLOT EnclosureSlot;
1117 MPI2_BOOT_DEVICE_DEVICE_NAME DeviceName;
1118} MPI2_BIOSPAGE2_BOOT_DEVICE, MPI2_POINTER PTR_MPI2_BIOSPAGE2_BOOT_DEVICE,
1119 Mpi2BiosPage2BootDevice_t, MPI2_POINTER pMpi2BiosPage2BootDevice_t;
1120
1121typedef struct _MPI2_CONFIG_PAGE_BIOS_2
1122{
1123 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1124 U32 Reserved1; /* 0x04 */
1125 U32 Reserved2; /* 0x08 */
1126 U32 Reserved3; /* 0x0C */
1127 U32 Reserved4; /* 0x10 */
1128 U32 Reserved5; /* 0x14 */
1129 U32 Reserved6; /* 0x18 */
1130 U8 ReqBootDeviceForm; /* 0x1C */
1131 U8 Reserved7; /* 0x1D */
1132 U16 Reserved8; /* 0x1E */
1133 MPI2_BIOSPAGE2_BOOT_DEVICE RequestedBootDevice; /* 0x20 */
1134 U8 ReqAltBootDeviceForm; /* 0x38 */
1135 U8 Reserved9; /* 0x39 */
1136 U16 Reserved10; /* 0x3A */
1137 MPI2_BIOSPAGE2_BOOT_DEVICE RequestedAltBootDevice; /* 0x3C */
1138 U8 CurrentBootDeviceForm; /* 0x58 */
1139 U8 Reserved11; /* 0x59 */
1140 U16 Reserved12; /* 0x5A */
1141 MPI2_BIOSPAGE2_BOOT_DEVICE CurrentBootDevice; /* 0x58 */
1142} MPI2_CONFIG_PAGE_BIOS_2, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_2,
1143 Mpi2BiosPage2_t, MPI2_POINTER pMpi2BiosPage2_t;
1144
1145#define MPI2_BIOSPAGE2_PAGEVERSION (0x04)
1146
1147/* values for BIOS Page 2 BootDeviceForm fields */
1148#define MPI2_BIOSPAGE2_FORM_MASK (0x0F)
1149#define MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED (0x00)
1150#define MPI2_BIOSPAGE2_FORM_SAS_WWID (0x05)
1151#define MPI2_BIOSPAGE2_FORM_ENCLOSURE_SLOT (0x06)
1152#define MPI2_BIOSPAGE2_FORM_DEVICE_NAME (0x07)
1153
1154
1155/* BIOS Page 3 */
1156
1157typedef struct _MPI2_ADAPTER_INFO
1158{
1159 U8 PciBusNumber; /* 0x00 */
1160 U8 PciDeviceAndFunctionNumber; /* 0x01 */
1161 U16 AdapterFlags; /* 0x02 */
1162} MPI2_ADAPTER_INFO, MPI2_POINTER PTR_MPI2_ADAPTER_INFO,
1163 Mpi2AdapterInfo_t, MPI2_POINTER pMpi2AdapterInfo_t;
1164
1165#define MPI2_ADAPTER_INFO_FLAGS_EMBEDDED (0x0001)
1166#define MPI2_ADAPTER_INFO_FLAGS_INIT_STATUS (0x0002)
1167
1168typedef struct _MPI2_CONFIG_PAGE_BIOS_3
1169{
1170 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1171 U32 GlobalFlags; /* 0x04 */
1172 U32 BiosVersion; /* 0x08 */
1173 MPI2_ADAPTER_INFO AdapterOrder[4]; /* 0x0C */
1174 U32 Reserved1; /* 0x1C */
1175} MPI2_CONFIG_PAGE_BIOS_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_3,
1176 Mpi2BiosPage3_t, MPI2_POINTER pMpi2BiosPage3_t;
1177
1178#define MPI2_BIOSPAGE3_PAGEVERSION (0x00)
1179
1180/* values for BIOS Page 3 GlobalFlags */
1181#define MPI2_BIOSPAGE3_FLAGS_PAUSE_ON_ERROR (0x00000002)
1182#define MPI2_BIOSPAGE3_FLAGS_VERBOSE_ENABLE (0x00000004)
1183#define MPI2_BIOSPAGE3_FLAGS_HOOK_INT_40_DISABLE (0x00000010)
1184
1185#define MPI2_BIOSPAGE3_FLAGS_DEV_LIST_DISPLAY_MASK (0x000000E0)
1186#define MPI2_BIOSPAGE3_FLAGS_INSTALLED_DEV_DISPLAY (0x00000000)
1187#define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DISPLAY (0x00000020)
1188#define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DEV_DISPLAY (0x00000040)
1189
1190
1191/* BIOS Page 4 */
1192
1193/*
1194 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1195 * one and check Header.PageLength or NumPhys at runtime.
1196 */
1197#ifndef MPI2_BIOS_PAGE_4_PHY_ENTRIES
1198#define MPI2_BIOS_PAGE_4_PHY_ENTRIES (1)
1199#endif
1200
1201typedef struct _MPI2_BIOS4_ENTRY
1202{
1203 U64 ReassignmentWWID; /* 0x00 */
1204 U64 ReassignmentDeviceName; /* 0x08 */
1205} MPI2_BIOS4_ENTRY, MPI2_POINTER PTR_MPI2_BIOS4_ENTRY,
1206 Mpi2MBios4Entry_t, MPI2_POINTER pMpi2Bios4Entry_t;
1207
1208typedef struct _MPI2_CONFIG_PAGE_BIOS_4
1209{
1210 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1211 U8 NumPhys; /* 0x04 */
1212 U8 Reserved1; /* 0x05 */
1213 U16 Reserved2; /* 0x06 */
1214 MPI2_BIOS4_ENTRY Phy[MPI2_BIOS_PAGE_4_PHY_ENTRIES]; /* 0x08 */
1215} MPI2_CONFIG_PAGE_BIOS_4, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_4,
1216 Mpi2BiosPage4_t, MPI2_POINTER pMpi2BiosPage4_t;
1217
1218#define MPI2_BIOSPAGE4_PAGEVERSION (0x01)
1219
1220
1221/****************************************************************************
1222* RAID Volume Config Pages
1223****************************************************************************/
1224
1225/* RAID Volume Page 0 */
1226
1227typedef struct _MPI2_RAIDVOL0_PHYS_DISK
1228{
1229 U8 RAIDSetNum; /* 0x00 */
1230 U8 PhysDiskMap; /* 0x01 */
1231 U8 PhysDiskNum; /* 0x02 */
1232 U8 Reserved; /* 0x03 */
1233} MPI2_RAIDVOL0_PHYS_DISK, MPI2_POINTER PTR_MPI2_RAIDVOL0_PHYS_DISK,
1234 Mpi2RaidVol0PhysDisk_t, MPI2_POINTER pMpi2RaidVol0PhysDisk_t;
1235
1236/* defines for the PhysDiskMap field */
1237#define MPI2_RAIDVOL0_PHYSDISK_PRIMARY (0x01)
1238#define MPI2_RAIDVOL0_PHYSDISK_SECONDARY (0x02)
1239
1240typedef struct _MPI2_RAIDVOL0_SETTINGS
1241{
1242 U16 Settings; /* 0x00 */
1243 U8 HotSparePool; /* 0x01 */
1244 U8 Reserved; /* 0x02 */
1245} MPI2_RAIDVOL0_SETTINGS, MPI2_POINTER PTR_MPI2_RAIDVOL0_SETTINGS,
1246 Mpi2RaidVol0Settings_t, MPI2_POINTER pMpi2RaidVol0Settings_t;
1247
1248/* RAID Volume Page 0 HotSparePool defines, also used in RAID Physical Disk */
1249#define MPI2_RAID_HOT_SPARE_POOL_0 (0x01)
1250#define MPI2_RAID_HOT_SPARE_POOL_1 (0x02)
1251#define MPI2_RAID_HOT_SPARE_POOL_2 (0x04)
1252#define MPI2_RAID_HOT_SPARE_POOL_3 (0x08)
1253#define MPI2_RAID_HOT_SPARE_POOL_4 (0x10)
1254#define MPI2_RAID_HOT_SPARE_POOL_5 (0x20)
1255#define MPI2_RAID_HOT_SPARE_POOL_6 (0x40)
1256#define MPI2_RAID_HOT_SPARE_POOL_7 (0x80)
1257
1258/* RAID Volume Page 0 VolumeSettings defines */
1259#define MPI2_RAIDVOL0_SETTING_USE_PRODUCT_ID_SUFFIX (0x0008)
1260#define MPI2_RAIDVOL0_SETTING_AUTO_CONFIG_HSWAP_DISABLE (0x0004)
1261
1262#define MPI2_RAIDVOL0_SETTING_MASK_WRITE_CACHING (0x0003)
1263#define MPI2_RAIDVOL0_SETTING_UNCHANGED (0x0000)
1264#define MPI2_RAIDVOL0_SETTING_DISABLE_WRITE_CACHING (0x0001)
1265#define MPI2_RAIDVOL0_SETTING_ENABLE_WRITE_CACHING (0x0002)
1266
1267/*
1268 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1269 * one and check Header.PageLength at runtime.
1270 */
1271#ifndef MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX
1272#define MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX (1)
1273#endif
1274
1275typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_0
1276{
1277 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1278 U16 DevHandle; /* 0x04 */
1279 U8 VolumeState; /* 0x06 */
1280 U8 VolumeType; /* 0x07 */
1281 U32 VolumeStatusFlags; /* 0x08 */
1282 MPI2_RAIDVOL0_SETTINGS VolumeSettings; /* 0x0C */
1283 U64 MaxLBA; /* 0x10 */
1284 U32 StripeSize; /* 0x18 */
1285 U16 BlockSize; /* 0x1C */
1286 U16 Reserved1; /* 0x1E */
1287 U8 SupportedPhysDisks; /* 0x20 */
1288 U8 ResyncRate; /* 0x21 */
1289 U16 DataScrubDuration; /* 0x22 */
1290 U8 NumPhysDisks; /* 0x24 */
1291 U8 Reserved2; /* 0x25 */
1292 U8 Reserved3; /* 0x26 */
1293 U8 InactiveStatus; /* 0x27 */
1294 MPI2_RAIDVOL0_PHYS_DISK PhysDisk[MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX]; /* 0x28 */
1295} MPI2_CONFIG_PAGE_RAID_VOL_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_VOL_0,
1296 Mpi2RaidVolPage0_t, MPI2_POINTER pMpi2RaidVolPage0_t;
1297
1298#define MPI2_RAIDVOLPAGE0_PAGEVERSION (0x0A)
1299
1300/* values for RAID VolumeState */
1301#define MPI2_RAID_VOL_STATE_MISSING (0x00)
1302#define MPI2_RAID_VOL_STATE_FAILED (0x01)
1303#define MPI2_RAID_VOL_STATE_INITIALIZING (0x02)
1304#define MPI2_RAID_VOL_STATE_ONLINE (0x03)
1305#define MPI2_RAID_VOL_STATE_DEGRADED (0x04)
1306#define MPI2_RAID_VOL_STATE_OPTIMAL (0x05)
1307
1308/* values for RAID VolumeType */
1309#define MPI2_RAID_VOL_TYPE_RAID0 (0x00)
1310#define MPI2_RAID_VOL_TYPE_RAID1E (0x01)
1311#define MPI2_RAID_VOL_TYPE_RAID1 (0x02)
1312#define MPI2_RAID_VOL_TYPE_RAID10 (0x05)
1313#define MPI2_RAID_VOL_TYPE_UNKNOWN (0xFF)
1314
1315/* values for RAID Volume Page 0 VolumeStatusFlags field */
1316#define MPI2_RAIDVOL0_STATUS_FLAG_PENDING_RESYNC (0x02000000)
1317#define MPI2_RAIDVOL0_STATUS_FLAG_BACKG_INIT_PENDING (0x01000000)
1318#define MPI2_RAIDVOL0_STATUS_FLAG_MDC_PENDING (0x00800000)
1319#define MPI2_RAIDVOL0_STATUS_FLAG_USER_CONSIST_PENDING (0x00400000)
1320#define MPI2_RAIDVOL0_STATUS_FLAG_MAKE_DATA_CONSISTENT (0x00200000)
1321#define MPI2_RAIDVOL0_STATUS_FLAG_DATA_SCRUB (0x00100000)
1322#define MPI2_RAIDVOL0_STATUS_FLAG_CONSISTENCY_CHECK (0x00080000)
1323#define MPI2_RAIDVOL0_STATUS_FLAG_CAPACITY_EXPANSION (0x00040000)
1324#define MPI2_RAIDVOL0_STATUS_FLAG_BACKGROUND_INIT (0x00020000)
1325#define MPI2_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS (0x00010000)
1326#define MPI2_RAIDVOL0_STATUS_FLAG_OCE_ALLOWED (0x00000040)
1327#define MPI2_RAIDVOL0_STATUS_FLAG_BGI_COMPLETE (0x00000020)
1328#define MPI2_RAIDVOL0_STATUS_FLAG_1E_OFFSET_MIRROR (0x00000000)
1329#define MPI2_RAIDVOL0_STATUS_FLAG_1E_ADJACENT_MIRROR (0x00000010)
1330#define MPI2_RAIDVOL0_STATUS_FLAG_BAD_BLOCK_TABLE_FULL (0x00000008)
1331#define MPI2_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE (0x00000004)
1332#define MPI2_RAIDVOL0_STATUS_FLAG_QUIESCED (0x00000002)
1333#define MPI2_RAIDVOL0_STATUS_FLAG_ENABLED (0x00000001)
1334
1335/* values for RAID Volume Page 0 SupportedPhysDisks field */
1336#define MPI2_RAIDVOL0_SUPPORT_SOLID_STATE_DISKS (0x08)
1337#define MPI2_RAIDVOL0_SUPPORT_HARD_DISKS (0x04)
1338#define MPI2_RAIDVOL0_SUPPORT_SAS_PROTOCOL (0x02)
1339#define MPI2_RAIDVOL0_SUPPORT_SATA_PROTOCOL (0x01)
1340
1341/* values for RAID Volume Page 0 InactiveStatus field */
1342#define MPI2_RAIDVOLPAGE0_UNKNOWN_INACTIVE (0x00)
1343#define MPI2_RAIDVOLPAGE0_STALE_METADATA_INACTIVE (0x01)
1344#define MPI2_RAIDVOLPAGE0_FOREIGN_VOLUME_INACTIVE (0x02)
1345#define MPI2_RAIDVOLPAGE0_INSUFFICIENT_RESOURCE_INACTIVE (0x03)
1346#define MPI2_RAIDVOLPAGE0_CLONE_VOLUME_INACTIVE (0x04)
1347#define MPI2_RAIDVOLPAGE0_INSUFFICIENT_METADATA_INACTIVE (0x05)
1348#define MPI2_RAIDVOLPAGE0_PREVIOUSLY_DELETED (0x06)
1349
1350
1351/* RAID Volume Page 1 */
1352
1353typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_1
1354{
1355 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1356 U16 DevHandle; /* 0x04 */
1357 U16 Reserved0; /* 0x06 */
1358 U8 GUID[24]; /* 0x08 */
1359 U8 Name[16]; /* 0x20 */
1360 U64 WWID; /* 0x30 */
1361 U32 Reserved1; /* 0x38 */
1362 U32 Reserved2; /* 0x3C */
1363} MPI2_CONFIG_PAGE_RAID_VOL_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_VOL_1,
1364 Mpi2RaidVolPage1_t, MPI2_POINTER pMpi2RaidVolPage1_t;
1365
1366#define MPI2_RAIDVOLPAGE1_PAGEVERSION (0x03)
1367
1368
1369/****************************************************************************
1370* RAID Physical Disk Config Pages
1371****************************************************************************/
1372
1373/* RAID Physical Disk Page 0 */
1374
1375typedef struct _MPI2_RAIDPHYSDISK0_SETTINGS
1376{
1377 U16 Reserved1; /* 0x00 */
1378 U8 HotSparePool; /* 0x02 */
1379 U8 Reserved2; /* 0x03 */
1380} MPI2_RAIDPHYSDISK0_SETTINGS, MPI2_POINTER PTR_MPI2_RAIDPHYSDISK0_SETTINGS,
1381 Mpi2RaidPhysDisk0Settings_t, MPI2_POINTER pMpi2RaidPhysDisk0Settings_t;
1382
1383/* use MPI2_RAID_HOT_SPARE_POOL_ defines for the HotSparePool field */
1384
1385typedef struct _MPI2_RAIDPHYSDISK0_INQUIRY_DATA
1386{
1387 U8 VendorID[8]; /* 0x00 */
1388 U8 ProductID[16]; /* 0x08 */
1389 U8 ProductRevLevel[4]; /* 0x18 */
1390 U8 SerialNum[32]; /* 0x1C */
1391} MPI2_RAIDPHYSDISK0_INQUIRY_DATA,
1392 MPI2_POINTER PTR_MPI2_RAIDPHYSDISK0_INQUIRY_DATA,
1393 Mpi2RaidPhysDisk0InquiryData_t, MPI2_POINTER pMpi2RaidPhysDisk0InquiryData_t;
1394
1395typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_0
1396{
1397 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1398 U16 DevHandle; /* 0x04 */
1399 U8 Reserved1; /* 0x06 */
1400 U8 PhysDiskNum; /* 0x07 */
1401 MPI2_RAIDPHYSDISK0_SETTINGS PhysDiskSettings; /* 0x08 */
1402 U32 Reserved2; /* 0x0C */
1403 MPI2_RAIDPHYSDISK0_INQUIRY_DATA InquiryData; /* 0x10 */
1404 U32 Reserved3; /* 0x4C */
1405 U8 PhysDiskState; /* 0x50 */
1406 U8 OfflineReason; /* 0x51 */
1407 U8 IncompatibleReason; /* 0x52 */
1408 U8 PhysDiskAttributes; /* 0x53 */
1409 U32 PhysDiskStatusFlags; /* 0x54 */
1410 U64 DeviceMaxLBA; /* 0x58 */
1411 U64 HostMaxLBA; /* 0x60 */
1412 U64 CoercedMaxLBA; /* 0x68 */
1413 U16 BlockSize; /* 0x70 */
1414 U16 Reserved5; /* 0x72 */
1415 U32 Reserved6; /* 0x74 */
1416} MPI2_CONFIG_PAGE_RD_PDISK_0,
1417 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RD_PDISK_0,
1418 Mpi2RaidPhysDiskPage0_t, MPI2_POINTER pMpi2RaidPhysDiskPage0_t;
1419
1420#define MPI2_RAIDPHYSDISKPAGE0_PAGEVERSION (0x05)
1421
1422/* PhysDiskState defines */
1423#define MPI2_RAID_PD_STATE_NOT_CONFIGURED (0x00)
1424#define MPI2_RAID_PD_STATE_NOT_COMPATIBLE (0x01)
1425#define MPI2_RAID_PD_STATE_OFFLINE (0x02)
1426#define MPI2_RAID_PD_STATE_ONLINE (0x03)
1427#define MPI2_RAID_PD_STATE_HOT_SPARE (0x04)
1428#define MPI2_RAID_PD_STATE_DEGRADED (0x05)
1429#define MPI2_RAID_PD_STATE_REBUILDING (0x06)
1430#define MPI2_RAID_PD_STATE_OPTIMAL (0x07)
1431
1432/* OfflineReason defines */
1433#define MPI2_PHYSDISK0_ONLINE (0x00)
1434#define MPI2_PHYSDISK0_OFFLINE_MISSING (0x01)
1435#define MPI2_PHYSDISK0_OFFLINE_FAILED (0x03)
1436#define MPI2_PHYSDISK0_OFFLINE_INITIALIZING (0x04)
1437#define MPI2_PHYSDISK0_OFFLINE_REQUESTED (0x05)
1438#define MPI2_PHYSDISK0_OFFLINE_FAILED_REQUESTED (0x06)
1439#define MPI2_PHYSDISK0_OFFLINE_OTHER (0xFF)
1440
1441/* IncompatibleReason defines */
1442#define MPI2_PHYSDISK0_COMPATIBLE (0x00)
1443#define MPI2_PHYSDISK0_INCOMPATIBLE_PROTOCOL (0x01)
1444#define MPI2_PHYSDISK0_INCOMPATIBLE_BLOCKSIZE (0x02)
1445#define MPI2_PHYSDISK0_INCOMPATIBLE_MAX_LBA (0x03)
1446#define MPI2_PHYSDISK0_INCOMPATIBLE_SATA_EXTENDED_CMD (0x04)
1447#define MPI2_PHYSDISK0_INCOMPATIBLE_REMOVEABLE_MEDIA (0x05)
1448#define MPI2_PHYSDISK0_INCOMPATIBLE_UNKNOWN (0xFF)
1449
1450/* PhysDiskAttributes defines */
1451#define MPI2_PHYSDISK0_ATTRIB_SOLID_STATE_DRIVE (0x08)
1452#define MPI2_PHYSDISK0_ATTRIB_HARD_DISK_DRIVE (0x04)
1453#define MPI2_PHYSDISK0_ATTRIB_SAS_PROTOCOL (0x02)
1454#define MPI2_PHYSDISK0_ATTRIB_SATA_PROTOCOL (0x01)
1455
1456/* PhysDiskStatusFlags defines */
1457#define MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED (0x00000040)
1458#define MPI2_PHYSDISK0_STATUS_FLAG_OCE_TARGET (0x00000020)
1459#define MPI2_PHYSDISK0_STATUS_FLAG_WRITE_CACHE_ENABLED (0x00000010)
1460#define MPI2_PHYSDISK0_STATUS_FLAG_OPTIMAL_PREVIOUS (0x00000000)
1461#define MPI2_PHYSDISK0_STATUS_FLAG_NOT_OPTIMAL_PREVIOUS (0x00000008)
1462#define MPI2_PHYSDISK0_STATUS_FLAG_INACTIVE_VOLUME (0x00000004)
1463#define MPI2_PHYSDISK0_STATUS_FLAG_QUIESCED (0x00000002)
1464#define MPI2_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC (0x00000001)
1465
1466
1467/* RAID Physical Disk Page 1 */
1468
1469/*
1470 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1471 * one and check Header.PageLength or NumPhysDiskPaths at runtime.
1472 */
1473#ifndef MPI2_RAID_PHYS_DISK1_PATH_MAX
1474#define MPI2_RAID_PHYS_DISK1_PATH_MAX (1)
1475#endif
1476
1477typedef struct _MPI2_RAIDPHYSDISK1_PATH
1478{
1479 U16 DevHandle; /* 0x00 */
1480 U16 Reserved1; /* 0x02 */
1481 U64 WWID; /* 0x04 */
1482 U64 OwnerWWID; /* 0x0C */
1483 U8 OwnerIdentifier; /* 0x14 */
1484 U8 Reserved2; /* 0x15 */
1485 U16 Flags; /* 0x16 */
1486} MPI2_RAIDPHYSDISK1_PATH, MPI2_POINTER PTR_MPI2_RAIDPHYSDISK1_PATH,
1487 Mpi2RaidPhysDisk1Path_t, MPI2_POINTER pMpi2RaidPhysDisk1Path_t;
1488
1489/* RAID Physical Disk Page 1 Physical Disk Path Flags field defines */
1490#define MPI2_RAID_PHYSDISK1_FLAG_PRIMARY (0x0004)
1491#define MPI2_RAID_PHYSDISK1_FLAG_BROKEN (0x0002)
1492#define MPI2_RAID_PHYSDISK1_FLAG_INVALID (0x0001)
1493
1494typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_1
1495{
1496 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1497 U8 NumPhysDiskPaths; /* 0x04 */
1498 U8 PhysDiskNum; /* 0x05 */
1499 U16 Reserved1; /* 0x06 */
1500 U32 Reserved2; /* 0x08 */
1501 MPI2_RAIDPHYSDISK1_PATH PhysicalDiskPath[MPI2_RAID_PHYS_DISK1_PATH_MAX];/* 0x0C */
1502} MPI2_CONFIG_PAGE_RD_PDISK_1,
1503 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RD_PDISK_1,
1504 Mpi2RaidPhysDiskPage1_t, MPI2_POINTER pMpi2RaidPhysDiskPage1_t;
1505
1506#define MPI2_RAIDPHYSDISKPAGE1_PAGEVERSION (0x02)
1507
1508
1509/****************************************************************************
1510* values for fields used by several types of SAS Config Pages
1511****************************************************************************/
1512
1513/* values for NegotiatedLinkRates fields */
1514#define MPI2_SAS_NEG_LINK_RATE_MASK_LOGICAL (0xF0)
1515#define MPI2_SAS_NEG_LINK_RATE_SHIFT_LOGICAL (4)
1516#define MPI2_SAS_NEG_LINK_RATE_MASK_PHYSICAL (0x0F)
1517/* link rates used for Negotiated Physical and Logical Link Rate */
1518#define MPI2_SAS_NEG_LINK_RATE_UNKNOWN_LINK_RATE (0x00)
1519#define MPI2_SAS_NEG_LINK_RATE_PHY_DISABLED (0x01)
1520#define MPI2_SAS_NEG_LINK_RATE_NEGOTIATION_FAILED (0x02)
1521#define MPI2_SAS_NEG_LINK_RATE_SATA_OOB_COMPLETE (0x03)
1522#define MPI2_SAS_NEG_LINK_RATE_PORT_SELECTOR (0x04)
1523#define MPI2_SAS_NEG_LINK_RATE_SMP_RESET_IN_PROGRESS (0x05)
1524#define MPI2_SAS_NEG_LINK_RATE_1_5 (0x08)
1525#define MPI2_SAS_NEG_LINK_RATE_3_0 (0x09)
1526#define MPI2_SAS_NEG_LINK_RATE_6_0 (0x0A)
1527
1528
1529/* values for AttachedPhyInfo fields */
1530#define MPI2_SAS_APHYINFO_INSIDE_ZPSDS_PERSISTENT (0x00000040)
1531#define MPI2_SAS_APHYINFO_REQUESTED_INSIDE_ZPSDS (0x00000020)
1532#define MPI2_SAS_APHYINFO_BREAK_REPLY_CAPABLE (0x00000010)
1533
1534#define MPI2_SAS_APHYINFO_REASON_MASK (0x0000000F)
1535#define MPI2_SAS_APHYINFO_REASON_UNKNOWN (0x00000000)
1536#define MPI2_SAS_APHYINFO_REASON_POWER_ON (0x00000001)
1537#define MPI2_SAS_APHYINFO_REASON_HARD_RESET (0x00000002)
1538#define MPI2_SAS_APHYINFO_REASON_SMP_PHY_CONTROL (0x00000003)
1539#define MPI2_SAS_APHYINFO_REASON_LOSS_OF_SYNC (0x00000004)
1540#define MPI2_SAS_APHYINFO_REASON_MULTIPLEXING_SEQ (0x00000005)
1541#define MPI2_SAS_APHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00000006)
1542#define MPI2_SAS_APHYINFO_REASON_BREAK_TIMEOUT (0x00000007)
1543#define MPI2_SAS_APHYINFO_REASON_PHY_TEST_STOPPED (0x00000008)
1544
1545
1546/* values for PhyInfo fields */
1547#define MPI2_SAS_PHYINFO_PHY_VACANT (0x80000000)
Kashyap, Desai9fec5f92009-09-23 17:26:20 +0530[diff] [blame]1548
1549#define MPI2_SAS_PHYINFO_PHY_POWER_CONDITION_MASK (0x18000000)
1550#define MPI2_SAS_PHYINFO_PHY_POWER_ACTIVE (0x00000000)
1551#define MPI2_SAS_PHYINFO_PHY_POWER_PARTIAL (0x08000000)
1552#define MPI2_SAS_PHYINFO_PHY_POWER_SLUMBER (0x10000000)
1553
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]1554#define MPI2_SAS_PHYINFO_CHANGED_REQ_INSIDE_ZPSDS (0x04000000)
1555#define MPI2_SAS_PHYINFO_INSIDE_ZPSDS_PERSISTENT (0x02000000)
1556#define MPI2_SAS_PHYINFO_REQ_INSIDE_ZPSDS (0x01000000)
1557#define MPI2_SAS_PHYINFO_ZONE_GROUP_PERSISTENT (0x00400000)
1558#define MPI2_SAS_PHYINFO_INSIDE_ZPSDS (0x00200000)
1559#define MPI2_SAS_PHYINFO_ZONING_ENABLED (0x00100000)
1560
1561#define MPI2_SAS_PHYINFO_REASON_MASK (0x000F0000)
1562#define MPI2_SAS_PHYINFO_REASON_UNKNOWN (0x00000000)
1563#define MPI2_SAS_PHYINFO_REASON_POWER_ON (0x00010000)
1564#define MPI2_SAS_PHYINFO_REASON_HARD_RESET (0x00020000)
1565#define MPI2_SAS_PHYINFO_REASON_SMP_PHY_CONTROL (0x00030000)
1566#define MPI2_SAS_PHYINFO_REASON_LOSS_OF_SYNC (0x00040000)
1567#define MPI2_SAS_PHYINFO_REASON_MULTIPLEXING_SEQ (0x00050000)
1568#define MPI2_SAS_PHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00060000)
1569#define MPI2_SAS_PHYINFO_REASON_BREAK_TIMEOUT (0x00070000)
1570#define MPI2_SAS_PHYINFO_REASON_PHY_TEST_STOPPED (0x00080000)
1571
1572#define MPI2_SAS_PHYINFO_MULTIPLEXING_SUPPORTED (0x00008000)
1573#define MPI2_SAS_PHYINFO_SATA_PORT_ACTIVE (0x00004000)
1574#define MPI2_SAS_PHYINFO_SATA_PORT_SELECTOR_PRESENT (0x00002000)
1575#define MPI2_SAS_PHYINFO_VIRTUAL_PHY (0x00001000)
1576
1577#define MPI2_SAS_PHYINFO_MASK_PARTIAL_PATHWAY_TIME (0x00000F00)
1578#define MPI2_SAS_PHYINFO_SHIFT_PARTIAL_PATHWAY_TIME (8)
1579
1580#define MPI2_SAS_PHYINFO_MASK_ROUTING_ATTRIBUTE (0x000000F0)
1581#define MPI2_SAS_PHYINFO_DIRECT_ROUTING (0x00000000)
1582#define MPI2_SAS_PHYINFO_SUBTRACTIVE_ROUTING (0x00000010)
1583#define MPI2_SAS_PHYINFO_TABLE_ROUTING (0x00000020)
1584
1585
1586/* values for SAS ProgrammedLinkRate fields */
1587#define MPI2_SAS_PRATE_MAX_RATE_MASK (0xF0)
1588#define MPI2_SAS_PRATE_MAX_RATE_NOT_PROGRAMMABLE (0x00)
1589#define MPI2_SAS_PRATE_MAX_RATE_1_5 (0x80)
1590#define MPI2_SAS_PRATE_MAX_RATE_3_0 (0x90)
1591#define MPI2_SAS_PRATE_MAX_RATE_6_0 (0xA0)
1592#define MPI2_SAS_PRATE_MIN_RATE_MASK (0x0F)
1593#define MPI2_SAS_PRATE_MIN_RATE_NOT_PROGRAMMABLE (0x00)
1594#define MPI2_SAS_PRATE_MIN_RATE_1_5 (0x08)
1595#define MPI2_SAS_PRATE_MIN_RATE_3_0 (0x09)
1596#define MPI2_SAS_PRATE_MIN_RATE_6_0 (0x0A)
1597
1598
1599/* values for SAS HwLinkRate fields */
1600#define MPI2_SAS_HWRATE_MAX_RATE_MASK (0xF0)
1601#define MPI2_SAS_HWRATE_MAX_RATE_1_5 (0x80)
1602#define MPI2_SAS_HWRATE_MAX_RATE_3_0 (0x90)
1603#define MPI2_SAS_HWRATE_MAX_RATE_6_0 (0xA0)
1604#define MPI2_SAS_HWRATE_MIN_RATE_MASK (0x0F)
1605#define MPI2_SAS_HWRATE_MIN_RATE_1_5 (0x08)
1606#define MPI2_SAS_HWRATE_MIN_RATE_3_0 (0x09)
1607#define MPI2_SAS_HWRATE_MIN_RATE_6_0 (0x0A)
1608
1609
1610
1611/****************************************************************************
1612* SAS IO Unit Config Pages
1613****************************************************************************/
1614
1615/* SAS IO Unit Page 0 */
1616
1617typedef struct _MPI2_SAS_IO_UNIT0_PHY_DATA
1618{
1619 U8 Port; /* 0x00 */
1620 U8 PortFlags; /* 0x01 */
1621 U8 PhyFlags; /* 0x02 */
1622 U8 NegotiatedLinkRate; /* 0x03 */
1623 U32 ControllerPhyDeviceInfo;/* 0x04 */
1624 U16 AttachedDevHandle; /* 0x08 */
1625 U16 ControllerDevHandle; /* 0x0A */
1626 U32 DiscoveryStatus; /* 0x0C */
1627 U32 Reserved; /* 0x10 */
1628} MPI2_SAS_IO_UNIT0_PHY_DATA, MPI2_POINTER PTR_MPI2_SAS_IO_UNIT0_PHY_DATA,
1629 Mpi2SasIOUnit0PhyData_t, MPI2_POINTER pMpi2SasIOUnit0PhyData_t;
1630
1631/*
1632 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1633 * one and check Header.ExtPageLength or NumPhys at runtime.
1634 */
1635#ifndef MPI2_SAS_IOUNIT0_PHY_MAX
1636#define MPI2_SAS_IOUNIT0_PHY_MAX (1)
1637#endif
1638
1639typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_0
1640{
1641 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
1642 U32 Reserved1; /* 0x08 */
1643 U8 NumPhys; /* 0x0C */
1644 U8 Reserved2; /* 0x0D */
1645 U16 Reserved3; /* 0x0E */
1646 MPI2_SAS_IO_UNIT0_PHY_DATA PhyData[MPI2_SAS_IOUNIT0_PHY_MAX]; /* 0x10 */
1647} MPI2_CONFIG_PAGE_SASIOUNIT_0,
1648 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_0,
1649 Mpi2SasIOUnitPage0_t, MPI2_POINTER pMpi2SasIOUnitPage0_t;
1650
1651#define MPI2_SASIOUNITPAGE0_PAGEVERSION (0x05)
1652
1653/* values for SAS IO Unit Page 0 PortFlags */
1654#define MPI2_SASIOUNIT0_PORTFLAGS_DISCOVERY_IN_PROGRESS (0x08)
1655#define MPI2_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG (0x01)
1656
1657/* values for SAS IO Unit Page 0 PhyFlags */
1658#define MPI2_SASIOUNIT0_PHYFLAGS_ZONING_ENABLED (0x10)
1659#define MPI2_SASIOUNIT0_PHYFLAGS_PHY_DISABLED (0x08)
1660
1661/* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
1662
1663/* see mpi2_sas.h for values for SAS IO Unit Page 0 ControllerPhyDeviceInfo values */
1664
1665/* values for SAS IO Unit Page 0 DiscoveryStatus */
1666#define MPI2_SASIOUNIT0_DS_MAX_ENCLOSURES_EXCEED (0x80000000)
1667#define MPI2_SASIOUNIT0_DS_MAX_EXPANDERS_EXCEED (0x40000000)
1668#define MPI2_SASIOUNIT0_DS_MAX_DEVICES_EXCEED (0x20000000)
1669#define MPI2_SASIOUNIT0_DS_MAX_TOPO_PHYS_EXCEED (0x10000000)
1670#define MPI2_SASIOUNIT0_DS_DOWNSTREAM_INITIATOR (0x08000000)
1671#define MPI2_SASIOUNIT0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000)
1672#define MPI2_SASIOUNIT0_DS_EXP_MULTI_SUBTRACTIVE (0x00004000)
1673#define MPI2_SASIOUNIT0_DS_MULTI_PORT_DOMAIN (0x00002000)
1674#define MPI2_SASIOUNIT0_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000)
1675#define MPI2_SASIOUNIT0_DS_UNSUPPORTED_DEVICE (0x00000800)
1676#define MPI2_SASIOUNIT0_DS_TABLE_LINK (0x00000400)
1677#define MPI2_SASIOUNIT0_DS_SUBTRACTIVE_LINK (0x00000200)
1678#define MPI2_SASIOUNIT0_DS_SMP_CRC_ERROR (0x00000100)
1679#define MPI2_SASIOUNIT0_DS_SMP_FUNCTION_FAILED (0x00000080)
1680#define MPI2_SASIOUNIT0_DS_INDEX_NOT_EXIST (0x00000040)
1681#define MPI2_SASIOUNIT0_DS_OUT_ROUTE_ENTRIES (0x00000020)
1682#define MPI2_SASIOUNIT0_DS_SMP_TIMEOUT (0x00000010)
1683#define MPI2_SASIOUNIT0_DS_MULTIPLE_PORTS (0x00000004)
1684#define MPI2_SASIOUNIT0_DS_UNADDRESSABLE_DEVICE (0x00000002)
1685#define MPI2_SASIOUNIT0_DS_LOOP_DETECTED (0x00000001)
1686
1687
1688/* SAS IO Unit Page 1 */
1689
1690typedef struct _MPI2_SAS_IO_UNIT1_PHY_DATA
1691{
1692 U8 Port; /* 0x00 */
1693 U8 PortFlags; /* 0x01 */
1694 U8 PhyFlags; /* 0x02 */
1695 U8 MaxMinLinkRate; /* 0x03 */
1696 U32 ControllerPhyDeviceInfo; /* 0x04 */
1697 U16 MaxTargetPortConnectTime; /* 0x08 */
1698 U16 Reserved1; /* 0x0A */
1699} MPI2_SAS_IO_UNIT1_PHY_DATA, MPI2_POINTER PTR_MPI2_SAS_IO_UNIT1_PHY_DATA,
1700 Mpi2SasIOUnit1PhyData_t, MPI2_POINTER pMpi2SasIOUnit1PhyData_t;
1701
1702/*
1703 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1704 * one and check Header.ExtPageLength or NumPhys at runtime.
1705 */
1706#ifndef MPI2_SAS_IOUNIT1_PHY_MAX
1707#define MPI2_SAS_IOUNIT1_PHY_MAX (1)
1708#endif
1709
1710typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_1
1711{
1712 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
1713 U16 ControlFlags; /* 0x08 */
1714 U16 SASNarrowMaxQueueDepth; /* 0x0A */
1715 U16 AdditionalControlFlags; /* 0x0C */
1716 U16 SASWideMaxQueueDepth; /* 0x0E */
1717 U8 NumPhys; /* 0x10 */
1718 U8 SATAMaxQDepth; /* 0x11 */
1719 U8 ReportDeviceMissingDelay; /* 0x12 */
1720 U8 IODeviceMissingDelay; /* 0x13 */
1721 MPI2_SAS_IO_UNIT1_PHY_DATA PhyData[MPI2_SAS_IOUNIT1_PHY_MAX]; /* 0x14 */
1722} MPI2_CONFIG_PAGE_SASIOUNIT_1,
1723 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_1,
1724 Mpi2SasIOUnitPage1_t, MPI2_POINTER pMpi2SasIOUnitPage1_t;
1725
1726#define MPI2_SASIOUNITPAGE1_PAGEVERSION (0x09)
1727
1728/* values for SAS IO Unit Page 1 ControlFlags */
1729#define MPI2_SASIOUNIT1_CONTROL_DEVICE_SELF_TEST (0x8000)
1730#define MPI2_SASIOUNIT1_CONTROL_SATA_3_0_MAX (0x4000)
1731#define MPI2_SASIOUNIT1_CONTROL_SATA_1_5_MAX (0x2000)
1732#define MPI2_SASIOUNIT1_CONTROL_SATA_SW_PRESERVE (0x1000)
1733
1734#define MPI2_SASIOUNIT1_CONTROL_MASK_DEV_SUPPORT (0x0600)
1735#define MPI2_SASIOUNIT1_CONTROL_SHIFT_DEV_SUPPORT (9)
1736#define MPI2_SASIOUNIT1_CONTROL_DEV_SUPPORT_BOTH (0x0)
1737#define MPI2_SASIOUNIT1_CONTROL_DEV_SAS_SUPPORT (0x1)
1738#define MPI2_SASIOUNIT1_CONTROL_DEV_SATA_SUPPORT (0x2)
1739
1740#define MPI2_SASIOUNIT1_CONTROL_SATA_48BIT_LBA_REQUIRED (0x0080)
1741#define MPI2_SASIOUNIT1_CONTROL_SATA_SMART_REQUIRED (0x0040)
1742#define MPI2_SASIOUNIT1_CONTROL_SATA_NCQ_REQUIRED (0x0020)
1743#define MPI2_SASIOUNIT1_CONTROL_SATA_FUA_REQUIRED (0x0010)
1744#define MPI2_SASIOUNIT1_CONTROL_TABLE_SUBTRACTIVE_ILLEGAL (0x0008)
1745#define MPI2_SASIOUNIT1_CONTROL_SUBTRACTIVE_ILLEGAL (0x0004)
1746#define MPI2_SASIOUNIT1_CONTROL_FIRST_LVL_DISC_ONLY (0x0002)
1747#define MPI2_SASIOUNIT1_CONTROL_CLEAR_AFFILIATION (0x0001)
1748
1749/* values for SAS IO Unit Page 1 AdditionalControlFlags */
1750#define MPI2_SASIOUNIT1_ACONTROL_MULTI_PORT_DOMAIN_ILLEGAL (0x0080)
1751#define MPI2_SASIOUNIT1_ACONTROL_SATA_ASYNCHROUNOUS_NOTIFICATION (0x0040)
1752#define MPI2_SASIOUNIT1_ACONTROL_INVALID_TOPOLOGY_CORRECTION (0x0020)
1753#define MPI2_SASIOUNIT1_ACONTROL_PORT_ENABLE_ONLY_SATA_LINK_RESET (0x0010)
1754#define MPI2_SASIOUNIT1_ACONTROL_OTHER_AFFILIATION_SATA_LINK_RESET (0x0008)
1755#define MPI2_SASIOUNIT1_ACONTROL_SELF_AFFILIATION_SATA_LINK_RESET (0x0004)
1756#define MPI2_SASIOUNIT1_ACONTROL_NO_AFFILIATION_SATA_LINK_RESET (0x0002)
1757#define MPI2_SASIOUNIT1_ACONTROL_ALLOW_TABLE_TO_TABLE (0x0001)
1758
1759/* defines for SAS IO Unit Page 1 ReportDeviceMissingDelay */
1760#define MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK (0x7F)
1761#define MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16 (0x80)
1762
1763/* values for SAS IO Unit Page 1 PortFlags */
1764#define MPI2_SASIOUNIT1_PORT_FLAGS_AUTO_PORT_CONFIG (0x01)
1765
Kashyap, Desai9fec5f92009-09-23 17:26:20 +0530[diff] [blame]1766/* values for SAS IO Unit Page 1 PhyFlags */
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]1767#define MPI2_SASIOUNIT1_PHYFLAGS_ZONING_ENABLE (0x10)
1768#define MPI2_SASIOUNIT1_PHYFLAGS_PHY_DISABLE (0x08)
1769
Kashyap, Desai9fec5f92009-09-23 17:26:20 +0530[diff] [blame]1770/* values for SAS IO Unit Page 1 MaxMinLinkRate */
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]1771#define MPI2_SASIOUNIT1_MAX_RATE_MASK (0xF0)
1772#define MPI2_SASIOUNIT1_MAX_RATE_1_5 (0x80)
1773#define MPI2_SASIOUNIT1_MAX_RATE_3_0 (0x90)
1774#define MPI2_SASIOUNIT1_MAX_RATE_6_0 (0xA0)
1775#define MPI2_SASIOUNIT1_MIN_RATE_MASK (0x0F)
1776#define MPI2_SASIOUNIT1_MIN_RATE_1_5 (0x08)
1777#define MPI2_SASIOUNIT1_MIN_RATE_3_0 (0x09)
1778#define MPI2_SASIOUNIT1_MIN_RATE_6_0 (0x0A)
1779
1780/* see mpi2_sas.h for values for SAS IO Unit Page 1 ControllerPhyDeviceInfo values */
1781
1782
1783/* SAS IO Unit Page 4 */
1784
1785typedef struct _MPI2_SAS_IOUNIT4_SPINUP_GROUP
1786{
1787 U8 MaxTargetSpinup; /* 0x00 */
1788 U8 SpinupDelay; /* 0x01 */
1789 U16 Reserved1; /* 0x02 */
1790} MPI2_SAS_IOUNIT4_SPINUP_GROUP, MPI2_POINTER PTR_MPI2_SAS_IOUNIT4_SPINUP_GROUP,
1791 Mpi2SasIOUnit4SpinupGroup_t, MPI2_POINTER pMpi2SasIOUnit4SpinupGroup_t;
1792
1793/*
1794 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1795 * four and check Header.ExtPageLength or NumPhys at runtime.
1796 */
1797#ifndef MPI2_SAS_IOUNIT4_PHY_MAX
1798#define MPI2_SAS_IOUNIT4_PHY_MAX (4)
1799#endif
1800
1801typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_4
1802{
1803 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
1804 MPI2_SAS_IOUNIT4_SPINUP_GROUP SpinupGroupParameters[4]; /* 0x08 */
1805 U32 Reserved1; /* 0x18 */
1806 U32 Reserved2; /* 0x1C */
1807 U32 Reserved3; /* 0x20 */
1808 U8 BootDeviceWaitTime; /* 0x24 */
1809 U8 Reserved4; /* 0x25 */
1810 U16 Reserved5; /* 0x26 */
1811 U8 NumPhys; /* 0x28 */
1812 U8 PEInitialSpinupDelay; /* 0x29 */
1813 U8 PEReplyDelay; /* 0x2A */
1814 U8 Flags; /* 0x2B */
1815 U8 PHY[MPI2_SAS_IOUNIT4_PHY_MAX]; /* 0x2C */
1816} MPI2_CONFIG_PAGE_SASIOUNIT_4,
1817 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_4,
1818 Mpi2SasIOUnitPage4_t, MPI2_POINTER pMpi2SasIOUnitPage4_t;
1819
1820#define MPI2_SASIOUNITPAGE4_PAGEVERSION (0x02)
1821
1822/* defines for Flags field */
1823#define MPI2_SASIOUNIT4_FLAGS_AUTO_PORTENABLE (0x01)
1824
1825/* defines for PHY field */
1826#define MPI2_SASIOUNIT4_PHY_SPINUP_GROUP_MASK (0x03)
1827
1828
Kashyap, Desai9fec5f92009-09-23 17:26:20 +0530[diff] [blame]1829/* SAS IO Unit Page 5 */
1830
1831typedef struct _MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS {
1832 U8 ControlFlags; /* 0x00 */
1833 U8 Reserved1; /* 0x01 */
1834 U16 InactivityTimerExponent; /* 0x02 */
1835 U8 SATAPartialTimeout; /* 0x04 */
1836 U8 Reserved2; /* 0x05 */
1837 U8 SATASlumberTimeout; /* 0x06 */
1838 U8 Reserved3; /* 0x07 */
1839 U8 SASPartialTimeout; /* 0x08 */
1840 U8 Reserved4; /* 0x09 */
1841 U8 SASSlumberTimeout; /* 0x0A */
1842 U8 Reserved5; /* 0x0B */
1843} MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS,
1844 MPI2_POINTER PTR_MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS,
1845 Mpi2SasIOUnit5PhyPmSettings_t, MPI2_POINTER pMpi2SasIOUnit5PhyPmSettings_t;
1846
1847/* defines for ControlFlags field */
1848#define MPI2_SASIOUNIT5_CONTROL_SAS_SLUMBER_ENABLE (0x08)
1849#define MPI2_SASIOUNIT5_CONTROL_SAS_PARTIAL_ENABLE (0x04)
1850#define MPI2_SASIOUNIT5_CONTROL_SATA_SLUMBER_ENABLE (0x02)
1851#define MPI2_SASIOUNIT5_CONTROL_SATA_PARTIAL_ENABLE (0x01)
1852
1853/* defines for InactivityTimerExponent field */
1854#define MPI2_SASIOUNIT5_ITE_MASK_SAS_SLUMBER (0x7000)
1855#define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_SLUMBER (12)
1856#define MPI2_SASIOUNIT5_ITE_MASK_SAS_PARTIAL (0x0700)
1857#define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_PARTIAL (8)
1858#define MPI2_SASIOUNIT5_ITE_MASK_SATA_SLUMBER (0x0070)
1859#define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_SLUMBER (4)
1860#define MPI2_SASIOUNIT5_ITE_MASK_SATA_PARTIAL (0x0007)
1861#define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_PARTIAL (0)
1862
1863#define MPI2_SASIOUNIT5_ITE_TEN_SECONDS (7)
1864#define MPI2_SASIOUNIT5_ITE_ONE_SECOND (6)
1865#define MPI2_SASIOUNIT5_ITE_HUNDRED_MILLISECONDS (5)
1866#define MPI2_SASIOUNIT5_ITE_TEN_MILLISECONDS (4)
1867#define MPI2_SASIOUNIT5_ITE_ONE_MILLISECOND (3)
1868#define MPI2_SASIOUNIT5_ITE_HUNDRED_MICROSECONDS (2)
1869#define MPI2_SASIOUNIT5_ITE_TEN_MICROSECONDS (1)
1870#define MPI2_SASIOUNIT5_ITE_ONE_MICROSECOND (0)
1871
1872/*
1873 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1874 * one and check Header.ExtPageLength or NumPhys at runtime.
1875 */
1876#ifndef MPI2_SAS_IOUNIT5_PHY_MAX
1877#define MPI2_SAS_IOUNIT5_PHY_MAX (1)
1878#endif
1879
1880typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_5 {
1881 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
1882 U8 NumPhys; /* 0x08 */
1883 U8 Reserved1; /* 0x09 */
1884 U16 Reserved2; /* 0x0A */
1885 U32 Reserved3; /* 0x0C */
1886 MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS SASPhyPowerManagementSettings
1887 [MPI2_SAS_IOUNIT5_PHY_MAX]; /* 0x10 */
1888} MPI2_CONFIG_PAGE_SASIOUNIT_5,
1889 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_5,
1890 Mpi2SasIOUnitPage5_t, MPI2_POINTER pMpi2SasIOUnitPage5_t;
1891
1892#define MPI2_SASIOUNITPAGE5_PAGEVERSION (0x00)
1893
1894
1895
1896
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]1897/****************************************************************************
1898* SAS Expander Config Pages
1899****************************************************************************/
1900
1901/* SAS Expander Page 0 */
1902
1903typedef struct _MPI2_CONFIG_PAGE_EXPANDER_0
1904{
1905 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
1906 U8 PhysicalPort; /* 0x08 */
1907 U8 ReportGenLength; /* 0x09 */
1908 U16 EnclosureHandle; /* 0x0A */
1909 U64 SASAddress; /* 0x0C */
1910 U32 DiscoveryStatus; /* 0x14 */
1911 U16 DevHandle; /* 0x18 */
1912 U16 ParentDevHandle; /* 0x1A */
1913 U16 ExpanderChangeCount; /* 0x1C */
1914 U16 ExpanderRouteIndexes; /* 0x1E */
1915 U8 NumPhys; /* 0x20 */
1916 U8 SASLevel; /* 0x21 */
1917 U16 Flags; /* 0x22 */
1918 U16 STPBusInactivityTimeLimit; /* 0x24 */
1919 U16 STPMaxConnectTimeLimit; /* 0x26 */
1920 U16 STP_SMP_NexusLossTime; /* 0x28 */
1921 U16 MaxNumRoutedSasAddresses; /* 0x2A */
1922 U64 ActiveZoneManagerSASAddress;/* 0x2C */
1923 U16 ZoneLockInactivityLimit; /* 0x34 */
1924 U16 Reserved1; /* 0x36 */
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]1925 U8 TimeToReducedFunc; /* 0x38 */
1926 U8 InitialTimeToReducedFunc; /* 0x39 */
1927 U8 MaxReducedFuncTime; /* 0x3A */
1928 U8 Reserved2; /* 0x3B */
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]1929} MPI2_CONFIG_PAGE_EXPANDER_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_EXPANDER_0,
1930 Mpi2ExpanderPage0_t, MPI2_POINTER pMpi2ExpanderPage0_t;
1931
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]1932#define MPI2_SASEXPANDER0_PAGEVERSION (0x06)
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]1933
1934/* values for SAS Expander Page 0 DiscoveryStatus field */
1935#define MPI2_SAS_EXPANDER0_DS_MAX_ENCLOSURES_EXCEED (0x80000000)
1936#define MPI2_SAS_EXPANDER0_DS_MAX_EXPANDERS_EXCEED (0x40000000)
1937#define MPI2_SAS_EXPANDER0_DS_MAX_DEVICES_EXCEED (0x20000000)
1938#define MPI2_SAS_EXPANDER0_DS_MAX_TOPO_PHYS_EXCEED (0x10000000)
1939#define MPI2_SAS_EXPANDER0_DS_DOWNSTREAM_INITIATOR (0x08000000)
1940#define MPI2_SAS_EXPANDER0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000)
1941#define MPI2_SAS_EXPANDER0_DS_EXP_MULTI_SUBTRACTIVE (0x00004000)
1942#define MPI2_SAS_EXPANDER0_DS_MULTI_PORT_DOMAIN (0x00002000)
1943#define MPI2_SAS_EXPANDER0_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000)
1944#define MPI2_SAS_EXPANDER0_DS_UNSUPPORTED_DEVICE (0x00000800)
1945#define MPI2_SAS_EXPANDER0_DS_TABLE_LINK (0x00000400)
1946#define MPI2_SAS_EXPANDER0_DS_SUBTRACTIVE_LINK (0x00000200)
1947#define MPI2_SAS_EXPANDER0_DS_SMP_CRC_ERROR (0x00000100)
1948#define MPI2_SAS_EXPANDER0_DS_SMP_FUNCTION_FAILED (0x00000080)
1949#define MPI2_SAS_EXPANDER0_DS_INDEX_NOT_EXIST (0x00000040)
1950#define MPI2_SAS_EXPANDER0_DS_OUT_ROUTE_ENTRIES (0x00000020)
1951#define MPI2_SAS_EXPANDER0_DS_SMP_TIMEOUT (0x00000010)
1952#define MPI2_SAS_EXPANDER0_DS_MULTIPLE_PORTS (0x00000004)
1953#define MPI2_SAS_EXPANDER0_DS_UNADDRESSABLE_DEVICE (0x00000002)
1954#define MPI2_SAS_EXPANDER0_DS_LOOP_DETECTED (0x00000001)
1955
1956/* values for SAS Expander Page 0 Flags field */
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]1957#define MPI2_SAS_EXPANDER0_FLAGS_REDUCED_FUNCTIONALITY (0x2000)
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]1958#define MPI2_SAS_EXPANDER0_FLAGS_ZONE_LOCKED (0x1000)
1959#define MPI2_SAS_EXPANDER0_FLAGS_SUPPORTED_PHYSICAL_PRES (0x0800)
1960#define MPI2_SAS_EXPANDER0_FLAGS_ASSERTED_PHYSICAL_PRES (0x0400)
1961#define MPI2_SAS_EXPANDER0_FLAGS_ZONING_SUPPORT (0x0200)
1962#define MPI2_SAS_EXPANDER0_FLAGS_ENABLED_ZONING (0x0100)
1963#define MPI2_SAS_EXPANDER0_FLAGS_TABLE_TO_TABLE_SUPPORT (0x0080)
1964#define MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE (0x0010)
1965#define MPI2_SAS_EXPANDER0_FLAGS_OTHERS_CONFIG (0x0004)
1966#define MPI2_SAS_EXPANDER0_FLAGS_CONFIG_IN_PROGRESS (0x0002)
1967#define MPI2_SAS_EXPANDER0_FLAGS_ROUTE_TABLE_CONFIG (0x0001)
1968
1969
1970/* SAS Expander Page 1 */
1971
1972typedef struct _MPI2_CONFIG_PAGE_EXPANDER_1
1973{
1974 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
1975 U8 PhysicalPort; /* 0x08 */
1976 U8 Reserved1; /* 0x09 */
1977 U16 Reserved2; /* 0x0A */
1978 U8 NumPhys; /* 0x0C */
1979 U8 Phy; /* 0x0D */
1980 U16 NumTableEntriesProgrammed; /* 0x0E */
1981 U8 ProgrammedLinkRate; /* 0x10 */
1982 U8 HwLinkRate; /* 0x11 */
1983 U16 AttachedDevHandle; /* 0x12 */
1984 U32 PhyInfo; /* 0x14 */
1985 U32 AttachedDeviceInfo; /* 0x18 */
1986 U16 ExpanderDevHandle; /* 0x1C */
1987 U8 ChangeCount; /* 0x1E */
1988 U8 NegotiatedLinkRate; /* 0x1F */
1989 U8 PhyIdentifier; /* 0x20 */
1990 U8 AttachedPhyIdentifier; /* 0x21 */
1991 U8 Reserved3; /* 0x22 */
1992 U8 DiscoveryInfo; /* 0x23 */
1993 U32 AttachedPhyInfo; /* 0x24 */
1994 U8 ZoneGroup; /* 0x28 */
1995 U8 SelfConfigStatus; /* 0x29 */
1996 U16 Reserved4; /* 0x2A */
1997} MPI2_CONFIG_PAGE_EXPANDER_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_EXPANDER_1,
1998 Mpi2ExpanderPage1_t, MPI2_POINTER pMpi2ExpanderPage1_t;
1999
2000#define MPI2_SASEXPANDER1_PAGEVERSION (0x02)
2001
2002/* use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */
2003
2004/* use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */
2005
2006/* use MPI2_SAS_PHYINFO_ for the PhyInfo field */
2007
2008/* see mpi2_sas.h for the MPI2_SAS_DEVICE_INFO_ defines used for the AttachedDeviceInfo field */
2009
2010/* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
2011
2012/* use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */
2013
2014/* values for SAS Expander Page 1 DiscoveryInfo field */
2015#define MPI2_SAS_EXPANDER1_DISCINFO_BAD_PHY_DISABLED (0x04)
2016#define MPI2_SAS_EXPANDER1_DISCINFO_LINK_STATUS_CHANGE (0x02)
2017#define MPI2_SAS_EXPANDER1_DISCINFO_NO_ROUTING_ENTRIES (0x01)
2018
2019
2020/****************************************************************************
2021* SAS Device Config Pages
2022****************************************************************************/
2023
2024/* SAS Device Page 0 */
2025
2026typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_0
2027{
2028 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2029 U16 Slot; /* 0x08 */
2030 U16 EnclosureHandle; /* 0x0A */
2031 U64 SASAddress; /* 0x0C */
2032 U16 ParentDevHandle; /* 0x14 */
2033 U8 PhyNum; /* 0x16 */
2034 U8 AccessStatus; /* 0x17 */
2035 U16 DevHandle; /* 0x18 */
2036 U8 AttachedPhyIdentifier; /* 0x1A */
2037 U8 ZoneGroup; /* 0x1B */
2038 U32 DeviceInfo; /* 0x1C */
2039 U16 Flags; /* 0x20 */
2040 U8 PhysicalPort; /* 0x22 */
2041 U8 MaxPortConnections; /* 0x23 */
2042 U64 DeviceName; /* 0x24 */
2043 U8 PortGroups; /* 0x2C */
2044 U8 DmaGroup; /* 0x2D */
2045 U8 ControlGroup; /* 0x2E */
2046 U8 Reserved1; /* 0x2F */
2047 U32 Reserved2; /* 0x30 */
2048 U32 Reserved3; /* 0x34 */
2049} MPI2_CONFIG_PAGE_SAS_DEV_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_DEV_0,
2050 Mpi2SasDevicePage0_t, MPI2_POINTER pMpi2SasDevicePage0_t;
2051
2052#define MPI2_SASDEVICE0_PAGEVERSION (0x08)
2053
2054/* values for SAS Device Page 0 AccessStatus field */
2055#define MPI2_SAS_DEVICE0_ASTATUS_NO_ERRORS (0x00)
2056#define MPI2_SAS_DEVICE0_ASTATUS_SATA_INIT_FAILED (0x01)
2057#define MPI2_SAS_DEVICE0_ASTATUS_SATA_CAPABILITY_FAILED (0x02)
2058#define MPI2_SAS_DEVICE0_ASTATUS_SATA_AFFILIATION_CONFLICT (0x03)
2059#define MPI2_SAS_DEVICE0_ASTATUS_SATA_NEEDS_INITIALIZATION (0x04)
2060#define MPI2_SAS_DEVICE0_ASTATUS_ROUTE_NOT_ADDRESSABLE (0x05)
2061#define MPI2_SAS_DEVICE0_ASTATUS_SMP_ERROR_NOT_ADDRESSABLE (0x06)
2062#define MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED (0x07)
2063/* specific values for SATA Init failures */
2064#define MPI2_SAS_DEVICE0_ASTATUS_SIF_UNKNOWN (0x10)
2065#define MPI2_SAS_DEVICE0_ASTATUS_SIF_AFFILIATION_CONFLICT (0x11)
2066#define MPI2_SAS_DEVICE0_ASTATUS_SIF_DIAG (0x12)
2067#define MPI2_SAS_DEVICE0_ASTATUS_SIF_IDENTIFICATION (0x13)
2068#define MPI2_SAS_DEVICE0_ASTATUS_SIF_CHECK_POWER (0x14)
2069#define MPI2_SAS_DEVICE0_ASTATUS_SIF_PIO_SN (0x15)
2070#define MPI2_SAS_DEVICE0_ASTATUS_SIF_MDMA_SN (0x16)
2071#define MPI2_SAS_DEVICE0_ASTATUS_SIF_UDMA_SN (0x17)
2072#define MPI2_SAS_DEVICE0_ASTATUS_SIF_ZONING_VIOLATION (0x18)
2073#define MPI2_SAS_DEVICE0_ASTATUS_SIF_NOT_ADDRESSABLE (0x19)
2074#define MPI2_SAS_DEVICE0_ASTATUS_SIF_MAX (0x1F)
2075
2076/* see mpi2_sas.h for values for SAS Device Page 0 DeviceInfo values */
2077
2078/* values for SAS Device Page 0 Flags field */
Kashyap, Desai9fec5f92009-09-23 17:26:20 +0530[diff] [blame]2079#define MPI2_SAS_DEVICE0_FLAGS_SLUMBER_PM_CAPABLE (0x1000)
2080#define MPI2_SAS_DEVICE0_FLAGS_PARTIAL_PM_CAPABLE (0x0800)
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]2081#define MPI2_SAS_DEVICE0_FLAGS_SATA_ASYNCHRONOUS_NOTIFY (0x0400)
2082#define MPI2_SAS_DEVICE0_FLAGS_SATA_SW_PRESERVE (0x0200)
2083#define MPI2_SAS_DEVICE0_FLAGS_UNSUPPORTED_DEVICE (0x0100)
2084#define MPI2_SAS_DEVICE0_FLAGS_SATA_48BIT_LBA_SUPPORTED (0x0080)
2085#define MPI2_SAS_DEVICE0_FLAGS_SATA_SMART_SUPPORTED (0x0040)
2086#define MPI2_SAS_DEVICE0_FLAGS_SATA_NCQ_SUPPORTED (0x0020)
2087#define MPI2_SAS_DEVICE0_FLAGS_SATA_FUA_SUPPORTED (0x0010)
2088#define MPI2_SAS_DEVICE0_FLAGS_PORT_SELECTOR_ATTACH (0x0008)
2089#define MPI2_SAS_DEVICE0_FLAGS_DEVICE_PRESENT (0x0001)
2090
2091
2092/* SAS Device Page 1 */
2093
2094typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_1
2095{
2096 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2097 U32 Reserved1; /* 0x08 */
2098 U64 SASAddress; /* 0x0C */
2099 U32 Reserved2; /* 0x14 */
2100 U16 DevHandle; /* 0x18 */
2101 U16 Reserved3; /* 0x1A */
2102 U8 InitialRegDeviceFIS[20];/* 0x1C */
2103} MPI2_CONFIG_PAGE_SAS_DEV_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_DEV_1,
2104 Mpi2SasDevicePage1_t, MPI2_POINTER pMpi2SasDevicePage1_t;
2105
2106#define MPI2_SASDEVICE1_PAGEVERSION (0x01)
2107
2108
2109/****************************************************************************
2110* SAS PHY Config Pages
2111****************************************************************************/
2112
2113/* SAS PHY Page 0 */
2114
2115typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_0
2116{
2117 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2118 U16 OwnerDevHandle; /* 0x08 */
2119 U16 Reserved1; /* 0x0A */
2120 U16 AttachedDevHandle; /* 0x0C */
2121 U8 AttachedPhyIdentifier; /* 0x0E */
2122 U8 Reserved2; /* 0x0F */
2123 U32 AttachedPhyInfo; /* 0x10 */
2124 U8 ProgrammedLinkRate; /* 0x14 */
2125 U8 HwLinkRate; /* 0x15 */
2126 U8 ChangeCount; /* 0x16 */
2127 U8 Flags; /* 0x17 */
2128 U32 PhyInfo; /* 0x18 */
2129 U8 NegotiatedLinkRate; /* 0x1C */
2130 U8 Reserved3; /* 0x1D */
2131 U16 Reserved4; /* 0x1E */
2132} MPI2_CONFIG_PAGE_SAS_PHY_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_0,
2133 Mpi2SasPhyPage0_t, MPI2_POINTER pMpi2SasPhyPage0_t;
2134
2135#define MPI2_SASPHY0_PAGEVERSION (0x03)
2136
2137/* use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */
2138
2139/* use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */
2140
2141/* values for SAS PHY Page 0 Flags field */
2142#define MPI2_SAS_PHY0_FLAGS_SGPIO_DIRECT_ATTACH_ENC (0x01)
2143
2144/* use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */
2145
2146/* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
2147
2148/* use MPI2_SAS_PHYINFO_ for the PhyInfo field */
2149
2150
2151/* SAS PHY Page 1 */
2152
2153typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_1
2154{
2155 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2156 U32 Reserved1; /* 0x08 */
2157 U32 InvalidDwordCount; /* 0x0C */
2158 U32 RunningDisparityErrorCount; /* 0x10 */
2159 U32 LossDwordSynchCount; /* 0x14 */
2160 U32 PhyResetProblemCount; /* 0x18 */
2161} MPI2_CONFIG_PAGE_SAS_PHY_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_1,
2162 Mpi2SasPhyPage1_t, MPI2_POINTER pMpi2SasPhyPage1_t;
2163
2164#define MPI2_SASPHY1_PAGEVERSION (0x01)
2165
2166
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]2167/* SAS PHY Page 2 */
2168
2169typedef struct _MPI2_SASPHY2_PHY_EVENT {
2170 U8 PhyEventCode; /* 0x00 */
2171 U8 Reserved1; /* 0x01 */
2172 U16 Reserved2; /* 0x02 */
2173 U32 PhyEventInfo; /* 0x04 */
2174} MPI2_SASPHY2_PHY_EVENT, MPI2_POINTER PTR_MPI2_SASPHY2_PHY_EVENT,
2175 Mpi2SasPhy2PhyEvent_t, MPI2_POINTER pMpi2SasPhy2PhyEvent_t;
2176
2177/* use MPI2_SASPHY3_EVENT_CODE_ for the PhyEventCode field */
2178
2179
2180/*
2181 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2182 * one and check Header.ExtPageLength or NumPhyEvents at runtime.
2183 */
2184#ifndef MPI2_SASPHY2_PHY_EVENT_MAX
2185#define MPI2_SASPHY2_PHY_EVENT_MAX (1)
2186#endif
2187
2188typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_2 {
2189 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2190 U32 Reserved1; /* 0x08 */
2191 U8 NumPhyEvents; /* 0x0C */
2192 U8 Reserved2; /* 0x0D */
2193 U16 Reserved3; /* 0x0E */
2194 MPI2_SASPHY2_PHY_EVENT PhyEvent[MPI2_SASPHY2_PHY_EVENT_MAX];
2195 /* 0x10 */
2196} MPI2_CONFIG_PAGE_SAS_PHY_2, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_2,
2197 Mpi2SasPhyPage2_t, MPI2_POINTER pMpi2SasPhyPage2_t;
2198
2199#define MPI2_SASPHY2_PAGEVERSION (0x00)
2200
2201
2202/* SAS PHY Page 3 */
2203
2204typedef struct _MPI2_SASPHY3_PHY_EVENT_CONFIG {
2205 U8 PhyEventCode; /* 0x00 */
2206 U8 Reserved1; /* 0x01 */
2207 U16 Reserved2; /* 0x02 */
2208 U8 CounterType; /* 0x04 */
2209 U8 ThresholdWindow; /* 0x05 */
2210 U8 TimeUnits; /* 0x06 */
2211 U8 Reserved3; /* 0x07 */
2212 U32 EventThreshold; /* 0x08 */
2213 U16 ThresholdFlags; /* 0x0C */
2214 U16 Reserved4; /* 0x0E */
2215} MPI2_SASPHY3_PHY_EVENT_CONFIG, MPI2_POINTER PTR_MPI2_SASPHY3_PHY_EVENT_CONFIG,
2216 Mpi2SasPhy3PhyEventConfig_t, MPI2_POINTER pMpi2SasPhy3PhyEventConfig_t;
2217
2218/* values for PhyEventCode field */
2219#define MPI2_SASPHY3_EVENT_CODE_NO_EVENT (0x00)
2220#define MPI2_SASPHY3_EVENT_CODE_INVALID_DWORD (0x01)
2221#define MPI2_SASPHY3_EVENT_CODE_RUNNING_DISPARITY_ERROR (0x02)
2222#define MPI2_SASPHY3_EVENT_CODE_LOSS_DWORD_SYNC (0x03)
2223#define MPI2_SASPHY3_EVENT_CODE_PHY_RESET_PROBLEM (0x04)
2224#define MPI2_SASPHY3_EVENT_CODE_ELASTICITY_BUF_OVERFLOW (0x05)
2225#define MPI2_SASPHY3_EVENT_CODE_RX_ERROR (0x06)
2226#define MPI2_SASPHY3_EVENT_CODE_RX_ADDR_FRAME_ERROR (0x20)
2227#define MPI2_SASPHY3_EVENT_CODE_TX_AC_OPEN_REJECT (0x21)
2228#define MPI2_SASPHY3_EVENT_CODE_RX_AC_OPEN_REJECT (0x22)
2229#define MPI2_SASPHY3_EVENT_CODE_TX_RC_OPEN_REJECT (0x23)
2230#define MPI2_SASPHY3_EVENT_CODE_RX_RC_OPEN_REJECT (0x24)
2231#define MPI2_SASPHY3_EVENT_CODE_RX_AIP_PARTIAL_WAITING_ON (0x25)
2232#define MPI2_SASPHY3_EVENT_CODE_RX_AIP_CONNECT_WAITING_ON (0x26)
2233#define MPI2_SASPHY3_EVENT_CODE_TX_BREAK (0x27)
2234#define MPI2_SASPHY3_EVENT_CODE_RX_BREAK (0x28)
2235#define MPI2_SASPHY3_EVENT_CODE_BREAK_TIMEOUT (0x29)
2236#define MPI2_SASPHY3_EVENT_CODE_CONNECTION (0x2A)
2237#define MPI2_SASPHY3_EVENT_CODE_PEAKTX_PATHWAY_BLOCKED (0x2B)
2238#define MPI2_SASPHY3_EVENT_CODE_PEAKTX_ARB_WAIT_TIME (0x2C)
2239#define MPI2_SASPHY3_EVENT_CODE_PEAK_ARB_WAIT_TIME (0x2D)
2240#define MPI2_SASPHY3_EVENT_CODE_PEAK_CONNECT_TIME (0x2E)
2241#define MPI2_SASPHY3_EVENT_CODE_TX_SSP_FRAMES (0x40)
2242#define MPI2_SASPHY3_EVENT_CODE_RX_SSP_FRAMES (0x41)
2243#define MPI2_SASPHY3_EVENT_CODE_TX_SSP_ERROR_FRAMES (0x42)
2244#define MPI2_SASPHY3_EVENT_CODE_RX_SSP_ERROR_FRAMES (0x43)
2245#define MPI2_SASPHY3_EVENT_CODE_TX_CREDIT_BLOCKED (0x44)
2246#define MPI2_SASPHY3_EVENT_CODE_RX_CREDIT_BLOCKED (0x45)
2247#define MPI2_SASPHY3_EVENT_CODE_TX_SATA_FRAMES (0x50)
2248#define MPI2_SASPHY3_EVENT_CODE_RX_SATA_FRAMES (0x51)
2249#define MPI2_SASPHY3_EVENT_CODE_SATA_OVERFLOW (0x52)
2250#define MPI2_SASPHY3_EVENT_CODE_TX_SMP_FRAMES (0x60)
2251#define MPI2_SASPHY3_EVENT_CODE_RX_SMP_FRAMES (0x61)
2252#define MPI2_SASPHY3_EVENT_CODE_RX_SMP_ERROR_FRAMES (0x63)
2253#define MPI2_SASPHY3_EVENT_CODE_HOTPLUG_TIMEOUT (0xD0)
2254#define MPI2_SASPHY3_EVENT_CODE_MISALIGNED_MUX_PRIMITIVE (0xD1)
2255#define MPI2_SASPHY3_EVENT_CODE_RX_AIP (0xD2)
2256
2257/* values for the CounterType field */
2258#define MPI2_SASPHY3_COUNTER_TYPE_WRAPPING (0x00)
2259#define MPI2_SASPHY3_COUNTER_TYPE_SATURATING (0x01)
2260#define MPI2_SASPHY3_COUNTER_TYPE_PEAK_VALUE (0x02)
2261
2262/* values for the TimeUnits field */
2263#define MPI2_SASPHY3_TIME_UNITS_10_MICROSECONDS (0x00)
2264#define MPI2_SASPHY3_TIME_UNITS_100_MICROSECONDS (0x01)
2265#define MPI2_SASPHY3_TIME_UNITS_1_MILLISECOND (0x02)
2266#define MPI2_SASPHY3_TIME_UNITS_10_MILLISECONDS (0x03)
2267
2268/* values for the ThresholdFlags field */
2269#define MPI2_SASPHY3_TFLAGS_PHY_RESET (0x0002)
2270#define MPI2_SASPHY3_TFLAGS_EVENT_NOTIFY (0x0001)
2271
2272/*
2273 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2274 * one and check Header.ExtPageLength or NumPhyEvents at runtime.
2275 */
2276#ifndef MPI2_SASPHY3_PHY_EVENT_MAX
2277#define MPI2_SASPHY3_PHY_EVENT_MAX (1)
2278#endif
2279
2280typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_3 {
2281 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2282 U32 Reserved1; /* 0x08 */
2283 U8 NumPhyEvents; /* 0x0C */
2284 U8 Reserved2; /* 0x0D */
2285 U16 Reserved3; /* 0x0E */
2286 MPI2_SASPHY3_PHY_EVENT_CONFIG PhyEventConfig
2287 [MPI2_SASPHY3_PHY_EVENT_MAX]; /* 0x10 */
2288} MPI2_CONFIG_PAGE_SAS_PHY_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_3,
2289 Mpi2SasPhyPage3_t, MPI2_POINTER pMpi2SasPhyPage3_t;
2290
2291#define MPI2_SASPHY3_PAGEVERSION (0x00)
2292
2293
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]2294/****************************************************************************
2295* SAS Port Config Pages
2296****************************************************************************/
2297
2298/* SAS Port Page 0 */
2299
2300typedef struct _MPI2_CONFIG_PAGE_SAS_PORT_0
2301{
2302 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2303 U8 PortNumber; /* 0x08 */
2304 U8 PhysicalPort; /* 0x09 */
2305 U8 PortWidth; /* 0x0A */
2306 U8 PhysicalPortWidth; /* 0x0B */
2307 U8 ZoneGroup; /* 0x0C */
2308 U8 Reserved1; /* 0x0D */
2309 U16 Reserved2; /* 0x0E */
2310 U64 SASAddress; /* 0x10 */
2311 U32 DeviceInfo; /* 0x18 */
2312 U32 Reserved3; /* 0x1C */
2313 U32 Reserved4; /* 0x20 */
2314} MPI2_CONFIG_PAGE_SAS_PORT_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PORT_0,
2315 Mpi2SasPortPage0_t, MPI2_POINTER pMpi2SasPortPage0_t;
2316
2317#define MPI2_SASPORT0_PAGEVERSION (0x00)
2318
2319/* see mpi2_sas.h for values for SAS Port Page 0 DeviceInfo values */
2320
2321
2322/****************************************************************************
2323* SAS Enclosure Config Pages
2324****************************************************************************/
2325
2326/* SAS Enclosure Page 0 */
2327
2328typedef struct _MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0
2329{
2330 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2331 U32 Reserved1; /* 0x08 */
2332 U64 EnclosureLogicalID; /* 0x0C */
2333 U16 Flags; /* 0x14 */
2334 U16 EnclosureHandle; /* 0x16 */
2335 U16 NumSlots; /* 0x18 */
2336 U16 StartSlot; /* 0x1A */
2337 U16 Reserved2; /* 0x1C */
2338 U16 SEPDevHandle; /* 0x1E */
2339 U32 Reserved3; /* 0x20 */
2340 U32 Reserved4; /* 0x24 */
2341} MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0,
2342 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0,
2343 Mpi2SasEnclosurePage0_t, MPI2_POINTER pMpi2SasEnclosurePage0_t;
2344
2345#define MPI2_SASENCLOSURE0_PAGEVERSION (0x03)
2346
2347/* values for SAS Enclosure Page 0 Flags field */
2348#define MPI2_SAS_ENCLS0_FLAGS_MNG_MASK (0x000F)
2349#define MPI2_SAS_ENCLS0_FLAGS_MNG_UNKNOWN (0x0000)
2350#define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SES (0x0001)
2351#define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SGPIO (0x0002)
2352#define MPI2_SAS_ENCLS0_FLAGS_MNG_EXP_SGPIO (0x0003)
2353#define MPI2_SAS_ENCLS0_FLAGS_MNG_SES_ENCLOSURE (0x0004)
2354#define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_GPIO (0x0005)
2355
2356
2357/****************************************************************************
2358* Log Config Page
2359****************************************************************************/
2360
2361/* Log Page 0 */
2362
2363/*
2364 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2365 * one and check Header.ExtPageLength or NumPhys at runtime.
2366 */
2367#ifndef MPI2_LOG_0_NUM_LOG_ENTRIES
2368#define MPI2_LOG_0_NUM_LOG_ENTRIES (1)
2369#endif
2370
2371#define MPI2_LOG_0_LOG_DATA_LENGTH (0x1C)
2372
2373typedef struct _MPI2_LOG_0_ENTRY
2374{
2375 U64 TimeStamp; /* 0x00 */
2376 U32 Reserved1; /* 0x08 */
2377 U16 LogSequence; /* 0x0C */
2378 U16 LogEntryQualifier; /* 0x0E */
2379 U8 VP_ID; /* 0x10 */
2380 U8 VF_ID; /* 0x11 */
2381 U16 Reserved2; /* 0x12 */
2382 U8 LogData[MPI2_LOG_0_LOG_DATA_LENGTH];/* 0x14 */
2383} MPI2_LOG_0_ENTRY, MPI2_POINTER PTR_MPI2_LOG_0_ENTRY,
2384 Mpi2Log0Entry_t, MPI2_POINTER pMpi2Log0Entry_t;
2385
2386/* values for Log Page 0 LogEntry LogEntryQualifier field */
2387#define MPI2_LOG_0_ENTRY_QUAL_ENTRY_UNUSED (0x0000)
2388#define MPI2_LOG_0_ENTRY_QUAL_POWER_ON_RESET (0x0001)
2389#define MPI2_LOG_0_ENTRY_QUAL_TIMESTAMP_UPDATE (0x0002)
2390#define MPI2_LOG_0_ENTRY_QUAL_MIN_IMPLEMENT_SPEC (0x8000)
2391#define MPI2_LOG_0_ENTRY_QUAL_MAX_IMPLEMENT_SPEC (0xFFFF)
2392
2393typedef struct _MPI2_CONFIG_PAGE_LOG_0
2394{
2395 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2396 U32 Reserved1; /* 0x08 */
2397 U32 Reserved2; /* 0x0C */
2398 U16 NumLogEntries; /* 0x10 */
2399 U16 Reserved3; /* 0x12 */
2400 MPI2_LOG_0_ENTRY LogEntry[MPI2_LOG_0_NUM_LOG_ENTRIES]; /* 0x14 */
2401} MPI2_CONFIG_PAGE_LOG_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_LOG_0,
2402 Mpi2LogPage0_t, MPI2_POINTER pMpi2LogPage0_t;
2403
2404#define MPI2_LOG_0_PAGEVERSION (0x02)
2405
2406
2407/****************************************************************************
2408* RAID Config Page
2409****************************************************************************/
2410
2411/* RAID Page 0 */
2412
2413/*
2414 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2415 * one and check Header.ExtPageLength or NumPhys at runtime.
2416 */
2417#ifndef MPI2_RAIDCONFIG0_MAX_ELEMENTS
2418#define MPI2_RAIDCONFIG0_MAX_ELEMENTS (1)
2419#endif
2420
2421typedef struct _MPI2_RAIDCONFIG0_CONFIG_ELEMENT
2422{
2423 U16 ElementFlags; /* 0x00 */
2424 U16 VolDevHandle; /* 0x02 */
2425 U8 HotSparePool; /* 0x04 */
2426 U8 PhysDiskNum; /* 0x05 */
2427 U16 PhysDiskDevHandle; /* 0x06 */
2428} MPI2_RAIDCONFIG0_CONFIG_ELEMENT,
2429 MPI2_POINTER PTR_MPI2_RAIDCONFIG0_CONFIG_ELEMENT,
2430 Mpi2RaidConfig0ConfigElement_t, MPI2_POINTER pMpi2RaidConfig0ConfigElement_t;
2431
2432/* values for the ElementFlags field */
2433#define MPI2_RAIDCONFIG0_EFLAGS_MASK_ELEMENT_TYPE (0x000F)
2434#define MPI2_RAIDCONFIG0_EFLAGS_VOLUME_ELEMENT (0x0000)
2435#define MPI2_RAIDCONFIG0_EFLAGS_VOL_PHYS_DISK_ELEMENT (0x0001)
2436#define MPI2_RAIDCONFIG0_EFLAGS_HOT_SPARE_ELEMENT (0x0002)
2437#define MPI2_RAIDCONFIG0_EFLAGS_OCE_ELEMENT (0x0003)
2438
2439
2440typedef struct _MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0
2441{
2442 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2443 U8 NumHotSpares; /* 0x08 */
2444 U8 NumPhysDisks; /* 0x09 */
2445 U8 NumVolumes; /* 0x0A */
2446 U8 ConfigNum; /* 0x0B */
2447 U32 Flags; /* 0x0C */
2448 U8 ConfigGUID[24]; /* 0x10 */
2449 U32 Reserved1; /* 0x28 */
2450 U8 NumElements; /* 0x2C */
2451 U8 Reserved2; /* 0x2D */
2452 U16 Reserved3; /* 0x2E */
2453 MPI2_RAIDCONFIG0_CONFIG_ELEMENT ConfigElement[MPI2_RAIDCONFIG0_MAX_ELEMENTS]; /* 0x30 */
2454} MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0,
2455 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0,
2456 Mpi2RaidConfigurationPage0_t, MPI2_POINTER pMpi2RaidConfigurationPage0_t;
2457
2458#define MPI2_RAIDCONFIG0_PAGEVERSION (0x00)
2459
2460/* values for RAID Configuration Page 0 Flags field */
2461#define MPI2_RAIDCONFIG0_FLAG_FOREIGN_CONFIG (0x00000001)
2462
2463
2464/****************************************************************************
2465* Driver Persistent Mapping Config Pages
2466****************************************************************************/
2467
2468/* Driver Persistent Mapping Page 0 */
2469
2470typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY
2471{
2472 U64 PhysicalIdentifier; /* 0x00 */
2473 U16 MappingInformation; /* 0x08 */
2474 U16 DeviceIndex; /* 0x0A */
2475 U32 PhysicalBitsMapping; /* 0x0C */
2476 U32 Reserved1; /* 0x10 */
2477} MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY,
2478 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY,
2479 Mpi2DriverMap0Entry_t, MPI2_POINTER pMpi2DriverMap0Entry_t;
2480
2481typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAPPING_0
2482{
2483 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2484 MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY Entry; /* 0x08 */
2485} MPI2_CONFIG_PAGE_DRIVER_MAPPING_0,
2486 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_DRIVER_MAPPING_0,
2487 Mpi2DriverMappingPage0_t, MPI2_POINTER pMpi2DriverMappingPage0_t;
2488
2489#define MPI2_DRIVERMAPPING0_PAGEVERSION (0x00)
2490
2491/* values for Driver Persistent Mapping Page 0 MappingInformation field */
2492#define MPI2_DRVMAP0_MAPINFO_SLOT_MASK (0x07F0)
2493#define MPI2_DRVMAP0_MAPINFO_SLOT_SHIFT (4)
2494#define MPI2_DRVMAP0_MAPINFO_MISSING_MASK (0x000F)
2495
2496
Kashyap, Desai9fec5f92009-09-23 17:26:20 +0530[diff] [blame]2497/****************************************************************************
2498* Ethernet Config Pages
2499****************************************************************************/
2500
2501/* Ethernet Page 0 */
2502
2503/* IP address (union of IPv4 and IPv6) */
2504typedef union _MPI2_ETHERNET_IP_ADDR {
2505 U32 IPv4Addr;
2506 U32 IPv6Addr[4];
2507} MPI2_ETHERNET_IP_ADDR, MPI2_POINTER PTR_MPI2_ETHERNET_IP_ADDR,
2508 Mpi2EthernetIpAddr_t, MPI2_POINTER pMpi2EthernetIpAddr_t;
2509
2510#define MPI2_ETHERNET_HOST_NAME_LENGTH (32)
2511
2512typedef struct _MPI2_CONFIG_PAGE_ETHERNET_0 {
2513 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2514 U8 NumInterfaces; /* 0x08 */
2515 U8 Reserved0; /* 0x09 */
2516 U16 Reserved1; /* 0x0A */
2517 U32 Status; /* 0x0C */
2518 U8 MediaState; /* 0x10 */
2519 U8 Reserved2; /* 0x11 */
2520 U16 Reserved3; /* 0x12 */
2521 U8 MacAddress[6]; /* 0x14 */
2522 U8 Reserved4; /* 0x1A */
2523 U8 Reserved5; /* 0x1B */
2524 MPI2_ETHERNET_IP_ADDR IpAddress; /* 0x1C */
2525 MPI2_ETHERNET_IP_ADDR SubnetMask; /* 0x2C */
2526 MPI2_ETHERNET_IP_ADDR GatewayIpAddress; /* 0x3C */
2527 MPI2_ETHERNET_IP_ADDR DNS1IpAddress; /* 0x4C */
2528 MPI2_ETHERNET_IP_ADDR DNS2IpAddress; /* 0x5C */
2529 MPI2_ETHERNET_IP_ADDR DhcpIpAddress; /* 0x6C */
2530 U8 HostName
2531 [MPI2_ETHERNET_HOST_NAME_LENGTH];/* 0x7C */
2532} MPI2_CONFIG_PAGE_ETHERNET_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_ETHERNET_0,
2533 Mpi2EthernetPage0_t, MPI2_POINTER pMpi2EthernetPage0_t;
2534
2535#define MPI2_ETHERNETPAGE0_PAGEVERSION (0x00)
2536
2537/* values for Ethernet Page 0 Status field */
2538#define MPI2_ETHPG0_STATUS_IPV6_CAPABLE (0x80000000)
2539#define MPI2_ETHPG0_STATUS_IPV4_CAPABLE (0x40000000)
2540#define MPI2_ETHPG0_STATUS_CONSOLE_CONNECTED (0x20000000)
2541#define MPI2_ETHPG0_STATUS_DEFAULT_IF (0x00000100)
2542#define MPI2_ETHPG0_STATUS_FW_DWNLD_ENABLED (0x00000080)
2543#define MPI2_ETHPG0_STATUS_TELNET_ENABLED (0x00000040)
2544#define MPI2_ETHPG0_STATUS_SSH2_ENABLED (0x00000020)
2545#define MPI2_ETHPG0_STATUS_DHCP_CLIENT_ENABLED (0x00000010)
2546#define MPI2_ETHPG0_STATUS_IPV6_ENABLED (0x00000008)
2547#define MPI2_ETHPG0_STATUS_IPV4_ENABLED (0x00000004)
2548#define MPI2_ETHPG0_STATUS_IPV6_ADDRESSES (0x00000002)
2549#define MPI2_ETHPG0_STATUS_ETH_IF_ENABLED (0x00000001)
2550
2551/* values for Ethernet Page 0 MediaState field */
2552#define MPI2_ETHPG0_MS_DUPLEX_MASK (0x80)
2553#define MPI2_ETHPG0_MS_HALF_DUPLEX (0x00)
2554#define MPI2_ETHPG0_MS_FULL_DUPLEX (0x80)
2555
2556#define MPI2_ETHPG0_MS_CONNECT_SPEED_MASK (0x07)
2557#define MPI2_ETHPG0_MS_NOT_CONNECTED (0x00)
2558#define MPI2_ETHPG0_MS_10MBIT (0x01)
2559#define MPI2_ETHPG0_MS_100MBIT (0x02)
2560#define MPI2_ETHPG0_MS_1GBIT (0x03)
2561
2562
2563/* Ethernet Page 1 */
2564
2565typedef struct _MPI2_CONFIG_PAGE_ETHERNET_1 {
2566 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2567 U32 Reserved0; /* 0x08 */
2568 U32 Flags; /* 0x0C */
2569 U8 MediaState; /* 0x10 */
2570 U8 Reserved1; /* 0x11 */
2571 U16 Reserved2; /* 0x12 */
2572 U8 MacAddress[6]; /* 0x14 */
2573 U8 Reserved3; /* 0x1A */
2574 U8 Reserved4; /* 0x1B */
2575 MPI2_ETHERNET_IP_ADDR StaticIpAddress; /* 0x1C */
2576 MPI2_ETHERNET_IP_ADDR StaticSubnetMask; /* 0x2C */
2577 MPI2_ETHERNET_IP_ADDR StaticGatewayIpAddress; /* 0x3C */
2578 MPI2_ETHERNET_IP_ADDR StaticDNS1IpAddress; /* 0x4C */
2579 MPI2_ETHERNET_IP_ADDR StaticDNS2IpAddress; /* 0x5C */
2580 U32 Reserved5; /* 0x6C */
2581 U32 Reserved6; /* 0x70 */
2582 U32 Reserved7; /* 0x74 */
2583 U32 Reserved8; /* 0x78 */
2584 U8 HostName
2585 [MPI2_ETHERNET_HOST_NAME_LENGTH];/* 0x7C */
2586} MPI2_CONFIG_PAGE_ETHERNET_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_ETHERNET_1,
2587 Mpi2EthernetPage1_t, MPI2_POINTER pMpi2EthernetPage1_t;
2588
2589#define MPI2_ETHERNETPAGE1_PAGEVERSION (0x00)
2590
2591/* values for Ethernet Page 1 Flags field */
2592#define MPI2_ETHPG1_FLAG_SET_DEFAULT_IF (0x00000100)
2593#define MPI2_ETHPG1_FLAG_ENABLE_FW_DOWNLOAD (0x00000080)
2594#define MPI2_ETHPG1_FLAG_ENABLE_TELNET (0x00000040)
2595#define MPI2_ETHPG1_FLAG_ENABLE_SSH2 (0x00000020)
2596#define MPI2_ETHPG1_FLAG_ENABLE_DHCP_CLIENT (0x00000010)
2597#define MPI2_ETHPG1_FLAG_ENABLE_IPV6 (0x00000008)
2598#define MPI2_ETHPG1_FLAG_ENABLE_IPV4 (0x00000004)
2599#define MPI2_ETHPG1_FLAG_USE_IPV6_ADDRESSES (0x00000002)
2600#define MPI2_ETHPG1_FLAG_ENABLE_ETH_IF (0x00000001)
2601
2602/* values for Ethernet Page 1 MediaState field */
2603#define MPI2_ETHPG1_MS_DUPLEX_MASK (0x80)
2604#define MPI2_ETHPG1_MS_HALF_DUPLEX (0x00)
2605#define MPI2_ETHPG1_MS_FULL_DUPLEX (0x80)
2606
2607#define MPI2_ETHPG1_MS_DATA_RATE_MASK (0x07)
2608#define MPI2_ETHPG1_MS_DATA_RATE_AUTO (0x00)
2609#define MPI2_ETHPG1_MS_DATA_RATE_10MBIT (0x01)
2610#define MPI2_ETHPG1_MS_DATA_RATE_100MBIT (0x02)
2611#define MPI2_ETHPG1_MS_DATA_RATE_1GBIT (0x03)
2612
2613
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]2614#endif
2615