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Chris Leechc13c8262006-05-23 17:18:44 -07001/*
2 * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the Free
6 * Software Foundation; either version 2 of the License, or (at your option)
7 * any later version.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59
16 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called COPYING.
20 */
Russell King - ARM Linuxd2ebfb32012-03-06 22:34:26 +000021#ifndef LINUX_DMAENGINE_H
22#define LINUX_DMAENGINE_H
David Woodhouse1c0f16e2006-06-27 02:53:56 -070023
Chris Leechc13c8262006-05-23 17:18:44 -070024#include <linux/device.h>
25#include <linux/uio.h>
Paul Gortmaker187f1882011-11-23 20:12:59 -050026#include <linux/bug.h>
Vinod Koul90b44f82011-07-25 19:57:52 +053027#include <linux/scatterlist.h>
Paul Gortmakera8efa9d2011-07-29 16:55:11 +100028#include <linux/bitmap.h>
Viresh Kumardcc043d2012-02-01 16:12:18 +053029#include <linux/types.h>
Paul Gortmakera8efa9d2011-07-29 16:55:11 +100030#include <asm/page.h>
Alexey Dobriyanb7f080c2011-06-16 11:01:34 +000031
Chris Leechc13c8262006-05-23 17:18:44 -070032/**
Randy Dunlapfe4ada22006-07-03 19:44:51 -070033 * typedef dma_cookie_t - an opaque DMA cookie
Chris Leechc13c8262006-05-23 17:18:44 -070034 *
35 * if dma_cookie_t is >0 it's a DMA request cookie, <0 it's an error code
36 */
37typedef s32 dma_cookie_t;
Steven J. Magnani76bd0612010-02-28 22:18:16 -070038#define DMA_MIN_COOKIE 1
39#define DMA_MAX_COOKIE INT_MAX
Chris Leechc13c8262006-05-23 17:18:44 -070040
41#define dma_submit_error(cookie) ((cookie) < 0 ? 1 : 0)
42
43/**
44 * enum dma_status - DMA transaction status
45 * @DMA_SUCCESS: transaction completed successfully
46 * @DMA_IN_PROGRESS: transaction not yet processed
Linus Walleij07934482010-03-26 16:50:49 -070047 * @DMA_PAUSED: transaction is paused
Chris Leechc13c8262006-05-23 17:18:44 -070048 * @DMA_ERROR: transaction failed
49 */
50enum dma_status {
51 DMA_SUCCESS,
52 DMA_IN_PROGRESS,
Linus Walleij07934482010-03-26 16:50:49 -070053 DMA_PAUSED,
Chris Leechc13c8262006-05-23 17:18:44 -070054 DMA_ERROR,
55};
56
57/**
Dan Williams7405f742007-01-02 11:10:43 -070058 * enum dma_transaction_type - DMA transaction types/indexes
Dan Williams138f4c32009-09-08 17:42:51 -070059 *
60 * Note: The DMA_ASYNC_TX capability is not to be set by drivers. It is
61 * automatically set as dma devices are registered.
Dan Williams7405f742007-01-02 11:10:43 -070062 */
63enum dma_transaction_type {
64 DMA_MEMCPY,
65 DMA_XOR,
Dan Williamsb2f46fd2009-07-14 12:20:36 -070066 DMA_PQ,
Dan Williams099f53c2009-04-08 14:28:37 -070067 DMA_XOR_VAL,
68 DMA_PQ_VAL,
Dan Williams7405f742007-01-02 11:10:43 -070069 DMA_MEMSET,
Dan Williams7405f742007-01-02 11:10:43 -070070 DMA_INTERRUPT,
Ira Snydera86ee032010-09-30 11:46:44 +000071 DMA_SG,
Dan Williams59b5ec22009-01-06 11:38:15 -070072 DMA_PRIVATE,
Dan Williams138f4c32009-09-08 17:42:51 -070073 DMA_ASYNC_TX,
Haavard Skinnemoendc0ee642008-07-08 11:59:35 -070074 DMA_SLAVE,
Sascha Hauer782bc952010-09-30 13:56:32 +000075 DMA_CYCLIC,
Jassi Brarb14dab72011-10-13 12:33:30 +053076 DMA_INTERLEAVE,
Dan Williams7405f742007-01-02 11:10:43 -070077/* last transaction type for creation of the capabilities mask */
Jassi Brarb14dab72011-10-13 12:33:30 +053078 DMA_TX_TYPE_END,
79};
Haavard Skinnemoendc0ee642008-07-08 11:59:35 -070080
Vinod Koul49920bc2011-10-13 15:15:27 +053081/**
82 * enum dma_transfer_direction - dma transfer mode and direction indicator
83 * @DMA_MEM_TO_MEM: Async/Memcpy mode
84 * @DMA_MEM_TO_DEV: Slave mode & From Memory to Device
85 * @DMA_DEV_TO_MEM: Slave mode & From Device to Memory
86 * @DMA_DEV_TO_DEV: Slave mode & From Device to Device
87 */
88enum dma_transfer_direction {
89 DMA_MEM_TO_MEM,
90 DMA_MEM_TO_DEV,
91 DMA_DEV_TO_MEM,
92 DMA_DEV_TO_DEV,
Shawn Guo62268ce2011-12-13 23:48:03 +080093 DMA_TRANS_NONE,
Vinod Koul49920bc2011-10-13 15:15:27 +053094};
Dan Williams7405f742007-01-02 11:10:43 -070095
96/**
Jassi Brarb14dab72011-10-13 12:33:30 +053097 * Interleaved Transfer Request
98 * ----------------------------
99 * A chunk is collection of contiguous bytes to be transfered.
100 * The gap(in bytes) between two chunks is called inter-chunk-gap(ICG).
101 * ICGs may or maynot change between chunks.
102 * A FRAME is the smallest series of contiguous {chunk,icg} pairs,
103 * that when repeated an integral number of times, specifies the transfer.
104 * A transfer template is specification of a Frame, the number of times
105 * it is to be repeated and other per-transfer attributes.
106 *
107 * Practically, a client driver would have ready a template for each
108 * type of transfer it is going to need during its lifetime and
109 * set only 'src_start' and 'dst_start' before submitting the requests.
110 *
111 *
112 * | Frame-1 | Frame-2 | ~ | Frame-'numf' |
113 * |====....==.===...=...|====....==.===...=...| ~ |====....==.===...=...|
114 *
115 * == Chunk size
116 * ... ICG
117 */
118
119/**
120 * struct data_chunk - Element of scatter-gather list that makes a frame.
121 * @size: Number of bytes to read from source.
122 * size_dst := fn(op, size_src), so doesn't mean much for destination.
123 * @icg: Number of bytes to jump after last src/dst address of this
124 * chunk and before first src/dst address for next chunk.
125 * Ignored for dst(assumed 0), if dst_inc is true and dst_sgl is false.
126 * Ignored for src(assumed 0), if src_inc is true and src_sgl is false.
127 */
128struct data_chunk {
129 size_t size;
130 size_t icg;
131};
132
133/**
134 * struct dma_interleaved_template - Template to convey DMAC the transfer pattern
135 * and attributes.
136 * @src_start: Bus address of source for the first chunk.
137 * @dst_start: Bus address of destination for the first chunk.
138 * @dir: Specifies the type of Source and Destination.
139 * @src_inc: If the source address increments after reading from it.
140 * @dst_inc: If the destination address increments after writing to it.
141 * @src_sgl: If the 'icg' of sgl[] applies to Source (scattered read).
142 * Otherwise, source is read contiguously (icg ignored).
143 * Ignored if src_inc is false.
144 * @dst_sgl: If the 'icg' of sgl[] applies to Destination (scattered write).
145 * Otherwise, destination is filled contiguously (icg ignored).
146 * Ignored if dst_inc is false.
147 * @numf: Number of frames in this template.
148 * @frame_size: Number of chunks in a frame i.e, size of sgl[].
149 * @sgl: Array of {chunk,icg} pairs that make up a frame.
150 */
151struct dma_interleaved_template {
152 dma_addr_t src_start;
153 dma_addr_t dst_start;
154 enum dma_transfer_direction dir;
155 bool src_inc;
156 bool dst_inc;
157 bool src_sgl;
158 bool dst_sgl;
159 size_t numf;
160 size_t frame_size;
161 struct data_chunk sgl[0];
162};
163
164/**
Dan Williams636bdea2008-04-17 20:17:26 -0700165 * enum dma_ctrl_flags - DMA flags to augment operation preparation,
Dan Williamsb2f46fd2009-07-14 12:20:36 -0700166 * control completion, and communicate status.
Dan Williamsd4c56f92008-02-02 19:49:58 -0700167 * @DMA_PREP_INTERRUPT - trigger an interrupt (callback) upon completion of
Dan Williamsb2f46fd2009-07-14 12:20:36 -0700168 * this transaction
Guennadi Liakhovetskia88f6662009-12-10 18:35:15 +0100169 * @DMA_CTRL_ACK - if clear, the descriptor cannot be reused until the client
Dan Williamsb2f46fd2009-07-14 12:20:36 -0700170 * acknowledges receipt, i.e. has has a chance to establish any dependency
171 * chains
Dan Williamse1d181e2008-07-04 00:13:40 -0700172 * @DMA_COMPL_SKIP_SRC_UNMAP - set to disable dma-unmapping the source buffer(s)
173 * @DMA_COMPL_SKIP_DEST_UNMAP - set to disable dma-unmapping the destination(s)
Maciej Sosnowski4f005db2009-04-23 12:31:51 +0200174 * @DMA_COMPL_SRC_UNMAP_SINGLE - set to do the source dma-unmapping as single
175 * (if not set, do the source dma-unmapping as page)
176 * @DMA_COMPL_DEST_UNMAP_SINGLE - set to do the destination dma-unmapping as single
177 * (if not set, do the destination dma-unmapping as page)
Dan Williamsb2f46fd2009-07-14 12:20:36 -0700178 * @DMA_PREP_PQ_DISABLE_P - prevent generation of P while generating Q
179 * @DMA_PREP_PQ_DISABLE_Q - prevent generation of Q while generating P
180 * @DMA_PREP_CONTINUE - indicate to a driver that it is reusing buffers as
181 * sources that were the result of a previous operation, in the case of a PQ
182 * operation it continues the calculation with new sources
Dan Williams0403e382009-09-08 17:42:50 -0700183 * @DMA_PREP_FENCE - tell the driver that subsequent operations depend
184 * on the result of this operation
Dan Williamsd4c56f92008-02-02 19:49:58 -0700185 */
Dan Williams636bdea2008-04-17 20:17:26 -0700186enum dma_ctrl_flags {
Dan Williamsd4c56f92008-02-02 19:49:58 -0700187 DMA_PREP_INTERRUPT = (1 << 0),
Dan Williams636bdea2008-04-17 20:17:26 -0700188 DMA_CTRL_ACK = (1 << 1),
Dan Williamse1d181e2008-07-04 00:13:40 -0700189 DMA_COMPL_SKIP_SRC_UNMAP = (1 << 2),
190 DMA_COMPL_SKIP_DEST_UNMAP = (1 << 3),
Maciej Sosnowski4f005db2009-04-23 12:31:51 +0200191 DMA_COMPL_SRC_UNMAP_SINGLE = (1 << 4),
192 DMA_COMPL_DEST_UNMAP_SINGLE = (1 << 5),
Dan Williamsf9dd2132009-09-08 17:42:29 -0700193 DMA_PREP_PQ_DISABLE_P = (1 << 6),
194 DMA_PREP_PQ_DISABLE_Q = (1 << 7),
195 DMA_PREP_CONTINUE = (1 << 8),
Dan Williams0403e382009-09-08 17:42:50 -0700196 DMA_PREP_FENCE = (1 << 9),
Dan Williamsd4c56f92008-02-02 19:49:58 -0700197};
198
199/**
Linus Walleijc3635c72010-03-26 16:44:01 -0700200 * enum dma_ctrl_cmd - DMA operations that can optionally be exercised
201 * on a running channel.
202 * @DMA_TERMINATE_ALL: terminate all ongoing transfers
203 * @DMA_PAUSE: pause ongoing transfers
204 * @DMA_RESUME: resume paused transfer
Linus Walleijc156d0a2010-08-04 13:37:33 +0200205 * @DMA_SLAVE_CONFIG: this command is only implemented by DMA controllers
206 * that need to runtime reconfigure the slave channels (as opposed to passing
207 * configuration data in statically from the platform). An additional
208 * argument of struct dma_slave_config must be passed in with this
209 * command.
Ira Snyder968f19a2010-09-30 11:46:46 +0000210 * @FSLDMA_EXTERNAL_START: this command will put the Freescale DMA controller
211 * into external start mode.
Linus Walleijc3635c72010-03-26 16:44:01 -0700212 */
213enum dma_ctrl_cmd {
214 DMA_TERMINATE_ALL,
215 DMA_PAUSE,
216 DMA_RESUME,
Linus Walleijc156d0a2010-08-04 13:37:33 +0200217 DMA_SLAVE_CONFIG,
Ira Snyder968f19a2010-09-30 11:46:46 +0000218 FSLDMA_EXTERNAL_START,
Linus Walleijc3635c72010-03-26 16:44:01 -0700219};
220
221/**
Dan Williamsad283ea2009-08-29 19:09:26 -0700222 * enum sum_check_bits - bit position of pq_check_flags
223 */
224enum sum_check_bits {
225 SUM_CHECK_P = 0,
226 SUM_CHECK_Q = 1,
227};
228
229/**
230 * enum pq_check_flags - result of async_{xor,pq}_zero_sum operations
231 * @SUM_CHECK_P_RESULT - 1 if xor zero sum error, 0 otherwise
232 * @SUM_CHECK_Q_RESULT - 1 if reed-solomon zero sum error, 0 otherwise
233 */
234enum sum_check_flags {
235 SUM_CHECK_P_RESULT = (1 << SUM_CHECK_P),
236 SUM_CHECK_Q_RESULT = (1 << SUM_CHECK_Q),
237};
238
239
240/**
Dan Williams7405f742007-01-02 11:10:43 -0700241 * dma_cap_mask_t - capabilities bitmap modeled after cpumask_t.
242 * See linux/cpumask.h
243 */
244typedef struct { DECLARE_BITMAP(bits, DMA_TX_TYPE_END); } dma_cap_mask_t;
245
246/**
Chris Leechc13c8262006-05-23 17:18:44 -0700247 * struct dma_chan_percpu - the per-CPU part of struct dma_chan
Chris Leechc13c8262006-05-23 17:18:44 -0700248 * @memcpy_count: transaction counter
249 * @bytes_transferred: byte counter
250 */
251
252struct dma_chan_percpu {
Chris Leechc13c8262006-05-23 17:18:44 -0700253 /* stats */
254 unsigned long memcpy_count;
255 unsigned long bytes_transferred;
256};
257
258/**
259 * struct dma_chan - devices supply DMA channels, clients use them
Randy Dunlapfe4ada22006-07-03 19:44:51 -0700260 * @device: ptr to the dma device who supplies this channel, always !%NULL
Chris Leechc13c8262006-05-23 17:18:44 -0700261 * @cookie: last cookie value returned to client
Russell King - ARM Linux4d4e58d2012-03-06 22:34:06 +0000262 * @completed_cookie: last completed cookie for this channel
Randy Dunlapfe4ada22006-07-03 19:44:51 -0700263 * @chan_id: channel ID for sysfs
Dan Williams41d5e592009-01-06 11:38:21 -0700264 * @dev: class device for sysfs
Chris Leechc13c8262006-05-23 17:18:44 -0700265 * @device_node: used to add this to the device chan list
266 * @local: per-cpu pointer to a struct dma_chan_percpu
Dan Williams7cc5bf92008-07-08 11:58:21 -0700267 * @client-count: how many clients are using this channel
Dan Williamsbec08512009-01-06 11:38:14 -0700268 * @table_count: number of appearances in the mem-to-mem allocation table
Dan Williams287d8592009-02-18 14:48:26 -0800269 * @private: private data for certain client-channel associations
Chris Leechc13c8262006-05-23 17:18:44 -0700270 */
271struct dma_chan {
Chris Leechc13c8262006-05-23 17:18:44 -0700272 struct dma_device *device;
273 dma_cookie_t cookie;
Russell King - ARM Linux4d4e58d2012-03-06 22:34:06 +0000274 dma_cookie_t completed_cookie;
Chris Leechc13c8262006-05-23 17:18:44 -0700275
276 /* sysfs */
277 int chan_id;
Dan Williams41d5e592009-01-06 11:38:21 -0700278 struct dma_chan_dev *dev;
Chris Leechc13c8262006-05-23 17:18:44 -0700279
Chris Leechc13c8262006-05-23 17:18:44 -0700280 struct list_head device_node;
Tejun Heoa29d8b82010-02-02 14:39:15 +0900281 struct dma_chan_percpu __percpu *local;
Dan Williams7cc5bf92008-07-08 11:58:21 -0700282 int client_count;
Dan Williamsbec08512009-01-06 11:38:14 -0700283 int table_count;
Dan Williams287d8592009-02-18 14:48:26 -0800284 void *private;
Chris Leechc13c8262006-05-23 17:18:44 -0700285};
286
Dan Williams41d5e592009-01-06 11:38:21 -0700287/**
288 * struct dma_chan_dev - relate sysfs device node to backing channel device
289 * @chan - driver channel device
290 * @device - sysfs device
Dan Williams864498a2009-01-06 11:38:21 -0700291 * @dev_id - parent dma_device dev_id
292 * @idr_ref - reference count to gate release of dma_device dev_id
Dan Williams41d5e592009-01-06 11:38:21 -0700293 */
294struct dma_chan_dev {
295 struct dma_chan *chan;
296 struct device device;
Dan Williams864498a2009-01-06 11:38:21 -0700297 int dev_id;
298 atomic_t *idr_ref;
Dan Williams41d5e592009-01-06 11:38:21 -0700299};
300
Linus Walleijc156d0a2010-08-04 13:37:33 +0200301/**
302 * enum dma_slave_buswidth - defines bus with of the DMA slave
303 * device, source or target buses
304 */
305enum dma_slave_buswidth {
306 DMA_SLAVE_BUSWIDTH_UNDEFINED = 0,
307 DMA_SLAVE_BUSWIDTH_1_BYTE = 1,
308 DMA_SLAVE_BUSWIDTH_2_BYTES = 2,
309 DMA_SLAVE_BUSWIDTH_4_BYTES = 4,
310 DMA_SLAVE_BUSWIDTH_8_BYTES = 8,
311};
312
313/**
314 * struct dma_slave_config - dma slave channel runtime config
315 * @direction: whether the data shall go in or out on this slave
316 * channel, right now. DMA_TO_DEVICE and DMA_FROM_DEVICE are
317 * legal values, DMA_BIDIRECTIONAL is not acceptable since we
318 * need to differentiate source and target addresses.
319 * @src_addr: this is the physical address where DMA slave data
320 * should be read (RX), if the source is memory this argument is
321 * ignored.
322 * @dst_addr: this is the physical address where DMA slave data
323 * should be written (TX), if the source is memory this argument
324 * is ignored.
325 * @src_addr_width: this is the width in bytes of the source (RX)
326 * register where DMA data shall be read. If the source
327 * is memory this may be ignored depending on architecture.
328 * Legal values: 1, 2, 4, 8.
329 * @dst_addr_width: same as src_addr_width but for destination
330 * target (TX) mutatis mutandis.
331 * @src_maxburst: the maximum number of words (note: words, as in
332 * units of the src_addr_width member, not bytes) that can be sent
333 * in one burst to the device. Typically something like half the
334 * FIFO depth on I/O peripherals so you don't overflow it. This
335 * may or may not be applicable on memory sources.
336 * @dst_maxburst: same as src_maxburst but for destination target
337 * mutatis mutandis.
Viresh Kumardcc043d2012-02-01 16:12:18 +0530338 * @device_fc: Flow Controller Settings. Only valid for slave channels. Fill
339 * with 'true' if peripheral should be flow controller. Direction will be
340 * selected at Runtime.
Linus Walleijc156d0a2010-08-04 13:37:33 +0200341 *
342 * This struct is passed in as configuration data to a DMA engine
343 * in order to set up a certain channel for DMA transport at runtime.
344 * The DMA device/engine has to provide support for an additional
345 * command in the channel config interface, DMA_SLAVE_CONFIG
346 * and this struct will then be passed in as an argument to the
347 * DMA engine device_control() function.
348 *
349 * The rationale for adding configuration information to this struct
350 * is as follows: if it is likely that most DMA slave controllers in
351 * the world will support the configuration option, then make it
352 * generic. If not: if it is fixed so that it be sent in static from
353 * the platform data, then prefer to do that. Else, if it is neither
354 * fixed at runtime, nor generic enough (such as bus mastership on
355 * some CPU family and whatnot) then create a custom slave config
356 * struct and pass that, then make this config a member of that
357 * struct, if applicable.
358 */
359struct dma_slave_config {
Vinod Koul49920bc2011-10-13 15:15:27 +0530360 enum dma_transfer_direction direction;
Linus Walleijc156d0a2010-08-04 13:37:33 +0200361 dma_addr_t src_addr;
362 dma_addr_t dst_addr;
363 enum dma_slave_buswidth src_addr_width;
364 enum dma_slave_buswidth dst_addr_width;
365 u32 src_maxburst;
366 u32 dst_maxburst;
Viresh Kumardcc043d2012-02-01 16:12:18 +0530367 bool device_fc;
Linus Walleijc156d0a2010-08-04 13:37:33 +0200368};
369
Dan Williams41d5e592009-01-06 11:38:21 -0700370static inline const char *dma_chan_name(struct dma_chan *chan)
371{
372 return dev_name(&chan->dev->device);
373}
Dan Williamsd379b012007-07-09 11:56:42 -0700374
Chris Leechc13c8262006-05-23 17:18:44 -0700375void dma_chan_cleanup(struct kref *kref);
376
Chris Leechc13c8262006-05-23 17:18:44 -0700377/**
Dan Williams59b5ec22009-01-06 11:38:15 -0700378 * typedef dma_filter_fn - callback filter for dma_request_channel
379 * @chan: channel to be reviewed
380 * @filter_param: opaque parameter passed through dma_request_channel
381 *
382 * When this optional parameter is specified in a call to dma_request_channel a
383 * suitable channel is passed to this routine for further dispositioning before
384 * being returned. Where 'suitable' indicates a non-busy channel that
Dan Williams7dd60252009-01-06 11:38:19 -0700385 * satisfies the given capability mask. It returns 'true' to indicate that the
386 * channel is suitable.
Dan Williams59b5ec22009-01-06 11:38:15 -0700387 */
Dan Williams7dd60252009-01-06 11:38:19 -0700388typedef bool (*dma_filter_fn)(struct dma_chan *chan, void *filter_param);
Dan Williams59b5ec22009-01-06 11:38:15 -0700389
Dan Williams7405f742007-01-02 11:10:43 -0700390typedef void (*dma_async_tx_callback)(void *dma_async_param);
391/**
392 * struct dma_async_tx_descriptor - async transaction descriptor
393 * ---dma generic offload fields---
394 * @cookie: tracking cookie for this transaction, set to -EBUSY if
395 * this tx is sitting on a dependency list
Dan Williams636bdea2008-04-17 20:17:26 -0700396 * @flags: flags to augment operation preparation, control completion, and
397 * communicate status
Dan Williams7405f742007-01-02 11:10:43 -0700398 * @phys: physical address of the descriptor
Dan Williams7405f742007-01-02 11:10:43 -0700399 * @chan: target channel for this operation
400 * @tx_submit: set the prepared descriptor(s) to be executed by the engine
Dan Williams7405f742007-01-02 11:10:43 -0700401 * @callback: routine to call after this operation is complete
402 * @callback_param: general parameter to pass to the callback routine
403 * ---async_tx api specific fields---
Dan Williams19242d72008-04-17 20:17:25 -0700404 * @next: at completion submit this descriptor
Dan Williams7405f742007-01-02 11:10:43 -0700405 * @parent: pointer to the next level up in the dependency chain
Dan Williams19242d72008-04-17 20:17:25 -0700406 * @lock: protect the parent and next pointers
Dan Williams7405f742007-01-02 11:10:43 -0700407 */
408struct dma_async_tx_descriptor {
409 dma_cookie_t cookie;
Dan Williams636bdea2008-04-17 20:17:26 -0700410 enum dma_ctrl_flags flags; /* not a 'long' to pack with cookie */
Dan Williams7405f742007-01-02 11:10:43 -0700411 dma_addr_t phys;
Dan Williams7405f742007-01-02 11:10:43 -0700412 struct dma_chan *chan;
413 dma_cookie_t (*tx_submit)(struct dma_async_tx_descriptor *tx);
Dan Williams7405f742007-01-02 11:10:43 -0700414 dma_async_tx_callback callback;
415 void *callback_param;
Dan Williams5fc6d892010-10-07 16:44:50 -0700416#ifdef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
Dan Williams19242d72008-04-17 20:17:25 -0700417 struct dma_async_tx_descriptor *next;
Dan Williams7405f742007-01-02 11:10:43 -0700418 struct dma_async_tx_descriptor *parent;
419 spinlock_t lock;
Dan Williamscaa20d972010-05-17 16:24:16 -0700420#endif
Dan Williams7405f742007-01-02 11:10:43 -0700421};
422
Dan Williams5fc6d892010-10-07 16:44:50 -0700423#ifndef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
Dan Williamscaa20d972010-05-17 16:24:16 -0700424static inline void txd_lock(struct dma_async_tx_descriptor *txd)
425{
426}
427static inline void txd_unlock(struct dma_async_tx_descriptor *txd)
428{
429}
430static inline void txd_chain(struct dma_async_tx_descriptor *txd, struct dma_async_tx_descriptor *next)
431{
432 BUG();
433}
434static inline void txd_clear_parent(struct dma_async_tx_descriptor *txd)
435{
436}
437static inline void txd_clear_next(struct dma_async_tx_descriptor *txd)
438{
439}
440static inline struct dma_async_tx_descriptor *txd_next(struct dma_async_tx_descriptor *txd)
441{
442 return NULL;
443}
444static inline struct dma_async_tx_descriptor *txd_parent(struct dma_async_tx_descriptor *txd)
445{
446 return NULL;
447}
448
449#else
450static inline void txd_lock(struct dma_async_tx_descriptor *txd)
451{
452 spin_lock_bh(&txd->lock);
453}
454static inline void txd_unlock(struct dma_async_tx_descriptor *txd)
455{
456 spin_unlock_bh(&txd->lock);
457}
458static inline void txd_chain(struct dma_async_tx_descriptor *txd, struct dma_async_tx_descriptor *next)
459{
460 txd->next = next;
461 next->parent = txd;
462}
463static inline void txd_clear_parent(struct dma_async_tx_descriptor *txd)
464{
465 txd->parent = NULL;
466}
467static inline void txd_clear_next(struct dma_async_tx_descriptor *txd)
468{
469 txd->next = NULL;
470}
471static inline struct dma_async_tx_descriptor *txd_parent(struct dma_async_tx_descriptor *txd)
472{
473 return txd->parent;
474}
475static inline struct dma_async_tx_descriptor *txd_next(struct dma_async_tx_descriptor *txd)
476{
477 return txd->next;
478}
479#endif
480
Chris Leechc13c8262006-05-23 17:18:44 -0700481/**
Linus Walleij07934482010-03-26 16:50:49 -0700482 * struct dma_tx_state - filled in to report the status of
483 * a transfer.
484 * @last: last completed DMA cookie
485 * @used: last issued DMA cookie (i.e. the one in progress)
486 * @residue: the remaining number of bytes left to transmit
487 * on the selected transfer for states DMA_IN_PROGRESS and
488 * DMA_PAUSED if this is implemented in the driver, else 0
489 */
490struct dma_tx_state {
491 dma_cookie_t last;
492 dma_cookie_t used;
493 u32 residue;
494};
495
496/**
Chris Leechc13c8262006-05-23 17:18:44 -0700497 * struct dma_device - info on the entity supplying DMA services
498 * @chancnt: how many DMA channels are supported
Atsushi Nemoto0f571512009-03-06 20:07:14 +0900499 * @privatecnt: how many DMA channels are requested by dma_request_channel
Chris Leechc13c8262006-05-23 17:18:44 -0700500 * @channels: the list of struct dma_chan
501 * @global_node: list_head for global dma_device_list
Dan Williams7405f742007-01-02 11:10:43 -0700502 * @cap_mask: one or more dma_capability flags
503 * @max_xor: maximum number of xor sources, 0 if no capability
Dan Williamsb2f46fd2009-07-14 12:20:36 -0700504 * @max_pq: maximum number of PQ sources and PQ-continue capability
Dan Williams83544ae2009-09-08 17:42:53 -0700505 * @copy_align: alignment shift for memcpy operations
506 * @xor_align: alignment shift for xor operations
507 * @pq_align: alignment shift for pq operations
508 * @fill_align: alignment shift for memset operations
Randy Dunlapfe4ada22006-07-03 19:44:51 -0700509 * @dev_id: unique device ID
Dan Williams7405f742007-01-02 11:10:43 -0700510 * @dev: struct device reference for dma mapping api
Randy Dunlapfe4ada22006-07-03 19:44:51 -0700511 * @device_alloc_chan_resources: allocate resources and return the
512 * number of allocated descriptors
513 * @device_free_chan_resources: release DMA channel's resources
Dan Williams7405f742007-01-02 11:10:43 -0700514 * @device_prep_dma_memcpy: prepares a memcpy operation
515 * @device_prep_dma_xor: prepares a xor operation
Dan Williams099f53c2009-04-08 14:28:37 -0700516 * @device_prep_dma_xor_val: prepares a xor validation operation
Dan Williamsb2f46fd2009-07-14 12:20:36 -0700517 * @device_prep_dma_pq: prepares a pq operation
518 * @device_prep_dma_pq_val: prepares a pqzero_sum operation
Dan Williams7405f742007-01-02 11:10:43 -0700519 * @device_prep_dma_memset: prepares a memset operation
520 * @device_prep_dma_interrupt: prepares an end of chain interrupt operation
Haavard Skinnemoendc0ee642008-07-08 11:59:35 -0700521 * @device_prep_slave_sg: prepares a slave dma operation
Sascha Hauer782bc952010-09-30 13:56:32 +0000522 * @device_prep_dma_cyclic: prepare a cyclic dma operation suitable for audio.
523 * The function takes a buffer of size buf_len. The callback function will
524 * be called after period_len bytes have been transferred.
Jassi Brarb14dab72011-10-13 12:33:30 +0530525 * @device_prep_interleaved_dma: Transfer expression in a generic way.
Linus Walleijc3635c72010-03-26 16:44:01 -0700526 * @device_control: manipulate all pending operations on a channel, returns
527 * zero or error code
Linus Walleij07934482010-03-26 16:50:49 -0700528 * @device_tx_status: poll for transaction completion, the optional
529 * txstate parameter can be supplied with a pointer to get a
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300530 * struct with auxiliary transfer status information, otherwise the call
Linus Walleij07934482010-03-26 16:50:49 -0700531 * will just return a simple status code
Dan Williams7405f742007-01-02 11:10:43 -0700532 * @device_issue_pending: push pending transactions to hardware
Chris Leechc13c8262006-05-23 17:18:44 -0700533 */
534struct dma_device {
535
536 unsigned int chancnt;
Atsushi Nemoto0f571512009-03-06 20:07:14 +0900537 unsigned int privatecnt;
Chris Leechc13c8262006-05-23 17:18:44 -0700538 struct list_head channels;
539 struct list_head global_node;
Dan Williams7405f742007-01-02 11:10:43 -0700540 dma_cap_mask_t cap_mask;
Dan Williamsb2f46fd2009-07-14 12:20:36 -0700541 unsigned short max_xor;
542 unsigned short max_pq;
Dan Williams83544ae2009-09-08 17:42:53 -0700543 u8 copy_align;
544 u8 xor_align;
545 u8 pq_align;
546 u8 fill_align;
Dan Williamsb2f46fd2009-07-14 12:20:36 -0700547 #define DMA_HAS_PQ_CONTINUE (1 << 15)
Chris Leechc13c8262006-05-23 17:18:44 -0700548
Chris Leechc13c8262006-05-23 17:18:44 -0700549 int dev_id;
Dan Williams7405f742007-01-02 11:10:43 -0700550 struct device *dev;
Chris Leechc13c8262006-05-23 17:18:44 -0700551
Dan Williamsaa1e6f12009-01-06 11:38:17 -0700552 int (*device_alloc_chan_resources)(struct dma_chan *chan);
Chris Leechc13c8262006-05-23 17:18:44 -0700553 void (*device_free_chan_resources)(struct dma_chan *chan);
Dan Williams7405f742007-01-02 11:10:43 -0700554
555 struct dma_async_tx_descriptor *(*device_prep_dma_memcpy)(
Dan Williams00367312008-02-02 19:49:57 -0700556 struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
Dan Williamsd4c56f92008-02-02 19:49:58 -0700557 size_t len, unsigned long flags);
Dan Williams7405f742007-01-02 11:10:43 -0700558 struct dma_async_tx_descriptor *(*device_prep_dma_xor)(
Dan Williams00367312008-02-02 19:49:57 -0700559 struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src,
Dan Williamsd4c56f92008-02-02 19:49:58 -0700560 unsigned int src_cnt, size_t len, unsigned long flags);
Dan Williams099f53c2009-04-08 14:28:37 -0700561 struct dma_async_tx_descriptor *(*device_prep_dma_xor_val)(
Dan Williams00367312008-02-02 19:49:57 -0700562 struct dma_chan *chan, dma_addr_t *src, unsigned int src_cnt,
Dan Williamsad283ea2009-08-29 19:09:26 -0700563 size_t len, enum sum_check_flags *result, unsigned long flags);
Dan Williamsb2f46fd2009-07-14 12:20:36 -0700564 struct dma_async_tx_descriptor *(*device_prep_dma_pq)(
565 struct dma_chan *chan, dma_addr_t *dst, dma_addr_t *src,
566 unsigned int src_cnt, const unsigned char *scf,
567 size_t len, unsigned long flags);
568 struct dma_async_tx_descriptor *(*device_prep_dma_pq_val)(
569 struct dma_chan *chan, dma_addr_t *pq, dma_addr_t *src,
570 unsigned int src_cnt, const unsigned char *scf, size_t len,
571 enum sum_check_flags *pqres, unsigned long flags);
Dan Williams7405f742007-01-02 11:10:43 -0700572 struct dma_async_tx_descriptor *(*device_prep_dma_memset)(
Dan Williams00367312008-02-02 19:49:57 -0700573 struct dma_chan *chan, dma_addr_t dest, int value, size_t len,
Dan Williamsd4c56f92008-02-02 19:49:58 -0700574 unsigned long flags);
Dan Williams7405f742007-01-02 11:10:43 -0700575 struct dma_async_tx_descriptor *(*device_prep_dma_interrupt)(
Dan Williams636bdea2008-04-17 20:17:26 -0700576 struct dma_chan *chan, unsigned long flags);
Ira Snydera86ee032010-09-30 11:46:44 +0000577 struct dma_async_tx_descriptor *(*device_prep_dma_sg)(
578 struct dma_chan *chan,
579 struct scatterlist *dst_sg, unsigned int dst_nents,
580 struct scatterlist *src_sg, unsigned int src_nents,
581 unsigned long flags);
Dan Williams7405f742007-01-02 11:10:43 -0700582
Haavard Skinnemoendc0ee642008-07-08 11:59:35 -0700583 struct dma_async_tx_descriptor *(*device_prep_slave_sg)(
584 struct dma_chan *chan, struct scatterlist *sgl,
Vinod Koul49920bc2011-10-13 15:15:27 +0530585 unsigned int sg_len, enum dma_transfer_direction direction,
Alexandre Bounine185ecb52012-03-08 15:35:13 -0500586 unsigned long flags, void *context);
Sascha Hauer782bc952010-09-30 13:56:32 +0000587 struct dma_async_tx_descriptor *(*device_prep_dma_cyclic)(
588 struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
Alexandre Bounine185ecb52012-03-08 15:35:13 -0500589 size_t period_len, enum dma_transfer_direction direction,
590 void *context);
Jassi Brarb14dab72011-10-13 12:33:30 +0530591 struct dma_async_tx_descriptor *(*device_prep_interleaved_dma)(
592 struct dma_chan *chan, struct dma_interleaved_template *xt,
593 unsigned long flags);
Linus Walleij05827632010-05-17 16:30:42 -0700594 int (*device_control)(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
595 unsigned long arg);
Haavard Skinnemoendc0ee642008-07-08 11:59:35 -0700596
Linus Walleij07934482010-03-26 16:50:49 -0700597 enum dma_status (*device_tx_status)(struct dma_chan *chan,
598 dma_cookie_t cookie,
599 struct dma_tx_state *txstate);
Dan Williams7405f742007-01-02 11:10:43 -0700600 void (*device_issue_pending)(struct dma_chan *chan);
Chris Leechc13c8262006-05-23 17:18:44 -0700601};
602
Sascha Hauer6e3ecaf2010-09-30 13:56:33 +0000603static inline int dmaengine_device_control(struct dma_chan *chan,
604 enum dma_ctrl_cmd cmd,
605 unsigned long arg)
606{
607 return chan->device->device_control(chan, cmd, arg);
608}
609
610static inline int dmaengine_slave_config(struct dma_chan *chan,
611 struct dma_slave_config *config)
612{
613 return dmaengine_device_control(chan, DMA_SLAVE_CONFIG,
614 (unsigned long)config);
615}
616
Vinod Koul90b44f82011-07-25 19:57:52 +0530617static inline struct dma_async_tx_descriptor *dmaengine_prep_slave_single(
618 struct dma_chan *chan, void *buf, size_t len,
Vinod Koul49920bc2011-10-13 15:15:27 +0530619 enum dma_transfer_direction dir, unsigned long flags)
Vinod Koul90b44f82011-07-25 19:57:52 +0530620{
621 struct scatterlist sg;
622 sg_init_one(&sg, buf, len);
623
Alexandre Bounine185ecb52012-03-08 15:35:13 -0500624 return chan->device->device_prep_slave_sg(chan, &sg, 1,
625 dir, flags, NULL);
Vinod Koul90b44f82011-07-25 19:57:52 +0530626}
627
Alexandre Bounine16052822012-03-08 16:11:18 -0500628static inline struct dma_async_tx_descriptor *dmaengine_prep_slave_sg(
629 struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len,
630 enum dma_transfer_direction dir, unsigned long flags)
631{
632 return chan->device->device_prep_slave_sg(chan, sgl, sg_len,
Alexandre Bounine185ecb52012-03-08 15:35:13 -0500633 dir, flags, NULL);
Alexandre Bounine16052822012-03-08 16:11:18 -0500634}
635
636static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_cyclic(
637 struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
638 size_t period_len, enum dma_transfer_direction dir)
639{
640 return chan->device->device_prep_dma_cyclic(chan, buf_addr, buf_len,
Alexandre Bounine185ecb52012-03-08 15:35:13 -0500641 period_len, dir, NULL);
Sascha Hauer6e3ecaf2010-09-30 13:56:33 +0000642}
643
644static inline int dmaengine_terminate_all(struct dma_chan *chan)
645{
646 return dmaengine_device_control(chan, DMA_TERMINATE_ALL, 0);
647}
Russell King - ARM Linux98d530f2011-01-01 23:00:23 +0000648
Sascha Hauer6e3ecaf2010-09-30 13:56:33 +0000649static inline int dmaengine_pause(struct dma_chan *chan)
650{
651 return dmaengine_device_control(chan, DMA_PAUSE, 0);
652}
Dan Williams83544ae2009-09-08 17:42:53 -0700653
654static inline int dmaengine_resume(struct dma_chan *chan)
655{
656 return dmaengine_device_control(chan, DMA_RESUME, 0);
657}
658
659static inline dma_cookie_t dmaengine_submit(struct dma_async_tx_descriptor *desc)
660{
661 return desc->tx_submit(desc);
662}
663
664static inline bool dmaengine_check_align(u8 align, size_t off1, size_t off2, size_t len)
665{
666 size_t mask;
667
668 if (!align)
669 return true;
670 mask = (1 << align) - 1;
671 if (mask & (off1 | off2 | len))
672 return false;
673 return true;
674}
675
676static inline bool is_dma_copy_aligned(struct dma_device *dev, size_t off1,
677 size_t off2, size_t len)
678{
679 return dmaengine_check_align(dev->copy_align, off1, off2, len);
680}
681
682static inline bool is_dma_xor_aligned(struct dma_device *dev, size_t off1,
683 size_t off2, size_t len)
684{
685 return dmaengine_check_align(dev->xor_align, off1, off2, len);
686}
687
688static inline bool is_dma_pq_aligned(struct dma_device *dev, size_t off1,
Dan Williamsb2f46fd2009-07-14 12:20:36 -0700689 size_t off2, size_t len)
690{
691 return dmaengine_check_align(dev->pq_align, off1, off2, len);
692}
693
694static inline bool is_dma_fill_aligned(struct dma_device *dev, size_t off1,
695 size_t off2, size_t len)
696{
697 return dmaengine_check_align(dev->fill_align, off1, off2, len);
698}
699
700static inline void
701dma_set_maxpq(struct dma_device *dma, int maxpq, int has_pq_continue)
702{
703 dma->max_pq = maxpq;
704 if (has_pq_continue)
705 dma->max_pq |= DMA_HAS_PQ_CONTINUE;
706}
707
708static inline bool dmaf_continue(enum dma_ctrl_flags flags)
709{
710 return (flags & DMA_PREP_CONTINUE) == DMA_PREP_CONTINUE;
711}
712
713static inline bool dmaf_p_disabled_continue(enum dma_ctrl_flags flags)
Mathieu Lacaged3f3cf82010-08-14 15:02:44 +0200714{
Dan Williamsb2f46fd2009-07-14 12:20:36 -0700715 enum dma_ctrl_flags mask = DMA_PREP_CONTINUE | DMA_PREP_PQ_DISABLE_P;
716
717 return (flags & mask) == mask;
718}
719
720static inline bool dma_dev_has_pq_continue(struct dma_device *dma)
721{
722 return (dma->max_pq & DMA_HAS_PQ_CONTINUE) == DMA_HAS_PQ_CONTINUE;
723}
724
725static inline unsigned short dma_dev_to_maxpq(struct dma_device *dma)
726{
727 return dma->max_pq & ~DMA_HAS_PQ_CONTINUE;
728}
729
730/* dma_maxpq - reduce maxpq in the face of continued operations
731 * @dma - dma device with PQ capability
732 * @flags - to check if DMA_PREP_CONTINUE and DMA_PREP_PQ_DISABLE_P are set
733 *
734 * When an engine does not support native continuation we need 3 extra
735 * source slots to reuse P and Q with the following coefficients:
736 * 1/ {00} * P : remove P from Q', but use it as a source for P'
737 * 2/ {01} * Q : use Q to continue Q' calculation
738 * 3/ {00} * Q : subtract Q from P' to cancel (2)
739 *
740 * In the case where P is disabled we only need 1 extra source:
741 * 1/ {01} * Q : use Q to continue Q' calculation
742 */
Chris Leechc13c8262006-05-23 17:18:44 -0700743static inline int dma_maxpq(struct dma_device *dma, enum dma_ctrl_flags flags)
744{
Dan Williams649274d2009-01-11 00:20:39 -0800745 if (dma_dev_has_pq_continue(dma) || !dmaf_continue(flags))
Dan Williams209b84a2009-01-06 11:38:17 -0700746 return dma_dev_to_maxpq(dma);
747 else if (dmaf_p_disabled_continue(flags))
Dan Williams649274d2009-01-11 00:20:39 -0800748 return dma_dev_to_maxpq(dma) - 1;
749 else if (dmaf_continue(flags))
750 return dma_dev_to_maxpq(dma) - 3;
751 BUG();
752}
753
754/* --- public DMA engine API --- */
755
756#ifdef CONFIG_DMA_ENGINE
David S. Millerb4bd07c2009-02-06 22:06:43 -0800757void dmaengine_get(void);
758void dmaengine_put(void);
759#else
760static inline void dmaengine_get(void)
761{
762}
763static inline void dmaengine_put(void)
764{
765}
766#endif
767
768#ifdef CONFIG_NET_DMA
Dan Williams729b5d12009-03-25 09:13:25 -0700769#define net_dmaengine_get() dmaengine_get()
770#define net_dmaengine_put() dmaengine_put()
771#else
Dan Williams5fc6d892010-10-07 16:44:50 -0700772static inline void net_dmaengine_get(void)
Dan Williams138f4c32009-09-08 17:42:51 -0700773{
774}
Dan Williams729b5d12009-03-25 09:13:25 -0700775static inline void net_dmaengine_put(void)
Dan Williams5fc6d892010-10-07 16:44:50 -0700776{
Dan Williams729b5d12009-03-25 09:13:25 -0700777}
778#endif
779
780#ifdef CONFIG_ASYNC_TX_DMA
781#define async_dmaengine_get() dmaengine_get()
782#define async_dmaengine_put() dmaengine_put()
783#ifndef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
784#define async_dma_find_channel(type) dma_find_channel(DMA_ASYNC_TX)
785#else
786#define async_dma_find_channel(type) dma_find_channel(type)
787#endif /* CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH */
788#else
Dan Williams138f4c32009-09-08 17:42:51 -0700789static inline void async_dmaengine_get(void)
Dan Williams729b5d12009-03-25 09:13:25 -0700790{
Dan Williams7405f742007-01-02 11:10:43 -0700791}
792static inline void async_dmaengine_put(void)
793{
794}
795static inline struct dma_chan *
Chris Leechc13c8262006-05-23 17:18:44 -0700796async_dma_find_channel(enum dma_transaction_type type)
Dan Williams7405f742007-01-02 11:10:43 -0700797{
798 return NULL;
799}
Chris Leechc13c8262006-05-23 17:18:44 -0700800#endif /* CONFIG_ASYNC_TX_DMA */
Dan Williams08398752008-07-17 17:59:56 -0700801
Dan Williams7405f742007-01-02 11:10:43 -0700802dma_cookie_t dma_async_memcpy_buf_to_buf(struct dma_chan *chan,
Dan Williams636bdea2008-04-17 20:17:26 -0700803 void *dest, void *src, size_t len);
804dma_cookie_t dma_async_memcpy_buf_to_pg(struct dma_chan *chan,
805 struct page *page, unsigned int offset, void *kdata, size_t len);
Guennadi Liakhovetskief560682009-01-19 15:36:21 -0700806dma_cookie_t dma_async_memcpy_pg_to_pg(struct dma_chan *chan,
807 struct page *dest_pg, unsigned int dest_off, struct page *src_pg,
808 unsigned int src_off, size_t len);
809void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx,
810 struct dma_chan *chan);
Dan Williams08398752008-07-17 17:59:56 -0700811
Dan Williams636bdea2008-04-17 20:17:26 -0700812static inline void async_tx_ack(struct dma_async_tx_descriptor *tx)
Dan Williams08398752008-07-17 17:59:56 -0700813{
Chris Leechc13c8262006-05-23 17:18:44 -0700814 tx->flags |= DMA_CTRL_ACK;
815}
Dan Williams7405f742007-01-02 11:10:43 -0700816
817static inline void async_tx_clear_ack(struct dma_async_tx_descriptor *tx)
818{
819 tx->flags &= ~DMA_CTRL_ACK;
820}
821
822static inline bool async_tx_test_ack(struct dma_async_tx_descriptor *tx)
823{
824 return (tx->flags & DMA_CTRL_ACK) == DMA_CTRL_ACK;
825}
826
827#define first_dma_cap(mask) __first_dma_cap(&(mask))
828static inline int __first_dma_cap(const dma_cap_mask_t *srcp)
829{
830 return min_t(int, DMA_TX_TYPE_END,
831 find_first_bit(srcp->bits, DMA_TX_TYPE_END));
832}
833
834#define next_dma_cap(n, mask) __next_dma_cap((n), &(mask))
835static inline int __next_dma_cap(int n, const dma_cap_mask_t *srcp)
836{
Atsushi Nemoto0f571512009-03-06 20:07:14 +0900837 return min_t(int, DMA_TX_TYPE_END,
838 find_next_bit(srcp->bits, DMA_TX_TYPE_END, n+1));
839}
840
841#define dma_cap_set(tx, mask) __dma_cap_set((tx), &(mask))
842static inline void
843__dma_cap_set(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp)
Dan Williams33df8ca2009-01-06 11:38:15 -0700844{
845 set_bit(tx_type, dstp->bits);
846}
847
848#define dma_cap_clear(tx, mask) __dma_cap_clear((tx), &(mask))
849static inline void
Dan Williams7405f742007-01-02 11:10:43 -0700850__dma_cap_clear(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp)
851{
852 clear_bit(tx_type, dstp->bits);
853}
854
855#define dma_cap_zero(mask) __dma_cap_zero(&(mask))
856static inline void __dma_cap_zero(dma_cap_mask_t *dstp)
857{
858 bitmap_zero(dstp->bits, DMA_TX_TYPE_END);
859}
860
861#define dma_has_cap(tx, mask) __dma_has_cap((tx), &(mask))
Chris Leechc13c8262006-05-23 17:18:44 -0700862static inline int
Dan Williams7405f742007-01-02 11:10:43 -0700863__dma_has_cap(enum dma_transaction_type tx_type, dma_cap_mask_t *srcp)
Randy Dunlapfe4ada22006-07-03 19:44:51 -0700864{
Chris Leechc13c8262006-05-23 17:18:44 -0700865 return test_bit(tx_type, srcp->bits);
866}
867
868#define for_each_dma_cap_mask(cap, mask) \
Dan Williams7405f742007-01-02 11:10:43 -0700869 for ((cap) = first_dma_cap(mask); \
Chris Leechc13c8262006-05-23 17:18:44 -0700870 (cap) < DMA_TX_TYPE_END; \
Dan Williamsec8670f2008-03-01 07:51:29 -0700871 (cap) = next_dma_cap((cap), (mask)))
Chris Leechc13c8262006-05-23 17:18:44 -0700872
873/**
Dan Williams7405f742007-01-02 11:10:43 -0700874 * dma_async_issue_pending - flush pending transactions to HW
875 * @chan: target DMA channel
Chris Leechc13c8262006-05-23 17:18:44 -0700876 *
Dan Williams7405f742007-01-02 11:10:43 -0700877 * This allows drivers to push copies to HW in batches,
Chris Leechc13c8262006-05-23 17:18:44 -0700878 * reducing MMIO writes where possible.
879 */
880static inline void dma_async_issue_pending(struct dma_chan *chan)
881{
882 chan->device->device_issue_pending(chan);
883}
884
885#define dma_async_memcpy_issue_pending(chan) dma_async_issue_pending(chan)
886
Dan Williams7405f742007-01-02 11:10:43 -0700887/**
Chris Leechc13c8262006-05-23 17:18:44 -0700888 * dma_async_is_tx_complete - poll for transaction completion
889 * @chan: DMA channel
Linus Walleij07934482010-03-26 16:50:49 -0700890 * @cookie: transaction identifier to check status of
891 * @last: returns last completed cookie, can be NULL
892 * @used: returns last issued cookie, can be NULL
893 *
894 * If @last and @used are passed in, upon return they reflect the driver
895 * internal state and can be used with dma_async_is_complete() to check
896 * the status of multiple cookies without re-checking hardware state.
897 */
898static inline enum dma_status dma_async_is_tx_complete(struct dma_chan *chan,
Chris Leechc13c8262006-05-23 17:18:44 -0700899 dma_cookie_t cookie, dma_cookie_t *last, dma_cookie_t *used)
900{
Dan Williams7405f742007-01-02 11:10:43 -0700901 struct dma_tx_state state;
902 enum dma_status status;
903
Chris Leechc13c8262006-05-23 17:18:44 -0700904 status = chan->device->device_tx_status(chan, cookie, &state);
905 if (last)
906 *last = state.last;
907 if (used)
908 *used = state.used;
909 return status;
910}
Sebastian Siewior8a5703f2008-04-21 22:38:45 +0000911
Chris Leechc13c8262006-05-23 17:18:44 -0700912#define dma_async_memcpy_complete(chan, cookie, last, used)\
913 dma_async_is_tx_complete(chan, cookie, last, used)
914
915/**
916 * dma_async_is_complete - test a cookie against chan state
917 * @cookie: transaction identifier to test status of
918 * @last_complete: last know completed transaction
919 * @last_used: last cookie value handed out
920 *
921 * dma_async_is_complete() is used in dma_async_memcpy_complete()
922 * the test logic is separated for lightweight testing of multiple cookies
923 */
924static inline enum dma_status dma_async_is_complete(dma_cookie_t cookie,
925 dma_cookie_t last_complete, dma_cookie_t last_used)
Dan Williamsbca34692010-03-26 16:52:10 -0700926{
927 if (last_complete <= last_used) {
928 if ((cookie <= last_complete) || (cookie > last_used))
929 return DMA_SUCCESS;
930 } else {
931 if ((cookie <= last_complete) && (cookie > last_used))
932 return DMA_SUCCESS;
933 }
934 return DMA_IN_PROGRESS;
935}
Dan Williams7405f742007-01-02 11:10:43 -0700936
Dan Williams07f22112009-01-05 17:14:31 -0700937static inline void
938dma_set_tx_state(struct dma_tx_state *st, dma_cookie_t last, dma_cookie_t used, u32 residue)
Dan Williamsc50331e2009-01-19 15:33:14 -0700939{
Guennadi Liakhovetski8f33d522010-12-22 14:46:46 +0100940 if (st) {
941 st->last = last;
Dan Williams07f22112009-01-05 17:14:31 -0700942 st->used = used;
943 st->residue = residue;
944 }
945}
946
Dan Williamsc50331e2009-01-19 15:33:14 -0700947enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie);
948#ifdef CONFIG_DMA_ENGINE
Guennadi Liakhovetski8f33d522010-12-22 14:46:46 +0100949enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx);
950void dma_issue_pending_all(void);
951struct dma_chan *__dma_request_channel(dma_cap_mask_t *mask, dma_filter_fn fn, void *fn_param);
952void dma_release_channel(struct dma_chan *chan);
953#else
954static inline enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx)
955{
956 return DMA_SUCCESS;
Dan Williamsc50331e2009-01-19 15:33:14 -0700957}
Dan Williams07f22112009-01-05 17:14:31 -0700958static inline void dma_issue_pending_all(void)
Chris Leechc13c8262006-05-23 17:18:44 -0700959{
960}
961static inline struct dma_chan *__dma_request_channel(dma_cap_mask_t *mask,
962 dma_filter_fn fn, void *fn_param)
963{
Dan Williams07f22112009-01-05 17:14:31 -0700964 return NULL;
Dan Williamsbec08512009-01-06 11:38:14 -0700965}
Dan Williams59b5ec22009-01-06 11:38:15 -0700966static inline void dma_release_channel(struct dma_chan *chan)
Chris Leechc13c8262006-05-23 17:18:44 -0700967{
Chris Leechde5506e2006-05-23 17:50:37 -0700968}
969#endif
970
Al Virob2ddb902008-03-29 03:09:38 +0000971/* --- DMA device --- */
Chris Leechde5506e2006-05-23 17:50:37 -0700972
973int dma_async_device_register(struct dma_device *device);
974void dma_async_device_unregister(struct dma_device *device);
975void dma_run_dependencies(struct dma_async_tx_descriptor *tx);
976struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type);
Dave Jianga2bd1142012-04-04 16:10:46 -0700977struct dma_chan *net_dma_find_channel(void);
Chris Leechde5506e2006-05-23 17:50:37 -0700978#define dma_request_channel(mask, x, y) __dma_request_channel(&(mask), x, y)
979
980/* --- Helper iov-locking functions --- */
981
982struct dma_page_list {
983 char __user *base_address;
984 int nr_pages;
985 struct page **pages;
986};
987
988struct dma_pinned_list {
989 int nr_iovecs;
990 struct dma_page_list page_list[0];
991};
992
993struct dma_pinned_list *dma_pin_iovec_pages(struct iovec *iov, size_t len);
994void dma_unpin_iovec_pages(struct dma_pinned_list* pinned_list);
Chris Leechc13c8262006-05-23 17:18:44 -0700995
996dma_cookie_t dma_memcpy_to_iovec(struct dma_chan *chan, struct iovec *iov,
997 struct dma_pinned_list *pinned_list, unsigned char *kdata, size_t len);
998dma_cookie_t dma_memcpy_pg_to_iovec(struct dma_chan *chan, struct iovec *iov,
999 struct dma_pinned_list *pinned_list, struct page *page,
1000 unsigned int offset, size_t len);
1001
1002#endif /* DMAENGINE_H */