Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * linux/drivers/ide/pci/piix.c Version 0.44 March 20, 2003 |
| 3 | * |
| 4 | * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer |
| 5 | * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org> |
| 6 | * Copyright (C) 2003 Red Hat Inc <alan@redhat.com> |
| 7 | * |
| 8 | * May be copied or modified under the terms of the GNU General Public License |
| 9 | * |
| 10 | * PIO mode setting function for Intel chipsets. |
| 11 | * For use instead of BIOS settings. |
| 12 | * |
| 13 | * 40-41 |
| 14 | * 42-43 |
| 15 | * |
| 16 | * 41 |
| 17 | * 43 |
| 18 | * |
| 19 | * | PIO 0 | c0 | 80 | 0 | piix_tune_drive(drive, 0); |
| 20 | * | PIO 2 | SW2 | d0 | 90 | 4 | piix_tune_drive(drive, 2); |
| 21 | * | PIO 3 | MW1 | e1 | a1 | 9 | piix_tune_drive(drive, 3); |
| 22 | * | PIO 4 | MW2 | e3 | a3 | b | piix_tune_drive(drive, 4); |
| 23 | * |
| 24 | * sitre = word40 & 0x4000; primary |
| 25 | * sitre = word42 & 0x4000; secondary |
| 26 | * |
| 27 | * 44 8421|8421 hdd|hdb |
| 28 | * |
| 29 | * 48 8421 hdd|hdc|hdb|hda udma enabled |
| 30 | * |
| 31 | * 0001 hda |
| 32 | * 0010 hdb |
| 33 | * 0100 hdc |
| 34 | * 1000 hdd |
| 35 | * |
| 36 | * 4a 84|21 hdb|hda |
| 37 | * 4b 84|21 hdd|hdc |
| 38 | * |
| 39 | * ata-33/82371AB |
| 40 | * ata-33/82371EB |
| 41 | * ata-33/82801AB ata-66/82801AA |
| 42 | * 00|00 udma 0 00|00 reserved |
| 43 | * 01|01 udma 1 01|01 udma 3 |
| 44 | * 10|10 udma 2 10|10 udma 4 |
| 45 | * 11|11 reserved 11|11 reserved |
| 46 | * |
| 47 | * 54 8421|8421 ata66 drive|ata66 enable |
| 48 | * |
| 49 | * pci_read_config_word(HWIF(drive)->pci_dev, 0x40, ®40); |
| 50 | * pci_read_config_word(HWIF(drive)->pci_dev, 0x42, ®42); |
| 51 | * pci_read_config_word(HWIF(drive)->pci_dev, 0x44, ®44); |
| 52 | * pci_read_config_byte(HWIF(drive)->pci_dev, 0x48, ®48); |
| 53 | * pci_read_config_word(HWIF(drive)->pci_dev, 0x4a, ®4a); |
| 54 | * pci_read_config_byte(HWIF(drive)->pci_dev, 0x54, ®54); |
| 55 | * |
| 56 | * Documentation |
| 57 | * Publically available from Intel web site. Errata documentation |
| 58 | * is also publically available. As an aide to anyone hacking on this |
| 59 | * driver the list of errata that are relevant is below.going back to |
| 60 | * PIIX4. Older device documentation is now a bit tricky to find. |
| 61 | * |
| 62 | * Errata of note: |
| 63 | * |
| 64 | * Unfixable |
| 65 | * PIIX4 errata #9 - Only on ultra obscure hw |
| 66 | * ICH3 errata #13 - Not observed to affect real hw |
| 67 | * by Intel |
| 68 | * |
| 69 | * Things we must deal with |
| 70 | * PIIX4 errata #10 - BM IDE hang with non UDMA |
| 71 | * (must stop/start dma to recover) |
| 72 | * 440MX errata #15 - As PIIX4 errata #10 |
| 73 | * PIIX4 errata #15 - Must not read control registers |
| 74 | * during a PIO transfer |
| 75 | * 440MX errata #13 - As PIIX4 errata #15 |
| 76 | * ICH2 errata #21 - DMA mode 0 doesn't work right |
| 77 | * ICH0/1 errata #55 - As ICH2 errata #21 |
| 78 | * ICH2 spec c #9 - Extra operations needed to handle |
| 79 | * drive hotswap [NOT YET SUPPORTED] |
| 80 | * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary |
| 81 | * and must be dword aligned |
| 82 | * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3 |
| 83 | * |
| 84 | * Should have been BIOS fixed: |
| 85 | * 450NX: errata #19 - DMA hangs on old 450NX |
| 86 | * 450NX: errata #20 - DMA hangs on old 450NX |
| 87 | * 450NX: errata #25 - Corruption with DMA on old 450NX |
| 88 | * ICH3 errata #15 - IDE deadlock under high load |
| 89 | * (BIOS must set dev 31 fn 0 bit 23) |
| 90 | * ICH3 errata #18 - Don't use native mode |
| 91 | */ |
| 92 | |
| 93 | #include <linux/config.h> |
| 94 | #include <linux/types.h> |
| 95 | #include <linux/module.h> |
| 96 | #include <linux/kernel.h> |
| 97 | #include <linux/ioport.h> |
| 98 | #include <linux/pci.h> |
| 99 | #include <linux/hdreg.h> |
| 100 | #include <linux/ide.h> |
| 101 | #include <linux/delay.h> |
| 102 | #include <linux/init.h> |
| 103 | |
| 104 | #include <asm/io.h> |
| 105 | |
| 106 | static int no_piix_dma; |
| 107 | |
| 108 | /** |
| 109 | * piix_ratemask - compute rate mask for PIIX IDE |
| 110 | * @drive: IDE drive to compute for |
| 111 | * |
| 112 | * Returns the available modes for the PIIX IDE controller. |
| 113 | */ |
| 114 | |
| 115 | static u8 piix_ratemask (ide_drive_t *drive) |
| 116 | { |
| 117 | struct pci_dev *dev = HWIF(drive)->pci_dev; |
| 118 | u8 mode; |
| 119 | |
| 120 | switch(dev->device) { |
| 121 | case PCI_DEVICE_ID_INTEL_82801EB_1: |
| 122 | mode = 3; |
| 123 | break; |
| 124 | /* UDMA 100 capable */ |
| 125 | case PCI_DEVICE_ID_INTEL_82801BA_8: |
| 126 | case PCI_DEVICE_ID_INTEL_82801BA_9: |
| 127 | case PCI_DEVICE_ID_INTEL_82801CA_10: |
| 128 | case PCI_DEVICE_ID_INTEL_82801CA_11: |
| 129 | case PCI_DEVICE_ID_INTEL_82801E_11: |
| 130 | case PCI_DEVICE_ID_INTEL_82801DB_1: |
| 131 | case PCI_DEVICE_ID_INTEL_82801DB_10: |
| 132 | case PCI_DEVICE_ID_INTEL_82801DB_11: |
| 133 | case PCI_DEVICE_ID_INTEL_82801EB_11: |
| 134 | case PCI_DEVICE_ID_INTEL_ESB_2: |
| 135 | case PCI_DEVICE_ID_INTEL_ICH6_19: |
| 136 | case PCI_DEVICE_ID_INTEL_ICH7_21: |
Jason Gaston | d69332b | 2005-04-16 15:24:42 -0700 | [diff] [blame] | 137 | case PCI_DEVICE_ID_INTEL_ESB2_18: |
Jason Gaston | b7bed9e | 2006-02-03 03:04:52 -0800 | [diff] [blame] | 138 | case PCI_DEVICE_ID_INTEL_ICH8_6: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 139 | mode = 3; |
| 140 | break; |
| 141 | /* UDMA 66 capable */ |
| 142 | case PCI_DEVICE_ID_INTEL_82801AA_1: |
| 143 | case PCI_DEVICE_ID_INTEL_82372FB_1: |
| 144 | mode = 2; |
| 145 | break; |
| 146 | /* UDMA 33 capable */ |
| 147 | case PCI_DEVICE_ID_INTEL_82371AB: |
| 148 | case PCI_DEVICE_ID_INTEL_82443MX_1: |
| 149 | case PCI_DEVICE_ID_INTEL_82451NX: |
| 150 | case PCI_DEVICE_ID_INTEL_82801AB_1: |
| 151 | return 1; |
| 152 | /* Non UDMA capable (MWDMA2) */ |
| 153 | case PCI_DEVICE_ID_INTEL_82371SB_1: |
| 154 | case PCI_DEVICE_ID_INTEL_82371FB_1: |
| 155 | case PCI_DEVICE_ID_INTEL_82371FB_0: |
| 156 | case PCI_DEVICE_ID_INTEL_82371MX: |
| 157 | default: |
| 158 | return 0; |
| 159 | } |
| 160 | |
| 161 | /* |
| 162 | * If we are UDMA66 capable fall back to UDMA33 |
| 163 | * if the drive cannot see an 80pin cable. |
| 164 | */ |
| 165 | if (!eighty_ninty_three(drive)) |
| 166 | mode = min(mode, (u8)1); |
| 167 | return mode; |
| 168 | } |
| 169 | |
| 170 | /** |
| 171 | * piix_dma_2_pio - return the PIO mode matching DMA |
| 172 | * @xfer_rate: transfer speed |
| 173 | * |
| 174 | * Returns the nearest equivalent PIO timing for the PIO or DMA |
| 175 | * mode requested by the controller. |
| 176 | */ |
| 177 | |
| 178 | static u8 piix_dma_2_pio (u8 xfer_rate) { |
| 179 | switch(xfer_rate) { |
| 180 | case XFER_UDMA_6: |
| 181 | case XFER_UDMA_5: |
| 182 | case XFER_UDMA_4: |
| 183 | case XFER_UDMA_3: |
| 184 | case XFER_UDMA_2: |
| 185 | case XFER_UDMA_1: |
| 186 | case XFER_UDMA_0: |
| 187 | case XFER_MW_DMA_2: |
| 188 | case XFER_PIO_4: |
| 189 | return 4; |
| 190 | case XFER_MW_DMA_1: |
| 191 | case XFER_PIO_3: |
| 192 | return 3; |
| 193 | case XFER_SW_DMA_2: |
| 194 | case XFER_PIO_2: |
| 195 | return 2; |
| 196 | case XFER_MW_DMA_0: |
| 197 | case XFER_SW_DMA_1: |
| 198 | case XFER_SW_DMA_0: |
| 199 | case XFER_PIO_1: |
| 200 | case XFER_PIO_0: |
| 201 | case XFER_PIO_SLOW: |
| 202 | default: |
| 203 | return 0; |
| 204 | } |
| 205 | } |
| 206 | |
| 207 | /** |
| 208 | * piix_tune_drive - tune a drive attached to a PIIX |
| 209 | * @drive: drive to tune |
| 210 | * @pio: desired PIO mode |
| 211 | * |
| 212 | * Set the interface PIO mode based upon the settings done by AMI BIOS |
| 213 | * (might be useful if drive is not registered in CMOS for any reason). |
| 214 | */ |
| 215 | static void piix_tune_drive (ide_drive_t *drive, u8 pio) |
| 216 | { |
| 217 | ide_hwif_t *hwif = HWIF(drive); |
| 218 | struct pci_dev *dev = hwif->pci_dev; |
| 219 | int is_slave = (&hwif->drives[1] == drive); |
| 220 | int master_port = hwif->channel ? 0x42 : 0x40; |
| 221 | int slave_port = 0x44; |
| 222 | unsigned long flags; |
| 223 | u16 master_data; |
| 224 | u8 slave_data; |
Alan Cox | 4fb0f76 | 2006-06-26 00:26:12 -0700 | [diff] [blame] | 225 | static DEFINE_SPINLOCK(tune_lock); |
| 226 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 227 | /* ISP RTC */ |
| 228 | u8 timings[][2] = { { 0, 0 }, |
| 229 | { 0, 0 }, |
| 230 | { 1, 0 }, |
| 231 | { 2, 1 }, |
| 232 | { 2, 3 }, }; |
| 233 | |
| 234 | pio = ide_get_best_pio_mode(drive, pio, 5, NULL); |
Alan Cox | 4fb0f76 | 2006-06-26 00:26:12 -0700 | [diff] [blame] | 235 | |
| 236 | /* |
| 237 | * Master vs slave is synchronized above us but the slave register is |
| 238 | * shared by the two hwifs so the corner case of two slave timeouts in |
| 239 | * parallel must be locked. |
| 240 | */ |
| 241 | spin_lock_irqsave(&tune_lock, flags); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 242 | pci_read_config_word(dev, master_port, &master_data); |
| 243 | if (is_slave) { |
| 244 | master_data = master_data | 0x4000; |
| 245 | if (pio > 1) |
| 246 | /* enable PPE, IE and TIME */ |
| 247 | master_data = master_data | 0x0070; |
| 248 | pci_read_config_byte(dev, slave_port, &slave_data); |
| 249 | slave_data = slave_data & (hwif->channel ? 0x0f : 0xf0); |
| 250 | slave_data = slave_data | (((timings[pio][0] << 2) | timings[pio][1]) << (hwif->channel ? 4 : 0)); |
| 251 | } else { |
| 252 | master_data = master_data & 0xccf8; |
| 253 | if (pio > 1) |
| 254 | /* enable PPE, IE and TIME */ |
| 255 | master_data = master_data | 0x0007; |
| 256 | master_data = master_data | (timings[pio][0] << 12) | (timings[pio][1] << 8); |
| 257 | } |
| 258 | pci_write_config_word(dev, master_port, master_data); |
| 259 | if (is_slave) |
| 260 | pci_write_config_byte(dev, slave_port, slave_data); |
Alan Cox | 4fb0f76 | 2006-06-26 00:26:12 -0700 | [diff] [blame] | 261 | spin_unlock_irqrestore(&tune_lock, flags); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 262 | } |
| 263 | |
| 264 | /** |
| 265 | * piix_tune_chipset - tune a PIIX interface |
| 266 | * @drive: IDE drive to tune |
| 267 | * @xferspeed: speed to configure |
| 268 | * |
| 269 | * Set a PIIX interface channel to the desired speeds. This involves |
| 270 | * requires the right timing data into the PIIX configuration space |
| 271 | * then setting the drive parameters appropriately |
| 272 | */ |
| 273 | |
| 274 | static int piix_tune_chipset (ide_drive_t *drive, u8 xferspeed) |
| 275 | { |
| 276 | ide_hwif_t *hwif = HWIF(drive); |
| 277 | struct pci_dev *dev = hwif->pci_dev; |
| 278 | u8 maslave = hwif->channel ? 0x42 : 0x40; |
| 279 | u8 speed = ide_rate_filter(piix_ratemask(drive), xferspeed); |
| 280 | int a_speed = 3 << (drive->dn * 4); |
| 281 | int u_flag = 1 << drive->dn; |
| 282 | int v_flag = 0x01 << drive->dn; |
| 283 | int w_flag = 0x10 << drive->dn; |
| 284 | int u_speed = 0; |
| 285 | int sitre; |
| 286 | u16 reg4042, reg4a; |
| 287 | u8 reg48, reg54, reg55; |
| 288 | |
| 289 | pci_read_config_word(dev, maslave, ®4042); |
| 290 | sitre = (reg4042 & 0x4000) ? 1 : 0; |
| 291 | pci_read_config_byte(dev, 0x48, ®48); |
| 292 | pci_read_config_word(dev, 0x4a, ®4a); |
| 293 | pci_read_config_byte(dev, 0x54, ®54); |
| 294 | pci_read_config_byte(dev, 0x55, ®55); |
| 295 | |
| 296 | switch(speed) { |
| 297 | case XFER_UDMA_4: |
| 298 | case XFER_UDMA_2: u_speed = 2 << (drive->dn * 4); break; |
| 299 | case XFER_UDMA_5: |
| 300 | case XFER_UDMA_3: |
| 301 | case XFER_UDMA_1: u_speed = 1 << (drive->dn * 4); break; |
| 302 | case XFER_UDMA_0: u_speed = 0 << (drive->dn * 4); break; |
| 303 | case XFER_MW_DMA_2: |
| 304 | case XFER_MW_DMA_1: |
| 305 | case XFER_SW_DMA_2: break; |
| 306 | case XFER_PIO_4: |
| 307 | case XFER_PIO_3: |
| 308 | case XFER_PIO_2: |
| 309 | case XFER_PIO_0: break; |
| 310 | default: return -1; |
| 311 | } |
| 312 | |
| 313 | if (speed >= XFER_UDMA_0) { |
| 314 | if (!(reg48 & u_flag)) |
| 315 | pci_write_config_byte(dev, 0x48, reg48 | u_flag); |
| 316 | if (speed == XFER_UDMA_5) { |
| 317 | pci_write_config_byte(dev, 0x55, (u8) reg55|w_flag); |
| 318 | } else { |
| 319 | pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag); |
| 320 | } |
| 321 | if ((reg4a & a_speed) != u_speed) |
| 322 | pci_write_config_word(dev, 0x4a, (reg4a & ~a_speed) | u_speed); |
| 323 | if (speed > XFER_UDMA_2) { |
| 324 | if (!(reg54 & v_flag)) |
| 325 | pci_write_config_byte(dev, 0x54, reg54 | v_flag); |
| 326 | } else |
| 327 | pci_write_config_byte(dev, 0x54, reg54 & ~v_flag); |
| 328 | } else { |
| 329 | if (reg48 & u_flag) |
| 330 | pci_write_config_byte(dev, 0x48, reg48 & ~u_flag); |
| 331 | if (reg4a & a_speed) |
| 332 | pci_write_config_word(dev, 0x4a, reg4a & ~a_speed); |
| 333 | if (reg54 & v_flag) |
| 334 | pci_write_config_byte(dev, 0x54, reg54 & ~v_flag); |
| 335 | if (reg55 & w_flag) |
| 336 | pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag); |
| 337 | } |
| 338 | |
| 339 | piix_tune_drive(drive, piix_dma_2_pio(speed)); |
| 340 | return (ide_config_drive_speed(drive, speed)); |
| 341 | } |
| 342 | |
| 343 | /** |
| 344 | * piix_faulty_dma0 - check for DMA0 errata |
| 345 | * @hwif: IDE interface to check |
| 346 | * |
| 347 | * If an ICH/ICH0/ICH2 interface is is operating in multi-word |
| 348 | * DMA mode with 600nS cycle time the IDE PIO prefetch buffer will |
| 349 | * inadvertently provide an extra piece of secondary data to the primary |
| 350 | * device resulting in data corruption. |
| 351 | * |
| 352 | * With such a device this test function returns true. This allows |
| 353 | * our tuning code to follow Intel recommendations and use PIO on |
| 354 | * such devices. |
| 355 | */ |
| 356 | |
| 357 | static int piix_faulty_dma0(ide_hwif_t *hwif) |
| 358 | { |
| 359 | switch(hwif->pci_dev->device) |
| 360 | { |
| 361 | case PCI_DEVICE_ID_INTEL_82801AA_1: /* ICH */ |
| 362 | case PCI_DEVICE_ID_INTEL_82801AB_1: /* ICH0 */ |
| 363 | case PCI_DEVICE_ID_INTEL_82801BA_8: /* ICH2 */ |
| 364 | case PCI_DEVICE_ID_INTEL_82801BA_9: /* ICH2 */ |
| 365 | return 1; |
| 366 | } |
| 367 | return 0; |
| 368 | } |
| 369 | |
| 370 | /** |
| 371 | * piix_config_drive_for_dma - configure drive for DMA |
| 372 | * @drive: IDE drive to configure |
| 373 | * |
| 374 | * Set up a PIIX interface channel for the best available speed. |
| 375 | * We prefer UDMA if it is available and then MWDMA. If DMA is |
| 376 | * not available we switch to PIO and return 0. |
| 377 | */ |
| 378 | |
| 379 | static int piix_config_drive_for_dma (ide_drive_t *drive) |
| 380 | { |
| 381 | u8 speed = ide_dma_speed(drive, piix_ratemask(drive)); |
| 382 | |
| 383 | /* Some ICH devices cannot support DMA mode 0 */ |
| 384 | if(speed == XFER_MW_DMA_0 && piix_faulty_dma0(HWIF(drive))) |
| 385 | speed = 0; |
| 386 | |
| 387 | /* If no DMA speed was available or the chipset has DMA bugs |
| 388 | then disable DMA and use PIO */ |
| 389 | |
| 390 | if (!speed || no_piix_dma) { |
| 391 | u8 tspeed = ide_get_best_pio_mode(drive, 255, 5, NULL); |
| 392 | speed = piix_dma_2_pio(XFER_PIO_0 + tspeed); |
| 393 | } |
| 394 | |
| 395 | (void) piix_tune_chipset(drive, speed); |
| 396 | return ide_dma_enable(drive); |
| 397 | } |
| 398 | |
| 399 | /** |
| 400 | * piix_config_drive_xfer_rate - set up an IDE device |
| 401 | * @drive: IDE drive to configure |
| 402 | * |
| 403 | * Set up the PIIX interface for the best available speed on this |
| 404 | * interface, preferring DMA to PIO. |
| 405 | */ |
| 406 | |
| 407 | static int piix_config_drive_xfer_rate (ide_drive_t *drive) |
| 408 | { |
| 409 | ide_hwif_t *hwif = HWIF(drive); |
| 410 | struct hd_driveid *id = drive->id; |
| 411 | |
| 412 | drive->init_speed = 0; |
| 413 | |
| 414 | if ((id->capability & 1) && drive->autodma) { |
| 415 | |
| 416 | if (ide_use_dma(drive)) { |
| 417 | if (piix_config_drive_for_dma(drive)) |
| 418 | return hwif->ide_dma_on(drive); |
| 419 | } |
| 420 | |
| 421 | goto fast_ata_pio; |
| 422 | |
| 423 | } else if ((id->capability & 8) || (id->field_valid & 2)) { |
| 424 | fast_ata_pio: |
| 425 | /* Find best PIO mode. */ |
| 426 | hwif->tuneproc(drive, 255); |
| 427 | return hwif->ide_dma_off_quietly(drive); |
| 428 | } |
| 429 | /* IORDY not supported */ |
| 430 | return 0; |
| 431 | } |
| 432 | |
| 433 | /** |
| 434 | * init_chipset_piix - set up the PIIX chipset |
| 435 | * @dev: PCI device to set up |
| 436 | * @name: Name of the device |
| 437 | * |
| 438 | * Initialize the PCI device as required. For the PIIX this turns |
| 439 | * out to be nice and simple |
| 440 | */ |
| 441 | |
| 442 | static unsigned int __devinit init_chipset_piix (struct pci_dev *dev, const char *name) |
| 443 | { |
| 444 | switch(dev->device) { |
| 445 | case PCI_DEVICE_ID_INTEL_82801EB_1: |
| 446 | case PCI_DEVICE_ID_INTEL_82801AA_1: |
| 447 | case PCI_DEVICE_ID_INTEL_82801AB_1: |
| 448 | case PCI_DEVICE_ID_INTEL_82801BA_8: |
| 449 | case PCI_DEVICE_ID_INTEL_82801BA_9: |
| 450 | case PCI_DEVICE_ID_INTEL_82801CA_10: |
| 451 | case PCI_DEVICE_ID_INTEL_82801CA_11: |
| 452 | case PCI_DEVICE_ID_INTEL_82801DB_1: |
| 453 | case PCI_DEVICE_ID_INTEL_82801DB_10: |
| 454 | case PCI_DEVICE_ID_INTEL_82801DB_11: |
| 455 | case PCI_DEVICE_ID_INTEL_82801EB_11: |
| 456 | case PCI_DEVICE_ID_INTEL_82801E_11: |
| 457 | case PCI_DEVICE_ID_INTEL_ESB_2: |
| 458 | case PCI_DEVICE_ID_INTEL_ICH6_19: |
| 459 | case PCI_DEVICE_ID_INTEL_ICH7_21: |
Jason Gaston | d69332b | 2005-04-16 15:24:42 -0700 | [diff] [blame] | 460 | case PCI_DEVICE_ID_INTEL_ESB2_18: |
Jason Gaston | b7bed9e | 2006-02-03 03:04:52 -0800 | [diff] [blame] | 461 | case PCI_DEVICE_ID_INTEL_ICH8_6: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 462 | { |
| 463 | unsigned int extra = 0; |
| 464 | pci_read_config_dword(dev, 0x54, &extra); |
| 465 | pci_write_config_dword(dev, 0x54, extra|0x400); |
| 466 | } |
| 467 | default: |
| 468 | break; |
| 469 | } |
| 470 | |
| 471 | return 0; |
| 472 | } |
| 473 | |
| 474 | /** |
| 475 | * init_hwif_piix - fill in the hwif for the PIIX |
| 476 | * @hwif: IDE interface |
| 477 | * |
| 478 | * Set up the ide_hwif_t for the PIIX interface according to the |
| 479 | * capabilities of the hardware. |
| 480 | */ |
| 481 | |
| 482 | static void __devinit init_hwif_piix(ide_hwif_t *hwif) |
| 483 | { |
| 484 | u8 reg54h = 0, reg55h = 0, ata66 = 0; |
| 485 | u8 mask = hwif->channel ? 0xc0 : 0x30; |
| 486 | |
| 487 | #ifndef CONFIG_IA64 |
| 488 | if (!hwif->irq) |
| 489 | hwif->irq = hwif->channel ? 15 : 14; |
| 490 | #endif /* CONFIG_IA64 */ |
| 491 | |
| 492 | if (hwif->pci_dev->device == PCI_DEVICE_ID_INTEL_82371MX) { |
| 493 | /* This is a painful system best to let it self tune for now */ |
| 494 | return; |
| 495 | } |
| 496 | |
| 497 | hwif->autodma = 0; |
| 498 | hwif->tuneproc = &piix_tune_drive; |
| 499 | hwif->speedproc = &piix_tune_chipset; |
| 500 | hwif->drives[0].autotune = 1; |
| 501 | hwif->drives[1].autotune = 1; |
| 502 | |
| 503 | if (!hwif->dma_base) |
| 504 | return; |
| 505 | |
| 506 | hwif->atapi_dma = 1; |
| 507 | hwif->ultra_mask = 0x3f; |
| 508 | hwif->mwdma_mask = 0x06; |
| 509 | hwif->swdma_mask = 0x04; |
| 510 | |
| 511 | switch(hwif->pci_dev->device) { |
| 512 | case PCI_DEVICE_ID_INTEL_82371MX: |
| 513 | hwif->mwdma_mask = 0x80; |
| 514 | hwif->swdma_mask = 0x80; |
| 515 | case PCI_DEVICE_ID_INTEL_82371FB_0: |
| 516 | case PCI_DEVICE_ID_INTEL_82371FB_1: |
| 517 | case PCI_DEVICE_ID_INTEL_82371SB_1: |
| 518 | hwif->ultra_mask = 0x80; |
| 519 | break; |
| 520 | case PCI_DEVICE_ID_INTEL_82371AB: |
| 521 | case PCI_DEVICE_ID_INTEL_82443MX_1: |
| 522 | case PCI_DEVICE_ID_INTEL_82451NX: |
| 523 | case PCI_DEVICE_ID_INTEL_82801AB_1: |
| 524 | hwif->ultra_mask = 0x07; |
| 525 | break; |
| 526 | default: |
| 527 | pci_read_config_byte(hwif->pci_dev, 0x54, ®54h); |
| 528 | pci_read_config_byte(hwif->pci_dev, 0x55, ®55h); |
| 529 | ata66 = (reg54h & mask) ? 1 : 0; |
| 530 | break; |
| 531 | } |
| 532 | |
| 533 | if (!(hwif->udma_four)) |
| 534 | hwif->udma_four = ata66; |
| 535 | hwif->ide_dma_check = &piix_config_drive_xfer_rate; |
| 536 | if (!noautodma) |
| 537 | hwif->autodma = 1; |
| 538 | |
| 539 | hwif->drives[1].autodma = hwif->autodma; |
| 540 | hwif->drives[0].autodma = hwif->autodma; |
| 541 | } |
| 542 | |
| 543 | #define DECLARE_PIIX_DEV(name_str) \ |
| 544 | { \ |
| 545 | .name = name_str, \ |
| 546 | .init_chipset = init_chipset_piix, \ |
| 547 | .init_hwif = init_hwif_piix, \ |
| 548 | .channels = 2, \ |
| 549 | .autodma = AUTODMA, \ |
| 550 | .enablebits = {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, \ |
| 551 | .bootable = ON_BOARD, \ |
| 552 | } |
| 553 | |
| 554 | static ide_pci_device_t piix_pci_info[] __devinitdata = { |
| 555 | /* 0 */ DECLARE_PIIX_DEV("PIIXa"), |
| 556 | /* 1 */ DECLARE_PIIX_DEV("PIIXb"), |
| 557 | |
| 558 | { /* 2 */ |
| 559 | .name = "MPIIX", |
| 560 | .init_hwif = init_hwif_piix, |
| 561 | .channels = 2, |
| 562 | .autodma = NODMA, |
| 563 | .enablebits = {{0x6D,0x80,0x80}, {0x6F,0x80,0x80}}, |
| 564 | .bootable = ON_BOARD, |
| 565 | }, |
| 566 | |
| 567 | /* 3 */ DECLARE_PIIX_DEV("PIIX3"), |
| 568 | /* 4 */ DECLARE_PIIX_DEV("PIIX4"), |
| 569 | /* 5 */ DECLARE_PIIX_DEV("ICH0"), |
| 570 | /* 6 */ DECLARE_PIIX_DEV("PIIX4"), |
| 571 | /* 7 */ DECLARE_PIIX_DEV("ICH"), |
| 572 | /* 8 */ DECLARE_PIIX_DEV("PIIX4"), |
| 573 | /* 9 */ DECLARE_PIIX_DEV("PIIX4"), |
| 574 | /* 10 */ DECLARE_PIIX_DEV("ICH2"), |
| 575 | /* 11 */ DECLARE_PIIX_DEV("ICH2M"), |
| 576 | /* 12 */ DECLARE_PIIX_DEV("ICH3M"), |
| 577 | /* 13 */ DECLARE_PIIX_DEV("ICH3"), |
| 578 | /* 14 */ DECLARE_PIIX_DEV("ICH4"), |
| 579 | /* 15 */ DECLARE_PIIX_DEV("ICH5"), |
| 580 | /* 16 */ DECLARE_PIIX_DEV("C-ICH"), |
| 581 | /* 17 */ DECLARE_PIIX_DEV("ICH4"), |
| 582 | /* 18 */ DECLARE_PIIX_DEV("ICH5-SATA"), |
| 583 | /* 19 */ DECLARE_PIIX_DEV("ICH5"), |
| 584 | /* 20 */ DECLARE_PIIX_DEV("ICH6"), |
| 585 | /* 21 */ DECLARE_PIIX_DEV("ICH7"), |
| 586 | /* 22 */ DECLARE_PIIX_DEV("ICH4"), |
Jason Gaston | d69332b | 2005-04-16 15:24:42 -0700 | [diff] [blame] | 587 | /* 23 */ DECLARE_PIIX_DEV("ESB2"), |
Jason Gaston | b7bed9e | 2006-02-03 03:04:52 -0800 | [diff] [blame] | 588 | /* 24 */ DECLARE_PIIX_DEV("ICH8M"), |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 589 | }; |
| 590 | |
| 591 | /** |
| 592 | * piix_init_one - called when a PIIX is found |
| 593 | * @dev: the piix device |
| 594 | * @id: the matching pci id |
| 595 | * |
| 596 | * Called when the PCI registration layer (or the IDE initialization) |
| 597 | * finds a device matching our IDE device tables. |
| 598 | */ |
| 599 | |
| 600 | static int __devinit piix_init_one(struct pci_dev *dev, const struct pci_device_id *id) |
| 601 | { |
| 602 | ide_pci_device_t *d = &piix_pci_info[id->driver_data]; |
| 603 | |
| 604 | return ide_setup_pci_device(dev, d); |
| 605 | } |
| 606 | |
| 607 | /** |
| 608 | * piix_check_450nx - Check for problem 450NX setup |
| 609 | * |
| 610 | * Check for the present of 450NX errata #19 and errata #25. If |
| 611 | * they are found, disable use of DMA IDE |
| 612 | */ |
| 613 | |
| 614 | static void __devinit piix_check_450nx(void) |
| 615 | { |
| 616 | struct pci_dev *pdev = NULL; |
| 617 | u16 cfg; |
| 618 | u8 rev; |
| 619 | while((pdev=pci_find_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev))!=NULL) |
| 620 | { |
| 621 | /* Look for 450NX PXB. Check for problem configurations |
| 622 | A PCI quirk checks bit 6 already */ |
| 623 | pci_read_config_byte(pdev, PCI_REVISION_ID, &rev); |
| 624 | pci_read_config_word(pdev, 0x41, &cfg); |
| 625 | /* Only on the original revision: IDE DMA can hang */ |
| 626 | if(rev == 0x00) |
| 627 | no_piix_dma = 1; |
| 628 | /* On all revisions below 5 PXB bus lock must be disabled for IDE */ |
| 629 | else if(cfg & (1<<14) && rev < 5) |
| 630 | no_piix_dma = 2; |
| 631 | } |
| 632 | if(no_piix_dma) |
| 633 | printk(KERN_WARNING "piix: 450NX errata present, disabling IDE DMA.\n"); |
| 634 | if(no_piix_dma == 2) |
| 635 | printk(KERN_WARNING "piix: A BIOS update may resolve this.\n"); |
| 636 | } |
| 637 | |
| 638 | static struct pci_device_id piix_pci_tbl[] = { |
| 639 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371FB_0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, |
| 640 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371FB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1}, |
| 641 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371MX, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2}, |
| 642 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3}, |
| 643 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4}, |
| 644 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5}, |
| 645 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 6}, |
| 646 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 7}, |
| 647 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82372FB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 8}, |
| 648 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82451NX, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 9}, |
| 649 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 10}, |
| 650 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 11}, |
| 651 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10,PCI_ANY_ID, PCI_ANY_ID, 0, 0, 12}, |
| 652 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_11,PCI_ANY_ID, PCI_ANY_ID, 0, 0, 13}, |
| 653 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_11,PCI_ANY_ID, PCI_ANY_ID, 0, 0, 14}, |
| 654 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_11,PCI_ANY_ID, PCI_ANY_ID, 0, 0, 15}, |
| 655 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801E_11, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 16}, |
| 656 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_10,PCI_ANY_ID, PCI_ANY_ID, 0, 0, 17}, |
| 657 | #ifdef CONFIG_BLK_DEV_IDE_SATA |
| 658 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 18}, |
| 659 | #endif |
| 660 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 19}, |
| 661 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_19, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 20}, |
| 662 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_21, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 21}, |
| 663 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 22}, |
Jason Gaston | d69332b | 2005-04-16 15:24:42 -0700 | [diff] [blame] | 664 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_18, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 23}, |
Jason Gaston | b7bed9e | 2006-02-03 03:04:52 -0800 | [diff] [blame] | 665 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 24}, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 666 | { 0, }, |
| 667 | }; |
| 668 | MODULE_DEVICE_TABLE(pci, piix_pci_tbl); |
| 669 | |
| 670 | static struct pci_driver driver = { |
| 671 | .name = "PIIX_IDE", |
| 672 | .id_table = piix_pci_tbl, |
| 673 | .probe = piix_init_one, |
| 674 | }; |
| 675 | |
| 676 | static int __init piix_ide_init(void) |
| 677 | { |
| 678 | piix_check_450nx(); |
| 679 | return ide_pci_register_driver(&driver); |
| 680 | } |
| 681 | |
| 682 | module_init(piix_ide_init); |
| 683 | |
| 684 | MODULE_AUTHOR("Andre Hedrick, Andrzej Krzysztofowicz"); |
| 685 | MODULE_DESCRIPTION("PCI driver module for Intel PIIX IDE"); |
| 686 | MODULE_LICENSE("GPL"); |