Hans J. Koch | da15797 | 2010-09-17 18:15:11 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Lowlevel clock handling for Telechips TCC8xxx SoCs |
| 3 | * |
| 4 | * Copyright (C) 2010 by Hans J. Koch <hjk@linutronix.de> |
| 5 | * |
| 6 | * Licensed under the terms of the GPL v2 |
| 7 | */ |
| 8 | |
| 9 | #include <linux/clk.h> |
| 10 | #include <linux/delay.h> |
| 11 | #include <linux/err.h> |
| 12 | #include <linux/io.h> |
| 13 | #include <linux/module.h> |
| 14 | #include <linux/spinlock.h> |
Jean-Christop PLAGNIOL-VILLARD | 6d803ba | 2010-11-17 10:04:33 +0100 | [diff] [blame] | 15 | #include <linux/clkdev.h> |
Hans J. Koch | da15797 | 2010-09-17 18:15:11 +0200 | [diff] [blame] | 16 | |
| 17 | #include <mach/clock.h> |
| 18 | #include <mach/irqs.h> |
| 19 | #include <mach/tcc8k-regs.h> |
| 20 | |
| 21 | #include "common.h" |
| 22 | |
| 23 | #define BCLKCTR0 (CKC_BASE + BCLKCTR0_OFFS) |
| 24 | #define BCLKCTR1 (CKC_BASE + BCLKCTR1_OFFS) |
| 25 | |
| 26 | #define ACLKREF (CKC_BASE + ACLKREF_OFFS) |
| 27 | #define ACLKUART0 (CKC_BASE + ACLKUART0_OFFS) |
| 28 | #define ACLKUART1 (CKC_BASE + ACLKUART1_OFFS) |
| 29 | #define ACLKUART2 (CKC_BASE + ACLKUART2_OFFS) |
| 30 | #define ACLKUART3 (CKC_BASE + ACLKUART3_OFFS) |
| 31 | #define ACLKUART4 (CKC_BASE + ACLKUART4_OFFS) |
| 32 | #define ACLKI2C (CKC_BASE + ACLKI2C_OFFS) |
| 33 | #define ACLKADC (CKC_BASE + ACLKADC_OFFS) |
| 34 | #define ACLKUSBH (CKC_BASE + ACLKUSBH_OFFS) |
| 35 | #define ACLKLCD (CKC_BASE + ACLKLCD_OFFS) |
| 36 | #define ACLKSDH0 (CKC_BASE + ACLKSDH0_OFFS) |
| 37 | #define ACLKSDH1 (CKC_BASE + ACLKSDH1_OFFS) |
| 38 | #define ACLKSPI0 (CKC_BASE + ACLKSPI0_OFFS) |
| 39 | #define ACLKSPI1 (CKC_BASE + ACLKSPI1_OFFS) |
| 40 | #define ACLKSPDIF (CKC_BASE + ACLKSPDIF_OFFS) |
| 41 | #define ACLKC3DEC (CKC_BASE + ACLKC3DEC_OFFS) |
| 42 | #define ACLKCAN0 (CKC_BASE + ACLKCAN0_OFFS) |
| 43 | #define ACLKCAN1 (CKC_BASE + ACLKCAN1_OFFS) |
| 44 | #define ACLKGSB0 (CKC_BASE + ACLKGSB0_OFFS) |
| 45 | #define ACLKGSB1 (CKC_BASE + ACLKGSB1_OFFS) |
| 46 | #define ACLKGSB2 (CKC_BASE + ACLKGSB2_OFFS) |
| 47 | #define ACLKGSB3 (CKC_BASE + ACLKGSB3_OFFS) |
Hans J. Koch | da15797 | 2010-09-17 18:15:11 +0200 | [diff] [blame] | 48 | #define ACLKTCT (CKC_BASE + ACLKTCT_OFFS) |
| 49 | #define ACLKTCX (CKC_BASE + ACLKTCX_OFFS) |
| 50 | #define ACLKTCZ (CKC_BASE + ACLKTCZ_OFFS) |
| 51 | |
Hans J. Koch | fe03a9f | 2011-02-17 16:42:59 +0100 | [diff] [blame] | 52 | #define ACLK_MAX_DIV (0xfff + 1) |
| 53 | |
Hans J. Koch | da15797 | 2010-09-17 18:15:11 +0200 | [diff] [blame] | 54 | /* Crystal frequencies */ |
| 55 | static unsigned long xi_rate, xti_rate; |
| 56 | |
| 57 | static void __iomem *pll_cfg_addr(int pll) |
| 58 | { |
| 59 | switch (pll) { |
| 60 | case 0: return (CKC_BASE + PLL0CFG_OFFS); |
| 61 | case 1: return (CKC_BASE + PLL1CFG_OFFS); |
| 62 | case 2: return (CKC_BASE + PLL2CFG_OFFS); |
| 63 | default: |
| 64 | BUG(); |
| 65 | } |
| 66 | } |
| 67 | |
| 68 | static int pll_enable(int pll, int enable) |
| 69 | { |
| 70 | u32 reg; |
| 71 | void __iomem *addr = pll_cfg_addr(pll); |
| 72 | |
| 73 | reg = __raw_readl(addr); |
| 74 | if (enable) |
| 75 | reg &= ~PLLxCFG_PD; |
| 76 | else |
| 77 | reg |= PLLxCFG_PD; |
| 78 | |
| 79 | __raw_writel(reg, addr); |
| 80 | return 0; |
| 81 | } |
| 82 | |
| 83 | static int xi_enable(int enable) |
| 84 | { |
| 85 | u32 reg; |
| 86 | |
| 87 | reg = __raw_readl(CKC_BASE + CLKCTRL_OFFS); |
| 88 | if (enable) |
| 89 | reg |= CLKCTRL_XE; |
| 90 | else |
| 91 | reg &= ~CLKCTRL_XE; |
| 92 | |
| 93 | __raw_writel(reg, CKC_BASE + CLKCTRL_OFFS); |
| 94 | return 0; |
| 95 | } |
| 96 | |
| 97 | static int root_clk_enable(enum root_clks src) |
| 98 | { |
| 99 | switch (src) { |
| 100 | case CLK_SRC_PLL0: return pll_enable(0, 1); |
| 101 | case CLK_SRC_PLL1: return pll_enable(1, 1); |
| 102 | case CLK_SRC_PLL2: return pll_enable(2, 1); |
| 103 | case CLK_SRC_XI: return xi_enable(1); |
| 104 | default: |
| 105 | BUG(); |
| 106 | } |
| 107 | return 0; |
| 108 | } |
| 109 | |
Oskar Schirmer | cfeeb2f | 2011-02-17 16:43:01 +0100 | [diff] [blame] | 110 | static int root_clk_disable(enum root_clks src) |
Hans J. Koch | da15797 | 2010-09-17 18:15:11 +0200 | [diff] [blame] | 111 | { |
Oskar Schirmer | cfeeb2f | 2011-02-17 16:43:01 +0100 | [diff] [blame] | 112 | switch (src) { |
Hans J. Koch | da15797 | 2010-09-17 18:15:11 +0200 | [diff] [blame] | 113 | case CLK_SRC_PLL0: return pll_enable(0, 0); |
| 114 | case CLK_SRC_PLL1: return pll_enable(1, 0); |
| 115 | case CLK_SRC_PLL2: return pll_enable(2, 0); |
| 116 | case CLK_SRC_XI: return xi_enable(0); |
| 117 | default: |
| 118 | BUG(); |
| 119 | } |
| 120 | return 0; |
| 121 | } |
| 122 | |
| 123 | static int enable_clk(struct clk *clk) |
| 124 | { |
| 125 | u32 reg; |
| 126 | |
| 127 | if (clk->root_id != CLK_SRC_NOROOT) |
| 128 | return root_clk_enable(clk->root_id); |
| 129 | |
| 130 | if (clk->aclkreg) { |
| 131 | reg = __raw_readl(clk->aclkreg); |
| 132 | reg |= ACLK_EN; |
| 133 | __raw_writel(reg, clk->aclkreg); |
| 134 | } |
| 135 | if (clk->bclkctr) { |
| 136 | reg = __raw_readl(clk->bclkctr); |
| 137 | reg |= 1 << clk->bclk_shift; |
| 138 | __raw_writel(reg, clk->bclkctr); |
| 139 | } |
| 140 | return 0; |
| 141 | } |
| 142 | |
| 143 | static void disable_clk(struct clk *clk) |
| 144 | { |
| 145 | u32 reg; |
| 146 | |
| 147 | if (clk->root_id != CLK_SRC_NOROOT) { |
| 148 | root_clk_disable(clk->root_id); |
| 149 | return; |
| 150 | } |
| 151 | |
| 152 | if (clk->bclkctr) { |
| 153 | reg = __raw_readl(clk->bclkctr); |
| 154 | reg &= ~(1 << clk->bclk_shift); |
| 155 | __raw_writel(reg, clk->bclkctr); |
| 156 | } |
| 157 | if (clk->aclkreg) { |
| 158 | reg = __raw_readl(clk->aclkreg); |
| 159 | reg &= ~ACLK_EN; |
| 160 | __raw_writel(reg, clk->aclkreg); |
| 161 | } |
| 162 | } |
| 163 | |
| 164 | static unsigned long get_rate_pll(int pll) |
| 165 | { |
| 166 | u32 reg; |
| 167 | unsigned long s, m, p; |
| 168 | void __iomem *addr = pll_cfg_addr(pll); |
| 169 | |
| 170 | reg = __raw_readl(addr); |
| 171 | s = (reg >> 16) & 0x07; |
| 172 | m = (reg >> 8) & 0xff; |
| 173 | p = reg & 0x3f; |
| 174 | |
| 175 | return (m * xi_rate) / (p * (1 << s)); |
| 176 | } |
| 177 | |
| 178 | static unsigned long get_rate_pll_div(int pll) |
| 179 | { |
| 180 | u32 reg; |
| 181 | unsigned long div = 0; |
| 182 | void __iomem *addr; |
| 183 | |
| 184 | switch (pll) { |
| 185 | case 0: |
| 186 | addr = CKC_BASE + CLKDIVC0_OFFS; |
| 187 | reg = __raw_readl(addr); |
| 188 | if (reg & CLKDIVC0_P0E) |
| 189 | div = (reg >> 24) & 0x3f; |
| 190 | break; |
| 191 | case 1: |
| 192 | addr = CKC_BASE + CLKDIVC0_OFFS; |
| 193 | reg = __raw_readl(addr); |
| 194 | if (reg & CLKDIVC0_P1E) |
| 195 | div = (reg >> 16) & 0x3f; |
| 196 | break; |
| 197 | case 2: |
| 198 | addr = CKC_BASE + CLKDIVC1_OFFS; |
| 199 | reg = __raw_readl(addr); |
| 200 | if (reg & CLKDIVC1_P2E) |
Oskar Schirmer | 25d7a60 | 2011-02-17 16:43:00 +0100 | [diff] [blame] | 201 | div = reg & 0x3f; |
Hans J. Koch | da15797 | 2010-09-17 18:15:11 +0200 | [diff] [blame] | 202 | break; |
| 203 | } |
| 204 | return get_rate_pll(pll) / (div + 1); |
| 205 | } |
| 206 | |
| 207 | static unsigned long get_rate_xi_div(void) |
| 208 | { |
| 209 | unsigned long div = 0; |
| 210 | u32 reg = __raw_readl(CKC_BASE + CLKDIVC0_OFFS); |
| 211 | |
| 212 | if (reg & CLKDIVC0_XE) |
| 213 | div = (reg >> 8) & 0x3f; |
| 214 | |
| 215 | return xi_rate / (div + 1); |
| 216 | } |
| 217 | |
| 218 | static unsigned long get_rate_xti_div(void) |
| 219 | { |
| 220 | unsigned long div = 0; |
| 221 | u32 reg = __raw_readl(CKC_BASE + CLKDIVC0_OFFS); |
| 222 | |
| 223 | if (reg & CLKDIVC0_XTE) |
| 224 | div = reg & 0x3f; |
| 225 | |
| 226 | return xti_rate / (div + 1); |
| 227 | } |
| 228 | |
| 229 | static unsigned long root_clk_get_rate(enum root_clks src) |
| 230 | { |
| 231 | switch (src) { |
| 232 | case CLK_SRC_PLL0: return get_rate_pll(0); |
| 233 | case CLK_SRC_PLL1: return get_rate_pll(1); |
| 234 | case CLK_SRC_PLL2: return get_rate_pll(2); |
| 235 | case CLK_SRC_PLL0DIV: return get_rate_pll_div(0); |
| 236 | case CLK_SRC_PLL1DIV: return get_rate_pll_div(1); |
| 237 | case CLK_SRC_PLL2DIV: return get_rate_pll_div(2); |
| 238 | case CLK_SRC_XI: return xi_rate; |
| 239 | case CLK_SRC_XTI: return xti_rate; |
| 240 | case CLK_SRC_XIDIV: return get_rate_xi_div(); |
| 241 | case CLK_SRC_XTIDIV: return get_rate_xti_div(); |
| 242 | default: return 0; |
| 243 | } |
| 244 | } |
| 245 | |
| 246 | static unsigned long aclk_get_rate(struct clk *clk) |
| 247 | { |
| 248 | u32 reg; |
| 249 | unsigned long div; |
| 250 | unsigned int src; |
| 251 | |
| 252 | reg = __raw_readl(clk->aclkreg); |
| 253 | div = reg & 0x0fff; |
| 254 | src = (reg >> ACLK_SEL_SHIFT) & CLK_SRC_MASK; |
| 255 | return root_clk_get_rate(src) / (div + 1); |
| 256 | } |
| 257 | |
| 258 | static unsigned long aclk_best_div(struct clk *clk, unsigned long rate) |
| 259 | { |
| 260 | unsigned long div, src, freq, r1, r2; |
| 261 | |
Hans J. Koch | fe03a9f | 2011-02-17 16:42:59 +0100 | [diff] [blame] | 262 | if (!rate) |
| 263 | return ACLK_MAX_DIV; |
| 264 | |
Hans J. Koch | da15797 | 2010-09-17 18:15:11 +0200 | [diff] [blame] | 265 | src = __raw_readl(clk->aclkreg) >> ACLK_SEL_SHIFT; |
| 266 | src &= CLK_SRC_MASK; |
| 267 | freq = root_clk_get_rate(src); |
Hans J. Koch | fe03a9f | 2011-02-17 16:42:59 +0100 | [diff] [blame] | 268 | div = freq / rate; |
| 269 | if (!div) |
| 270 | return 1; |
| 271 | if (div >= ACLK_MAX_DIV) |
| 272 | return ACLK_MAX_DIV; |
Hans J. Koch | da15797 | 2010-09-17 18:15:11 +0200 | [diff] [blame] | 273 | r1 = freq / div; |
| 274 | r2 = freq / (div + 1); |
Hans J. Koch | da15797 | 2010-09-17 18:15:11 +0200 | [diff] [blame] | 275 | if ((rate - r2) < (r1 - rate)) |
| 276 | return div + 1; |
| 277 | |
| 278 | return div; |
| 279 | } |
| 280 | |
| 281 | static unsigned long aclk_round_rate(struct clk *clk, unsigned long rate) |
| 282 | { |
| 283 | unsigned int src; |
| 284 | |
| 285 | src = __raw_readl(clk->aclkreg) >> ACLK_SEL_SHIFT; |
| 286 | src &= CLK_SRC_MASK; |
| 287 | |
| 288 | return root_clk_get_rate(src) / aclk_best_div(clk, rate); |
| 289 | } |
| 290 | |
| 291 | static int aclk_set_rate(struct clk *clk, unsigned long rate) |
| 292 | { |
| 293 | u32 reg; |
| 294 | |
| 295 | reg = __raw_readl(clk->aclkreg) & ~ACLK_DIV_MASK; |
Hans J. Koch | fe03a9f | 2011-02-17 16:42:59 +0100 | [diff] [blame] | 296 | reg |= aclk_best_div(clk, rate) - 1; |
| 297 | __raw_writel(reg, clk->aclkreg); |
Hans J. Koch | da15797 | 2010-09-17 18:15:11 +0200 | [diff] [blame] | 298 | return 0; |
| 299 | } |
| 300 | |
| 301 | static unsigned long get_rate_sys(struct clk *clk) |
| 302 | { |
| 303 | unsigned int src; |
| 304 | |
| 305 | src = __raw_readl(CKC_BASE + CLKCTRL_OFFS) & CLK_SRC_MASK; |
Oskar Schirmer | cfeeb2f | 2011-02-17 16:43:01 +0100 | [diff] [blame] | 306 | return root_clk_get_rate(src); |
Hans J. Koch | da15797 | 2010-09-17 18:15:11 +0200 | [diff] [blame] | 307 | } |
| 308 | |
| 309 | static unsigned long get_rate_bus(struct clk *clk) |
| 310 | { |
Oskar Schirmer | f91f9cd | 2011-02-17 16:43:02 +0100 | [diff] [blame] | 311 | unsigned int reg, sdiv, bdiv, rate; |
Hans J. Koch | da15797 | 2010-09-17 18:15:11 +0200 | [diff] [blame] | 312 | |
Oskar Schirmer | f91f9cd | 2011-02-17 16:43:02 +0100 | [diff] [blame] | 313 | reg = __raw_readl(CKC_BASE + CLKCTRL_OFFS); |
| 314 | rate = get_rate_sys(clk); |
| 315 | sdiv = (reg >> 20) & 3; |
| 316 | if (sdiv) |
| 317 | rate /= sdiv + 1; |
| 318 | bdiv = (reg >> 4) & 0xff; |
| 319 | if (bdiv) |
| 320 | rate /= bdiv + 1; |
| 321 | return rate; |
Hans J. Koch | da15797 | 2010-09-17 18:15:11 +0200 | [diff] [blame] | 322 | } |
| 323 | |
| 324 | static unsigned long get_rate_cpu(struct clk *clk) |
| 325 | { |
| 326 | unsigned int reg, div, fsys, fbus; |
| 327 | |
| 328 | fbus = get_rate_bus(clk); |
| 329 | reg = __raw_readl(CKC_BASE + CLKCTRL_OFFS); |
| 330 | if (reg & (1 << 29)) |
| 331 | return fbus; |
| 332 | fsys = get_rate_sys(clk); |
| 333 | div = (reg >> 16) & 0x0f; |
| 334 | return fbus + ((fsys - fbus) * (div + 1)) / 16; |
| 335 | } |
| 336 | |
| 337 | static unsigned long get_rate_root(struct clk *clk) |
| 338 | { |
| 339 | return root_clk_get_rate(clk->root_id); |
| 340 | } |
| 341 | |
| 342 | static int aclk_set_parent(struct clk *clock, struct clk *parent) |
| 343 | { |
| 344 | u32 reg; |
| 345 | |
| 346 | if (clock->parent == parent) |
| 347 | return 0; |
| 348 | |
| 349 | clock->parent = parent; |
| 350 | |
| 351 | if (!parent) |
| 352 | return 0; |
| 353 | |
| 354 | if (parent->root_id == CLK_SRC_NOROOT) |
| 355 | return 0; |
| 356 | reg = __raw_readl(clock->aclkreg); |
| 357 | reg &= ~ACLK_SEL_MASK; |
| 358 | reg |= (parent->root_id << ACLK_SEL_SHIFT) & ACLK_SEL_MASK; |
| 359 | __raw_writel(reg, clock->aclkreg); |
| 360 | |
| 361 | return 0; |
| 362 | } |
| 363 | |
| 364 | #define DEFINE_ROOT_CLOCK(name, ri, p) \ |
| 365 | static struct clk name = { \ |
| 366 | .root_id = ri, \ |
| 367 | .get_rate = get_rate_root, \ |
| 368 | .enable = enable_clk, \ |
| 369 | .disable = disable_clk, \ |
| 370 | .parent = p, \ |
| 371 | }; |
| 372 | |
| 373 | #define DEFINE_SPECIAL_CLOCK(name, gr, p) \ |
| 374 | static struct clk name = { \ |
| 375 | .root_id = CLK_SRC_NOROOT, \ |
| 376 | .get_rate = gr, \ |
| 377 | .parent = p, \ |
| 378 | }; |
| 379 | |
| 380 | #define DEFINE_ACLOCK(name, bc, bs, ar) \ |
| 381 | static struct clk name = { \ |
| 382 | .root_id = CLK_SRC_NOROOT, \ |
| 383 | .bclkctr = bc, \ |
| 384 | .bclk_shift = bs, \ |
| 385 | .aclkreg = ar, \ |
| 386 | .get_rate = aclk_get_rate, \ |
| 387 | .set_rate = aclk_set_rate, \ |
| 388 | .round_rate = aclk_round_rate, \ |
| 389 | .enable = enable_clk, \ |
| 390 | .disable = disable_clk, \ |
| 391 | .set_parent = aclk_set_parent, \ |
| 392 | }; |
| 393 | |
| 394 | #define DEFINE_BCLOCK(name, bc, bs, gr, p) \ |
| 395 | static struct clk name = { \ |
| 396 | .root_id = CLK_SRC_NOROOT, \ |
| 397 | .bclkctr = bc, \ |
| 398 | .bclk_shift = bs, \ |
| 399 | .get_rate = gr, \ |
| 400 | .enable = enable_clk, \ |
| 401 | .disable = disable_clk, \ |
| 402 | .parent = p, \ |
| 403 | }; |
| 404 | |
| 405 | DEFINE_ROOT_CLOCK(xi, CLK_SRC_XI, NULL) |
| 406 | DEFINE_ROOT_CLOCK(xti, CLK_SRC_XTI, NULL) |
| 407 | DEFINE_ROOT_CLOCK(xidiv, CLK_SRC_XIDIV, &xi) |
| 408 | DEFINE_ROOT_CLOCK(xtidiv, CLK_SRC_XTIDIV, &xti) |
| 409 | DEFINE_ROOT_CLOCK(pll0, CLK_SRC_PLL0, &xi) |
| 410 | DEFINE_ROOT_CLOCK(pll1, CLK_SRC_PLL1, &xi) |
| 411 | DEFINE_ROOT_CLOCK(pll2, CLK_SRC_PLL2, &xi) |
| 412 | DEFINE_ROOT_CLOCK(pll0div, CLK_SRC_PLL0DIV, &pll0) |
| 413 | DEFINE_ROOT_CLOCK(pll1div, CLK_SRC_PLL1DIV, &pll1) |
| 414 | DEFINE_ROOT_CLOCK(pll2div, CLK_SRC_PLL2DIV, &pll2) |
| 415 | |
| 416 | /* The following 3 clocks are special and are initialized explicitly later */ |
| 417 | DEFINE_SPECIAL_CLOCK(sys, get_rate_sys, NULL) |
| 418 | DEFINE_SPECIAL_CLOCK(bus, get_rate_bus, &sys) |
| 419 | DEFINE_SPECIAL_CLOCK(cpu, get_rate_cpu, &sys) |
| 420 | |
| 421 | DEFINE_ACLOCK(tct, NULL, 0, ACLKTCT) |
| 422 | DEFINE_ACLOCK(tcx, NULL, 0, ACLKTCX) |
| 423 | DEFINE_ACLOCK(tcz, NULL, 0, ACLKTCZ) |
| 424 | DEFINE_ACLOCK(ref, NULL, 0, ACLKREF) |
| 425 | DEFINE_ACLOCK(uart0, BCLKCTR0, 5, ACLKUART0) |
| 426 | DEFINE_ACLOCK(uart1, BCLKCTR0, 23, ACLKUART1) |
| 427 | DEFINE_ACLOCK(uart2, BCLKCTR0, 6, ACLKUART2) |
| 428 | DEFINE_ACLOCK(uart3, BCLKCTR0, 8, ACLKUART3) |
| 429 | DEFINE_ACLOCK(uart4, BCLKCTR1, 6, ACLKUART4) |
| 430 | DEFINE_ACLOCK(i2c, BCLKCTR0, 7, ACLKI2C) |
| 431 | DEFINE_ACLOCK(adc, BCLKCTR0, 10, ACLKADC) |
| 432 | DEFINE_ACLOCK(usbh0, BCLKCTR0, 11, ACLKUSBH) |
| 433 | DEFINE_ACLOCK(lcd, BCLKCTR0, 13, ACLKLCD) |
| 434 | DEFINE_ACLOCK(sd0, BCLKCTR0, 17, ACLKSDH0) |
| 435 | DEFINE_ACLOCK(sd1, BCLKCTR1, 5, ACLKSDH1) |
| 436 | DEFINE_ACLOCK(spi0, BCLKCTR0, 24, ACLKSPI0) |
| 437 | DEFINE_ACLOCK(spi1, BCLKCTR0, 30, ACLKSPI1) |
| 438 | DEFINE_ACLOCK(spdif, BCLKCTR1, 2, ACLKSPDIF) |
| 439 | DEFINE_ACLOCK(c3dec, BCLKCTR1, 9, ACLKC3DEC) |
| 440 | DEFINE_ACLOCK(can0, BCLKCTR1, 10, ACLKCAN0) |
| 441 | DEFINE_ACLOCK(can1, BCLKCTR1, 11, ACLKCAN1) |
| 442 | DEFINE_ACLOCK(gsb0, BCLKCTR1, 13, ACLKGSB0) |
| 443 | DEFINE_ACLOCK(gsb1, BCLKCTR1, 14, ACLKGSB1) |
| 444 | DEFINE_ACLOCK(gsb2, BCLKCTR1, 15, ACLKGSB2) |
| 445 | DEFINE_ACLOCK(gsb3, BCLKCTR1, 16, ACLKGSB3) |
| 446 | DEFINE_ACLOCK(usbh1, BCLKCTR1, 20, ACLKUSBH) |
| 447 | |
| 448 | DEFINE_BCLOCK(dai0, BCLKCTR0, 0, NULL, NULL) |
| 449 | DEFINE_BCLOCK(pic, BCLKCTR0, 1, NULL, NULL) |
| 450 | DEFINE_BCLOCK(tc, BCLKCTR0, 2, NULL, NULL) |
| 451 | DEFINE_BCLOCK(gpio, BCLKCTR0, 3, NULL, NULL) |
| 452 | DEFINE_BCLOCK(usbd, BCLKCTR0, 4, NULL, NULL) |
| 453 | DEFINE_BCLOCK(ecc, BCLKCTR0, 9, NULL, NULL) |
| 454 | DEFINE_BCLOCK(gdma0, BCLKCTR0, 12, NULL, NULL) |
| 455 | DEFINE_BCLOCK(rtc, BCLKCTR0, 15, NULL, NULL) |
| 456 | DEFINE_BCLOCK(nfc, BCLKCTR0, 16, NULL, NULL) |
| 457 | DEFINE_BCLOCK(g2d, BCLKCTR0, 18, NULL, NULL) |
| 458 | DEFINE_BCLOCK(gdma1, BCLKCTR0, 22, NULL, NULL) |
| 459 | DEFINE_BCLOCK(mscl, BCLKCTR0, 25, NULL, NULL) |
| 460 | DEFINE_BCLOCK(bdma, BCLKCTR1, 0, NULL, NULL) |
| 461 | DEFINE_BCLOCK(adma0, BCLKCTR1, 1, NULL, NULL) |
| 462 | DEFINE_BCLOCK(scfg, BCLKCTR1, 3, NULL, NULL) |
| 463 | DEFINE_BCLOCK(cid, BCLKCTR1, 4, NULL, NULL) |
| 464 | DEFINE_BCLOCK(dai1, BCLKCTR1, 7, NULL, NULL) |
| 465 | DEFINE_BCLOCK(adma1, BCLKCTR1, 8, NULL, NULL) |
| 466 | DEFINE_BCLOCK(gps, BCLKCTR1, 12, NULL, NULL) |
| 467 | DEFINE_BCLOCK(gdma2, BCLKCTR1, 17, NULL, NULL) |
| 468 | DEFINE_BCLOCK(gdma3, BCLKCTR1, 18, NULL, NULL) |
| 469 | DEFINE_BCLOCK(ddrc, BCLKCTR1, 19, NULL, NULL) |
| 470 | |
| 471 | #define _REGISTER_CLOCK(d, n, c) \ |
| 472 | { \ |
| 473 | .dev_id = d, \ |
| 474 | .con_id = n, \ |
| 475 | .clk = &c, \ |
| 476 | }, |
| 477 | |
| 478 | static struct clk_lookup lookups[] = { |
| 479 | _REGISTER_CLOCK(NULL, "bus", bus) |
| 480 | _REGISTER_CLOCK(NULL, "cpu", cpu) |
| 481 | _REGISTER_CLOCK(NULL, "tct", tct) |
| 482 | _REGISTER_CLOCK(NULL, "tcx", tcx) |
| 483 | _REGISTER_CLOCK(NULL, "tcz", tcz) |
| 484 | _REGISTER_CLOCK(NULL, "ref", ref) |
| 485 | _REGISTER_CLOCK(NULL, "dai0", dai0) |
| 486 | _REGISTER_CLOCK(NULL, "pic", pic) |
| 487 | _REGISTER_CLOCK(NULL, "tc", tc) |
| 488 | _REGISTER_CLOCK(NULL, "gpio", gpio) |
| 489 | _REGISTER_CLOCK(NULL, "usbd", usbd) |
| 490 | _REGISTER_CLOCK("tcc-uart.0", NULL, uart0) |
| 491 | _REGISTER_CLOCK("tcc-uart.2", NULL, uart2) |
| 492 | _REGISTER_CLOCK("tcc-i2c", NULL, i2c) |
| 493 | _REGISTER_CLOCK("tcc-uart.3", NULL, uart3) |
| 494 | _REGISTER_CLOCK(NULL, "ecc", ecc) |
| 495 | _REGISTER_CLOCK(NULL, "adc", adc) |
| 496 | _REGISTER_CLOCK("tcc-usbh.0", "usb", usbh0) |
| 497 | _REGISTER_CLOCK(NULL, "gdma0", gdma0) |
| 498 | _REGISTER_CLOCK(NULL, "lcd", lcd) |
| 499 | _REGISTER_CLOCK(NULL, "rtc", rtc) |
| 500 | _REGISTER_CLOCK(NULL, "nfc", nfc) |
| 501 | _REGISTER_CLOCK("tcc-mmc.0", NULL, sd0) |
| 502 | _REGISTER_CLOCK(NULL, "g2d", g2d) |
| 503 | _REGISTER_CLOCK(NULL, "gdma1", gdma1) |
| 504 | _REGISTER_CLOCK("tcc-uart.1", NULL, uart1) |
| 505 | _REGISTER_CLOCK("tcc-spi.0", NULL, spi0) |
| 506 | _REGISTER_CLOCK(NULL, "mscl", mscl) |
| 507 | _REGISTER_CLOCK("tcc-spi.1", NULL, spi1) |
| 508 | _REGISTER_CLOCK(NULL, "bdma", bdma) |
| 509 | _REGISTER_CLOCK(NULL, "adma0", adma0) |
| 510 | _REGISTER_CLOCK(NULL, "spdif", spdif) |
| 511 | _REGISTER_CLOCK(NULL, "scfg", scfg) |
| 512 | _REGISTER_CLOCK(NULL, "cid", cid) |
| 513 | _REGISTER_CLOCK("tcc-mmc.1", NULL, sd1) |
| 514 | _REGISTER_CLOCK("tcc-uart.4", NULL, uart4) |
| 515 | _REGISTER_CLOCK(NULL, "dai1", dai1) |
| 516 | _REGISTER_CLOCK(NULL, "adma1", adma1) |
| 517 | _REGISTER_CLOCK(NULL, "c3dec", c3dec) |
| 518 | _REGISTER_CLOCK("tcc-can.0", NULL, can0) |
| 519 | _REGISTER_CLOCK("tcc-can.1", NULL, can1) |
| 520 | _REGISTER_CLOCK(NULL, "gps", gps) |
| 521 | _REGISTER_CLOCK("tcc-gsb.0", NULL, gsb0) |
| 522 | _REGISTER_CLOCK("tcc-gsb.1", NULL, gsb1) |
| 523 | _REGISTER_CLOCK("tcc-gsb.2", NULL, gsb2) |
| 524 | _REGISTER_CLOCK("tcc-gsb.3", NULL, gsb3) |
| 525 | _REGISTER_CLOCK(NULL, "gdma2", gdma2) |
| 526 | _REGISTER_CLOCK(NULL, "gdma3", gdma3) |
| 527 | _REGISTER_CLOCK(NULL, "ddrc", ddrc) |
| 528 | _REGISTER_CLOCK("tcc-usbh.1", "usb", usbh1) |
| 529 | }; |
| 530 | |
| 531 | static struct clk *root_clk_by_index(enum root_clks src) |
| 532 | { |
| 533 | switch (src) { |
| 534 | case CLK_SRC_PLL0: return &pll0; |
| 535 | case CLK_SRC_PLL1: return &pll1; |
| 536 | case CLK_SRC_PLL2: return &pll2; |
| 537 | case CLK_SRC_PLL0DIV: return &pll0div; |
| 538 | case CLK_SRC_PLL1DIV: return &pll1div; |
| 539 | case CLK_SRC_PLL2DIV: return &pll2div; |
| 540 | case CLK_SRC_XI: return ξ |
| 541 | case CLK_SRC_XTI: return &xti; |
| 542 | case CLK_SRC_XIDIV: return &xidiv; |
| 543 | case CLK_SRC_XTIDIV: return &xtidiv; |
| 544 | default: return NULL; |
| 545 | } |
| 546 | } |
| 547 | |
| 548 | static void find_aclk_parent(struct clk *clk) |
| 549 | { |
| 550 | unsigned int src; |
| 551 | struct clk *clock; |
| 552 | |
| 553 | if (!clk->aclkreg) |
| 554 | return; |
| 555 | |
| 556 | src = __raw_readl(clk->aclkreg) >> ACLK_SEL_SHIFT; |
| 557 | src &= CLK_SRC_MASK; |
| 558 | |
| 559 | clock = root_clk_by_index(src); |
| 560 | if (!clock) |
| 561 | return; |
| 562 | |
| 563 | clk->parent = clock; |
| 564 | clk->set_parent = aclk_set_parent; |
| 565 | } |
| 566 | |
| 567 | void __init tcc_clocks_init(unsigned long xi_freq, unsigned long xti_freq) |
| 568 | { |
| 569 | int i; |
| 570 | |
| 571 | xi_rate = xi_freq; |
| 572 | xti_rate = xti_freq; |
| 573 | |
| 574 | /* fixup parents and add the clock */ |
| 575 | for (i = 0; i < ARRAY_SIZE(lookups); i++) { |
| 576 | find_aclk_parent(lookups[i].clk); |
| 577 | clkdev_add(&lookups[i]); |
| 578 | } |
Hans J. Koch | 3de7b51 | 2010-09-17 18:17:42 +0200 | [diff] [blame] | 579 | tcc8k_timer_init(&tcz, (void __iomem *)TIMER_BASE, INT_TC32); |
Hans J. Koch | da15797 | 2010-09-17 18:15:11 +0200 | [diff] [blame] | 580 | } |