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Chris Zankel9a8fd552005-06-23 22:01:26 -07001/*
Uwe Zeisbergerf30c2262006-10-03 23:01:26 +02002 * include/asm-xtensa/cache.h
Chris Zankel9a8fd552005-06-23 22:01:26 -07003 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
Chris Zankel9a8fd552005-06-23 22:01:26 -07007 *
8 * (C) 2001 - 2005 Tensilica Inc.
9 */
10
11#ifndef _XTENSA_CACHE_H
12#define _XTENSA_CACHE_H
13
Chris Zankel173d6682006-12-10 02:18:48 -080014#include <asm/variant/core.h>
Chris Zankel9a8fd552005-06-23 22:01:26 -070015
Chris Zankel173d6682006-12-10 02:18:48 -080016#define L1_CACHE_SHIFT XCHAL_DCACHE_LINEWIDTH
17#define L1_CACHE_BYTES XCHAL_DCACHE_LINESIZE
18#define SMP_CACHE_BYTES L1_CACHE_BYTES
Chris Zankel9a8fd552005-06-23 22:01:26 -070019
Chris Zankel173d6682006-12-10 02:18:48 -080020#define DCACHE_WAY_SIZE (XCHAL_DCACHE_SIZE/XCHAL_DCACHE_WAYS)
21#define ICACHE_WAY_SIZE (XCHAL_ICACHE_SIZE/XCHAL_ICACHE_WAYS)
Chris Zankel66569202007-08-22 10:14:51 -070022#define DCACHE_WAY_SHIFT (XCHAL_DCACHE_SETWIDTH + XCHAL_DCACHE_LINEWIDTH)
23#define ICACHE_WAY_SHIFT (XCHAL_ICACHE_SETWIDTH + XCHAL_ICACHE_LINEWIDTH)
24
25/* Maximum cache size per way. */
26#if DCACHE_WAY_SIZE >= ICACHE_WAY_SIZE
27# define CACHE_WAY_SIZE DCACHE_WAY_SIZE
28#else
29# define CACHE_WAY_SIZE ICACHE_WAY_SIZE
30#endif
Chris Zankel9a8fd552005-06-23 22:01:26 -070031
Chris Zankel9a8fd552005-06-23 22:01:26 -070032
33#endif /* _XTENSA_CACHE_H */