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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * Header for MultiMediaCard (MMC)
3 *
4 * Copyright 2002 Hewlett-Packard Company
5 *
6 * Use consistent with the GNU GPL is permitted,
7 * provided that this copyright notice is
8 * preserved in its entirety in all copies and derived works.
9 *
10 * HEWLETT-PACKARD COMPANY MAKES NO WARRANTIES, EXPRESSED OR IMPLIED,
11 * AS TO THE USEFULNESS OR CORRECTNESS OF THIS CODE OR ITS
12 * FITNESS FOR ANY PARTICULAR PURPOSE.
13 *
14 * Many thanks to Alessandro Rubini and Jonathan Corbet!
15 *
16 * Based strongly on code by:
17 *
18 * Author: Yong-iL Joh <tolkien@mizi.com>
Linus Torvalds1da177e2005-04-16 15:20:36 -070019 *
20 * Author: Andrew Christian
21 * 15 May 2002
22 */
23
Robert P. J. Day100e9182011-05-27 16:04:03 -040024#ifndef LINUX_MMC_MMC_H
25#define LINUX_MMC_MMC_H
Linus Torvalds1da177e2005-04-16 15:20:36 -070026
Philip Langdalebce40a32006-10-21 12:35:02 +020027/* Standard MMC commands (4.1) type argument response */
Linus Torvalds1da177e2005-04-16 15:20:36 -070028 /* class 1 */
David Brownell97018582007-08-08 09:09:01 -070029#define MMC_GO_IDLE_STATE 0 /* bc */
Linus Torvalds1da177e2005-04-16 15:20:36 -070030#define MMC_SEND_OP_COND 1 /* bcr [31:0] OCR R3 */
31#define MMC_ALL_SEND_CID 2 /* bcr R2 */
32#define MMC_SET_RELATIVE_ADDR 3 /* ac [31:16] RCA R1 */
33#define MMC_SET_DSR 4 /* bc [31:16] RCA */
Jarkko Lavinenb1ebe382009-09-22 16:44:34 -070034#define MMC_SLEEP_AWAKE 5 /* ac [31:16] RCA 15:flg R1b */
Philip Langdalebce40a32006-10-21 12:35:02 +020035#define MMC_SWITCH 6 /* ac [31:0] See below R1b */
Linus Torvalds1da177e2005-04-16 15:20:36 -070036#define MMC_SELECT_CARD 7 /* ac [31:16] RCA R1 */
Philip Langdalebce40a32006-10-21 12:35:02 +020037#define MMC_SEND_EXT_CSD 8 /* adtc R1 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070038#define MMC_SEND_CSD 9 /* ac [31:16] RCA R2 */
39#define MMC_SEND_CID 10 /* ac [31:16] RCA R2 */
40#define MMC_READ_DAT_UNTIL_STOP 11 /* adtc [31:0] dadr R1 */
41#define MMC_STOP_TRANSMISSION 12 /* ac R1b */
David Brownell97018582007-08-08 09:09:01 -070042#define MMC_SEND_STATUS 13 /* ac [31:16] RCA R1 */
Aries Lee22113ef2010-12-15 08:14:24 +010043#define MMC_BUS_TEST_R 14 /* adtc R1 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070044#define MMC_GO_INACTIVE_STATE 15 /* ac [31:16] RCA */
Aries Lee22113ef2010-12-15 08:14:24 +010045#define MMC_BUS_TEST_W 19 /* adtc R1 */
David Brownell97018582007-08-08 09:09:01 -070046#define MMC_SPI_READ_OCR 58 /* spi spi_R3 */
47#define MMC_SPI_CRC_ON_OFF 59 /* spi [0:0] flag spi_R1 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070048
49 /* class 2 */
50#define MMC_SET_BLOCKLEN 16 /* ac [31:0] block len R1 */
51#define MMC_READ_SINGLE_BLOCK 17 /* adtc [31:0] data addr R1 */
52#define MMC_READ_MULTIPLE_BLOCK 18 /* adtc [31:0] data addr R1 */
Arindam Nathb513ea22011-05-05 12:19:04 +053053#define MMC_SEND_TUNING_BLOCK 19 /* adtc R1 */
Girish K Sa4924c72012-01-11 14:04:52 -050054#define MMC_SEND_TUNING_BLOCK_HS200 21 /* adtc R1 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070055
56 /* class 3 */
57#define MMC_WRITE_DAT_UNTIL_STOP 20 /* adtc [31:0] data addr R1 */
58
59 /* class 4 */
60#define MMC_SET_BLOCK_COUNT 23 /* adtc [31:0] data addr R1 */
61#define MMC_WRITE_BLOCK 24 /* adtc [31:0] data addr R1 */
62#define MMC_WRITE_MULTIPLE_BLOCK 25 /* adtc R1 */
63#define MMC_PROGRAM_CID 26 /* adtc R1 */
64#define MMC_PROGRAM_CSD 27 /* adtc R1 */
65
66 /* class 6 */
67#define MMC_SET_WRITE_PROT 28 /* ac [31:0] data addr R1b */
68#define MMC_CLR_WRITE_PROT 29 /* ac [31:0] data addr R1b */
69#define MMC_SEND_WRITE_PROT 30 /* adtc [31:0] wpdata addr R1 */
70
71 /* class 5 */
72#define MMC_ERASE_GROUP_START 35 /* ac [31:0] data addr R1 */
73#define MMC_ERASE_GROUP_END 36 /* ac [31:0] data addr R1 */
Pierre Ossman24117de2005-11-28 21:00:29 +000074#define MMC_ERASE 38 /* ac R1b */
Linus Torvalds1da177e2005-04-16 15:20:36 -070075
76 /* class 9 */
77#define MMC_FAST_IO 39 /* ac <Complex> R4 */
78#define MMC_GO_IRQ_STATE 40 /* bcr R5 */
79
80 /* class 7 */
81#define MMC_LOCK_UNLOCK 42 /* adtc R1b */
82
83 /* class 8 */
84#define MMC_APP_CMD 55 /* ac [31:16] RCA R1 */
Pierre Ossman24117de2005-11-28 21:00:29 +000085#define MMC_GEN_CMD 56 /* adtc [0] RD/WR R1 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070086
Andrei Warkentind0c97cf2011-05-23 15:06:36 -050087static inline bool mmc_op_multi(u32 opcode)
88{
89 return opcode == MMC_WRITE_MULTIPLE_BLOCK ||
90 opcode == MMC_READ_MULTIPLE_BLOCK;
91}
92
Linus Torvalds1da177e2005-04-16 15:20:36 -070093/*
Philip Langdalebce40a32006-10-21 12:35:02 +020094 * MMC_SWITCH argument format:
95 *
96 * [31:26] Always 0
97 * [25:24] Access Mode
98 * [23:16] Location of target Byte in EXT_CSD
99 * [15:08] Value Byte
100 * [07:03] Always 0
101 * [02:00] Command Set
102 */
103
104/*
David Brownell97018582007-08-08 09:09:01 -0700105 MMC status in R1, for native mode (SPI bits are different)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700106 Type
David Brownell97018582007-08-08 09:09:01 -0700107 e : error bit
Linus Torvalds1da177e2005-04-16 15:20:36 -0700108 s : status bit
109 r : detected and set for the actual command response
110 x : detected and set during command execution. the host must poll
111 the card by sending status command in order to read these bits.
112 Clear condition
David Brownell97018582007-08-08 09:09:01 -0700113 a : according to the card state
Linus Torvalds1da177e2005-04-16 15:20:36 -0700114 b : always related to the previous command. Reception of
115 a valid command will clear it (with a delay of one command)
116 c : clear by read
117 */
118
119#define R1_OUT_OF_RANGE (1 << 31) /* er, c */
120#define R1_ADDRESS_ERROR (1 << 30) /* erx, c */
121#define R1_BLOCK_LEN_ERROR (1 << 29) /* er, c */
122#define R1_ERASE_SEQ_ERROR (1 << 28) /* er, c */
123#define R1_ERASE_PARAM (1 << 27) /* ex, c */
124#define R1_WP_VIOLATION (1 << 26) /* erx, c */
125#define R1_CARD_IS_LOCKED (1 << 25) /* sx, a */
126#define R1_LOCK_UNLOCK_FAILED (1 << 24) /* erx, c */
127#define R1_COM_CRC_ERROR (1 << 23) /* er, b */
128#define R1_ILLEGAL_COMMAND (1 << 22) /* er, b */
129#define R1_CARD_ECC_FAILED (1 << 21) /* ex, c */
130#define R1_CC_ERROR (1 << 20) /* erx, c */
131#define R1_ERROR (1 << 19) /* erx, c */
132#define R1_UNDERRUN (1 << 18) /* ex, c */
133#define R1_OVERRUN (1 << 17) /* ex, c */
134#define R1_CID_CSD_OVERWRITE (1 << 16) /* erx, c, CID/CSD overwrite */
135#define R1_WP_ERASE_SKIP (1 << 15) /* sx, c */
136#define R1_CARD_ECC_DISABLED (1 << 14) /* sx, a */
137#define R1_ERASE_RESET (1 << 13) /* sr, c */
138#define R1_STATUS(x) (x & 0xFFFFE000)
David Brownell97018582007-08-08 09:09:01 -0700139#define R1_CURRENT_STATE(x) ((x & 0x00001E00) >> 9) /* sx, b (4 bits) */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700140#define R1_READY_FOR_DATA (1 << 8) /* sx, a */
Adrian Hunteref0b27d2009-09-22 16:44:37 -0700141#define R1_SWITCH_ERROR (1 << 7) /* sx, c */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700142#define R1_APP_CMD (1 << 5) /* sr, c */
143
Russell King - ARM Linux0a2d4042011-06-20 20:10:08 +0100144#define R1_STATE_IDLE 0
145#define R1_STATE_READY 1
146#define R1_STATE_IDENT 2
147#define R1_STATE_STBY 3
148#define R1_STATE_TRAN 4
149#define R1_STATE_DATA 5
150#define R1_STATE_RCV 6
151#define R1_STATE_PRG 7
152#define R1_STATE_DIS 8
153
David Brownell97018582007-08-08 09:09:01 -0700154/*
155 * MMC/SD in SPI mode reports R1 status always, and R2 for SEND_STATUS
156 * R1 is the low order byte; R2 is the next highest byte, when present.
157 */
158#define R1_SPI_IDLE (1 << 0)
159#define R1_SPI_ERASE_RESET (1 << 1)
160#define R1_SPI_ILLEGAL_COMMAND (1 << 2)
161#define R1_SPI_COM_CRC (1 << 3)
162#define R1_SPI_ERASE_SEQ (1 << 4)
163#define R1_SPI_ADDRESS (1 << 5)
164#define R1_SPI_PARAMETER (1 << 6)
165/* R1 bit 7 is always zero */
166#define R2_SPI_CARD_LOCKED (1 << 8)
167#define R2_SPI_WP_ERASE_SKIP (1 << 9) /* or lock/unlock fail */
168#define R2_SPI_LOCK_UNLOCK_FAIL R2_SPI_WP_ERASE_SKIP
169#define R2_SPI_ERROR (1 << 10)
170#define R2_SPI_CC_ERROR (1 << 11)
171#define R2_SPI_CARD_ECC_ERROR (1 << 12)
172#define R2_SPI_WP_VIOLATION (1 << 13)
173#define R2_SPI_ERASE_PARAM (1 << 14)
174#define R2_SPI_OUT_OF_RANGE (1 << 15) /* or CSD overwrite */
175#define R2_SPI_CSD_OVERWRITE R2_SPI_OUT_OF_RANGE
176
Linus Torvalds1da177e2005-04-16 15:20:36 -0700177/* These are unpacked versions of the actual responses */
178
179struct _mmc_csd {
180 u8 csd_structure;
181 u8 spec_vers;
182 u8 taac;
183 u8 nsac;
184 u8 tran_speed;
185 u16 ccc;
186 u8 read_bl_len;
187 u8 read_bl_partial;
188 u8 write_blk_misalign;
189 u8 read_blk_misalign;
190 u8 dsr_imp;
191 u16 c_size;
192 u8 vdd_r_curr_min;
193 u8 vdd_r_curr_max;
194 u8 vdd_w_curr_min;
195 u8 vdd_w_curr_max;
196 u8 c_size_mult;
197 union {
198 struct { /* MMC system specification version 3.1 */
199 u8 erase_grp_size;
200 u8 erase_grp_mult;
201 } v31;
202 struct { /* MMC system specification version 2.2 */
203 u8 sector_size;
204 u8 erase_grp_size;
205 } v22;
206 } erase;
207 u8 wp_grp_size;
208 u8 wp_grp_enable;
209 u8 default_ecc;
210 u8 r2w_factor;
211 u8 write_bl_len;
212 u8 write_bl_partial;
213 u8 file_format_grp;
214 u8 copy;
215 u8 perm_write_protect;
216 u8 tmp_write_protect;
217 u8 file_format;
218 u8 ecc;
219};
220
Pierre Ossmanf74d1322007-02-09 22:49:31 +0100221/*
222 * OCR bits are mostly in host.h
223 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700224#define MMC_CARD_BUSY 0x80000000 /* Card Power up status bit */
225
Pierre Ossman912490d2005-05-21 10:27:02 +0100226/*
227 * Card Command Classes (CCC)
228 */
229#define CCC_BASIC (1<<0) /* (0) Basic protocol functions */
230 /* (CMD0,1,2,3,4,7,9,10,12,13,15) */
David Brownell97018582007-08-08 09:09:01 -0700231 /* (and for SPI, CMD58,59) */
Pierre Ossman912490d2005-05-21 10:27:02 +0100232#define CCC_STREAM_READ (1<<1) /* (1) Stream read commands */
233 /* (CMD11) */
234#define CCC_BLOCK_READ (1<<2) /* (2) Block read commands */
235 /* (CMD16,17,18) */
236#define CCC_STREAM_WRITE (1<<3) /* (3) Stream write commands */
237 /* (CMD20) */
238#define CCC_BLOCK_WRITE (1<<4) /* (4) Block write commands */
239 /* (CMD16,24,25,26,27) */
240#define CCC_ERASE (1<<5) /* (5) Ability to erase blocks */
241 /* (CMD32,33,34,35,36,37,38,39) */
242#define CCC_WRITE_PROT (1<<6) /* (6) Able to write protect blocks */
243 /* (CMD28,29,30) */
244#define CCC_LOCK_CARD (1<<7) /* (7) Able to lock down card */
245 /* (CMD16,CMD42) */
246#define CCC_APP_SPEC (1<<8) /* (8) Application specific */
247 /* (CMD55,56,57,ACMD*) */
248#define CCC_IO_MODE (1<<9) /* (9) I/O mode */
249 /* (CMD5,39,40,52,53) */
250#define CCC_SWITCH (1<<10) /* (10) High speed switch */
251 /* (CMD6,34,35,36,37,50) */
252 /* (11) Reserved */
253 /* (CMD?) */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700254
255/*
256 * CSD field definitions
257 */
258
259#define CSD_STRUCT_VER_1_0 0 /* Valid for system specification 1.0 - 1.2 */
260#define CSD_STRUCT_VER_1_1 1 /* Valid for system specification 1.4 - 2.2 */
Philip Langdalebce40a32006-10-21 12:35:02 +0200261#define CSD_STRUCT_VER_1_2 2 /* Valid for system specification 3.1 - 3.2 - 3.31 - 4.0 - 4.1 */
262#define CSD_STRUCT_EXT_CSD 3 /* Version is coded in CSD_STRUCTURE in EXT_CSD */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700263
264#define CSD_SPEC_VER_0 0 /* Implements system specification 1.0 - 1.2 */
265#define CSD_SPEC_VER_1 1 /* Implements system specification 1.4 */
266#define CSD_SPEC_VER_2 2 /* Implements system specification 2.0 - 2.2 */
Philip Langdalebce40a32006-10-21 12:35:02 +0200267#define CSD_SPEC_VER_3 3 /* Implements system specification 3.1 - 3.2 - 3.31 */
268#define CSD_SPEC_VER_4 4 /* Implements system specification 4.0 - 4.1 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700269
Philip Langdalebce40a32006-10-21 12:35:02 +0200270/*
271 * EXT_CSD fields
272 */
273
Seungwon Jeon881d1c22011-10-14 14:03:21 +0900274#define EXT_CSD_FLUSH_CACHE 32 /* W */
275#define EXT_CSD_CACHE_CTRL 33 /* R/W */
Girish K Sbec87262011-10-13 12:04:16 +0530276#define EXT_CSD_POWER_OFF_NOTIFICATION 34 /* R/W */
Namjae Jeone0c368d2011-10-06 23:41:38 +0900277#define EXT_CSD_GP_SIZE_MULT 143 /* R/W */
Chuanxiao Dong709de992011-01-22 04:09:41 +0800278#define EXT_CSD_PARTITION_ATTRIBUTE 156 /* R/W */
279#define EXT_CSD_PARTITION_SUPPORT 160 /* RO */
Jaehoon Chungeb0d8f12011-10-18 01:26:42 -0400280#define EXT_CSD_HPI_MGMT 161 /* R/W */
Adrian Hunterb2499512011-08-29 16:42:11 +0300281#define EXT_CSD_RST_N_FUNCTION 162 /* R/W */
Kyungmin Parkd9ddd622011-10-14 14:15:48 +0900282#define EXT_CSD_SANITIZE_START 165 /* W */
Andrei Warkentinf4c55222011-03-31 18:40:00 -0500283#define EXT_CSD_WR_REL_PARAM 166 /* RO */
Johan Rudholmadd710e2011-12-02 08:51:06 +0100284#define EXT_CSD_BOOT_WP 173 /* R/W */
Adrian Hunterdfe86cb2010-08-11 14:17:46 -0700285#define EXT_CSD_ERASE_GROUP_DEF 175 /* R/W */
Andrei Warkentin371a6892011-04-11 18:10:25 -0500286#define EXT_CSD_PART_CONFIG 179 /* R/W */
Adrian Hunterdfe86cb2010-08-11 14:17:46 -0700287#define EXT_CSD_ERASED_MEM_CONT 181 /* RO */
288#define EXT_CSD_BUS_WIDTH 183 /* R/W */
289#define EXT_CSD_HS_TIMING 185 /* R/W */
Girish K Sb87d8db2011-09-23 20:41:47 +0530290#define EXT_CSD_POWER_CLASS 187 /* R/W */
Adrian Hunterdfe86cb2010-08-11 14:17:46 -0700291#define EXT_CSD_REV 192 /* RO */
292#define EXT_CSD_STRUCTURE 194 /* RO */
293#define EXT_CSD_CARD_TYPE 196 /* RO */
Jaehoon Chungeb0d8f12011-10-18 01:26:42 -0400294#define EXT_CSD_OUT_OF_INTERRUPT_TIME 198 /* RO */
Andrei Warkentin371a6892011-04-11 18:10:25 -0500295#define EXT_CSD_PART_SWITCH_TIME 199 /* RO */
Girish K Sb87d8db2011-09-23 20:41:47 +0530296#define EXT_CSD_PWR_CL_52_195 200 /* RO */
297#define EXT_CSD_PWR_CL_26_195 201 /* RO */
298#define EXT_CSD_PWR_CL_52_360 202 /* RO */
299#define EXT_CSD_PWR_CL_26_360 203 /* RO */
Adrian Hunterdfe86cb2010-08-11 14:17:46 -0700300#define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */
301#define EXT_CSD_S_A_TIMEOUT 217 /* RO */
Andrei Warkentinf4c55222011-03-31 18:40:00 -0500302#define EXT_CSD_REL_WR_SEC_C 222 /* RO */
Chuanxiao Dong709de992011-01-22 04:09:41 +0800303#define EXT_CSD_HC_WP_GRP_SIZE 221 /* RO */
Adrian Hunterdfe86cb2010-08-11 14:17:46 -0700304#define EXT_CSD_ERASE_TIMEOUT_MULT 223 /* RO */
305#define EXT_CSD_HC_ERASE_GRP_SIZE 224 /* RO */
Andrei Warkentin371a6892011-04-11 18:10:25 -0500306#define EXT_CSD_BOOT_MULT 226 /* RO */
Adrian Hunterdfe86cb2010-08-11 14:17:46 -0700307#define EXT_CSD_SEC_TRIM_MULT 229 /* RO */
308#define EXT_CSD_SEC_ERASE_MULT 230 /* RO */
309#define EXT_CSD_SEC_FEATURE_SUPPORT 231 /* RO */
310#define EXT_CSD_TRIM_MULT 232 /* RO */
Girish K Sb87d8db2011-09-23 20:41:47 +0530311#define EXT_CSD_PWR_CL_200_195 236 /* RO */
312#define EXT_CSD_PWR_CL_200_360 237 /* RO */
313#define EXT_CSD_PWR_CL_DDR_52_195 238 /* RO */
314#define EXT_CSD_PWR_CL_DDR_52_360 239 /* RO */
315#define EXT_CSD_POWER_OFF_LONG_TIME 247 /* RO */
Seungwon Jeonb23cf0b2011-09-23 14:15:29 +0900316#define EXT_CSD_GENERIC_CMD6_TIME 248 /* RO */
Seungwon Jeon881d1c22011-10-14 14:03:21 +0900317#define EXT_CSD_CACHE_SIZE 249 /* RO, 4 bytes */
Jaehoon Chungeb0d8f12011-10-18 01:26:42 -0400318#define EXT_CSD_HPI_FEATURES 503 /* RO */
Philip Langdalebce40a32006-10-21 12:35:02 +0200319
320/*
321 * EXT_CSD field definitions
322 */
323
Andrei Warkentinf4c55222011-03-31 18:40:00 -0500324#define EXT_CSD_WR_REL_PARAM_EN (1<<2)
325
Johan Rudholmadd710e2011-12-02 08:51:06 +0100326#define EXT_CSD_BOOT_WP_B_PWR_WP_DIS (0x40)
327#define EXT_CSD_BOOT_WP_B_PERM_WP_DIS (0x10)
328#define EXT_CSD_BOOT_WP_B_PERM_WP_EN (0x04)
329#define EXT_CSD_BOOT_WP_B_PWR_WP_EN (0x01)
330
Andrei Warkentin371a6892011-04-11 18:10:25 -0500331#define EXT_CSD_PART_CONFIG_ACC_MASK (0x7)
332#define EXT_CSD_PART_CONFIG_ACC_BOOT0 (0x1)
Namjae Jeone0c368d2011-10-06 23:41:38 +0900333#define EXT_CSD_PART_CONFIG_ACC_GP0 (0x4)
334
335#define EXT_CSD_PART_SUPPORT_PART_EN (0x1)
Andrei Warkentin371a6892011-04-11 18:10:25 -0500336
Philip Langdalebce40a32006-10-21 12:35:02 +0200337#define EXT_CSD_CMD_SET_NORMAL (1<<0)
338#define EXT_CSD_CMD_SET_SECURE (1<<1)
339#define EXT_CSD_CMD_SET_CPSECURE (1<<2)
340
341#define EXT_CSD_CARD_TYPE_26 (1<<0) /* Card can run at 26MHz */
342#define EXT_CSD_CARD_TYPE_52 (1<<1) /* Card can run at 52MHz */
Girish K Sa4924c72012-01-11 14:04:52 -0500343#define EXT_CSD_CARD_TYPE_MASK 0x3F /* Mask out reserved bits */
Hanumath Prasaddfc13e82010-09-30 17:37:23 -0400344#define EXT_CSD_CARD_TYPE_DDR_1_8V (1<<2) /* Card can run at 52MHz */
345 /* DDR mode @1.8V or 3V I/O */
346#define EXT_CSD_CARD_TYPE_DDR_1_2V (1<<3) /* Card can run at 52MHz */
347 /* DDR mode @1.2V I/O */
348#define EXT_CSD_CARD_TYPE_DDR_52 (EXT_CSD_CARD_TYPE_DDR_1_8V \
349 | EXT_CSD_CARD_TYPE_DDR_1_2V)
Girish K Sa4924c72012-01-11 14:04:52 -0500350#define EXT_CSD_CARD_TYPE_SDR_1_8V (1<<4) /* Card can run at 200MHz */
351#define EXT_CSD_CARD_TYPE_SDR_1_2V (1<<5) /* Card can run at 200MHz */
352 /* SDR mode @1.2V I/O */
353
354#define EXT_CSD_CARD_TYPE_SDR_200 (EXT_CSD_CARD_TYPE_SDR_1_8V | \
355 EXT_CSD_CARD_TYPE_SDR_1_2V)
356
357#define EXT_CSD_CARD_TYPE_SDR_ALL (EXT_CSD_CARD_TYPE_SDR_200 | \
358 EXT_CSD_CARD_TYPE_52 | \
359 EXT_CSD_CARD_TYPE_26)
360
361#define EXT_CSD_CARD_TYPE_SDR_1_2V_ALL (EXT_CSD_CARD_TYPE_SDR_1_2V | \
362 EXT_CSD_CARD_TYPE_52 | \
363 EXT_CSD_CARD_TYPE_26)
364
365#define EXT_CSD_CARD_TYPE_SDR_1_8V_ALL (EXT_CSD_CARD_TYPE_SDR_1_8V | \
366 EXT_CSD_CARD_TYPE_52 | \
367 EXT_CSD_CARD_TYPE_26)
368
369#define EXT_CSD_CARD_TYPE_SDR_1_2V_DDR_1_8V (EXT_CSD_CARD_TYPE_SDR_1_2V | \
370 EXT_CSD_CARD_TYPE_DDR_1_8V | \
371 EXT_CSD_CARD_TYPE_52 | \
372 EXT_CSD_CARD_TYPE_26)
373
374#define EXT_CSD_CARD_TYPE_SDR_1_8V_DDR_1_8V (EXT_CSD_CARD_TYPE_SDR_1_8V | \
375 EXT_CSD_CARD_TYPE_DDR_1_8V | \
376 EXT_CSD_CARD_TYPE_52 | \
377 EXT_CSD_CARD_TYPE_26)
378
379#define EXT_CSD_CARD_TYPE_SDR_1_2V_DDR_1_2V (EXT_CSD_CARD_TYPE_SDR_1_2V | \
380 EXT_CSD_CARD_TYPE_DDR_1_2V | \
381 EXT_CSD_CARD_TYPE_52 | \
382 EXT_CSD_CARD_TYPE_26)
383
384#define EXT_CSD_CARD_TYPE_SDR_1_8V_DDR_1_2V (EXT_CSD_CARD_TYPE_SDR_1_8V | \
385 EXT_CSD_CARD_TYPE_DDR_1_2V | \
386 EXT_CSD_CARD_TYPE_52 | \
387 EXT_CSD_CARD_TYPE_26)
388
389#define EXT_CSD_CARD_TYPE_SDR_1_2V_DDR_52 (EXT_CSD_CARD_TYPE_SDR_1_2V | \
390 EXT_CSD_CARD_TYPE_DDR_52 | \
391 EXT_CSD_CARD_TYPE_52 | \
392 EXT_CSD_CARD_TYPE_26)
393
394#define EXT_CSD_CARD_TYPE_SDR_1_8V_DDR_52 (EXT_CSD_CARD_TYPE_SDR_1_8V | \
395 EXT_CSD_CARD_TYPE_DDR_52 | \
396 EXT_CSD_CARD_TYPE_52 | \
397 EXT_CSD_CARD_TYPE_26)
398
399#define EXT_CSD_CARD_TYPE_SDR_ALL_DDR_1_8V (EXT_CSD_CARD_TYPE_SDR_200 | \
400 EXT_CSD_CARD_TYPE_DDR_1_8V | \
401 EXT_CSD_CARD_TYPE_52 | \
402 EXT_CSD_CARD_TYPE_26)
403
404#define EXT_CSD_CARD_TYPE_SDR_ALL_DDR_1_2V (EXT_CSD_CARD_TYPE_SDR_200 | \
405 EXT_CSD_CARD_TYPE_DDR_1_2V | \
406 EXT_CSD_CARD_TYPE_52 | \
407 EXT_CSD_CARD_TYPE_26)
408
409#define EXT_CSD_CARD_TYPE_SDR_ALL_DDR_52 (EXT_CSD_CARD_TYPE_SDR_200 | \
410 EXT_CSD_CARD_TYPE_DDR_52 | \
411 EXT_CSD_CARD_TYPE_52 | \
412 EXT_CSD_CARD_TYPE_26)
Philip Langdalebce40a32006-10-21 12:35:02 +0200413
Philip Langdalee45a1bd2006-10-29 10:14:19 +0100414#define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */
415#define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */
416#define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */
Hanumath Prasaddfc13e82010-09-30 17:37:23 -0400417#define EXT_CSD_DDR_BUS_WIDTH_4 5 /* Card is in 4 bit DDR mode */
418#define EXT_CSD_DDR_BUS_WIDTH_8 6 /* Card is in 8 bit DDR mode */
Philip Langdalee45a1bd2006-10-29 10:14:19 +0100419
Adrian Hunterdfe86cb2010-08-11 14:17:46 -0700420#define EXT_CSD_SEC_ER_EN BIT(0)
421#define EXT_CSD_SEC_BD_BLK_EN BIT(2)
422#define EXT_CSD_SEC_GB_CL_EN BIT(4)
Kyungmin Parkd9ddd622011-10-14 14:15:48 +0900423#define EXT_CSD_SEC_SANITIZE BIT(6) /* v4.5 only */
Adrian Hunterdfe86cb2010-08-11 14:17:46 -0700424
Adrian Hunterb2499512011-08-29 16:42:11 +0300425#define EXT_CSD_RST_N_EN_MASK 0x3
426#define EXT_CSD_RST_N_ENABLED 1 /* RST_n is enabled on card */
427
Girish K Sbec87262011-10-13 12:04:16 +0530428#define EXT_CSD_NO_POWER_NOTIFICATION 0
429#define EXT_CSD_POWER_ON 1
430#define EXT_CSD_POWER_OFF_SHORT 2
431#define EXT_CSD_POWER_OFF_LONG 3
432
Girish K Sb87d8db2011-09-23 20:41:47 +0530433#define EXT_CSD_PWR_CL_8BIT_MASK 0xF0 /* 8 bit PWR CLS */
434#define EXT_CSD_PWR_CL_4BIT_MASK 0x0F /* 8 bit PWR CLS */
435#define EXT_CSD_PWR_CL_8BIT_SHIFT 4
436#define EXT_CSD_PWR_CL_4BIT_SHIFT 0
Philip Langdalebce40a32006-10-21 12:35:02 +0200437/*
438 * MMC_SWITCH access modes
439 */
440
441#define MMC_SWITCH_MODE_CMD_SET 0x00 /* Change the command set */
442#define MMC_SWITCH_MODE_SET_BITS 0x01 /* Set bits which are 1 in value */
443#define MMC_SWITCH_MODE_CLEAR_BITS 0x02 /* Clear bits which are 1 in value */
444#define MMC_SWITCH_MODE_WRITE_BYTE 0x03 /* Set target to value */
Pierre Ossmanf2182782005-09-06 15:18:55 -0700445
Robert P. J. Day100e9182011-05-27 16:04:03 -0400446#endif /* LINUX_MMC_MMC_H */