Arthur Jones | 8f421c5 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Intel 5100 Memory Controllers kernel module |
| 3 | * |
| 4 | * This file may be distributed under the terms of the |
| 5 | * GNU General Public License. |
| 6 | * |
| 7 | * This module is based on the following document: |
| 8 | * |
| 9 | * Intel 5100X Chipset Memory Controller Hub (MCH) - Datasheet |
| 10 | * http://download.intel.com/design/chipsets/datashts/318378.pdf |
| 11 | * |
Nils Carlson | bbead21 | 2009-12-15 16:47:42 -0800 | [diff] [blame] | 12 | * The intel 5100 has two independent channels. EDAC core currently |
| 13 | * can not reflect this configuration so instead the chip-select |
| 14 | * rows for each respective channel are layed out one after another, |
| 15 | * the first half belonging to channel 0, the second half belonging |
| 16 | * to channel 1. |
Arthur Jones | 8f421c5 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 17 | */ |
| 18 | #include <linux/module.h> |
| 19 | #include <linux/init.h> |
| 20 | #include <linux/pci.h> |
| 21 | #include <linux/pci_ids.h> |
Arthur Jones | 8f421c5 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 22 | #include <linux/edac.h> |
| 23 | #include <linux/delay.h> |
| 24 | #include <linux/mmzone.h> |
| 25 | |
| 26 | #include "edac_core.h" |
| 27 | |
Arthur Jones | b238e57 | 2008-07-25 01:49:08 -0700 | [diff] [blame] | 28 | /* register addresses */ |
Arthur Jones | 8f421c5 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 29 | |
| 30 | /* device 16, func 1 */ |
Arthur Jones | 43920a5 | 2008-07-25 01:49:06 -0700 | [diff] [blame] | 31 | #define I5100_MC 0x40 /* Memory Control Register */ |
Nils Carlson | 295439f | 2009-12-15 16:47:42 -0800 | [diff] [blame] | 32 | #define I5100_MC_SCRBEN_MASK (1 << 7) |
| 33 | #define I5100_MC_SCRBDONE_MASK (1 << 4) |
Arthur Jones | 8f421c5 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 34 | #define I5100_MS 0x44 /* Memory Status Register */ |
| 35 | #define I5100_SPDDATA 0x48 /* Serial Presence Detect Status Reg */ |
Arthur Jones | 8f421c5 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 36 | #define I5100_SPDCMD 0x4c /* Serial Presence Detect Command Reg */ |
Arthur Jones | 8f421c5 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 37 | #define I5100_TOLM 0x6c /* Top of Low Memory */ |
Arthur Jones | 8f421c5 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 38 | #define I5100_MIR0 0x80 /* Memory Interleave Range 0 */ |
| 39 | #define I5100_MIR1 0x84 /* Memory Interleave Range 1 */ |
| 40 | #define I5100_AMIR_0 0x8c /* Adjusted Memory Interleave Range 0 */ |
| 41 | #define I5100_AMIR_1 0x90 /* Adjusted Memory Interleave Range 1 */ |
Arthur Jones | 8f421c5 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 42 | #define I5100_FERR_NF_MEM 0xa0 /* MC First Non Fatal Errors */ |
Arthur Jones | 8f421c5 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 43 | #define I5100_FERR_NF_MEM_M16ERR_MASK (1 << 16) |
| 44 | #define I5100_FERR_NF_MEM_M15ERR_MASK (1 << 15) |
| 45 | #define I5100_FERR_NF_MEM_M14ERR_MASK (1 << 14) |
Arthur Jones | f7952ff | 2008-07-25 01:49:05 -0700 | [diff] [blame] | 46 | #define I5100_FERR_NF_MEM_M12ERR_MASK (1 << 12) |
| 47 | #define I5100_FERR_NF_MEM_M11ERR_MASK (1 << 11) |
| 48 | #define I5100_FERR_NF_MEM_M10ERR_MASK (1 << 10) |
| 49 | #define I5100_FERR_NF_MEM_M6ERR_MASK (1 << 6) |
| 50 | #define I5100_FERR_NF_MEM_M5ERR_MASK (1 << 5) |
| 51 | #define I5100_FERR_NF_MEM_M4ERR_MASK (1 << 4) |
| 52 | #define I5100_FERR_NF_MEM_M1ERR_MASK 1 |
Arthur Jones | 8f421c5 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 53 | #define I5100_FERR_NF_MEM_ANY_MASK \ |
| 54 | (I5100_FERR_NF_MEM_M16ERR_MASK | \ |
| 55 | I5100_FERR_NF_MEM_M15ERR_MASK | \ |
Arthur Jones | f7952ff | 2008-07-25 01:49:05 -0700 | [diff] [blame] | 56 | I5100_FERR_NF_MEM_M14ERR_MASK | \ |
| 57 | I5100_FERR_NF_MEM_M12ERR_MASK | \ |
| 58 | I5100_FERR_NF_MEM_M11ERR_MASK | \ |
| 59 | I5100_FERR_NF_MEM_M10ERR_MASK | \ |
| 60 | I5100_FERR_NF_MEM_M6ERR_MASK | \ |
| 61 | I5100_FERR_NF_MEM_M5ERR_MASK | \ |
| 62 | I5100_FERR_NF_MEM_M4ERR_MASK | \ |
| 63 | I5100_FERR_NF_MEM_M1ERR_MASK) |
Arthur Jones | 8f421c5 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 64 | #define I5100_NERR_NF_MEM 0xa4 /* MC Next Non-Fatal Errors */ |
Arthur Jones | 178d5a7 | 2008-07-25 01:49:06 -0700 | [diff] [blame] | 65 | #define I5100_EMASK_MEM 0xa8 /* MC Error Mask Register */ |
Arthur Jones | 8f421c5 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 66 | |
| 67 | /* device 21 and 22, func 0 */ |
| 68 | #define I5100_MTR_0 0x154 /* Memory Technology Registers 0-3 */ |
| 69 | #define I5100_DMIR 0x15c /* DIMM Interleave Range */ |
Arthur Jones | 8f421c5 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 70 | #define I5100_VALIDLOG 0x18c /* Valid Log Markers */ |
Arthur Jones | 8f421c5 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 71 | #define I5100_NRECMEMA 0x190 /* Non-Recoverable Memory Error Log Reg A */ |
Arthur Jones | 8f421c5 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 72 | #define I5100_NRECMEMB 0x194 /* Non-Recoverable Memory Error Log Reg B */ |
Arthur Jones | 8f421c5 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 73 | #define I5100_REDMEMA 0x198 /* Recoverable Memory Data Error Log Reg A */ |
Arthur Jones | 8f421c5 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 74 | #define I5100_REDMEMB 0x19c /* Recoverable Memory Data Error Log Reg B */ |
Arthur Jones | 8f421c5 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 75 | #define I5100_RECMEMA 0x1a0 /* Recoverable Memory Error Log Reg A */ |
Arthur Jones | 8f421c5 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 76 | #define I5100_RECMEMB 0x1a4 /* Recoverable Memory Error Log Reg B */ |
Arthur Jones | b238e57 | 2008-07-25 01:49:08 -0700 | [diff] [blame] | 77 | #define I5100_MTR_4 0x1b0 /* Memory Technology Registers 4,5 */ |
| 78 | |
| 79 | /* bit field accessors */ |
| 80 | |
Nils Carlson | 295439f | 2009-12-15 16:47:42 -0800 | [diff] [blame] | 81 | static inline u32 i5100_mc_scrben(u32 mc) |
| 82 | { |
| 83 | return mc >> 7 & 1; |
| 84 | } |
| 85 | |
Arthur Jones | b238e57 | 2008-07-25 01:49:08 -0700 | [diff] [blame] | 86 | static inline u32 i5100_mc_errdeten(u32 mc) |
| 87 | { |
| 88 | return mc >> 5 & 1; |
| 89 | } |
| 90 | |
Nils Carlson | 295439f | 2009-12-15 16:47:42 -0800 | [diff] [blame] | 91 | static inline u32 i5100_mc_scrbdone(u32 mc) |
| 92 | { |
| 93 | return mc >> 4 & 1; |
| 94 | } |
| 95 | |
Arthur Jones | b238e57 | 2008-07-25 01:49:08 -0700 | [diff] [blame] | 96 | static inline u16 i5100_spddata_rdo(u16 a) |
| 97 | { |
| 98 | return a >> 15 & 1; |
| 99 | } |
| 100 | |
| 101 | static inline u16 i5100_spddata_sbe(u16 a) |
| 102 | { |
| 103 | return a >> 13 & 1; |
| 104 | } |
| 105 | |
| 106 | static inline u16 i5100_spddata_busy(u16 a) |
| 107 | { |
| 108 | return a >> 12 & 1; |
| 109 | } |
| 110 | |
| 111 | static inline u16 i5100_spddata_data(u16 a) |
| 112 | { |
| 113 | return a & ((1 << 8) - 1); |
| 114 | } |
| 115 | |
| 116 | static inline u32 i5100_spdcmd_create(u32 dti, u32 ckovrd, u32 sa, u32 ba, |
| 117 | u32 data, u32 cmd) |
| 118 | { |
| 119 | return ((dti & ((1 << 4) - 1)) << 28) | |
| 120 | ((ckovrd & 1) << 27) | |
| 121 | ((sa & ((1 << 3) - 1)) << 24) | |
| 122 | ((ba & ((1 << 8) - 1)) << 16) | |
| 123 | ((data & ((1 << 8) - 1)) << 8) | |
| 124 | (cmd & 1); |
| 125 | } |
| 126 | |
| 127 | static inline u16 i5100_tolm_tolm(u16 a) |
| 128 | { |
| 129 | return a >> 12 & ((1 << 4) - 1); |
| 130 | } |
| 131 | |
| 132 | static inline u16 i5100_mir_limit(u16 a) |
| 133 | { |
| 134 | return a >> 4 & ((1 << 12) - 1); |
| 135 | } |
| 136 | |
| 137 | static inline u16 i5100_mir_way1(u16 a) |
| 138 | { |
| 139 | return a >> 1 & 1; |
| 140 | } |
| 141 | |
| 142 | static inline u16 i5100_mir_way0(u16 a) |
| 143 | { |
| 144 | return a & 1; |
| 145 | } |
| 146 | |
| 147 | static inline u32 i5100_ferr_nf_mem_chan_indx(u32 a) |
| 148 | { |
| 149 | return a >> 28 & 1; |
| 150 | } |
| 151 | |
| 152 | static inline u32 i5100_ferr_nf_mem_any(u32 a) |
| 153 | { |
| 154 | return a & I5100_FERR_NF_MEM_ANY_MASK; |
| 155 | } |
| 156 | |
| 157 | static inline u32 i5100_nerr_nf_mem_any(u32 a) |
| 158 | { |
| 159 | return i5100_ferr_nf_mem_any(a); |
| 160 | } |
| 161 | |
| 162 | static inline u32 i5100_dmir_limit(u32 a) |
| 163 | { |
| 164 | return a >> 16 & ((1 << 11) - 1); |
| 165 | } |
| 166 | |
| 167 | static inline u32 i5100_dmir_rank(u32 a, u32 i) |
| 168 | { |
| 169 | return a >> (4 * i) & ((1 << 2) - 1); |
| 170 | } |
| 171 | |
| 172 | static inline u16 i5100_mtr_present(u16 a) |
| 173 | { |
| 174 | return a >> 10 & 1; |
| 175 | } |
| 176 | |
| 177 | static inline u16 i5100_mtr_ethrottle(u16 a) |
| 178 | { |
| 179 | return a >> 9 & 1; |
| 180 | } |
| 181 | |
| 182 | static inline u16 i5100_mtr_width(u16 a) |
| 183 | { |
| 184 | return a >> 8 & 1; |
| 185 | } |
| 186 | |
| 187 | static inline u16 i5100_mtr_numbank(u16 a) |
| 188 | { |
| 189 | return a >> 6 & 1; |
| 190 | } |
| 191 | |
| 192 | static inline u16 i5100_mtr_numrow(u16 a) |
| 193 | { |
| 194 | return a >> 2 & ((1 << 2) - 1); |
| 195 | } |
| 196 | |
| 197 | static inline u16 i5100_mtr_numcol(u16 a) |
| 198 | { |
| 199 | return a & ((1 << 2) - 1); |
| 200 | } |
| 201 | |
| 202 | |
| 203 | static inline u32 i5100_validlog_redmemvalid(u32 a) |
| 204 | { |
| 205 | return a >> 2 & 1; |
| 206 | } |
| 207 | |
| 208 | static inline u32 i5100_validlog_recmemvalid(u32 a) |
| 209 | { |
| 210 | return a >> 1 & 1; |
| 211 | } |
| 212 | |
| 213 | static inline u32 i5100_validlog_nrecmemvalid(u32 a) |
| 214 | { |
| 215 | return a & 1; |
| 216 | } |
| 217 | |
| 218 | static inline u32 i5100_nrecmema_merr(u32 a) |
| 219 | { |
| 220 | return a >> 15 & ((1 << 5) - 1); |
| 221 | } |
| 222 | |
| 223 | static inline u32 i5100_nrecmema_bank(u32 a) |
| 224 | { |
| 225 | return a >> 12 & ((1 << 3) - 1); |
| 226 | } |
| 227 | |
| 228 | static inline u32 i5100_nrecmema_rank(u32 a) |
| 229 | { |
| 230 | return a >> 8 & ((1 << 3) - 1); |
| 231 | } |
| 232 | |
| 233 | static inline u32 i5100_nrecmema_dm_buf_id(u32 a) |
| 234 | { |
| 235 | return a & ((1 << 8) - 1); |
| 236 | } |
| 237 | |
| 238 | static inline u32 i5100_nrecmemb_cas(u32 a) |
| 239 | { |
| 240 | return a >> 16 & ((1 << 13) - 1); |
| 241 | } |
| 242 | |
| 243 | static inline u32 i5100_nrecmemb_ras(u32 a) |
| 244 | { |
| 245 | return a & ((1 << 16) - 1); |
| 246 | } |
| 247 | |
| 248 | static inline u32 i5100_redmemb_ecc_locator(u32 a) |
| 249 | { |
| 250 | return a & ((1 << 18) - 1); |
| 251 | } |
| 252 | |
| 253 | static inline u32 i5100_recmema_merr(u32 a) |
| 254 | { |
| 255 | return i5100_nrecmema_merr(a); |
| 256 | } |
| 257 | |
| 258 | static inline u32 i5100_recmema_bank(u32 a) |
| 259 | { |
| 260 | return i5100_nrecmema_bank(a); |
| 261 | } |
| 262 | |
| 263 | static inline u32 i5100_recmema_rank(u32 a) |
| 264 | { |
| 265 | return i5100_nrecmema_rank(a); |
| 266 | } |
| 267 | |
| 268 | static inline u32 i5100_recmema_dm_buf_id(u32 a) |
| 269 | { |
| 270 | return i5100_nrecmema_dm_buf_id(a); |
| 271 | } |
| 272 | |
| 273 | static inline u32 i5100_recmemb_cas(u32 a) |
| 274 | { |
| 275 | return i5100_nrecmemb_cas(a); |
| 276 | } |
| 277 | |
| 278 | static inline u32 i5100_recmemb_ras(u32 a) |
| 279 | { |
| 280 | return i5100_nrecmemb_ras(a); |
| 281 | } |
Arthur Jones | 8f421c5 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 282 | |
| 283 | /* some generic limits */ |
Nils Carlson | b18dfd0 | 2009-12-15 16:47:40 -0800 | [diff] [blame] | 284 | #define I5100_MAX_RANKS_PER_CHAN 6 |
| 285 | #define I5100_CHANNELS 2 |
Arthur Jones | 8f421c5 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 286 | #define I5100_MAX_RANKS_PER_DIMM 4 |
| 287 | #define I5100_DIMM_ADDR_LINES (6 - 3) /* 64 bits / 8 bits per byte */ |
Nils Carlson | b18dfd0 | 2009-12-15 16:47:40 -0800 | [diff] [blame] | 288 | #define I5100_MAX_DIMM_SLOTS_PER_CHAN 4 |
Arthur Jones | 8f421c5 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 289 | #define I5100_MAX_RANK_INTERLEAVE 4 |
| 290 | #define I5100_MAX_DMIRS 5 |
Nils Carlson | 295439f | 2009-12-15 16:47:42 -0800 | [diff] [blame] | 291 | #define I5100_SCRUB_REFRESH_RATE (5 * 60 * HZ) |
Arthur Jones | 8f421c5 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 292 | |
| 293 | struct i5100_priv { |
| 294 | /* ranks on each dimm -- 0 maps to not present -- obtained via SPD */ |
Nils Carlson | b18dfd0 | 2009-12-15 16:47:40 -0800 | [diff] [blame] | 295 | int dimm_numrank[I5100_CHANNELS][I5100_MAX_DIMM_SLOTS_PER_CHAN]; |
Arthur Jones | 8f421c5 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 296 | |
| 297 | /* |
| 298 | * mainboard chip select map -- maps i5100 chip selects to |
| 299 | * DIMM slot chip selects. In the case of only 4 ranks per |
Nils Carlson | b18dfd0 | 2009-12-15 16:47:40 -0800 | [diff] [blame] | 300 | * channel, the mapping is fairly obvious but not unique. |
| 301 | * we map -1 -> NC and assume both channels use the same |
Arthur Jones | 8f421c5 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 302 | * map... |
| 303 | * |
| 304 | */ |
Nils Carlson | b18dfd0 | 2009-12-15 16:47:40 -0800 | [diff] [blame] | 305 | int dimm_csmap[I5100_MAX_DIMM_SLOTS_PER_CHAN][I5100_MAX_RANKS_PER_DIMM]; |
Arthur Jones | 8f421c5 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 306 | |
| 307 | /* memory interleave range */ |
| 308 | struct { |
| 309 | u64 limit; |
| 310 | unsigned way[2]; |
Nils Carlson | b18dfd0 | 2009-12-15 16:47:40 -0800 | [diff] [blame] | 311 | } mir[I5100_CHANNELS]; |
Arthur Jones | 8f421c5 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 312 | |
| 313 | /* adjusted memory interleave range register */ |
Nils Carlson | b18dfd0 | 2009-12-15 16:47:40 -0800 | [diff] [blame] | 314 | unsigned amir[I5100_CHANNELS]; |
Arthur Jones | 8f421c5 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 315 | |
| 316 | /* dimm interleave range */ |
| 317 | struct { |
| 318 | unsigned rank[I5100_MAX_RANK_INTERLEAVE]; |
| 319 | u64 limit; |
Nils Carlson | b18dfd0 | 2009-12-15 16:47:40 -0800 | [diff] [blame] | 320 | } dmir[I5100_CHANNELS][I5100_MAX_DMIRS]; |
Arthur Jones | 8f421c5 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 321 | |
| 322 | /* memory technology registers... */ |
| 323 | struct { |
| 324 | unsigned present; /* 0 or 1 */ |
| 325 | unsigned ethrottle; /* 0 or 1 */ |
| 326 | unsigned width; /* 4 or 8 bits */ |
| 327 | unsigned numbank; /* 2 or 3 lines */ |
| 328 | unsigned numrow; /* 13 .. 16 lines */ |
| 329 | unsigned numcol; /* 11 .. 12 lines */ |
Nils Carlson | b18dfd0 | 2009-12-15 16:47:40 -0800 | [diff] [blame] | 330 | } mtr[I5100_CHANNELS][I5100_MAX_RANKS_PER_CHAN]; |
Arthur Jones | 8f421c5 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 331 | |
| 332 | u64 tolm; /* top of low memory in bytes */ |
Nils Carlson | b18dfd0 | 2009-12-15 16:47:40 -0800 | [diff] [blame] | 333 | unsigned ranksperchan; /* number of ranks per channel */ |
Arthur Jones | 8f421c5 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 334 | |
| 335 | struct pci_dev *mc; /* device 16 func 1 */ |
| 336 | struct pci_dev *ch0mm; /* device 21 func 0 */ |
| 337 | struct pci_dev *ch1mm; /* device 22 func 0 */ |
Nils Carlson | 295439f | 2009-12-15 16:47:42 -0800 | [diff] [blame] | 338 | |
| 339 | struct delayed_work i5100_scrubbing; |
| 340 | int scrub_enable; |
Arthur Jones | 8f421c5 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 341 | }; |
| 342 | |
Nils Carlson | b18dfd0 | 2009-12-15 16:47:40 -0800 | [diff] [blame] | 343 | /* map a rank/chan to a slot number on the mainboard */ |
Arthur Jones | 8f421c5 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 344 | static int i5100_rank_to_slot(const struct mem_ctl_info *mci, |
Nils Carlson | b18dfd0 | 2009-12-15 16:47:40 -0800 | [diff] [blame] | 345 | int chan, int rank) |
Arthur Jones | 8f421c5 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 346 | { |
| 347 | const struct i5100_priv *priv = mci->pvt_info; |
| 348 | int i; |
| 349 | |
Nils Carlson | b18dfd0 | 2009-12-15 16:47:40 -0800 | [diff] [blame] | 350 | for (i = 0; i < I5100_MAX_DIMM_SLOTS_PER_CHAN; i++) { |
Arthur Jones | 8f421c5 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 351 | int j; |
Nils Carlson | b18dfd0 | 2009-12-15 16:47:40 -0800 | [diff] [blame] | 352 | const int numrank = priv->dimm_numrank[chan][i]; |
Arthur Jones | 8f421c5 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 353 | |
| 354 | for (j = 0; j < numrank; j++) |
| 355 | if (priv->dimm_csmap[i][j] == rank) |
Nils Carlson | b18dfd0 | 2009-12-15 16:47:40 -0800 | [diff] [blame] | 356 | return i * 2 + chan; |
Arthur Jones | 8f421c5 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 357 | } |
| 358 | |
| 359 | return -1; |
| 360 | } |
| 361 | |
Arthur Jones | 8f421c5 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 362 | static const char *i5100_err_msg(unsigned err) |
| 363 | { |
Arthur Jones | b238e57 | 2008-07-25 01:49:08 -0700 | [diff] [blame] | 364 | static const char *merrs[] = { |
Arthur Jones | 8f421c5 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 365 | "unknown", /* 0 */ |
| 366 | "uncorrectable data ECC on replay", /* 1 */ |
| 367 | "unknown", /* 2 */ |
| 368 | "unknown", /* 3 */ |
| 369 | "aliased uncorrectable demand data ECC", /* 4 */ |
| 370 | "aliased uncorrectable spare-copy data ECC", /* 5 */ |
| 371 | "aliased uncorrectable patrol data ECC", /* 6 */ |
| 372 | "unknown", /* 7 */ |
| 373 | "unknown", /* 8 */ |
| 374 | "unknown", /* 9 */ |
| 375 | "non-aliased uncorrectable demand data ECC", /* 10 */ |
| 376 | "non-aliased uncorrectable spare-copy data ECC", /* 11 */ |
| 377 | "non-aliased uncorrectable patrol data ECC", /* 12 */ |
| 378 | "unknown", /* 13 */ |
| 379 | "correctable demand data ECC", /* 14 */ |
| 380 | "correctable spare-copy data ECC", /* 15 */ |
| 381 | "correctable patrol data ECC", /* 16 */ |
| 382 | "unknown", /* 17 */ |
| 383 | "SPD protocol error", /* 18 */ |
| 384 | "unknown", /* 19 */ |
| 385 | "spare copy initiated", /* 20 */ |
| 386 | "spare copy completed", /* 21 */ |
| 387 | }; |
| 388 | unsigned i; |
| 389 | |
| 390 | for (i = 0; i < ARRAY_SIZE(merrs); i++) |
| 391 | if (1 << i & err) |
| 392 | return merrs[i]; |
| 393 | |
| 394 | return "none"; |
| 395 | } |
| 396 | |
Nils Carlson | b18dfd0 | 2009-12-15 16:47:40 -0800 | [diff] [blame] | 397 | /* convert csrow index into a rank (per channel -- 0..5) */ |
Arthur Jones | 8f421c5 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 398 | static int i5100_csrow_to_rank(const struct mem_ctl_info *mci, int csrow) |
| 399 | { |
| 400 | const struct i5100_priv *priv = mci->pvt_info; |
| 401 | |
Nils Carlson | b18dfd0 | 2009-12-15 16:47:40 -0800 | [diff] [blame] | 402 | return csrow % priv->ranksperchan; |
Arthur Jones | 8f421c5 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 403 | } |
| 404 | |
Nils Carlson | b18dfd0 | 2009-12-15 16:47:40 -0800 | [diff] [blame] | 405 | /* convert csrow index into a channel (0..1) */ |
| 406 | static int i5100_csrow_to_chan(const struct mem_ctl_info *mci, int csrow) |
Arthur Jones | 8f421c5 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 407 | { |
| 408 | const struct i5100_priv *priv = mci->pvt_info; |
| 409 | |
Nils Carlson | b18dfd0 | 2009-12-15 16:47:40 -0800 | [diff] [blame] | 410 | return csrow / priv->ranksperchan; |
Arthur Jones | 8f421c5 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 411 | } |
| 412 | |
| 413 | static unsigned i5100_rank_to_csrow(const struct mem_ctl_info *mci, |
Nils Carlson | b18dfd0 | 2009-12-15 16:47:40 -0800 | [diff] [blame] | 414 | int chan, int rank) |
Arthur Jones | 8f421c5 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 415 | { |
| 416 | const struct i5100_priv *priv = mci->pvt_info; |
| 417 | |
Nils Carlson | b18dfd0 | 2009-12-15 16:47:40 -0800 | [diff] [blame] | 418 | return chan * priv->ranksperchan + rank; |
Arthur Jones | 8f421c5 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 419 | } |
| 420 | |
| 421 | static void i5100_handle_ce(struct mem_ctl_info *mci, |
Nils Carlson | b18dfd0 | 2009-12-15 16:47:40 -0800 | [diff] [blame] | 422 | int chan, |
Arthur Jones | 8f421c5 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 423 | unsigned bank, |
| 424 | unsigned rank, |
| 425 | unsigned long syndrome, |
| 426 | unsigned cas, |
| 427 | unsigned ras, |
| 428 | const char *msg) |
| 429 | { |
Nils Carlson | b18dfd0 | 2009-12-15 16:47:40 -0800 | [diff] [blame] | 430 | const int csrow = i5100_rank_to_csrow(mci, chan, rank); |
Arthur Jones | 8f421c5 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 431 | |
| 432 | printk(KERN_ERR |
Nils Carlson | b18dfd0 | 2009-12-15 16:47:40 -0800 | [diff] [blame] | 433 | "CE chan %d, bank %u, rank %u, syndrome 0x%lx, " |
Arthur Jones | 8f421c5 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 434 | "cas %u, ras %u, csrow %u, label \"%s\": %s\n", |
Nils Carlson | b18dfd0 | 2009-12-15 16:47:40 -0800 | [diff] [blame] | 435 | chan, bank, rank, syndrome, cas, ras, |
Arthur Jones | 8f421c5 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 436 | csrow, mci->csrows[csrow].channels[0].label, msg); |
| 437 | |
| 438 | mci->ce_count++; |
| 439 | mci->csrows[csrow].ce_count++; |
| 440 | mci->csrows[csrow].channels[0].ce_count++; |
| 441 | } |
| 442 | |
| 443 | static void i5100_handle_ue(struct mem_ctl_info *mci, |
Nils Carlson | b18dfd0 | 2009-12-15 16:47:40 -0800 | [diff] [blame] | 444 | int chan, |
Arthur Jones | 8f421c5 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 445 | unsigned bank, |
| 446 | unsigned rank, |
| 447 | unsigned long syndrome, |
| 448 | unsigned cas, |
| 449 | unsigned ras, |
| 450 | const char *msg) |
| 451 | { |
Nils Carlson | b18dfd0 | 2009-12-15 16:47:40 -0800 | [diff] [blame] | 452 | const int csrow = i5100_rank_to_csrow(mci, chan, rank); |
Arthur Jones | 8f421c5 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 453 | |
| 454 | printk(KERN_ERR |
Nils Carlson | b18dfd0 | 2009-12-15 16:47:40 -0800 | [diff] [blame] | 455 | "UE chan %d, bank %u, rank %u, syndrome 0x%lx, " |
Arthur Jones | 8f421c5 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 456 | "cas %u, ras %u, csrow %u, label \"%s\": %s\n", |
Nils Carlson | b18dfd0 | 2009-12-15 16:47:40 -0800 | [diff] [blame] | 457 | chan, bank, rank, syndrome, cas, ras, |
Arthur Jones | 8f421c5 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 458 | csrow, mci->csrows[csrow].channels[0].label, msg); |
| 459 | |
| 460 | mci->ue_count++; |
| 461 | mci->csrows[csrow].ue_count++; |
| 462 | } |
| 463 | |
Nils Carlson | b18dfd0 | 2009-12-15 16:47:40 -0800 | [diff] [blame] | 464 | static void i5100_read_log(struct mem_ctl_info *mci, int chan, |
Arthur Jones | 8f421c5 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 465 | u32 ferr, u32 nerr) |
| 466 | { |
| 467 | struct i5100_priv *priv = mci->pvt_info; |
Nils Carlson | b18dfd0 | 2009-12-15 16:47:40 -0800 | [diff] [blame] | 468 | struct pci_dev *pdev = (chan) ? priv->ch1mm : priv->ch0mm; |
Arthur Jones | 8f421c5 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 469 | u32 dw; |
| 470 | u32 dw2; |
| 471 | unsigned syndrome = 0; |
| 472 | unsigned ecc_loc = 0; |
| 473 | unsigned merr; |
| 474 | unsigned bank; |
| 475 | unsigned rank; |
| 476 | unsigned cas; |
| 477 | unsigned ras; |
| 478 | |
| 479 | pci_read_config_dword(pdev, I5100_VALIDLOG, &dw); |
| 480 | |
Arthur Jones | b238e57 | 2008-07-25 01:49:08 -0700 | [diff] [blame] | 481 | if (i5100_validlog_redmemvalid(dw)) { |
Arthur Jones | 8f421c5 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 482 | pci_read_config_dword(pdev, I5100_REDMEMA, &dw2); |
Arthur Jones | b238e57 | 2008-07-25 01:49:08 -0700 | [diff] [blame] | 483 | syndrome = dw2; |
Arthur Jones | 8f421c5 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 484 | pci_read_config_dword(pdev, I5100_REDMEMB, &dw2); |
Arthur Jones | b238e57 | 2008-07-25 01:49:08 -0700 | [diff] [blame] | 485 | ecc_loc = i5100_redmemb_ecc_locator(dw2); |
Arthur Jones | 8f421c5 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 486 | } |
| 487 | |
Arthur Jones | b238e57 | 2008-07-25 01:49:08 -0700 | [diff] [blame] | 488 | if (i5100_validlog_recmemvalid(dw)) { |
Arthur Jones | 8f421c5 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 489 | const char *msg; |
| 490 | |
| 491 | pci_read_config_dword(pdev, I5100_RECMEMA, &dw2); |
Arthur Jones | b238e57 | 2008-07-25 01:49:08 -0700 | [diff] [blame] | 492 | merr = i5100_recmema_merr(dw2); |
| 493 | bank = i5100_recmema_bank(dw2); |
| 494 | rank = i5100_recmema_rank(dw2); |
Arthur Jones | 8f421c5 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 495 | |
| 496 | pci_read_config_dword(pdev, I5100_RECMEMB, &dw2); |
Arthur Jones | b238e57 | 2008-07-25 01:49:08 -0700 | [diff] [blame] | 497 | cas = i5100_recmemb_cas(dw2); |
| 498 | ras = i5100_recmemb_ras(dw2); |
Arthur Jones | 8f421c5 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 499 | |
| 500 | /* FIXME: not really sure if this is what merr is... |
| 501 | */ |
| 502 | if (!merr) |
| 503 | msg = i5100_err_msg(ferr); |
| 504 | else |
| 505 | msg = i5100_err_msg(nerr); |
| 506 | |
Nils Carlson | b18dfd0 | 2009-12-15 16:47:40 -0800 | [diff] [blame] | 507 | i5100_handle_ce(mci, chan, bank, rank, syndrome, cas, ras, msg); |
Arthur Jones | 8f421c5 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 508 | } |
| 509 | |
Arthur Jones | b238e57 | 2008-07-25 01:49:08 -0700 | [diff] [blame] | 510 | if (i5100_validlog_nrecmemvalid(dw)) { |
Arthur Jones | 8f421c5 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 511 | const char *msg; |
| 512 | |
| 513 | pci_read_config_dword(pdev, I5100_NRECMEMA, &dw2); |
Arthur Jones | b238e57 | 2008-07-25 01:49:08 -0700 | [diff] [blame] | 514 | merr = i5100_nrecmema_merr(dw2); |
| 515 | bank = i5100_nrecmema_bank(dw2); |
| 516 | rank = i5100_nrecmema_rank(dw2); |
Arthur Jones | 8f421c5 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 517 | |
| 518 | pci_read_config_dword(pdev, I5100_NRECMEMB, &dw2); |
Arthur Jones | b238e57 | 2008-07-25 01:49:08 -0700 | [diff] [blame] | 519 | cas = i5100_nrecmemb_cas(dw2); |
| 520 | ras = i5100_nrecmemb_ras(dw2); |
Arthur Jones | 8f421c5 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 521 | |
| 522 | /* FIXME: not really sure if this is what merr is... |
| 523 | */ |
| 524 | if (!merr) |
| 525 | msg = i5100_err_msg(ferr); |
| 526 | else |
| 527 | msg = i5100_err_msg(nerr); |
| 528 | |
Nils Carlson | b18dfd0 | 2009-12-15 16:47:40 -0800 | [diff] [blame] | 529 | i5100_handle_ue(mci, chan, bank, rank, syndrome, cas, ras, msg); |
Arthur Jones | 8f421c5 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 530 | } |
| 531 | |
| 532 | pci_write_config_dword(pdev, I5100_VALIDLOG, dw); |
| 533 | } |
| 534 | |
| 535 | static void i5100_check_error(struct mem_ctl_info *mci) |
| 536 | { |
| 537 | struct i5100_priv *priv = mci->pvt_info; |
| 538 | u32 dw; |
| 539 | |
| 540 | |
| 541 | pci_read_config_dword(priv->mc, I5100_FERR_NF_MEM, &dw); |
Arthur Jones | b238e57 | 2008-07-25 01:49:08 -0700 | [diff] [blame] | 542 | if (i5100_ferr_nf_mem_any(dw)) { |
Arthur Jones | 8f421c5 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 543 | u32 dw2; |
| 544 | |
| 545 | pci_read_config_dword(priv->mc, I5100_NERR_NF_MEM, &dw2); |
| 546 | if (dw2) |
| 547 | pci_write_config_dword(priv->mc, I5100_NERR_NF_MEM, |
| 548 | dw2); |
| 549 | pci_write_config_dword(priv->mc, I5100_FERR_NF_MEM, dw); |
| 550 | |
Arthur Jones | b238e57 | 2008-07-25 01:49:08 -0700 | [diff] [blame] | 551 | i5100_read_log(mci, i5100_ferr_nf_mem_chan_indx(dw), |
| 552 | i5100_ferr_nf_mem_any(dw), |
| 553 | i5100_nerr_nf_mem_any(dw2)); |
Arthur Jones | 8f421c5 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 554 | } |
| 555 | } |
| 556 | |
Nils Carlson | 295439f | 2009-12-15 16:47:42 -0800 | [diff] [blame] | 557 | /* The i5100 chipset will scrub the entire memory once, then |
| 558 | * set a done bit. Continuous scrubbing is achieved by enqueing |
| 559 | * delayed work to a workqueue, checking every few minutes if |
| 560 | * the scrubbing has completed and if so reinitiating it. |
| 561 | */ |
| 562 | |
| 563 | static void i5100_refresh_scrubbing(struct work_struct *work) |
| 564 | { |
| 565 | struct delayed_work *i5100_scrubbing = container_of(work, |
| 566 | struct delayed_work, |
| 567 | work); |
| 568 | struct i5100_priv *priv = container_of(i5100_scrubbing, |
| 569 | struct i5100_priv, |
| 570 | i5100_scrubbing); |
| 571 | u32 dw; |
| 572 | |
| 573 | pci_read_config_dword(priv->mc, I5100_MC, &dw); |
| 574 | |
| 575 | if (priv->scrub_enable) { |
| 576 | |
| 577 | pci_read_config_dword(priv->mc, I5100_MC, &dw); |
| 578 | |
| 579 | if (i5100_mc_scrbdone(dw)) { |
| 580 | dw |= I5100_MC_SCRBEN_MASK; |
| 581 | pci_write_config_dword(priv->mc, I5100_MC, dw); |
| 582 | pci_read_config_dword(priv->mc, I5100_MC, &dw); |
| 583 | } |
| 584 | |
| 585 | schedule_delayed_work(&(priv->i5100_scrubbing), |
| 586 | I5100_SCRUB_REFRESH_RATE); |
| 587 | } |
| 588 | } |
| 589 | /* |
| 590 | * The bandwidth is based on experimentation, feel free to refine it. |
| 591 | */ |
Borislav Petkov | eba042a | 2010-05-25 18:21:07 +0200 | [diff] [blame] | 592 | static int i5100_set_scrub_rate(struct mem_ctl_info *mci, u32 bandwidth) |
Nils Carlson | 295439f | 2009-12-15 16:47:42 -0800 | [diff] [blame] | 593 | { |
| 594 | struct i5100_priv *priv = mci->pvt_info; |
| 595 | u32 dw; |
| 596 | |
| 597 | pci_read_config_dword(priv->mc, I5100_MC, &dw); |
Borislav Petkov | eba042a | 2010-05-25 18:21:07 +0200 | [diff] [blame] | 598 | if (bandwidth) { |
Nils Carlson | 295439f | 2009-12-15 16:47:42 -0800 | [diff] [blame] | 599 | priv->scrub_enable = 1; |
| 600 | dw |= I5100_MC_SCRBEN_MASK; |
| 601 | schedule_delayed_work(&(priv->i5100_scrubbing), |
| 602 | I5100_SCRUB_REFRESH_RATE); |
| 603 | } else { |
| 604 | priv->scrub_enable = 0; |
| 605 | dw &= ~I5100_MC_SCRBEN_MASK; |
| 606 | cancel_delayed_work(&(priv->i5100_scrubbing)); |
| 607 | } |
| 608 | pci_write_config_dword(priv->mc, I5100_MC, dw); |
| 609 | |
| 610 | pci_read_config_dword(priv->mc, I5100_MC, &dw); |
| 611 | |
Borislav Petkov | eba042a | 2010-05-25 18:21:07 +0200 | [diff] [blame] | 612 | bandwidth = 5900000 * i5100_mc_scrben(dw); |
Nils Carlson | 295439f | 2009-12-15 16:47:42 -0800 | [diff] [blame] | 613 | |
| 614 | return 0; |
| 615 | } |
| 616 | |
| 617 | static int i5100_get_scrub_rate(struct mem_ctl_info *mci, |
| 618 | u32 *bandwidth) |
| 619 | { |
| 620 | struct i5100_priv *priv = mci->pvt_info; |
| 621 | u32 dw; |
| 622 | |
| 623 | pci_read_config_dword(priv->mc, I5100_MC, &dw); |
| 624 | |
| 625 | *bandwidth = 5900000 * i5100_mc_scrben(dw); |
| 626 | |
| 627 | return 0; |
| 628 | } |
| 629 | |
Arthur Jones | 8f421c5 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 630 | static struct pci_dev *pci_get_device_func(unsigned vendor, |
| 631 | unsigned device, |
| 632 | unsigned func) |
| 633 | { |
| 634 | struct pci_dev *ret = NULL; |
| 635 | |
| 636 | while (1) { |
| 637 | ret = pci_get_device(vendor, device, ret); |
| 638 | |
| 639 | if (!ret) |
| 640 | break; |
| 641 | |
| 642 | if (PCI_FUNC(ret->devfn) == func) |
| 643 | break; |
| 644 | } |
| 645 | |
| 646 | return ret; |
| 647 | } |
| 648 | |
| 649 | static unsigned long __devinit i5100_npages(struct mem_ctl_info *mci, |
| 650 | int csrow) |
| 651 | { |
| 652 | struct i5100_priv *priv = mci->pvt_info; |
Nils Carlson | b18dfd0 | 2009-12-15 16:47:40 -0800 | [diff] [blame] | 653 | const unsigned chan_rank = i5100_csrow_to_rank(mci, csrow); |
| 654 | const unsigned chan = i5100_csrow_to_chan(mci, csrow); |
Arthur Jones | 8f421c5 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 655 | unsigned addr_lines; |
| 656 | |
| 657 | /* dimm present? */ |
Nils Carlson | b18dfd0 | 2009-12-15 16:47:40 -0800 | [diff] [blame] | 658 | if (!priv->mtr[chan][chan_rank].present) |
Arthur Jones | 8f421c5 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 659 | return 0ULL; |
| 660 | |
| 661 | addr_lines = |
| 662 | I5100_DIMM_ADDR_LINES + |
Nils Carlson | b18dfd0 | 2009-12-15 16:47:40 -0800 | [diff] [blame] | 663 | priv->mtr[chan][chan_rank].numcol + |
| 664 | priv->mtr[chan][chan_rank].numrow + |
| 665 | priv->mtr[chan][chan_rank].numbank; |
Arthur Jones | 8f421c5 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 666 | |
| 667 | return (unsigned long) |
| 668 | ((unsigned long long) (1ULL << addr_lines) / PAGE_SIZE); |
| 669 | } |
| 670 | |
| 671 | static void __devinit i5100_init_mtr(struct mem_ctl_info *mci) |
| 672 | { |
| 673 | struct i5100_priv *priv = mci->pvt_info; |
| 674 | struct pci_dev *mms[2] = { priv->ch0mm, priv->ch1mm }; |
| 675 | int i; |
| 676 | |
Nils Carlson | b18dfd0 | 2009-12-15 16:47:40 -0800 | [diff] [blame] | 677 | for (i = 0; i < I5100_CHANNELS; i++) { |
Arthur Jones | 8f421c5 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 678 | int j; |
| 679 | struct pci_dev *pdev = mms[i]; |
| 680 | |
Nils Carlson | b18dfd0 | 2009-12-15 16:47:40 -0800 | [diff] [blame] | 681 | for (j = 0; j < I5100_MAX_RANKS_PER_CHAN; j++) { |
Arthur Jones | 8f421c5 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 682 | const unsigned addr = |
| 683 | (j < 4) ? I5100_MTR_0 + j * 2 : |
| 684 | I5100_MTR_4 + (j - 4) * 2; |
| 685 | u16 w; |
| 686 | |
| 687 | pci_read_config_word(pdev, addr, &w); |
| 688 | |
Arthur Jones | b238e57 | 2008-07-25 01:49:08 -0700 | [diff] [blame] | 689 | priv->mtr[i][j].present = i5100_mtr_present(w); |
| 690 | priv->mtr[i][j].ethrottle = i5100_mtr_ethrottle(w); |
| 691 | priv->mtr[i][j].width = 4 + 4 * i5100_mtr_width(w); |
| 692 | priv->mtr[i][j].numbank = 2 + i5100_mtr_numbank(w); |
| 693 | priv->mtr[i][j].numrow = 13 + i5100_mtr_numrow(w); |
| 694 | priv->mtr[i][j].numcol = 10 + i5100_mtr_numcol(w); |
Arthur Jones | 8f421c5 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 695 | } |
| 696 | } |
| 697 | } |
| 698 | |
| 699 | /* |
| 700 | * FIXME: make this into a real i2c adapter (so that dimm-decode |
| 701 | * will work)? |
| 702 | */ |
| 703 | static int i5100_read_spd_byte(const struct mem_ctl_info *mci, |
| 704 | u8 ch, u8 slot, u8 addr, u8 *byte) |
| 705 | { |
| 706 | struct i5100_priv *priv = mci->pvt_info; |
| 707 | u16 w; |
Arthur Jones | 8f421c5 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 708 | unsigned long et; |
| 709 | |
| 710 | pci_read_config_word(priv->mc, I5100_SPDDATA, &w); |
Arthur Jones | b238e57 | 2008-07-25 01:49:08 -0700 | [diff] [blame] | 711 | if (i5100_spddata_busy(w)) |
Arthur Jones | 8f421c5 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 712 | return -1; |
| 713 | |
Arthur Jones | b238e57 | 2008-07-25 01:49:08 -0700 | [diff] [blame] | 714 | pci_write_config_dword(priv->mc, I5100_SPDCMD, |
| 715 | i5100_spdcmd_create(0xa, 1, ch * 4 + slot, addr, |
| 716 | 0, 0)); |
Arthur Jones | 8f421c5 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 717 | |
| 718 | /* wait up to 100ms */ |
| 719 | et = jiffies + HZ / 10; |
| 720 | udelay(100); |
| 721 | while (1) { |
| 722 | pci_read_config_word(priv->mc, I5100_SPDDATA, &w); |
Arthur Jones | b238e57 | 2008-07-25 01:49:08 -0700 | [diff] [blame] | 723 | if (!i5100_spddata_busy(w)) |
Arthur Jones | 8f421c5 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 724 | break; |
| 725 | udelay(100); |
| 726 | } |
| 727 | |
Arthur Jones | b238e57 | 2008-07-25 01:49:08 -0700 | [diff] [blame] | 728 | if (!i5100_spddata_rdo(w) || i5100_spddata_sbe(w)) |
Arthur Jones | 8f421c5 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 729 | return -1; |
| 730 | |
Arthur Jones | b238e57 | 2008-07-25 01:49:08 -0700 | [diff] [blame] | 731 | *byte = i5100_spddata_data(w); |
Arthur Jones | 8f421c5 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 732 | |
| 733 | return 0; |
| 734 | } |
| 735 | |
| 736 | /* |
| 737 | * fill dimm chip select map |
| 738 | * |
| 739 | * FIXME: |
Arthur Jones | 8f421c5 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 740 | * o not the only way to may chip selects to dimm slots |
| 741 | * o investigate if there is some way to obtain this map from the bios |
| 742 | */ |
| 743 | static void __devinit i5100_init_dimm_csmap(struct mem_ctl_info *mci) |
| 744 | { |
| 745 | struct i5100_priv *priv = mci->pvt_info; |
| 746 | int i; |
| 747 | |
Nils Carlson | b18dfd0 | 2009-12-15 16:47:40 -0800 | [diff] [blame] | 748 | for (i = 0; i < I5100_MAX_DIMM_SLOTS_PER_CHAN; i++) { |
Arthur Jones | 8f421c5 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 749 | int j; |
| 750 | |
| 751 | for (j = 0; j < I5100_MAX_RANKS_PER_DIMM; j++) |
| 752 | priv->dimm_csmap[i][j] = -1; /* default NC */ |
| 753 | } |
| 754 | |
| 755 | /* only 2 chip selects per slot... */ |
Nils Carlson | bbead21 | 2009-12-15 16:47:42 -0800 | [diff] [blame] | 756 | if (priv->ranksperchan == 4) { |
| 757 | priv->dimm_csmap[0][0] = 0; |
| 758 | priv->dimm_csmap[0][1] = 3; |
| 759 | priv->dimm_csmap[1][0] = 1; |
| 760 | priv->dimm_csmap[1][1] = 2; |
| 761 | priv->dimm_csmap[2][0] = 2; |
| 762 | priv->dimm_csmap[3][0] = 3; |
| 763 | } else { |
| 764 | priv->dimm_csmap[0][0] = 0; |
| 765 | priv->dimm_csmap[0][1] = 1; |
| 766 | priv->dimm_csmap[1][0] = 2; |
| 767 | priv->dimm_csmap[1][1] = 3; |
| 768 | priv->dimm_csmap[2][0] = 4; |
| 769 | priv->dimm_csmap[2][1] = 5; |
| 770 | } |
Arthur Jones | 8f421c5 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 771 | } |
| 772 | |
| 773 | static void __devinit i5100_init_dimm_layout(struct pci_dev *pdev, |
| 774 | struct mem_ctl_info *mci) |
| 775 | { |
| 776 | struct i5100_priv *priv = mci->pvt_info; |
| 777 | int i; |
| 778 | |
Nils Carlson | b18dfd0 | 2009-12-15 16:47:40 -0800 | [diff] [blame] | 779 | for (i = 0; i < I5100_CHANNELS; i++) { |
Arthur Jones | 8f421c5 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 780 | int j; |
| 781 | |
Nils Carlson | b18dfd0 | 2009-12-15 16:47:40 -0800 | [diff] [blame] | 782 | for (j = 0; j < I5100_MAX_DIMM_SLOTS_PER_CHAN; j++) { |
Arthur Jones | 8f421c5 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 783 | u8 rank; |
| 784 | |
| 785 | if (i5100_read_spd_byte(mci, i, j, 5, &rank) < 0) |
| 786 | priv->dimm_numrank[i][j] = 0; |
| 787 | else |
| 788 | priv->dimm_numrank[i][j] = (rank & 3) + 1; |
| 789 | } |
| 790 | } |
| 791 | |
| 792 | i5100_init_dimm_csmap(mci); |
| 793 | } |
| 794 | |
| 795 | static void __devinit i5100_init_interleaving(struct pci_dev *pdev, |
| 796 | struct mem_ctl_info *mci) |
| 797 | { |
| 798 | u16 w; |
| 799 | u32 dw; |
| 800 | struct i5100_priv *priv = mci->pvt_info; |
| 801 | struct pci_dev *mms[2] = { priv->ch0mm, priv->ch1mm }; |
| 802 | int i; |
| 803 | |
| 804 | pci_read_config_word(pdev, I5100_TOLM, &w); |
Arthur Jones | b238e57 | 2008-07-25 01:49:08 -0700 | [diff] [blame] | 805 | priv->tolm = (u64) i5100_tolm_tolm(w) * 256 * 1024 * 1024; |
Arthur Jones | 8f421c5 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 806 | |
| 807 | pci_read_config_word(pdev, I5100_MIR0, &w); |
Arthur Jones | b238e57 | 2008-07-25 01:49:08 -0700 | [diff] [blame] | 808 | priv->mir[0].limit = (u64) i5100_mir_limit(w) << 28; |
| 809 | priv->mir[0].way[1] = i5100_mir_way1(w); |
| 810 | priv->mir[0].way[0] = i5100_mir_way0(w); |
Arthur Jones | 8f421c5 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 811 | |
| 812 | pci_read_config_word(pdev, I5100_MIR1, &w); |
Arthur Jones | b238e57 | 2008-07-25 01:49:08 -0700 | [diff] [blame] | 813 | priv->mir[1].limit = (u64) i5100_mir_limit(w) << 28; |
| 814 | priv->mir[1].way[1] = i5100_mir_way1(w); |
| 815 | priv->mir[1].way[0] = i5100_mir_way0(w); |
Arthur Jones | 8f421c5 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 816 | |
| 817 | pci_read_config_word(pdev, I5100_AMIR_0, &w); |
| 818 | priv->amir[0] = w; |
| 819 | pci_read_config_word(pdev, I5100_AMIR_1, &w); |
| 820 | priv->amir[1] = w; |
| 821 | |
Nils Carlson | b18dfd0 | 2009-12-15 16:47:40 -0800 | [diff] [blame] | 822 | for (i = 0; i < I5100_CHANNELS; i++) { |
Arthur Jones | 8f421c5 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 823 | int j; |
| 824 | |
| 825 | for (j = 0; j < 5; j++) { |
| 826 | int k; |
| 827 | |
| 828 | pci_read_config_dword(mms[i], I5100_DMIR + j * 4, &dw); |
| 829 | |
| 830 | priv->dmir[i][j].limit = |
Arthur Jones | b238e57 | 2008-07-25 01:49:08 -0700 | [diff] [blame] | 831 | (u64) i5100_dmir_limit(dw) << 28; |
Arthur Jones | 8f421c5 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 832 | for (k = 0; k < I5100_MAX_RANKS_PER_DIMM; k++) |
| 833 | priv->dmir[i][j].rank[k] = |
Arthur Jones | b238e57 | 2008-07-25 01:49:08 -0700 | [diff] [blame] | 834 | i5100_dmir_rank(dw, k); |
Arthur Jones | 8f421c5 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 835 | } |
| 836 | } |
| 837 | |
| 838 | i5100_init_mtr(mci); |
| 839 | } |
| 840 | |
| 841 | static void __devinit i5100_init_csrows(struct mem_ctl_info *mci) |
| 842 | { |
| 843 | int i; |
| 844 | unsigned long total_pages = 0UL; |
| 845 | struct i5100_priv *priv = mci->pvt_info; |
| 846 | |
| 847 | for (i = 0; i < mci->nr_csrows; i++) { |
| 848 | const unsigned long npages = i5100_npages(mci, i); |
Nils Carlson | b18dfd0 | 2009-12-15 16:47:40 -0800 | [diff] [blame] | 849 | const unsigned chan = i5100_csrow_to_chan(mci, i); |
Arthur Jones | 8f421c5 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 850 | const unsigned rank = i5100_csrow_to_rank(mci, i); |
| 851 | |
| 852 | if (!npages) |
| 853 | continue; |
| 854 | |
| 855 | /* |
| 856 | * FIXME: these two are totally bogus -- I don't see how to |
| 857 | * map them correctly to this structure... |
| 858 | */ |
| 859 | mci->csrows[i].first_page = total_pages; |
| 860 | mci->csrows[i].last_page = total_pages + npages - 1; |
| 861 | mci->csrows[i].page_mask = 0UL; |
| 862 | |
| 863 | mci->csrows[i].nr_pages = npages; |
| 864 | mci->csrows[i].grain = 32; |
| 865 | mci->csrows[i].csrow_idx = i; |
| 866 | mci->csrows[i].dtype = |
Nils Carlson | b18dfd0 | 2009-12-15 16:47:40 -0800 | [diff] [blame] | 867 | (priv->mtr[chan][rank].width == 4) ? DEV_X4 : DEV_X8; |
Arthur Jones | 8f421c5 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 868 | mci->csrows[i].ue_count = 0; |
| 869 | mci->csrows[i].ce_count = 0; |
| 870 | mci->csrows[i].mtype = MEM_RDDR2; |
| 871 | mci->csrows[i].edac_mode = EDAC_SECDED; |
| 872 | mci->csrows[i].mci = mci; |
| 873 | mci->csrows[i].nr_channels = 1; |
| 874 | mci->csrows[i].channels[0].chan_idx = 0; |
| 875 | mci->csrows[i].channels[0].ce_count = 0; |
| 876 | mci->csrows[i].channels[0].csrow = mci->csrows + i; |
| 877 | snprintf(mci->csrows[i].channels[0].label, |
| 878 | sizeof(mci->csrows[i].channels[0].label), |
Nils Carlson | b18dfd0 | 2009-12-15 16:47:40 -0800 | [diff] [blame] | 879 | "DIMM%u", i5100_rank_to_slot(mci, chan, rank)); |
Arthur Jones | 8f421c5 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 880 | |
| 881 | total_pages += npages; |
| 882 | } |
| 883 | } |
| 884 | |
| 885 | static int __devinit i5100_init_one(struct pci_dev *pdev, |
| 886 | const struct pci_device_id *id) |
| 887 | { |
| 888 | int rc; |
| 889 | struct mem_ctl_info *mci; |
| 890 | struct i5100_priv *priv; |
| 891 | struct pci_dev *ch0mm, *ch1mm; |
| 892 | int ret = 0; |
| 893 | u32 dw; |
| 894 | int ranksperch; |
| 895 | |
| 896 | if (PCI_FUNC(pdev->devfn) != 1) |
| 897 | return -ENODEV; |
| 898 | |
| 899 | rc = pci_enable_device(pdev); |
| 900 | if (rc < 0) { |
| 901 | ret = rc; |
| 902 | goto bail; |
| 903 | } |
| 904 | |
Arthur Jones | 43920a5 | 2008-07-25 01:49:06 -0700 | [diff] [blame] | 905 | /* ECC enabled? */ |
| 906 | pci_read_config_dword(pdev, I5100_MC, &dw); |
Arthur Jones | b238e57 | 2008-07-25 01:49:08 -0700 | [diff] [blame] | 907 | if (!i5100_mc_errdeten(dw)) { |
Arthur Jones | 43920a5 | 2008-07-25 01:49:06 -0700 | [diff] [blame] | 908 | printk(KERN_INFO "i5100_edac: ECC not enabled.\n"); |
| 909 | ret = -ENODEV; |
Arthur Jones | b238e57 | 2008-07-25 01:49:08 -0700 | [diff] [blame] | 910 | goto bail_pdev; |
Arthur Jones | 43920a5 | 2008-07-25 01:49:06 -0700 | [diff] [blame] | 911 | } |
| 912 | |
Arthur Jones | 8f421c5 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 913 | /* figure out how many ranks, from strapped state of 48GB_Mode input */ |
| 914 | pci_read_config_dword(pdev, I5100_MS, &dw); |
| 915 | ranksperch = !!(dw & (1 << 8)) * 2 + 4; |
| 916 | |
Arthur Jones | 178d5a7 | 2008-07-25 01:49:06 -0700 | [diff] [blame] | 917 | /* enable error reporting... */ |
| 918 | pci_read_config_dword(pdev, I5100_EMASK_MEM, &dw); |
| 919 | dw &= ~I5100_FERR_NF_MEM_ANY_MASK; |
| 920 | pci_write_config_dword(pdev, I5100_EMASK_MEM, dw); |
| 921 | |
Arthur Jones | 8f421c5 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 922 | /* device 21, func 0, Channel 0 Memory Map, Error Flag/Mask, etc... */ |
| 923 | ch0mm = pci_get_device_func(PCI_VENDOR_ID_INTEL, |
| 924 | PCI_DEVICE_ID_INTEL_5100_21, 0); |
Arthur Jones | b238e57 | 2008-07-25 01:49:08 -0700 | [diff] [blame] | 925 | if (!ch0mm) { |
| 926 | ret = -ENODEV; |
| 927 | goto bail_pdev; |
| 928 | } |
Arthur Jones | 8f421c5 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 929 | |
| 930 | rc = pci_enable_device(ch0mm); |
| 931 | if (rc < 0) { |
| 932 | ret = rc; |
| 933 | goto bail_ch0; |
| 934 | } |
| 935 | |
| 936 | /* device 22, func 0, Channel 1 Memory Map, Error Flag/Mask, etc... */ |
| 937 | ch1mm = pci_get_device_func(PCI_VENDOR_ID_INTEL, |
| 938 | PCI_DEVICE_ID_INTEL_5100_22, 0); |
| 939 | if (!ch1mm) { |
| 940 | ret = -ENODEV; |
Arthur Jones | b238e57 | 2008-07-25 01:49:08 -0700 | [diff] [blame] | 941 | goto bail_disable_ch0; |
Arthur Jones | 8f421c5 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 942 | } |
| 943 | |
| 944 | rc = pci_enable_device(ch1mm); |
| 945 | if (rc < 0) { |
| 946 | ret = rc; |
| 947 | goto bail_ch1; |
| 948 | } |
| 949 | |
| 950 | mci = edac_mc_alloc(sizeof(*priv), ranksperch * 2, 1, 0); |
| 951 | if (!mci) { |
| 952 | ret = -ENOMEM; |
Arthur Jones | b238e57 | 2008-07-25 01:49:08 -0700 | [diff] [blame] | 953 | goto bail_disable_ch1; |
Arthur Jones | 8f421c5 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 954 | } |
| 955 | |
| 956 | mci->dev = &pdev->dev; |
| 957 | |
| 958 | priv = mci->pvt_info; |
Nils Carlson | b18dfd0 | 2009-12-15 16:47:40 -0800 | [diff] [blame] | 959 | priv->ranksperchan = ranksperch; |
Arthur Jones | 8f421c5 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 960 | priv->mc = pdev; |
| 961 | priv->ch0mm = ch0mm; |
| 962 | priv->ch1mm = ch1mm; |
| 963 | |
Nils Carlson | 295439f | 2009-12-15 16:47:42 -0800 | [diff] [blame] | 964 | INIT_DELAYED_WORK(&(priv->i5100_scrubbing), i5100_refresh_scrubbing); |
| 965 | |
| 966 | /* If scrubbing was already enabled by the bios, start maintaining it */ |
| 967 | pci_read_config_dword(pdev, I5100_MC, &dw); |
| 968 | if (i5100_mc_scrben(dw)) { |
| 969 | priv->scrub_enable = 1; |
| 970 | schedule_delayed_work(&(priv->i5100_scrubbing), |
| 971 | I5100_SCRUB_REFRESH_RATE); |
| 972 | } |
| 973 | |
Arthur Jones | 8f421c5 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 974 | i5100_init_dimm_layout(pdev, mci); |
| 975 | i5100_init_interleaving(pdev, mci); |
| 976 | |
| 977 | mci->mtype_cap = MEM_FLAG_FB_DDR2; |
| 978 | mci->edac_ctl_cap = EDAC_FLAG_SECDED; |
| 979 | mci->edac_cap = EDAC_FLAG_SECDED; |
| 980 | mci->mod_name = "i5100_edac.c"; |
| 981 | mci->mod_ver = "not versioned"; |
| 982 | mci->ctl_name = "i5100"; |
| 983 | mci->dev_name = pci_name(pdev); |
Arthur Jones | b238e57 | 2008-07-25 01:49:08 -0700 | [diff] [blame] | 984 | mci->ctl_page_to_phys = NULL; |
Arthur Jones | 8f421c5 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 985 | |
| 986 | mci->edac_check = i5100_check_error; |
Nils Carlson | 295439f | 2009-12-15 16:47:42 -0800 | [diff] [blame] | 987 | mci->set_sdram_scrub_rate = i5100_set_scrub_rate; |
| 988 | mci->get_sdram_scrub_rate = i5100_get_scrub_rate; |
Arthur Jones | 8f421c5 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 989 | |
| 990 | i5100_init_csrows(mci); |
| 991 | |
| 992 | /* this strange construction seems to be in every driver, dunno why */ |
| 993 | switch (edac_op_state) { |
| 994 | case EDAC_OPSTATE_POLL: |
| 995 | case EDAC_OPSTATE_NMI: |
| 996 | break; |
| 997 | default: |
| 998 | edac_op_state = EDAC_OPSTATE_POLL; |
| 999 | break; |
| 1000 | } |
| 1001 | |
| 1002 | if (edac_mc_add_mc(mci)) { |
| 1003 | ret = -ENODEV; |
Nils Carlson | 295439f | 2009-12-15 16:47:42 -0800 | [diff] [blame] | 1004 | goto bail_scrub; |
Arthur Jones | 8f421c5 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 1005 | } |
| 1006 | |
Arthur Jones | b238e57 | 2008-07-25 01:49:08 -0700 | [diff] [blame] | 1007 | return ret; |
Arthur Jones | 8f421c5 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 1008 | |
Nils Carlson | 295439f | 2009-12-15 16:47:42 -0800 | [diff] [blame] | 1009 | bail_scrub: |
| 1010 | priv->scrub_enable = 0; |
| 1011 | cancel_delayed_work_sync(&(priv->i5100_scrubbing)); |
Arthur Jones | 8f421c5 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 1012 | edac_mc_free(mci); |
| 1013 | |
Arthur Jones | b238e57 | 2008-07-25 01:49:08 -0700 | [diff] [blame] | 1014 | bail_disable_ch1: |
| 1015 | pci_disable_device(ch1mm); |
| 1016 | |
Arthur Jones | 8f421c5 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 1017 | bail_ch1: |
| 1018 | pci_dev_put(ch1mm); |
| 1019 | |
Arthur Jones | b238e57 | 2008-07-25 01:49:08 -0700 | [diff] [blame] | 1020 | bail_disable_ch0: |
| 1021 | pci_disable_device(ch0mm); |
| 1022 | |
Arthur Jones | 8f421c5 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 1023 | bail_ch0: |
| 1024 | pci_dev_put(ch0mm); |
| 1025 | |
Arthur Jones | b238e57 | 2008-07-25 01:49:08 -0700 | [diff] [blame] | 1026 | bail_pdev: |
| 1027 | pci_disable_device(pdev); |
| 1028 | |
Arthur Jones | 8f421c5 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 1029 | bail: |
| 1030 | return ret; |
| 1031 | } |
| 1032 | |
| 1033 | static void __devexit i5100_remove_one(struct pci_dev *pdev) |
| 1034 | { |
| 1035 | struct mem_ctl_info *mci; |
| 1036 | struct i5100_priv *priv; |
| 1037 | |
| 1038 | mci = edac_mc_del_mc(&pdev->dev); |
| 1039 | |
| 1040 | if (!mci) |
| 1041 | return; |
| 1042 | |
| 1043 | priv = mci->pvt_info; |
Nils Carlson | 295439f | 2009-12-15 16:47:42 -0800 | [diff] [blame] | 1044 | |
| 1045 | priv->scrub_enable = 0; |
| 1046 | cancel_delayed_work_sync(&(priv->i5100_scrubbing)); |
| 1047 | |
Arthur Jones | b238e57 | 2008-07-25 01:49:08 -0700 | [diff] [blame] | 1048 | pci_disable_device(pdev); |
| 1049 | pci_disable_device(priv->ch0mm); |
| 1050 | pci_disable_device(priv->ch1mm); |
Arthur Jones | 8f421c5 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 1051 | pci_dev_put(priv->ch0mm); |
| 1052 | pci_dev_put(priv->ch1mm); |
| 1053 | |
| 1054 | edac_mc_free(mci); |
| 1055 | } |
| 1056 | |
| 1057 | static const struct pci_device_id i5100_pci_tbl[] __devinitdata = { |
| 1058 | /* Device 16, Function 0, Channel 0 Memory Map, Error Flag/Mask, ... */ |
| 1059 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5100_16) }, |
| 1060 | { 0, } |
| 1061 | }; |
| 1062 | MODULE_DEVICE_TABLE(pci, i5100_pci_tbl); |
| 1063 | |
| 1064 | static struct pci_driver i5100_driver = { |
| 1065 | .name = KBUILD_BASENAME, |
| 1066 | .probe = i5100_init_one, |
| 1067 | .remove = __devexit_p(i5100_remove_one), |
| 1068 | .id_table = i5100_pci_tbl, |
| 1069 | }; |
| 1070 | |
| 1071 | static int __init i5100_init(void) |
| 1072 | { |
| 1073 | int pci_rc; |
| 1074 | |
| 1075 | pci_rc = pci_register_driver(&i5100_driver); |
| 1076 | |
| 1077 | return (pci_rc < 0) ? pci_rc : 0; |
| 1078 | } |
| 1079 | |
| 1080 | static void __exit i5100_exit(void) |
| 1081 | { |
| 1082 | pci_unregister_driver(&i5100_driver); |
| 1083 | } |
| 1084 | |
| 1085 | module_init(i5100_init); |
| 1086 | module_exit(i5100_exit); |
| 1087 | |
| 1088 | MODULE_LICENSE("GPL"); |
| 1089 | MODULE_AUTHOR |
| 1090 | ("Arthur Jones <ajones@riverbed.com>"); |
| 1091 | MODULE_DESCRIPTION("MC Driver for Intel I5100 memory controllers"); |