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gerrit-public.fairphone.software / kernel / msm / fab5db97e44f76461f76b24adfa8ccb14d4df498 / . / include / asm-powerpc / cputable.h
blob: 69f2c242797ff16d3c85867f817e0c1fbf9c3727 [file] [log] [blame]
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]1#ifndef __ASM_POWERPC_CPUTABLE_H
2#define __ASM_POWERPC_CPUTABLE_H
3
David Gibson3ddfbcf2005-11-10 12:56:55 +1100[diff] [blame]4#include <asm/asm-compat.h>
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]5
6#define PPC_FEATURE_32 0x80000000
7#define PPC_FEATURE_64 0x40000000
8#define PPC_FEATURE_601_INSTR 0x20000000
9#define PPC_FEATURE_HAS_ALTIVEC 0x10000000
10#define PPC_FEATURE_HAS_FPU 0x08000000
11#define PPC_FEATURE_HAS_MMU 0x04000000
12#define PPC_FEATURE_HAS_4xxMAC 0x02000000
13#define PPC_FEATURE_UNIFIED_CACHE 0x01000000
14#define PPC_FEATURE_HAS_SPE 0x00800000
15#define PPC_FEATURE_HAS_EFP_SINGLE 0x00400000
16#define PPC_FEATURE_HAS_EFP_DOUBLE 0x00200000
Paul Mackerras98599012005-10-22 16:51:34 +1000[diff] [blame]17#define PPC_FEATURE_NO_TB 0x00100000
Paul Mackerrasa7ddc5e2005-11-10 14:29:18 +1100[diff] [blame]18#define PPC_FEATURE_POWER4 0x00080000
19#define PPC_FEATURE_POWER5 0x00040000
20#define PPC_FEATURE_POWER5_PLUS 0x00020000
21#define PPC_FEATURE_CELL 0x00010000
Paul Mackerras80f15dc2006-01-14 10:11:39 +1100[diff] [blame]22#define PPC_FEATURE_BOOKE 0x00008000
Benjamin Herrenschmidtaa5cb022006-03-01 15:07:07 +1100[diff] [blame]23#define PPC_FEATURE_SMT 0x00004000
24#define PPC_FEATURE_ICACHE_SNOOP 0x00002000
Anton Blanchard03054d52006-04-29 09:51:06 +1000[diff] [blame]25#define PPC_FEATURE_ARCH_2_05 0x00001000
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]26
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame^]27#define PPC_FEATURE_TRUE_LE 0x00000002
28#define PPC_FEATURE_PPC_LE 0x00000001
29
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]30#ifdef __KERNEL__
31#ifndef __ASSEMBLY__
32
33/* This structure can grow, it's real size is used by head.S code
34 * via the mkdefs mechanism.
35 */
36struct cpu_spec;
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]37
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]38typedef void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec);
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]39
Anton Blanchard32a33992006-01-09 15:41:31 +1100[diff] [blame]40enum powerpc_oprofile_type {
Andy Whitcroft7a45fb12006-01-13 12:35:49 +0000[diff] [blame]41 PPC_OPROFILE_INVALID = 0,
42 PPC_OPROFILE_RS64 = 1,
43 PPC_OPROFILE_POWER4 = 2,
44 PPC_OPROFILE_G4 = 3,
45 PPC_OPROFILE_BOOKE = 4,
Anton Blanchard32a33992006-01-09 15:41:31 +1100[diff] [blame]46};
47
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]48struct cpu_spec {
49 /* CPU is matched via (PVR & pvr_mask) == pvr_value */
50 unsigned int pvr_mask;
51 unsigned int pvr_value;
52
53 char *cpu_name;
54 unsigned long cpu_features; /* Kernel features */
55 unsigned int cpu_user_features; /* Userland features */
56
57 /* cache line sizes */
58 unsigned int icache_bsize;
59 unsigned int dcache_bsize;
60
61 /* number of performance monitor counters */
62 unsigned int num_pmcs;
63
64 /* this is called to initialize various CPU bits like L1 cache,
65 * BHT, SPD, etc... from head.S before branching to identify_machine
66 */
67 cpu_setup_t cpu_setup;
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]68
69 /* Used by oprofile userspace to select the right counters */
70 char *oprofile_cpu_type;
71
72 /* Processor specific oprofile operations */
Anton Blanchard32a33992006-01-09 15:41:31 +1100[diff] [blame]73 enum powerpc_oprofile_type oprofile_type;
Paul Mackerras80f15dc2006-01-14 10:11:39 +1100[diff] [blame]74
Michael Neulinge78dbc82006-06-08 14:42:34 +1000[diff] [blame]75 /* Bit locations inside the mmcra change */
76 unsigned long oprofile_mmcra_sihv;
77 unsigned long oprofile_mmcra_sipr;
78
79 /* Bits to clear during an oprofile exception */
80 unsigned long oprofile_mmcra_clear;
81
Paul Mackerras80f15dc2006-01-14 10:11:39 +1100[diff] [blame]82 /* Name of processor class, for the ELF AT_PLATFORM entry */
83 char *platform;
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]84};
85
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]86extern struct cpu_spec *cur_cpu_spec;
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]87
Paul Mackerras9b6b5632005-10-06 12:06:20 +1000[diff] [blame]88extern void identify_cpu(unsigned long offset, unsigned long cpu);
89extern void do_cpu_ftr_fixups(unsigned long offset);
90
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]91#endif /* __ASSEMBLY__ */
92
93/* CPU kernel features */
94
95/* Retain the 32b definitions all use bottom half of word */
96#define CPU_FTR_SPLIT_ID_CACHE ASM_CONST(0x0000000000000001)
97#define CPU_FTR_L2CR ASM_CONST(0x0000000000000002)
98#define CPU_FTR_SPEC7450 ASM_CONST(0x0000000000000004)
99#define CPU_FTR_ALTIVEC ASM_CONST(0x0000000000000008)
100#define CPU_FTR_TAU ASM_CONST(0x0000000000000010)
101#define CPU_FTR_CAN_DOZE ASM_CONST(0x0000000000000020)
102#define CPU_FTR_USE_TB ASM_CONST(0x0000000000000040)
103#define CPU_FTR_604_PERF_MON ASM_CONST(0x0000000000000080)
104#define CPU_FTR_601 ASM_CONST(0x0000000000000100)
105#define CPU_FTR_HPTE_TABLE ASM_CONST(0x0000000000000200)
106#define CPU_FTR_CAN_NAP ASM_CONST(0x0000000000000400)
107#define CPU_FTR_L3CR ASM_CONST(0x0000000000000800)
108#define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x0000000000001000)
109#define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x0000000000002000)
110#define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x0000000000004000)
111#define CPU_FTR_NO_DPM ASM_CONST(0x0000000000008000)
112#define CPU_FTR_HAS_HIGH_BATS ASM_CONST(0x0000000000010000)
113#define CPU_FTR_NEED_COHERENT ASM_CONST(0x0000000000020000)
114#define CPU_FTR_NO_BTIC ASM_CONST(0x0000000000040000)
115#define CPU_FTR_BIG_PHYS ASM_CONST(0x0000000000080000)
Michael Ellerman3d159102006-03-21 20:45:58 +1100[diff] [blame]116#define CPU_FTR_NODSISRALIGN ASM_CONST(0x0000000000100000)
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame^]117#define CPU_FTR_PPC_LE ASM_CONST(0x0000000000200000)
118#define CPU_FTR_REAL_LE ASM_CONST(0x0000000000400000)
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]119
120#ifdef __powerpc64__
121/* Add the 64b processor unique features in the top half of the word */
Michael Ellerman3d159102006-03-21 20:45:58 +1100[diff] [blame]122#define CPU_FTR_SLB ASM_CONST(0x0000000100000000)
123#define CPU_FTR_16M_PAGE ASM_CONST(0x0000000200000000)
124#define CPU_FTR_TLBIEL ASM_CONST(0x0000000400000000)
125#define CPU_FTR_NOEXECUTE ASM_CONST(0x0000000800000000)
126#define CPU_FTR_IABR ASM_CONST(0x0000002000000000)
127#define CPU_FTR_MMCRA ASM_CONST(0x0000004000000000)
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]128#define CPU_FTR_CTRL ASM_CONST(0x0000008000000000)
Michael Ellerman3d159102006-03-21 20:45:58 +1100[diff] [blame]129#define CPU_FTR_SMT ASM_CONST(0x0000010000000000)
130#define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x0000020000000000)
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]131#define CPU_FTR_LOCKLESS_TLBIE ASM_CONST(0x0000040000000000)
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100[diff] [blame]132#define CPU_FTR_CI_LARGE_PAGE ASM_CONST(0x0000100000000000)
Arnd Bergmannc902be72006-01-04 19:55:53 +0000[diff] [blame]133#define CPU_FTR_PAUSE_ZERO ASM_CONST(0x0000200000000000)
Paul Mackerrasc6622f62006-02-24 10:06:59 +1100[diff] [blame]134#define CPU_FTR_PURR ASM_CONST(0x0000400000000000)
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]135#else
136/* ensure on 32b processors the flags are available for compiling but
137 * don't do anything */
Michael Ellerman3d159102006-03-21 20:45:58 +1100[diff] [blame]138#define CPU_FTR_SLB ASM_CONST(0x0)
139#define CPU_FTR_16M_PAGE ASM_CONST(0x0)
140#define CPU_FTR_TLBIEL ASM_CONST(0x0)
141#define CPU_FTR_NOEXECUTE ASM_CONST(0x0)
142#define CPU_FTR_IABR ASM_CONST(0x0)
143#define CPU_FTR_MMCRA ASM_CONST(0x0)
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]144#define CPU_FTR_CTRL ASM_CONST(0x0)
Michael Ellerman3d159102006-03-21 20:45:58 +1100[diff] [blame]145#define CPU_FTR_SMT ASM_CONST(0x0)
146#define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x0)
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]147#define CPU_FTR_LOCKLESS_TLBIE ASM_CONST(0x0)
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100[diff] [blame]148#define CPU_FTR_CI_LARGE_PAGE ASM_CONST(0x0)
Paul Mackerrasc6622f62006-02-24 10:06:59 +1100[diff] [blame]149#define CPU_FTR_PURR ASM_CONST(0x0)
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]150#endif
151
152#ifndef __ASSEMBLY__
153
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]154#define CPU_FTR_PPCAS_ARCH_V2_BASE (CPU_FTR_SLB | \
155 CPU_FTR_TLBIEL | CPU_FTR_NOEXECUTE | \
156 CPU_FTR_NODSISRALIGN | CPU_FTR_CTRL)
157
158/* iSeries doesn't support large pages */
159#ifdef CONFIG_PPC_ISERIES
160#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_PPCAS_ARCH_V2_BASE)
161#else
162#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_PPCAS_ARCH_V2_BASE | CPU_FTR_16M_PAGE)
163#endif /* CONFIG_PPC_ISERIES */
164
165/* We only set the altivec features if the kernel was compiled with altivec
166 * support
167 */
168#ifdef CONFIG_ALTIVEC
169#define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC
170#define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
171#else
172#define CPU_FTR_ALTIVEC_COMP 0
173#define PPC_FEATURE_HAS_ALTIVEC_COMP 0
174#endif
175
176/* We need to mark all pages as being coherent if we're SMP or we
Kumar Gala1775dbb2006-02-22 09:46:02 -0600[diff] [blame]177 * have a 74[45]x and an MPC107 host bridge. Also 83xx requires
178 * it for PCI "streaming/prefetch" to work properly.
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]179 */
Kumar Gala1775dbb2006-02-22 09:46:02 -0600[diff] [blame]180#if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE) \
181 || defined(CONFIG_PPC_83xx)
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]182#define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT
183#else
184#define CPU_FTR_COMMON 0
185#endif
186
187/* The powersave features NAP & DOZE seems to confuse BDI when
188 debugging. So if a BDI is used, disable theses
189 */
190#ifndef CONFIG_BDI_SWITCH
191#define CPU_FTR_MAYBE_CAN_DOZE CPU_FTR_CAN_DOZE
192#define CPU_FTR_MAYBE_CAN_NAP CPU_FTR_CAN_NAP
193#else
194#define CPU_FTR_MAYBE_CAN_DOZE 0
195#define CPU_FTR_MAYBE_CAN_NAP 0
196#endif
197
198#define CLASSIC_PPC (!defined(CONFIG_8xx) && !defined(CONFIG_4xx) && \
199 !defined(CONFIG_POWER3) && !defined(CONFIG_POWER4) && \
200 !defined(CONFIG_BOOKE))
201
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]202#define CPU_FTRS_PPC601 (CPU_FTR_COMMON | CPU_FTR_601 | CPU_FTR_HPTE_TABLE)
203#define CPU_FTRS_603 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
204 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame^]205 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]206#define CPU_FTRS_604 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame^]207 CPU_FTR_USE_TB | CPU_FTR_604_PERF_MON | CPU_FTR_HPTE_TABLE | \
208 CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]209#define CPU_FTRS_740_NOTAU (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
210 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame^]211 CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]212#define CPU_FTRS_740 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
213 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame^]214 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
215 CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]216#define CPU_FTRS_750 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
217 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame^]218 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
219 CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]220#define CPU_FTRS_750FX1 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
221 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
222 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame^]223 CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]224#define CPU_FTRS_750FX2 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
225 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
226 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame^]227 CPU_FTR_NO_DPM | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]228#define CPU_FTRS_750FX (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
229 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
230 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame^]231 CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]232#define CPU_FTRS_750GX (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | \
233 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU | \
234 CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame^]235 CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]236#define CPU_FTRS_7400_NOTAU (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
237 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
238 CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame^]239 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]240#define CPU_FTRS_7400 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
241 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
242 CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame^]243 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]244#define CPU_FTRS_7450_20 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
245 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
246 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame^]247 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]248#define CPU_FTRS_7450_21 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
249 CPU_FTR_USE_TB | \
250 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
251 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
252 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame^]253 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]254#define CPU_FTRS_7450_23 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
255 CPU_FTR_USE_TB | \
256 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
257 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame^]258 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]259#define CPU_FTRS_7455_1 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
260 CPU_FTR_USE_TB | \
261 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \
262 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_HAS_HIGH_BATS | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame^]263 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]264#define CPU_FTRS_7455_20 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
265 CPU_FTR_USE_TB | \
266 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
267 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
268 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame^]269 CPU_FTR_NEED_COHERENT | CPU_FTR_HAS_HIGH_BATS | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]270#define CPU_FTRS_7455 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
271 CPU_FTR_USE_TB | \
272 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
273 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
274 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame^]275 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]276#define CPU_FTRS_7447_10 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
277 CPU_FTR_USE_TB | \
278 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
279 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
280 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame^]281 CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]282#define CPU_FTRS_7447 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
283 CPU_FTR_USE_TB | \
284 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
285 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
286 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame^]287 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]288#define CPU_FTRS_7447A (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
289 CPU_FTR_USE_TB | \
290 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
291 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
292 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame^]293 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]294#define CPU_FTRS_82XX (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
295 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB)
296#define CPU_FTRS_G2_LE (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | \
297 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS)
298#define CPU_FTRS_E300 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | \
299 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS | \
300 CPU_FTR_COMMON)
301#define CPU_FTRS_CLASSIC32 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
302 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE)
303#define CPU_FTRS_POWER3_32 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
304 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE)
305#define CPU_FTRS_POWER4_32 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
306 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_NODSISRALIGN)
307#define CPU_FTRS_970_32 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
308 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_ALTIVEC_COMP | \
309 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN)
310#define CPU_FTRS_8XX (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB)
311#define CPU_FTRS_40X (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
312 CPU_FTR_NODSISRALIGN)
313#define CPU_FTRS_44X (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
314 CPU_FTR_NODSISRALIGN)
315#define CPU_FTRS_E200 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN)
316#define CPU_FTRS_E500 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
317 CPU_FTR_NODSISRALIGN)
318#define CPU_FTRS_E500_2 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
319 CPU_FTR_BIG_PHYS | CPU_FTR_NODSISRALIGN)
320#define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]321#ifdef __powerpc64__
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]322#define CPU_FTRS_POWER3 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame^]323 CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]324#define CPU_FTRS_RS64 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
325 CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | \
326 CPU_FTR_MMCRA | CPU_FTR_CTRL)
327#define CPU_FTRS_POWER4 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
328 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_MMCRA)
329#define CPU_FTRS_PPC970 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
330 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \
331 CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA)
332#define CPU_FTRS_POWER5 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
333 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \
334 CPU_FTR_MMCRA | CPU_FTR_SMT | \
335 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
Michael Neulinge78dbc82006-06-08 14:42:34 +1000[diff] [blame]336 CPU_FTR_PURR)
Anton Blanchard03054d52006-04-29 09:51:06 +1000[diff] [blame]337#define CPU_FTRS_POWER6 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
338 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \
339 CPU_FTR_MMCRA | CPU_FTR_SMT | \
340 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame^]341 CPU_FTR_PURR | CPU_FTR_CI_LARGE_PAGE | CPU_FTR_REAL_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]342#define CPU_FTRS_CELL (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
343 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \
344 CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
345 CPU_FTR_CTRL | CPU_FTR_PAUSE_ZERO)
346#define CPU_FTRS_COMPATIBLE (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
347 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2)
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]348#endif
349
Anton Blanchard2406f602005-12-13 07:45:33 +1100[diff] [blame]350#ifdef __powerpc64__
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]351#define CPU_FTRS_POSSIBLE \
352 (CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 | \
Anton Blanchard03054d52006-04-29 09:51:06 +1000[diff] [blame]353 CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_POWER6 | \
354 CPU_FTRS_CELL | CPU_FTR_CI_LARGE_PAGE)
Anton Blanchard2406f602005-12-13 07:45:33 +1100[diff] [blame]355#else
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]356enum {
357 CPU_FTRS_POSSIBLE =
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]358#if CLASSIC_PPC
359 CPU_FTRS_PPC601 | CPU_FTRS_603 | CPU_FTRS_604 | CPU_FTRS_740_NOTAU |
360 CPU_FTRS_740 | CPU_FTRS_750 | CPU_FTRS_750FX1 |
361 CPU_FTRS_750FX2 | CPU_FTRS_750FX | CPU_FTRS_750GX |
362 CPU_FTRS_7400_NOTAU | CPU_FTRS_7400 | CPU_FTRS_7450_20 |
363 CPU_FTRS_7450_21 | CPU_FTRS_7450_23 | CPU_FTRS_7455_1 |
364 CPU_FTRS_7455_20 | CPU_FTRS_7455 | CPU_FTRS_7447_10 |
365 CPU_FTRS_7447 | CPU_FTRS_7447A | CPU_FTRS_82XX |
366 CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_CLASSIC32 |
367#else
368 CPU_FTRS_GENERIC_32 |
369#endif
370#ifdef CONFIG_PPC64BRIDGE
371 CPU_FTRS_POWER3_32 |
372#endif
373#ifdef CONFIG_POWER4
374 CPU_FTRS_POWER4_32 | CPU_FTRS_970_32 |
375#endif
376#ifdef CONFIG_8xx
377 CPU_FTRS_8XX |
378#endif
379#ifdef CONFIG_40x
380 CPU_FTRS_40X |
381#endif
382#ifdef CONFIG_44x
383 CPU_FTRS_44X |
384#endif
385#ifdef CONFIG_E200
386 CPU_FTRS_E200 |
387#endif
388#ifdef CONFIG_E500
389 CPU_FTRS_E500 | CPU_FTRS_E500_2 |
390#endif
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]391 0,
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]392};
393#endif /* __powerpc64__ */
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]394
Anton Blanchard2406f602005-12-13 07:45:33 +1100[diff] [blame]395#ifdef __powerpc64__
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]396#define CPU_FTRS_ALWAYS \
397 (CPU_FTRS_POWER3 & CPU_FTRS_RS64 & CPU_FTRS_POWER4 & \
Anton Blanchard03054d52006-04-29 09:51:06 +1000[diff] [blame]398 CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & CPU_FTRS_POWER6 & \
399 CPU_FTRS_CELL & CPU_FTRS_POSSIBLE)
Anton Blanchard2406f602005-12-13 07:45:33 +1100[diff] [blame]400#else
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]401enum {
402 CPU_FTRS_ALWAYS =
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]403#if CLASSIC_PPC
404 CPU_FTRS_PPC601 & CPU_FTRS_603 & CPU_FTRS_604 & CPU_FTRS_740_NOTAU &
405 CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 &
406 CPU_FTRS_750FX2 & CPU_FTRS_750FX & CPU_FTRS_750GX &
407 CPU_FTRS_7400_NOTAU & CPU_FTRS_7400 & CPU_FTRS_7450_20 &
408 CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 &
409 CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 &
410 CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX &
411 CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_CLASSIC32 &
412#else
413 CPU_FTRS_GENERIC_32 &
414#endif
415#ifdef CONFIG_PPC64BRIDGE
416 CPU_FTRS_POWER3_32 &
417#endif
418#ifdef CONFIG_POWER4
419 CPU_FTRS_POWER4_32 & CPU_FTRS_970_32 &
420#endif
421#ifdef CONFIG_8xx
422 CPU_FTRS_8XX &
423#endif
424#ifdef CONFIG_40x
425 CPU_FTRS_40X &
426#endif
427#ifdef CONFIG_44x
428 CPU_FTRS_44X &
429#endif
430#ifdef CONFIG_E200
431 CPU_FTRS_E200 &
432#endif
433#ifdef CONFIG_E500
434 CPU_FTRS_E500 & CPU_FTRS_E500_2 &
435#endif
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]436 CPU_FTRS_POSSIBLE,
437};
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]438#endif /* __powerpc64__ */
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]439
440static inline int cpu_has_feature(unsigned long feature)
441{
442 return (CPU_FTRS_ALWAYS & feature) ||
443 (CPU_FTRS_POSSIBLE
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]444 & cur_cpu_spec->cpu_features
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]445 & feature);
446}
447
448#endif /* !__ASSEMBLY__ */
449
450#ifdef __ASSEMBLY__
451
452#define BEGIN_FTR_SECTION 98:
453
454#ifndef __powerpc64__
455#define END_FTR_SECTION(msk, val) \
45699: \
457 .section __ftr_fixup,"a"; \
458 .align 2; \
459 .long msk; \
460 .long val; \
461 .long 98b; \
462 .long 99b; \
463 .previous
464#else /* __powerpc64__ */
465#define END_FTR_SECTION(msk, val) \
46699: \
467 .section __ftr_fixup,"a"; \
468 .align 3; \
469 .llong msk; \
470 .llong val; \
471 .llong 98b; \
472 .llong 99b; \
473 .previous
474#endif /* __powerpc64__ */
475
476#define END_FTR_SECTION_IFSET(msk) END_FTR_SECTION((msk), (msk))
477#define END_FTR_SECTION_IFCLR(msk) END_FTR_SECTION((msk), 0)
478#endif /* __ASSEMBLY__ */
479
480#endif /* __KERNEL__ */
481#endif /* __ASM_POWERPC_CPUTABLE_H */