Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 1 | /* |
| 2 | * OMAP4 SMP source file. It contains platform specific fucntions |
| 3 | * needed for the linux smp kernel. |
| 4 | * |
| 5 | * Copyright (C) 2009 Texas Instruments, Inc. |
| 6 | * |
| 7 | * Author: |
| 8 | * Santosh Shilimkar <santosh.shilimkar@ti.com> |
| 9 | * |
| 10 | * Platform file needed for the OMAP4 SMP. This file is based on arm |
| 11 | * realview smp platform. |
| 12 | * * Copyright (c) 2002 ARM Limited. |
| 13 | * |
| 14 | * This program is free software; you can redistribute it and/or modify |
| 15 | * it under the terms of the GNU General Public License version 2 as |
| 16 | * published by the Free Software Foundation. |
| 17 | */ |
| 18 | #include <linux/init.h> |
| 19 | #include <linux/device.h> |
Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 20 | #include <linux/smp.h> |
| 21 | #include <linux/io.h> |
| 22 | |
Santosh Shilimkar | 942e2c9 | 2009-12-11 16:16:35 -0800 | [diff] [blame] | 23 | #include <asm/cacheflush.h> |
Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 24 | #include <asm/localtimer.h> |
| 25 | #include <asm/smp_scu.h> |
| 26 | #include <mach/hardware.h> |
Santosh Shilimkar | fbc9be1 | 2010-05-14 12:05:26 -0700 | [diff] [blame] | 27 | #include <mach/omap4-common.h> |
Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 28 | |
Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 29 | /* SCU base address */ |
Tony Lindgren | e4e7a13 | 2009-10-19 15:25:26 -0700 | [diff] [blame] | 30 | static void __iomem *scu_base; |
Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 31 | |
Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 32 | static DEFINE_SPINLOCK(boot_lock); |
| 33 | |
| 34 | void __cpuinit platform_secondary_init(unsigned int cpu) |
| 35 | { |
| 36 | trace_hardirqs_off(); |
| 37 | |
| 38 | /* |
| 39 | * If any interrupts are already enabled for the primary |
| 40 | * core (e.g. timer irq), then they will not have been enabled |
| 41 | * for us: do so |
| 42 | */ |
Tony Lindgren | e4e7a13 | 2009-10-19 15:25:26 -0700 | [diff] [blame] | 43 | gic_cpu_init(0, gic_cpu_base_addr); |
Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 44 | |
| 45 | /* |
| 46 | * Synchronise with the boot thread. |
| 47 | */ |
| 48 | spin_lock(&boot_lock); |
| 49 | spin_unlock(&boot_lock); |
| 50 | } |
| 51 | |
| 52 | int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) |
| 53 | { |
Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 54 | /* |
| 55 | * Set synchronisation state between this boot processor |
| 56 | * and the secondary one |
| 57 | */ |
| 58 | spin_lock(&boot_lock); |
| 59 | |
| 60 | /* |
Santosh Shilimkar | 942e2c9 | 2009-12-11 16:16:35 -0800 | [diff] [blame] | 61 | * Update the AuxCoreBoot0 with boot state for secondary core. |
Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 62 | * omap_secondary_startup() routine will hold the secondary core till |
| 63 | * the AuxCoreBoot1 register is updated with cpu state |
| 64 | * A barrier is added to ensure that write buffer is drained |
| 65 | */ |
Santosh Shilimkar | 7d35b8d | 2010-08-02 13:18:19 +0300 | [diff] [blame] | 66 | omap_modify_auxcoreboot0(0x200, 0xfffffdff); |
Santosh Shilimkar | 942e2c9 | 2009-12-11 16:16:35 -0800 | [diff] [blame] | 67 | flush_cache_all(); |
Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 68 | smp_wmb(); |
Russell King | ad3b699 | 2010-11-15 09:42:08 +0000 | [diff] [blame] | 69 | smp_cross_call(cpumask_of(cpu), 1); |
Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 70 | |
Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 71 | /* |
| 72 | * Now the secondary core is starting up let it run its |
| 73 | * calibrations, then wait for it to finish |
| 74 | */ |
| 75 | spin_unlock(&boot_lock); |
| 76 | |
| 77 | return 0; |
| 78 | } |
| 79 | |
| 80 | static void __init wakeup_secondary(void) |
| 81 | { |
| 82 | /* |
| 83 | * Write the address of secondary startup routine into the |
Santosh Shilimkar | 942e2c9 | 2009-12-11 16:16:35 -0800 | [diff] [blame] | 84 | * AuxCoreBoot1 where ROM code will jump and start executing |
Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 85 | * on secondary core once out of WFE |
| 86 | * A barrier is added to ensure that write buffer is drained |
| 87 | */ |
Santosh Shilimkar | 942e2c9 | 2009-12-11 16:16:35 -0800 | [diff] [blame] | 88 | omap_auxcoreboot_addr(virt_to_phys(omap_secondary_startup)); |
Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 89 | smp_wmb(); |
| 90 | |
| 91 | /* |
| 92 | * Send a 'sev' to wake the secondary core from WFE. |
Santosh Shilimkar | 942e2c9 | 2009-12-11 16:16:35 -0800 | [diff] [blame] | 93 | * Drain the outstanding writes to memory |
Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 94 | */ |
Tony Lindgren | a4192d3 | 2010-08-16 09:21:20 +0300 | [diff] [blame] | 95 | dsb_sev(); |
Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 96 | mb(); |
| 97 | } |
| 98 | |
| 99 | /* |
| 100 | * Initialise the CPU possible map early - this describes the CPUs |
| 101 | * which may be present or become present in the system. |
| 102 | */ |
| 103 | void __init smp_init_cpus(void) |
| 104 | { |
Tony Lindgren | e4e7a13 | 2009-10-19 15:25:26 -0700 | [diff] [blame] | 105 | unsigned int i, ncores; |
| 106 | |
| 107 | /* Never released */ |
| 108 | scu_base = ioremap(OMAP44XX_SCU_BASE, SZ_256); |
| 109 | BUG_ON(!scu_base); |
| 110 | |
Russell King | fd778f0 | 2010-12-02 18:09:37 +0000 | [diff] [blame^] | 111 | ncores = scu_get_core_count(scu_base); |
Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 112 | |
Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 113 | /* sanity check */ |
Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 114 | if (ncores > NR_CPUS) { |
| 115 | printk(KERN_WARNING |
| 116 | "OMAP4: no. of cores (%d) greater than configured " |
| 117 | "maximum of %d - clipping\n", |
| 118 | ncores, NR_CPUS); |
| 119 | ncores = NR_CPUS; |
| 120 | } |
Russell King | bbc3d14 | 2010-12-03 10:42:58 +0000 | [diff] [blame] | 121 | |
| 122 | for (i = 0; i < ncores; i++) |
| 123 | set_cpu_possible(i, true); |
| 124 | } |
| 125 | |
| 126 | void __init smp_prepare_cpus(unsigned int max_cpus) |
| 127 | { |
| 128 | unsigned int ncores = num_possible_cpus(); |
| 129 | unsigned int cpu = smp_processor_id(); |
| 130 | int i; |
| 131 | |
Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 132 | smp_store_cpu_info(cpu); |
| 133 | |
| 134 | /* |
| 135 | * are we trying to boot more cores than exist? |
| 136 | */ |
| 137 | if (max_cpus > ncores) |
| 138 | max_cpus = ncores; |
| 139 | |
| 140 | /* |
| 141 | * Initialise the present map, which describes the set of CPUs |
| 142 | * actually populated at the present time. |
| 143 | */ |
| 144 | for (i = 0; i < max_cpus; i++) |
| 145 | set_cpu_present(i, true); |
| 146 | |
Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 147 | if (max_cpus > 1) { |
| 148 | /* |
| 149 | * Enable the local timer or broadcast device for the |
| 150 | * boot CPU, but only if we have more than one CPU. |
| 151 | */ |
| 152 | percpu_timer_setup(); |
| 153 | |
| 154 | /* |
| 155 | * Initialise the SCU and wake up the secondary core using |
| 156 | * wakeup_secondary(). |
| 157 | */ |
| 158 | scu_enable(scu_base); |
| 159 | wakeup_secondary(); |
| 160 | } |
| 161 | } |