Taniya Das | 137dc8e | 2011-12-02 14:50:00 +0530 | [diff] [blame] | 1 | /* Copyright (c) 2012, Code Aurora Forum. All rights reserved. |
| 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | */ |
| 12 | |
| 13 | #include <linux/init.h> |
| 14 | #include <linux/errno.h> |
| 15 | #include <linux/delay.h> |
| 16 | #include <linux/device.h> |
| 17 | #include <linux/jiffies.h> |
| 18 | #include <linux/smp.h> |
| 19 | #include <linux/io.h> |
| 20 | |
| 21 | #include <asm/cacheflush.h> |
| 22 | #include <asm/hardware/gic.h> |
| 23 | #include <asm/hardware/cache-l2x0.h> |
| 24 | #include <asm/smp_scu.h> |
| 25 | #include <asm/unified.h> |
| 26 | #include <mach/msm_iomap.h> |
| 27 | #include <mach/smp.h> |
| 28 | #include "pm.h" |
| 29 | |
| 30 | #define MSM_CORE1_RESET 0xA8600590 |
Taniya Das | 63da646 | 2012-02-27 17:22:11 +0530 | [diff] [blame] | 31 | #define MSM_CORE1_STATUS_MSK 0x02800000 |
| 32 | |
Taniya Das | 137dc8e | 2011-12-02 14:50:00 +0530 | [diff] [blame] | 33 | /* |
| 34 | * control for which core is the next to come out of the secondary |
| 35 | * boot "holding pen" |
| 36 | */ |
| 37 | int pen_release = -1; |
| 38 | |
| 39 | static bool cold_boot_done; |
| 40 | |
| 41 | static uint32_t *msm8625_boot_vector; |
| 42 | |
| 43 | /* |
| 44 | * Write pen_release in a way that is guaranteed to be visible to all |
| 45 | * observers, irrespective of whether they're taking part in coherency |
| 46 | * or not. This is necessary for the hotplug code to work reliably. |
| 47 | */ |
| 48 | static void __cpuinit write_pen_release(int val) |
| 49 | { |
| 50 | pen_release = val; |
| 51 | smp_wmb(); |
| 52 | __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release)); |
| 53 | outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1)); |
| 54 | } |
| 55 | |
| 56 | static void __iomem *scu_base_addr(void) |
| 57 | { |
| 58 | return MSM_SCU_BASE; |
| 59 | } |
| 60 | |
| 61 | static DEFINE_SPINLOCK(boot_lock); |
| 62 | |
| 63 | void __cpuinit platform_secondary_init(unsigned int cpu) |
| 64 | { |
Murali Nalajala | a7efba1 | 2012-02-23 18:13:52 +0530 | [diff] [blame] | 65 | pr_debug("CPU%u: Booted secondary processor\n", cpu); |
| 66 | |
| 67 | WARN_ON(msm_platform_secondary_init(cpu)); |
| 68 | |
Taniya Das | 137dc8e | 2011-12-02 14:50:00 +0530 | [diff] [blame] | 69 | /* |
| 70 | * if any interrupts are already enabled for the primary |
| 71 | * core (e.g. timer irq), then they will not have been enabled |
| 72 | * for us: do so |
| 73 | */ |
| 74 | gic_secondary_init(0); |
| 75 | |
| 76 | /* |
| 77 | * let the primary processor know we're out of the |
| 78 | * pen, then head off into the C entry point |
| 79 | */ |
| 80 | write_pen_release(-1); |
| 81 | |
| 82 | /* |
| 83 | * Synchronise with the boot thread. |
| 84 | */ |
| 85 | spin_lock(&boot_lock); |
| 86 | spin_unlock(&boot_lock); |
| 87 | } |
| 88 | |
Taniya Das | 63da646 | 2012-02-27 17:22:11 +0530 | [diff] [blame] | 89 | static int __cpuinit msm8625_release_secondary(void) |
| 90 | { |
| 91 | void __iomem *base_ptr; |
| 92 | int value = 0; |
| 93 | unsigned long timeout; |
| 94 | |
| 95 | /* |
| 96 | * loop to ensure that the GHS_STATUS_CORE1 bit in the |
| 97 | * MPA5_STATUS_REG(0x3c) is set. The timeout for the while |
| 98 | * loop can be set as 20us as of now |
| 99 | */ |
| 100 | timeout = jiffies + usecs_to_jiffies(20); |
| 101 | while (time_before(jiffies, timeout)) { |
| 102 | value = __raw_readl(MSM_CFG_CTL_BASE + 0x3c); |
| 103 | if ((value & MSM_CORE1_STATUS_MSK) == |
| 104 | MSM_CORE1_STATUS_MSK) |
| 105 | break; |
| 106 | udelay(1); |
| 107 | } |
| 108 | |
| 109 | if (!value) { |
| 110 | pr_err("Core 1 cannot be brought out of Reset!!!\n"); |
| 111 | return -ENODEV; |
| 112 | } |
| 113 | |
| 114 | base_ptr = ioremap_nocache(MSM_CORE1_RESET, SZ_4); |
| 115 | if (!base_ptr) |
| 116 | return -ENODEV; |
| 117 | /* Reset core 1 out of reset */ |
| 118 | __raw_writel(0x0, base_ptr); |
| 119 | mb(); |
| 120 | |
| 121 | iounmap(base_ptr); |
| 122 | |
| 123 | return 0; |
| 124 | } |
| 125 | |
Taniya Das | 137dc8e | 2011-12-02 14:50:00 +0530 | [diff] [blame] | 126 | int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) |
| 127 | { |
| 128 | unsigned long timeout; |
Taniya Das | 137dc8e | 2011-12-02 14:50:00 +0530 | [diff] [blame] | 129 | |
| 130 | if (cold_boot_done == false) { |
Taniya Das | 63da646 | 2012-02-27 17:22:11 +0530 | [diff] [blame] | 131 | if (msm8625_release_secondary()) { |
| 132 | pr_err("Failed to release secondary core\n"); |
Taniya Das | 137dc8e | 2011-12-02 14:50:00 +0530 | [diff] [blame] | 133 | return -ENODEV; |
Taniya Das | 63da646 | 2012-02-27 17:22:11 +0530 | [diff] [blame] | 134 | } |
Taniya Das | 137dc8e | 2011-12-02 14:50:00 +0530 | [diff] [blame] | 135 | cold_boot_done = true; |
Taniya Das | 137dc8e | 2011-12-02 14:50:00 +0530 | [diff] [blame] | 136 | } |
| 137 | |
| 138 | /* |
| 139 | * Set synchronisation state between this boot processor |
| 140 | * and the secondary one |
| 141 | */ |
| 142 | spin_lock(&boot_lock); |
| 143 | |
| 144 | /* |
| 145 | * This is really belt and braces; we hold unintended secondary |
| 146 | * CPUs in the holding pen until we're ready for them. However, |
| 147 | * since we haven't sent them a soft interrupt, they shouldn't |
| 148 | * be there. |
| 149 | */ |
| 150 | write_pen_release(cpu); |
| 151 | |
| 152 | /* |
| 153 | * Send the secondary CPU a soft interrupt, thereby causing |
| 154 | * the boot monitor to read the system wide flags register, |
| 155 | * and branch to the address found there. |
| 156 | */ |
| 157 | gic_raise_softirq(cpumask_of(cpu), 1); |
| 158 | |
| 159 | timeout = jiffies + (1 * HZ); |
| 160 | while (time_before(jiffies, timeout)) { |
| 161 | smp_rmb(); |
| 162 | if (pen_release == -1) |
| 163 | break; |
| 164 | |
| 165 | udelay(10); |
| 166 | } |
| 167 | |
| 168 | /* |
| 169 | * now the secondary core is starting up let it run its |
| 170 | * calibrations, then wait for it to finish |
| 171 | */ |
| 172 | spin_unlock(&boot_lock); |
| 173 | |
| 174 | return 0; |
| 175 | } |
| 176 | |
| 177 | /* |
| 178 | * Initialise the CPU possible map early - this describes the CPUs |
| 179 | * which may be present or become present in the system. |
| 180 | */ |
| 181 | void __init smp_init_cpus(void) |
| 182 | { |
| 183 | void __iomem *scu_base = scu_base_addr(); |
| 184 | |
| 185 | unsigned int i, ncores; |
| 186 | |
| 187 | ncores = scu_base ? scu_get_core_count(scu_base) : 1; |
| 188 | |
| 189 | for (i = 0; i < ncores; i++) |
| 190 | set_cpu_possible(i, true); |
| 191 | |
| 192 | set_smp_cross_call(gic_raise_softirq); |
| 193 | } |
| 194 | |
| 195 | static void __init msm8625_boot_vector_init(uint32_t *boot_vector, |
| 196 | unsigned long entry) |
| 197 | { |
| 198 | if (!boot_vector) |
| 199 | return; |
| 200 | msm8625_boot_vector = boot_vector; |
| 201 | |
| 202 | msm8625_boot_vector[0] = 0xE51FF004; /* ldr pc, 4 */ |
| 203 | msm8625_boot_vector[1] = entry; |
| 204 | } |
| 205 | |
| 206 | void __init platform_smp_prepare_cpus(unsigned int max_cpus) |
| 207 | { |
| 208 | int i, value; |
Taniya Das | fe04d4f | 2012-03-14 11:13:21 +0530 | [diff] [blame^] | 209 | void __iomem *second_ptr; |
Taniya Das | 137dc8e | 2011-12-02 14:50:00 +0530 | [diff] [blame] | 210 | |
| 211 | /* |
| 212 | * Initialise the present map, which describes the set of CPUs |
| 213 | * actually populated at the present time. |
| 214 | */ |
| 215 | for (i = 0; i < max_cpus; i++) |
| 216 | set_cpu_present(i, true); |
| 217 | |
| 218 | scu_enable(scu_base_addr()); |
| 219 | |
| 220 | /* |
| 221 | * Write the address of secondary startup into the |
| 222 | * boot remapper register. The secondary CPU branches to this address. |
| 223 | */ |
Taniya Das | fe04d4f | 2012-03-14 11:13:21 +0530 | [diff] [blame^] | 224 | __raw_writel(MSM8625_SECONDARY_PHYS, (MSM_CFG_CTL_BASE + 0x34)); |
Taniya Das | 137dc8e | 2011-12-02 14:50:00 +0530 | [diff] [blame] | 225 | mb(); |
| 226 | |
Taniya Das | fe04d4f | 2012-03-14 11:13:21 +0530 | [diff] [blame^] | 227 | second_ptr = ioremap_nocache(MSM8625_SECONDARY_PHYS, SZ_8); |
| 228 | if (!second_ptr) { |
| 229 | pr_err("failed to ioremap for secondary core\n"); |
| 230 | return; |
| 231 | } |
Taniya Das | 137dc8e | 2011-12-02 14:50:00 +0530 | [diff] [blame] | 232 | |
Taniya Das | fe04d4f | 2012-03-14 11:13:21 +0530 | [diff] [blame^] | 233 | msm8625_boot_vector_init(second_ptr, |
| 234 | virt_to_phys(msm_secondary_startup)); |
| 235 | iounmap(second_ptr); |
Taniya Das | 137dc8e | 2011-12-02 14:50:00 +0530 | [diff] [blame] | 236 | |
| 237 | /* Enable boot remapper address: bit 26 for core1 */ |
| 238 | value = __raw_readl(MSM_CFG_CTL_BASE + 0x30); |
| 239 | __raw_writel(value | (0x4 << 24), MSM_CFG_CTL_BASE + 0x30) ; |
| 240 | mb(); |
| 241 | } |