commit 0f9b9c508814a62c6e21c6a06cfe4de39b5036c0
author Ian Rogers <irogers@google.com> Mon Jun 09 01:32:12 2014 -0700
committer Ian Rogers <irogers@google.com> Mon Jun 09 21:42:22 2014 -0700
tree 2e7ea538fa80ba4186239e79842bcf9cf3ea61df
parent b14f2e0f98ebe08585058826084a586d23698357

Tidy up x86 assembler and fix byte register encoding.

Also fix reg storage int size issues.
Also fix bad use of byte registers in GenInlinedCas.

Change-Id: Id47424f36f9000e051110553e0b51816910e2fe8

compiler/dex/quick/x86/target_x86.cc

diff --git a/compiler/dex/quick/x86/target_x86.cc b/compiler/dex/quick/x86/target_x86.cc
index 1ac15a2..4372739 100644
--- a/compiler/dex/quick/x86/target_x86.cc
+++ b/compiler/dex/quick/x86/target_x86.cc
@@ -530,8 +530,8 @@
     switch (opcode) {
       case kX86LockCmpxchgMR:
       case kX86LockCmpxchgAR:
-      case kX86LockCmpxchg8bM:
-      case kX86LockCmpxchg8bA:
+      case kX86LockCmpxchg64M:
+      case kX86LockCmpxchg64A:
       case kX86XchgMR:
       case kX86Mfence:
         // Atomic memory instructions provide full barrier.