Merge "Make subs alter flags when rn is an immediate"
diff --git a/compiler/utils/arm/assembler_thumb2.cc b/compiler/utils/arm/assembler_thumb2.cc
index eb5b454..e8eb019 100644
--- a/compiler/utils/arm/assembler_thumb2.cc
+++ b/compiler/utils/arm/assembler_thumb2.cc
@@ -826,7 +826,9 @@
// Check special cases.
if ((opcode == SUB || opcode == ADD) && (so.GetImmediate() < (1u << 12))) {
if (opcode == SUB) {
- thumb_opcode = 5U /* 0b0101 */;
+ if (!set_cc) {
+ thumb_opcode = 5U /* 0b0101 */;
+ }
} else {
thumb_opcode = 0;
}
@@ -836,13 +838,14 @@
uint32_t imm3 = (imm >> 8) & 7U /* 0b111 */;
uint32_t imm8 = imm & 0xff;
- encoding = B31 | B30 | B29 | B28 | B25 |
- thumb_opcode << 21 |
- rn << 16 |
- rd << 8 |
- i << 26 |
- imm3 << 12 |
- imm8;
+ encoding = B31 | B30 | B29 | B28 |
+ (set_cc ? B20 : B25) |
+ thumb_opcode << 21 |
+ rn << 16 |
+ rd << 8 |
+ i << 26 |
+ imm3 << 12 |
+ imm8;
} else {
// Modified immediate.
uint32_t imm = ModifiedImmediate(so.encodingThumb());
@@ -858,13 +861,13 @@
imm;
}
} else if (so.IsRegister()) {
- // Register (possibly shifted)
- encoding = B31 | B30 | B29 | B27 | B25 |
- thumb_opcode << 21 |
- (set_cc ? 1 : 0) << 20 |
- rn << 16 |
- rd << 8 |
- so.encodingThumb();
+ // Register (possibly shifted)
+ encoding = B31 | B30 | B29 | B27 | B25 |
+ thumb_opcode << 21 |
+ (set_cc ? 1 : 0) << 20 |
+ rn << 16 |
+ rd << 8 |
+ so.encodingThumb();
}
Emit32(encoding);
}
diff --git a/compiler/utils/arm/assembler_thumb2_test.cc b/compiler/utils/arm/assembler_thumb2_test.cc
index ebea9d4..d802852 100644
--- a/compiler/utils/arm/assembler_thumb2_test.cc
+++ b/compiler/utils/arm/assembler_thumb2_test.cc
@@ -227,4 +227,14 @@
DriverStr(expected, "abs");
}
+TEST_F(AssemblerThumb2Test, sub) {
+ __ subs(arm::R1, arm::R0, arm::ShifterOperand(42));
+ __ sub(arm::R1, arm::R0, arm::ShifterOperand(42));
+
+ const char* expected =
+ "subs r1, r0, #42\n"
+ "subw r1, r0, #42\n";
+ DriverStr(expected, "sub");
+}
+
} // namespace art