tree 7b7764521a0b67392e023f1efacc0dbae64fe675
parent 89ae0f42e38a2f985ac404830f2a05fecf9547e2
author xueliang.zhong <xueliang.zhong@linaro.org> 1494265000 +0100
committer xueliang.zhong <xueliang.zhong@linaro.org> 1498836774 +0100

Disambiguate memory accesses in instruction scheduling

Based on aliasing information from heap location collector,
instruction scheduling can further eliminate side-effect
dependencies between memory accesses to different locations,
and perform better scheduling on memory loads and stores.

Performance improvements of this CL, measured on Cortex-A53:
| benchmarks     | ARM64 backend | ARM backend |
|----------------+---------------|-------------|
| algorithm      |         0.1 % |       0.1 % |
| benchmarksgame |         0.5 % |       1.3 % |
| caffeinemark   |         0.0 % |       0.0 % |
| math           |         5.1 % |       5.0 % |
| stanford       |         1.1 % |       0.6 % |
| testsimd       |         0.4 % |       0.1 % |

Compilation time impact is negligible, because this
heap location load store analysis is only performed
on loop basic blocks that get instruction scheduled.

Test: m test-art-host
Test: m test-art-target
Test: 706-checker-scheduler

Change-Id: I43d7003c09bfab9d3a1814715df666aea9a7360b