More target-independence
Continuing to move target-specific code from the Arm
code generator into the independent realm. This will be
done in multiple small steps.
In this CL, the focus is on unifying the LIR data structure and
various enums that don't really need to be target specific. Also
creates two new shared source files: GenCommon.cc (to hold
top-level code generation functions) and GenInvoke.cc (which
is likely to be shared only by the Arm and Mips targets).
Also added is a makefile hack to build for Mips (which we'll
eventually remove when the compiler support multiple targets
via the command line) and various minor cleanups.
Overall, this CL moves more than 3,000 lines of code from
target dependent to target independent.
Change-Id: I431ca4ae728100ed7d0e9d83a966a3f789f731b1
diff --git a/src/compiler/codegen/mips/Mips32/Factory.cc b/src/compiler/codegen/mips/Mips32/Factory.cc
index ffbb223..f76adff 100644
--- a/src/compiler/codegen/mips/Mips32/Factory.cc
+++ b/src/compiler/codegen/mips/Mips32/Factory.cc
@@ -38,21 +38,17 @@
r_F8, r_F9, r_F10, r_F11, r_F12, r_F13, r_F14, r_F15};
#endif
-static void storePair(CompilationUnit *cUnit, int base, int lowReg,
- int highReg);
-static void loadPair(CompilationUnit *cUnit, int base, int lowReg, int highReg);
-static MipsLIR *loadWordDisp(CompilationUnit *cUnit, int rBase, int displacement,
- int rDest);
-static MipsLIR *storeWordDisp(CompilationUnit *cUnit, int rBase,
- int displacement, int rSrc);
-static MipsLIR *genRegRegCheck(CompilationUnit *cUnit,
- MipsConditionCode cond,
- int reg1, int reg2, int dOffset,
- MipsLIR *pcrLabel);
-static MipsLIR *loadConstant(CompilationUnit *cUnit, int rDest, int value);
+void storePair(CompilationUnit *cUnit, int base, int lowReg,
+ int highReg);
+void loadPair(CompilationUnit *cUnit, int base, int lowReg, int highReg);
+MipsLIR *loadWordDisp(CompilationUnit *cUnit, int rBase, int displacement,
+ int rDest);
+MipsLIR *storeWordDisp(CompilationUnit *cUnit, int rBase,
+ int displacement, int rSrc);
+MipsLIR *loadConstant(CompilationUnit *cUnit, int rDest, int value);
#ifdef __mips_hard_float
-static MipsLIR *fpRegCopy(CompilationUnit *cUnit, int rDest, int rSrc)
+MipsLIR *fpRegCopy(CompilationUnit *cUnit, int rDest, int rSrc)
{
MipsLIR* res = (MipsLIR *) oatNew(cUnit, sizeof(MipsLIR), true, kAllocLIR);
res->operands[0] = rDest;
@@ -94,8 +90,8 @@
* 1) rDest is freshly returned from oatAllocTemp or
* 2) The codegen is under fixed register usage
*/
-static MipsLIR *loadConstantNoClobber(CompilationUnit *cUnit, int rDest,
- int value)
+MipsLIR *loadConstantNoClobber(CompilationUnit *cUnit, int rDest,
+ int value)
{
MipsLIR *res;
@@ -135,7 +131,7 @@
* Load an immediate value into a fixed or temp register. Target
* register is clobbered, and marked inUse.
*/
-static MipsLIR *loadConstant(CompilationUnit *cUnit, int rDest, int value)
+MipsLIR *loadConstant(CompilationUnit *cUnit, int rDest, int value)
{
if (oatIsTemp(cUnit, rDest)) {
oatClobber(cUnit, rDest);
@@ -144,24 +140,7 @@
return loadConstantNoClobber(cUnit, rDest, value);
}
-/*
- * Load a class pointer value into a fixed or temp register. Target
- * register is clobbered, and marked inUse.
- */
-static MipsLIR *loadClassPointer(CompilationUnit *cUnit, int rDest, int value)
-{
- MipsLIR *res;
- if (oatIsTemp(cUnit, rDest)) {
- oatClobber(cUnit, rDest);
- oatMarkInUse(cUnit, rDest);
- }
- res = newLIR2(cUnit, kMipsLui, rDest, value>>16);
- if (value & 0xffff)
- newLIR3(cUnit, kMipsOri, rDest, rDest, value);
- return res;
-}
-
-static MipsLIR *opNone(CompilationUnit *cUnit, OpKind op)
+MipsLIR *opNone(CompilationUnit *cUnit, OpKind op)
{
MipsLIR *res;
MipsOpCode opcode = kMipsNop;
@@ -176,7 +155,27 @@
return res;
}
-static MipsLIR *opCompareBranch(CompilationUnit *cUnit, MipsOpCode opc, int rs, int rt)
+
+MipsLIR *opCmpBranchCC(CompilationUnit *cUnit, MipsConditionCode cc,
+ int rs, int rt)
+{
+ UNIMPLEMENTED(FATAL);
+ return 0;
+}
+MipsLIR *opCmpImmBranchCC(CompilationUnit *cUnit, MipsConditionCode cc,
+ int rs, int immVal)
+{
+ UNIMPLEMENTED(FATAL);
+ return 0;
+}
+MipsLIR *opCmpImmBranch(CompilationUnit *cUnit, MipsOpCode cc,
+ int rs, int immVal)
+{
+ UNIMPLEMENTED(FATAL);
+ return 0;
+}
+
+MipsLIR *opCmpBranch(CompilationUnit *cUnit, MipsOpCode opc, int rs, int rt)
{
MipsLIR *res;
if (rt < 0) {
@@ -189,9 +188,9 @@
return res;
}
-static MipsLIR *loadMultiple(CompilationUnit *cUnit, int rBase, int rMask);
+MipsLIR *loadMultiple(CompilationUnit *cUnit, int rBase, int rMask);
-static MipsLIR *opReg(CompilationUnit *cUnit, OpKind op, int rDestSrc)
+MipsLIR *opReg(CompilationUnit *cUnit, OpKind op, int rDestSrc)
{
MipsOpCode opcode = kMipsNop;
switch (op) {
@@ -204,8 +203,8 @@
return newLIR2(cUnit, opcode, r_RA, rDestSrc);
}
-static MipsLIR *opRegRegImm(CompilationUnit *cUnit, OpKind op, int rDest,
- int rSrc1, int value);
+MipsLIR *opRegRegImm(CompilationUnit *cUnit, OpKind op, int rDest,
+ int rSrc1, int value);
MipsLIR *opRegImm(CompilationUnit *cUnit, OpKind op, int rDestSrc1,
int value)
{
@@ -238,7 +237,7 @@
return res;
}
-static MipsLIR *opRegRegReg(CompilationUnit *cUnit, OpKind op, int rDest,
+MipsLIR *opRegRegReg(CompilationUnit *cUnit, OpKind op, int rDest,
int rSrc1, int rSrc2)
{
MipsOpCode opcode = kMipsNop;
@@ -277,7 +276,7 @@
return newLIR3(cUnit, opcode, rDest, rSrc1, rSrc2);
}
-static MipsLIR *opRegRegImm(CompilationUnit *cUnit, OpKind op, int rDest,
+MipsLIR *opRegRegImm(CompilationUnit *cUnit, OpKind op, int rDest,
int rSrc1, int value)
{
MipsLIR *res;
@@ -412,7 +411,7 @@
return newLIR2(cUnit, opcode, rDestSrc1, rSrc2);
}
-static MipsLIR *loadConstantValueWide(CompilationUnit *cUnit, int rDestLo,
+MipsLIR *loadConstantValueWide(CompilationUnit *cUnit, int rDestLo,
int rDestHi, int valLo, int valHi)
{
MipsLIR *res;
@@ -422,7 +421,7 @@
}
/* Load value from base + scaled index. */
-static MipsLIR *loadBaseIndexed(CompilationUnit *cUnit, int rBase,
+MipsLIR *loadBaseIndexed(CompilationUnit *cUnit, int rBase,
int rIndex, int rDest, int scale, OpSize size)
{
MipsLIR *first = NULL;
@@ -479,7 +478,7 @@
}
/* store value base base + scaled index. */
-static MipsLIR *storeBaseIndexed(CompilationUnit *cUnit, int rBase,
+MipsLIR *storeBaseIndexed(CompilationUnit *cUnit, int rBase,
int rIndex, int rSrc, int scale, OpSize size)
{
MipsLIR *first = NULL;
@@ -531,7 +530,7 @@
return first;
}
-static MipsLIR *loadMultiple(CompilationUnit *cUnit, int rBase, int rMask)
+MipsLIR *loadMultiple(CompilationUnit *cUnit, int rBase, int rMask)
{
int i;
int loadCnt = 0;
@@ -553,7 +552,7 @@
return res; /* NULL always returned which should be ok since no callers use it */
}
-static MipsLIR *storeMultiple(CompilationUnit *cUnit, int rBase, int rMask)
+MipsLIR *storeMultiple(CompilationUnit *cUnit, int rBase, int rMask)
{
int i;
int storeCnt = 0;
@@ -575,7 +574,7 @@
return res; /* NULL always returned which should be ok since no callers use it */
}
-static MipsLIR *loadBaseDispBody(CompilationUnit *cUnit, MIR *mir, int rBase,
+MipsLIR *loadBaseDispBody(CompilationUnit *cUnit, MIR *mir, int rBase,
int displacement, int rDest, int rDestHi,
OpSize size, int sReg)
/*
@@ -681,7 +680,7 @@
return load;
}
-static MipsLIR *loadBaseDisp(CompilationUnit *cUnit, MIR *mir, int rBase,
+MipsLIR *loadBaseDisp(CompilationUnit *cUnit, MIR *mir, int rBase,
int displacement, int rDest, OpSize size,
int sReg)
{
@@ -689,15 +688,15 @@
size, sReg);
}
-static MipsLIR *loadBaseDispWide(CompilationUnit *cUnit, MIR *mir, int rBase,
- int displacement, int rDestLo, int rDestHi,
+MipsLIR *loadBaseDispWide(CompilationUnit *cUnit, MIR *mir, int rBase,
+ int displacement, int rDestLo, int rDestHi,
int sReg)
{
return loadBaseDispBody(cUnit, mir, rBase, displacement, rDestLo, rDestHi,
kLong, sReg);
}
-static MipsLIR *storeBaseDispBody(CompilationUnit *cUnit, int rBase,
+MipsLIR *storeBaseDispBody(CompilationUnit *cUnit, int rBase,
int displacement, int rSrc, int rSrcHi,
OpSize size)
{
@@ -786,31 +785,25 @@
return res;
}
-static MipsLIR *storeBaseDisp(CompilationUnit *cUnit, int rBase,
- int displacement, int rSrc, OpSize size)
+MipsLIR *storeBaseDisp(CompilationUnit *cUnit, int rBase,
+ int displacement, int rSrc, OpSize size)
{
return storeBaseDispBody(cUnit, rBase, displacement, rSrc, -1, size);
}
-static MipsLIR *storeBaseDispWide(CompilationUnit *cUnit, int rBase,
- int displacement, int rSrcLo, int rSrcHi)
+MipsLIR *storeBaseDispWide(CompilationUnit *cUnit, int rBase,
+ int displacement, int rSrcLo, int rSrcHi)
{
return storeBaseDispBody(cUnit, rBase, displacement, rSrcLo, rSrcHi, kLong);
}
-static void storePair(CompilationUnit *cUnit, int base, int lowReg, int highReg)
-{
- storeWordDisp(cUnit, base, LOWORD_OFFSET, lowReg);
- storeWordDisp(cUnit, base, HIWORD_OFFSET, highReg);
-}
-
-static void loadPair(CompilationUnit *cUnit, int base, int lowReg, int highReg)
+void loadPair(CompilationUnit *cUnit, int base, int lowReg, int highReg)
{
loadWordDisp(cUnit, base, LOWORD_OFFSET , lowReg);
loadWordDisp(cUnit, base, HIWORD_OFFSET , highReg);
}
-static MipsLIR* genRegCopyNoInsert(CompilationUnit *cUnit, int rDest, int rSrc)
+MipsLIR* genRegCopyNoInsert(CompilationUnit *cUnit, int rDest, int rSrc)
{
MipsLIR* res;
MipsOpCode opcode;
@@ -831,14 +824,14 @@
return res;
}
-static MipsLIR* genRegCopy(CompilationUnit *cUnit, int rDest, int rSrc)
+MipsLIR* genRegCopy(CompilationUnit *cUnit, int rDest, int rSrc)
{
MipsLIR *res = genRegCopyNoInsert(cUnit, rDest, rSrc);
oatAppendLIR(cUnit, (LIR*)res);
return res;
}
-static void genRegCopyWide(CompilationUnit *cUnit, int destLo, int destHi,
+void genRegCopyWide(CompilationUnit *cUnit, int destLo, int destHi,
int srcLo, int srcHi)
{
#ifdef __mips_hard_float
@@ -881,10 +874,10 @@
#endif
}
-static inline MipsLIR *genRegImmCheck(CompilationUnit *cUnit,
- MipsConditionCode cond, int reg,
- int checkValue, int dOffset,
- MipsLIR *pcrLabel)
+inline MipsLIR *genRegImmCheck(CompilationUnit *cUnit,
+ MipsConditionCode cond, int reg,
+ int checkValue, int dOffset,
+ MipsLIR *pcrLabel)
{
MipsLIR *branch = NULL;
diff --git a/src/compiler/codegen/mips/Mips32/Gen.cc b/src/compiler/codegen/mips/Mips32/Gen.cc
index f49cdab..8801692 100644
--- a/src/compiler/codegen/mips/Mips32/Gen.cc
+++ b/src/compiler/codegen/mips/Mips32/Gen.cc
@@ -62,10 +62,192 @@
bool genArithOpIntLit(CompilationUnit* cUnit, MIR* mir,
RegLocation rlDest, RegLocation rlSrc,
int lit) { return 0; }
+void oatArchDump(void) {};
+void genDebuggerUpdate(CompilationUnit* cUnit, int32_t offset) {};
+STATIC bool genConversionCall(CompilationUnit* cUnit, MIR* mir, int funcOffset,
+ int srcSize, int tgtSize)
+{
+ UNIMPLEMENTED(FATAL) << "Need Mips implementation";
+ return 0;
+#if 0
+ /*
+ * Don't optimize the register usage since it calls out to support
+ * functions
+ */
+ RegLocation rlSrc;
+ RegLocation rlDest;
+ oatFlushAllRegs(cUnit); /* Send everything to home location */
+ loadWordDisp(cUnit, rSELF, funcOffset, rLR);
+ if (srcSize == 1) {
+ rlSrc = oatGetSrc(cUnit, mir, 0);
+ loadValueDirectFixed(cUnit, rlSrc, r0);
+ } else {
+ rlSrc = oatGetSrcWide(cUnit, mir, 0, 1);
+ loadValueDirectWideFixed(cUnit, rlSrc, r0, r1);
+ }
+ callRuntimeHelper(cUnit, rLR);
+ if (tgtSize == 1) {
+ RegLocation rlResult;
+ rlDest = oatGetDest(cUnit, mir, 0);
+ rlResult = oatGetReturn(cUnit);
+ storeValue(cUnit, rlDest, rlResult);
+ } else {
+ RegLocation rlResult;
+ rlDest = oatGetDestWide(cUnit, mir, 0, 1);
+ rlResult = oatGetReturnWide(cUnit);
+ storeValueWide(cUnit, rlDest, rlResult);
+ }
+ return false;
+#endif
+}
+
+bool genArithOpFloatPortable(CompilationUnit* cUnit, MIR* mir,
+ RegLocation rlDest, RegLocation rlSrc1,
+ RegLocation rlSrc2)
+{
+ UNIMPLEMENTED(FATAL) << "Need Mips implementation";
+ return 0;
+#if 0
+ RegLocation rlResult;
+ int funcOffset;
+
+ switch (mir->dalvikInsn.opcode) {
+ case OP_ADD_FLOAT_2ADDR:
+ case OP_ADD_FLOAT:
+ funcOffset = OFFSETOF_MEMBER(Thread, pFadd);
+ break;
+ case OP_SUB_FLOAT_2ADDR:
+ case OP_SUB_FLOAT:
+ funcOffset = OFFSETOF_MEMBER(Thread, pFsub);
+ break;
+ case OP_DIV_FLOAT_2ADDR:
+ case OP_DIV_FLOAT:
+ funcOffset = OFFSETOF_MEMBER(Thread, pFdiv);
+ break;
+ case OP_MUL_FLOAT_2ADDR:
+ case OP_MUL_FLOAT:
+ funcOffset = OFFSETOF_MEMBER(Thread, pFmul);
+ break;
+ case OP_REM_FLOAT_2ADDR:
+ case OP_REM_FLOAT:
+ funcOffset = OFFSETOF_MEMBER(Thread, pFmodf);
+ break;
+ case OP_NEG_FLOAT: {
+ genNegFloat(cUnit, rlDest, rlSrc1);
+ return false;
+ }
+ default:
+ return true;
+ }
+ oatFlushAllRegs(cUnit); /* Send everything to home location */
+ loadWordDisp(cUnit, rSELF, funcOffset, rLR);
+ loadValueDirectFixed(cUnit, rlSrc1, r0);
+ loadValueDirectFixed(cUnit, rlSrc2, r1);
+ callRuntimeHelper(cUnit, rLR);
+ rlResult = oatGetReturn(cUnit);
+ storeValue(cUnit, rlDest, rlResult);
+ return false;
+#endif
+}
+
+bool genArithOpDoublePortable(CompilationUnit* cUnit, MIR* mir,
+ RegLocation rlDest, RegLocation rlSrc1,
+ RegLocation rlSrc2)
+{
+ UNIMPLEMENTED(FATAL) << "Need Mips implementation";
+ return 0;
+#if 0
+ RegLocation rlResult;
+ int funcOffset;
+
+ switch (mir->dalvikInsn.opcode) {
+ case OP_ADD_DOUBLE_2ADDR:
+ case OP_ADD_DOUBLE:
+ funcOffset = OFFSETOF_MEMBER(Thread, pDadd);
+ break;
+ case OP_SUB_DOUBLE_2ADDR:
+ case OP_SUB_DOUBLE:
+ funcOffset = OFFSETOF_MEMBER(Thread, pDsub);
+ break;
+ case OP_DIV_DOUBLE_2ADDR:
+ case OP_DIV_DOUBLE:
+ funcOffset = OFFSETOF_MEMBER(Thread, pDdiv);
+ break;
+ case OP_MUL_DOUBLE_2ADDR:
+ case OP_MUL_DOUBLE:
+ funcOffset = OFFSETOF_MEMBER(Thread, pDmul);
+ break;
+ case OP_REM_DOUBLE_2ADDR:
+ case OP_REM_DOUBLE:
+ funcOffset = OFFSETOF_MEMBER(Thread, pFmod);
+ break;
+ case OP_NEG_DOUBLE: {
+ genNegDouble(cUnit, rlDest, rlSrc1);
+ return false;
+ }
+ default:
+ return true;
+ }
+ oatFlushAllRegs(cUnit); /* Send everything to home location */
+ loadWordDisp(cUnit, rSELF, funcOffset, rLR);
+ loadValueDirectWideFixed(cUnit, rlSrc1, r0, r1);
+ loadValueDirectWideFixed(cUnit, rlSrc2, r2, r3);
+ callRuntimeHelper(cUnit, rLR);
+ rlResult = oatGetReturnWide(cUnit);
+ storeValueWide(cUnit, rlDest, rlResult);
+ return false;
+#endif
+}
+
+bool genConversionPortable(CompilationUnit* cUnit, MIR* mir)
+{
+ UNIMPLEMENTED(FATAL) << "Need Mips implementation";
+ return 0;
+#if 0
+ Opcode opcode = mir->dalvikInsn.opcode;
+
+ switch (opcode) {
+ case OP_INT_TO_FLOAT:
+ return genConversionCall(cUnit, mir, OFFSETOF_MEMBER(Thread, pI2f),
+ 1, 1);
+ case OP_FLOAT_TO_INT:
+ return genConversionCall(cUnit, mir, OFFSETOF_MEMBER(Thread, pF2iz),
+ 1, 1);
+ case OP_DOUBLE_TO_FLOAT:
+ return genConversionCall(cUnit, mir, OFFSETOF_MEMBER(Thread, pD2f),
+ 2, 1);
+ case OP_FLOAT_TO_DOUBLE:
+ return genConversionCall(cUnit, mir, OFFSETOF_MEMBER(Thread, pF2d),
+ 1, 2);
+ case OP_INT_TO_DOUBLE:
+ return genConversionCall(cUnit, mir, OFFSETOF_MEMBER(Thread, pI2d),
+ 1, 2);
+ case OP_DOUBLE_TO_INT:
+ return genConversionCall(cUnit, mir, OFFSETOF_MEMBER(Thread, pD2iz),
+ 2, 1);
+ case OP_FLOAT_TO_LONG:
+ return genConversionCall(cUnit, mir, OFFSETOF_MEMBER(Thread,
+ pF2l), 1, 2);
+ case OP_LONG_TO_FLOAT:
+ return genConversionCall(cUnit, mir, OFFSETOF_MEMBER(Thread, pL2f),
+ 2, 1);
+ case OP_DOUBLE_TO_LONG:
+ return genConversionCall(cUnit, mir, OFFSETOF_MEMBER(Thread,
+ pD2l), 2, 2);
+ case OP_LONG_TO_DOUBLE:
+ return genConversionCall(cUnit, mir, OFFSETOF_MEMBER(Thread, pL2d),
+ 2, 2);
+ default:
+ return true;
+ }
+ return false;
+#endif
+}
+
@@ -102,7 +284,7 @@
}
#endif
/*
- * Insert a kMipsPseudoCaseLabel at the beginning of the Dalvik
+ * Insert a kPseudoCaseLabel at the beginning of the Dalvik
* offset vaddr. This label will be used to fix up the case
* branch table during the assembly phase. Be sure to set
* all resource flags on this to prevent code motion across
@@ -117,7 +299,7 @@
}
MipsLIR* newLabel = (MipsLIR*)oatNew(cUnit, sizeof(MipsLIR), true, kAllocLIR);
newLabel->generic.dalvikOffset = vaddr;
- newLabel->opcode = kMipsPseudoCaseLabel;
+ newLabel->opcode = kPseudoCaseLabel;
newLabel->operands[0] = keyVal;
oatInsertLIRAfter(it->second, (LIR*)newLabel);
return newLabel;
@@ -269,7 +451,7 @@
int rIdx = oatAllocTemp(cUnit);
loadConstant(cUnit, rIdx, size);
// Establish loop branch target
- MipsLIR* target = newLIR0(cUnit, kMipsPseudoTargetLabel);
+ MipsLIR* target = newLIR0(cUnit, kPseudoTargetLabel);
target->defMask = ENCODE_ALL;
// Load next key/disp
newLIR2(cUnit, kThumb2LdmiaWB, rBase, (1 << rKey) | (1 << rDisp));
@@ -331,7 +513,7 @@
tabRec->bxInst = switchBranch;
/* branchOver target here */
- MipsLIR* target = newLIR0(cUnit, kMipsPseudoTargetLabel);
+ MipsLIR* target = newLIR0(cUnit, kPseudoTargetLabel);
target->defMask = ENCODE_ALL;
branchOver->generic.target = (LIR*)target;
#endif