ART: Make InstructionSet an enum class and add kLast.
Adding InstructionSet::kLast shall make it easier to encode
the InstructionSet in fewer bits using BitField<>. However,
introducing `kLast` into the `art` namespace is not a good
idea, so we change the InstructionSet to an enum class.
This also uncovered a case of InstructionSet::kNone being
erroneously used instead of vixl32::Condition::None(), so
it's good to remove `kNone` from the `art` namespace.
Test: m test-art-host-gtest
Test: testrunner.py --host --optimizing
Change-Id: I6fa6168dfba4ed6da86d021a69c80224f09997a6
diff --git a/compiler/debug/elf_debug_frame_writer.h b/compiler/debug/elf_debug_frame_writer.h
index 6dacdfa..d0c98a7 100644
--- a/compiler/debug/elf_debug_frame_writer.h
+++ b/compiler/debug/elf_debug_frame_writer.h
@@ -37,8 +37,8 @@
// debugger that its value in the previous frame is not recoverable.
bool is64bit = Is64BitInstructionSet(isa);
switch (isa) {
- case kArm:
- case kThumb2: {
+ case InstructionSet::kArm:
+ case InstructionSet::kThumb2: {
dwarf::DebugFrameOpCodeWriter<> opcodes;
opcodes.DefCFA(Reg::ArmCore(13), 0); // R13(SP).
// core registers.
@@ -61,7 +61,7 @@
WriteCIE(is64bit, return_reg, opcodes, format, buffer);
return;
}
- case kArm64: {
+ case InstructionSet::kArm64: {
dwarf::DebugFrameOpCodeWriter<> opcodes;
opcodes.DefCFA(Reg::Arm64Core(31), 0); // R31(SP).
// core registers.
@@ -84,8 +84,8 @@
WriteCIE(is64bit, return_reg, opcodes, format, buffer);
return;
}
- case kMips:
- case kMips64: {
+ case InstructionSet::kMips:
+ case InstructionSet::kMips64: {
dwarf::DebugFrameOpCodeWriter<> opcodes;
opcodes.DefCFA(Reg::MipsCore(29), 0); // R29(SP).
// core registers.
@@ -108,7 +108,7 @@
WriteCIE(is64bit, return_reg, opcodes, format, buffer);
return;
}
- case kX86: {
+ case InstructionSet::kX86: {
// FIXME: Add fp registers once libunwind adds support for them. Bug: 20491296
constexpr bool generate_opcodes_for_x86_fp = false;
dwarf::DebugFrameOpCodeWriter<> opcodes;
@@ -134,7 +134,7 @@
WriteCIE(is64bit, return_reg, opcodes, format, buffer);
return;
}
- case kX86_64: {
+ case InstructionSet::kX86_64: {
dwarf::DebugFrameOpCodeWriter<> opcodes;
opcodes.DefCFA(Reg::X86_64Core(4), 8); // R4(RSP).
opcodes.Offset(Reg::X86_64Core(16), -8); // R16(RIP).
@@ -160,7 +160,7 @@
WriteCIE(is64bit, return_reg, opcodes, format, buffer);
return;
}
- case kNone:
+ case InstructionSet::kNone:
break;
}
LOG(FATAL) << "Cannot write CIE frame for ISA " << isa;