commit 5192cbb12856b12620dc346758605baaa1469ced
author Yixin Shou <yixin.shou@intel.com> Tue Jul 01 13:48:17 2014 -0400
committer Yixin Shou <yixin.shou@intel.com> Wed Jul 02 06:40:12 2014 -0400
tree 46f8727c0009978e1c15f94ea353a9fc92d2fe42
parent 7a59a24987beb52877b72b4e3f841e406413bb6d

Load 64 bit constant into GPR by single instruction for 64bit mode

This patch load 64 bit constant into a register by a single movabsq
instruction on 64 bit bit instead of previous mov, shift, add
instruction sequences.

Change-Id: I9d013c4f6c0b5c2e43bd125f91436263c7e6028c
Signed-off-by: Yixin Shou <yixin.shou@intel.com>

compiler/dex/quick/x86/target_x86.cc

diff --git a/compiler/dex/quick/x86/target_x86.cc b/compiler/dex/quick/x86/target_x86.cc
index 4169005..04a7a8e 100644
--- a/compiler/dex/quick/x86/target_x86.cc
+++ b/compiler/dex/quick/x86/target_x86.cc
@@ -330,6 +330,11 @@
           case 'd':
             buf += StringPrintf("%d", operand);
             break;
+          case 'q': {
+             int64_t value = static_cast<int64_t>(static_cast<int64_t>(operand) << 32 |
+                             static_cast<uint32_t>(lir->operands[operand_number+1]));
+             buf +=StringPrintf("%" PRId64, value);
+          }
           case 'p': {
             EmbeddedData *tab_rec = reinterpret_cast<EmbeddedData*>(UnwrapPointer(operand));
             buf += StringPrintf("0x%08x", tab_rec->offset);