Quick Compiler function renaming
Move the Quick compiler's function naming to Art coding conventions. Will
be done is pieces: names first, then arguments and locals. Also removed
some dead code and marked statics for the top level source files
No logic changes aside from eliminating a few useless exported "oat"
routines.
Change-Id: Iadaddc560942a0fc1199ba5b1c261cd6ac5cfd9a
diff --git a/src/compiler/codegen/mips/assemble_mips.cc b/src/compiler/codegen/mips/assemble_mips.cc
index 79259fb..889541f 100644
--- a/src/compiler/codegen/mips/assemble_mips.cc
+++ b/src/compiler/codegen/mips/assemble_mips.cc
@@ -458,7 +458,7 @@
* NOTE: An out-of-range bal isn't supported because it should
* never happen with the current PIC model.
*/
-void convertShortToLongBranch(CompilationUnit* cUnit, LIR* lir)
+void ConvertShortToLongBranch(CompilationUnit* cUnit, LIR* lir)
{
// For conditional branches we'll need to reverse the sense
bool unconditional = false;
@@ -483,27 +483,27 @@
}
LIR* hopTarget = NULL;
if (!unconditional) {
- hopTarget = rawLIR(cUnit, dalvikOffset, kPseudoTargetLabel);
- LIR* hopBranch = rawLIR(cUnit, dalvikOffset, opcode, lir->operands[0],
+ hopTarget = RawLIR(cUnit, dalvikOffset, kPseudoTargetLabel);
+ LIR* hopBranch = RawLIR(cUnit, dalvikOffset, opcode, lir->operands[0],
lir->operands[1], 0, 0, 0, hopTarget);
- oatInsertLIRBefore(lir, hopBranch);
+ InsertLIRBefore(lir, hopBranch);
}
- LIR* currPC = rawLIR(cUnit, dalvikOffset, kMipsCurrPC);
- oatInsertLIRBefore(lir, currPC);
- LIR* anchor = rawLIR(cUnit, dalvikOffset, kPseudoTargetLabel);
- LIR* deltaHi = rawLIR(cUnit, dalvikOffset, kMipsDeltaHi, r_AT, 0,
+ LIR* currPC = RawLIR(cUnit, dalvikOffset, kMipsCurrPC);
+ InsertLIRBefore(lir, currPC);
+ LIR* anchor = RawLIR(cUnit, dalvikOffset, kPseudoTargetLabel);
+ LIR* deltaHi = RawLIR(cUnit, dalvikOffset, kMipsDeltaHi, r_AT, 0,
reinterpret_cast<uintptr_t>(anchor), 0, 0, lir->target);
- oatInsertLIRBefore(lir, deltaHi);
- oatInsertLIRBefore(lir, anchor);
- LIR* deltaLo = rawLIR(cUnit, dalvikOffset, kMipsDeltaLo, r_AT, 0,
+ InsertLIRBefore(lir, deltaHi);
+ InsertLIRBefore(lir, anchor);
+ LIR* deltaLo = RawLIR(cUnit, dalvikOffset, kMipsDeltaLo, r_AT, 0,
reinterpret_cast<uintptr_t>(anchor), 0, 0, lir->target);
- oatInsertLIRBefore(lir, deltaLo);
- LIR* addu = rawLIR(cUnit, dalvikOffset, kMipsAddu, r_AT, r_AT, r_RA);
- oatInsertLIRBefore(lir, addu);
- LIR* jr = rawLIR(cUnit, dalvikOffset, kMipsJr, r_AT);
- oatInsertLIRBefore(lir, jr);
+ InsertLIRBefore(lir, deltaLo);
+ LIR* addu = RawLIR(cUnit, dalvikOffset, kMipsAddu, r_AT, r_AT, r_RA);
+ InsertLIRBefore(lir, addu);
+ LIR* jr = RawLIR(cUnit, dalvikOffset, kMipsJr, r_AT);
+ InsertLIRBefore(lir, jr);
if (!unconditional) {
- oatInsertLIRBefore(lir, hopTarget);
+ InsertLIRBefore(lir, hopTarget);
}
lir->flags.isNop = true;
}
@@ -514,7 +514,7 @@
* instruction. In those cases we will try to substitute a new code
* sequence or request that the trace be shortened and retried.
*/
-AssemblerStatus oatAssembleInstructions(CompilationUnit *cUnit,
+AssemblerStatus AssembleInstructions(CompilationUnit *cUnit,
uintptr_t startAddr)
{
LIR *lir;
@@ -552,19 +552,19 @@
} else {
// Doesn't fit - must expand to kMipsDelta[Hi|Lo] pair
LIR *newDeltaHi =
- rawLIR(cUnit, lir->dalvikOffset, kMipsDeltaHi,
+ RawLIR(cUnit, lir->dalvikOffset, kMipsDeltaHi,
lir->operands[0], 0, lir->operands[2],
lir->operands[3], 0, lir->target);
- oatInsertLIRBefore(lir, newDeltaHi);
+ InsertLIRBefore(lir, newDeltaHi);
LIR *newDeltaLo =
- rawLIR(cUnit, lir->dalvikOffset, kMipsDeltaLo,
+ RawLIR(cUnit, lir->dalvikOffset, kMipsDeltaLo,
lir->operands[0], 0, lir->operands[2],
lir->operands[3], 0, lir->target);
- oatInsertLIRBefore(lir, newDeltaLo);
+ InsertLIRBefore(lir, newDeltaLo);
LIR *newAddu =
- rawLIR(cUnit, lir->dalvikOffset, kMipsAddu,
+ RawLIR(cUnit, lir->dalvikOffset, kMipsAddu,
lir->operands[0], lir->operands[0], r_RA);
- oatInsertLIRBefore(lir, newAddu);
+ InsertLIRBefore(lir, newAddu);
lir->flags.isNop = true;
res = kRetryAll;
}
@@ -590,7 +590,7 @@
}
if (delta > 131068 || delta < -131069) {
res = kRetryAll;
- convertShortToLongBranch(cUnit, lir);
+ ConvertShortToLongBranch(cUnit, lir);
} else {
lir->operands[0] = delta >> 2;
}
@@ -604,7 +604,7 @@
}
if (delta > 131068 || delta < -131069) {
res = kRetryAll;
- convertShortToLongBranch(cUnit, lir);
+ ConvertShortToLongBranch(cUnit, lir);
} else {
lir->operands[1] = delta >> 2;
}
@@ -618,7 +618,7 @@
}
if (delta > 131068 || delta < -131069) {
res = kRetryAll;
- convertShortToLongBranch(cUnit, lir);
+ ConvertShortToLongBranch(cUnit, lir);
} else {
lir->operands[2] = delta >> 2;
}
@@ -710,7 +710,7 @@
return res;
}
-int oatGetInsnSize(LIR* lir)
+int GetInsnSize(LIR* lir)
{
return EncodingMap[lir->opcode].size;
}
@@ -718,7 +718,7 @@
* Target-dependent offset assignment.
* independent.
*/
-int oatAssignInsnOffsets(CompilationUnit* cUnit)
+int AssignInsnOffsets(CompilationUnit* cUnit)
{
LIR* mipsLIR;
int offset = 0;
diff --git a/src/compiler/codegen/mips/call_mips.cc b/src/compiler/codegen/mips/call_mips.cc
index 5049eec..33a7aed 100644
--- a/src/compiler/codegen/mips/call_mips.cc
+++ b/src/compiler/codegen/mips/call_mips.cc
@@ -23,7 +23,7 @@
namespace art {
-void genSpecialCase(CompilationUnit* cUnit, BasicBlock* bb, MIR* mir,
+void GenSpecialCase(CompilationUnit* cUnit, BasicBlock* bb, MIR* mir,
SpecialCaseHandler specialCase)
{
// TODO
@@ -60,22 +60,22 @@
* done:
*
*/
-void genSparseSwitch(CompilationUnit* cUnit, uint32_t tableOffset,
+void GenSparseSwitch(CompilationUnit* cUnit, uint32_t tableOffset,
RegLocation rlSrc)
{
const uint16_t* table = cUnit->insns + cUnit->currentDalvikOffset + tableOffset;
if (cUnit->printMe) {
- dumpSparseSwitchTable(table);
+ DumpSparseSwitchTable(table);
}
// Add the table to the list - we'll process it later
SwitchTable *tabRec =
- static_cast<SwitchTable*>(oatNew(cUnit, sizeof(SwitchTable), true, kAllocData));
+ static_cast<SwitchTable*>(NewMem(cUnit, sizeof(SwitchTable), true, kAllocData));
tabRec->table = table;
tabRec->vaddr = cUnit->currentDalvikOffset;
int elements = table[1];
tabRec->targets =
- static_cast<LIR**>(oatNew(cUnit, elements * sizeof(LIR*), true, kAllocLIR));
- oatInsertGrowableList(cUnit, &cUnit->switchTables, reinterpret_cast<uintptr_t>(tabRec));
+ static_cast<LIR**>(NewMem(cUnit, elements * sizeof(LIR*), true, kAllocLIR));
+ InsertGrowableList(cUnit, &cUnit->switchTables, reinterpret_cast<uintptr_t>(tabRec));
// The table is composed of 8-byte key/disp pairs
int byteSize = elements * 8;
@@ -83,47 +83,47 @@
int sizeHi = byteSize >> 16;
int sizeLo = byteSize & 0xffff;
- int rEnd = oatAllocTemp(cUnit);
+ int rEnd = AllocTemp(cUnit);
if (sizeHi) {
- newLIR2(cUnit, kMipsLui, rEnd, sizeHi);
+ NewLIR2(cUnit, kMipsLui, rEnd, sizeHi);
}
// Must prevent code motion for the curr pc pair
- genBarrier(cUnit); // Scheduling barrier
- newLIR0(cUnit, kMipsCurrPC); // Really a jal to .+8
+ GenBarrier(cUnit); // Scheduling barrier
+ NewLIR0(cUnit, kMipsCurrPC); // Really a jal to .+8
// Now, fill the branch delay slot
if (sizeHi) {
- newLIR3(cUnit, kMipsOri, rEnd, rEnd, sizeLo);
+ NewLIR3(cUnit, kMipsOri, rEnd, rEnd, sizeLo);
} else {
- newLIR3(cUnit, kMipsOri, rEnd, r_ZERO, sizeLo);
+ NewLIR3(cUnit, kMipsOri, rEnd, r_ZERO, sizeLo);
}
- genBarrier(cUnit); // Scheduling barrier
+ GenBarrier(cUnit); // Scheduling barrier
// Construct BaseLabel and set up table base register
- LIR* baseLabel = newLIR0(cUnit, kPseudoTargetLabel);
+ LIR* baseLabel = NewLIR0(cUnit, kPseudoTargetLabel);
// Remember base label so offsets can be computed later
tabRec->anchor = baseLabel;
- int rBase = oatAllocTemp(cUnit);
- newLIR4(cUnit, kMipsDelta, rBase, 0, reinterpret_cast<uintptr_t>(baseLabel),
+ int rBase = AllocTemp(cUnit);
+ NewLIR4(cUnit, kMipsDelta, rBase, 0, reinterpret_cast<uintptr_t>(baseLabel),
reinterpret_cast<uintptr_t>(tabRec));
- opRegRegReg(cUnit, kOpAdd, rEnd, rEnd, rBase);
+ OpRegRegReg(cUnit, kOpAdd, rEnd, rEnd, rBase);
// Grab switch test value
- rlSrc = loadValue(cUnit, rlSrc, kCoreReg);
+ rlSrc = LoadValue(cUnit, rlSrc, kCoreReg);
// Test loop
- int rKey = oatAllocTemp(cUnit);
- LIR* loopLabel = newLIR0(cUnit, kPseudoTargetLabel);
- LIR* exitBranch = opCmpBranch(cUnit , kCondEq, rBase, rEnd, NULL);
- loadWordDisp(cUnit, rBase, 0, rKey);
- opRegImm(cUnit, kOpAdd, rBase, 8);
- opCmpBranch(cUnit, kCondNe, rlSrc.lowReg, rKey, loopLabel);
- int rDisp = oatAllocTemp(cUnit);
- loadWordDisp(cUnit, rBase, -4, rDisp);
- opRegRegReg(cUnit, kOpAdd, r_RA, r_RA, rDisp);
- opReg(cUnit, kOpBx, r_RA);
+ int rKey = AllocTemp(cUnit);
+ LIR* loopLabel = NewLIR0(cUnit, kPseudoTargetLabel);
+ LIR* exitBranch = OpCmpBranch(cUnit , kCondEq, rBase, rEnd, NULL);
+ LoadWordDisp(cUnit, rBase, 0, rKey);
+ OpRegImm(cUnit, kOpAdd, rBase, 8);
+ OpCmpBranch(cUnit, kCondNe, rlSrc.lowReg, rKey, loopLabel);
+ int rDisp = AllocTemp(cUnit);
+ LoadWordDisp(cUnit, rBase, -4, rDisp);
+ OpRegRegReg(cUnit, kOpAdd, r_RA, r_RA, rDisp);
+ OpReg(cUnit, kOpBx, r_RA);
// Loop exit
- LIR* exitLabel = newLIR0(cUnit, kPseudoTargetLabel);
+ LIR* exitLabel = NewLIR0(cUnit, kPseudoTargetLabel);
exitBranch->target = exitLabel;
}
@@ -140,24 +140,24 @@
* jr r_RA
* done:
*/
-void genPackedSwitch(CompilationUnit* cUnit, uint32_t tableOffset,
+void GenPackedSwitch(CompilationUnit* cUnit, uint32_t tableOffset,
RegLocation rlSrc)
{
const uint16_t* table = cUnit->insns + cUnit->currentDalvikOffset + tableOffset;
if (cUnit->printMe) {
- dumpPackedSwitchTable(table);
+ DumpPackedSwitchTable(table);
}
// Add the table to the list - we'll process it later
SwitchTable *tabRec =
- static_cast<SwitchTable*>(oatNew(cUnit, sizeof(SwitchTable), true, kAllocData));
+ static_cast<SwitchTable*>(NewMem(cUnit, sizeof(SwitchTable), true, kAllocData));
tabRec->table = table;
tabRec->vaddr = cUnit->currentDalvikOffset;
int size = table[1];
- tabRec->targets = static_cast<LIR**>(oatNew(cUnit, size * sizeof(LIR*), true, kAllocLIR));
- oatInsertGrowableList(cUnit, &cUnit->switchTables, reinterpret_cast<uintptr_t>(tabRec));
+ tabRec->targets = static_cast<LIR**>(NewMem(cUnit, size * sizeof(LIR*), true, kAllocLIR));
+ InsertGrowableList(cUnit, &cUnit->switchTables, reinterpret_cast<uintptr_t>(tabRec));
// Get the switch value
- rlSrc = loadValue(cUnit, rlSrc, kCoreReg);
+ rlSrc = LoadValue(cUnit, rlSrc, kCoreReg);
// Prepare the bias. If too big, handle 1st stage here
int lowKey = s4FromSwitchData(&table[2]);
@@ -166,51 +166,51 @@
if (lowKey == 0) {
rKey = rlSrc.lowReg;
} else if ((lowKey & 0xffff) != lowKey) {
- rKey = oatAllocTemp(cUnit);
- loadConstant(cUnit, rKey, lowKey);
+ rKey = AllocTemp(cUnit);
+ LoadConstant(cUnit, rKey, lowKey);
largeBias = true;
} else {
- rKey = oatAllocTemp(cUnit);
+ rKey = AllocTemp(cUnit);
}
// Must prevent code motion for the curr pc pair
- genBarrier(cUnit);
- newLIR0(cUnit, kMipsCurrPC); // Really a jal to .+8
+ GenBarrier(cUnit);
+ NewLIR0(cUnit, kMipsCurrPC); // Really a jal to .+8
// Now, fill the branch delay slot with bias strip
if (lowKey == 0) {
- newLIR0(cUnit, kMipsNop);
+ NewLIR0(cUnit, kMipsNop);
} else {
if (largeBias) {
- opRegRegReg(cUnit, kOpSub, rKey, rlSrc.lowReg, rKey);
+ OpRegRegReg(cUnit, kOpSub, rKey, rlSrc.lowReg, rKey);
} else {
- opRegRegImm(cUnit, kOpSub, rKey, rlSrc.lowReg, lowKey);
+ OpRegRegImm(cUnit, kOpSub, rKey, rlSrc.lowReg, lowKey);
}
}
- genBarrier(cUnit); // Scheduling barrier
+ GenBarrier(cUnit); // Scheduling barrier
// Construct BaseLabel and set up table base register
- LIR* baseLabel = newLIR0(cUnit, kPseudoTargetLabel);
+ LIR* baseLabel = NewLIR0(cUnit, kPseudoTargetLabel);
// Remember base label so offsets can be computed later
tabRec->anchor = baseLabel;
// Bounds check - if < 0 or >= size continue following switch
- LIR* branchOver = opCmpImmBranch(cUnit, kCondHi, rKey, size-1, NULL);
+ LIR* branchOver = OpCmpImmBranch(cUnit, kCondHi, rKey, size-1, NULL);
// Materialize the table base pointer
- int rBase = oatAllocTemp(cUnit);
- newLIR4(cUnit, kMipsDelta, rBase, 0, reinterpret_cast<uintptr_t>(baseLabel),
+ int rBase = AllocTemp(cUnit);
+ NewLIR4(cUnit, kMipsDelta, rBase, 0, reinterpret_cast<uintptr_t>(baseLabel),
reinterpret_cast<uintptr_t>(tabRec));
// Load the displacement from the switch table
- int rDisp = oatAllocTemp(cUnit);
- loadBaseIndexed(cUnit, rBase, rKey, rDisp, 2, kWord);
+ int rDisp = AllocTemp(cUnit);
+ LoadBaseIndexed(cUnit, rBase, rKey, rDisp, 2, kWord);
// Add to r_AP and go
- opRegRegReg(cUnit, kOpAdd, r_RA, r_RA, rDisp);
- opReg(cUnit, kOpBx, r_RA);
+ OpRegRegReg(cUnit, kOpAdd, r_RA, r_RA, rDisp);
+ OpReg(cUnit, kOpBx, r_RA);
/* branchOver target here */
- LIR* target = newLIR0(cUnit, kPseudoTargetLabel);
+ LIR* target = NewLIR0(cUnit, kPseudoTargetLabel);
branchOver->target = target;
}
@@ -224,96 +224,96 @@
*
* Total size is 4+(width * size + 1)/2 16-bit code units.
*/
-void genFillArrayData(CompilationUnit* cUnit, uint32_t tableOffset,
+void GenFillArrayData(CompilationUnit* cUnit, uint32_t tableOffset,
RegLocation rlSrc)
{
const uint16_t* table = cUnit->insns + cUnit->currentDalvikOffset + tableOffset;
// Add the table to the list - we'll process it later
FillArrayData *tabRec =
- reinterpret_cast<FillArrayData*>(oatNew(cUnit, sizeof(FillArrayData), true, kAllocData));
+ reinterpret_cast<FillArrayData*>(NewMem(cUnit, sizeof(FillArrayData), true, kAllocData));
tabRec->table = table;
tabRec->vaddr = cUnit->currentDalvikOffset;
uint16_t width = tabRec->table[1];
uint32_t size = tabRec->table[2] | ((static_cast<uint32_t>(tabRec->table[3])) << 16);
tabRec->size = (size * width) + 8;
- oatInsertGrowableList(cUnit, &cUnit->fillArrayData, reinterpret_cast<uintptr_t>(tabRec));
+ InsertGrowableList(cUnit, &cUnit->fillArrayData, reinterpret_cast<uintptr_t>(tabRec));
// Making a call - use explicit registers
- oatFlushAllRegs(cUnit); /* Everything to home location */
- oatLockCallTemps(cUnit);
- loadValueDirectFixed(cUnit, rlSrc, rMIPS_ARG0);
+ FlushAllRegs(cUnit); /* Everything to home location */
+ LockCallTemps(cUnit);
+ LoadValueDirectFixed(cUnit, rlSrc, rMIPS_ARG0);
// Must prevent code motion for the curr pc pair
- genBarrier(cUnit);
- newLIR0(cUnit, kMipsCurrPC); // Really a jal to .+8
+ GenBarrier(cUnit);
+ NewLIR0(cUnit, kMipsCurrPC); // Really a jal to .+8
// Now, fill the branch delay slot with the helper load
- int rTgt = loadHelper(cUnit, ENTRYPOINT_OFFSET(pHandleFillArrayDataFromCode));
- genBarrier(cUnit); // Scheduling barrier
+ int rTgt = LoadHelper(cUnit, ENTRYPOINT_OFFSET(pHandleFillArrayDataFromCode));
+ GenBarrier(cUnit); // Scheduling barrier
// Construct BaseLabel and set up table base register
- LIR* baseLabel = newLIR0(cUnit, kPseudoTargetLabel);
+ LIR* baseLabel = NewLIR0(cUnit, kPseudoTargetLabel);
// Materialize a pointer to the fill data image
- newLIR4(cUnit, kMipsDelta, rMIPS_ARG1, 0, reinterpret_cast<uintptr_t>(baseLabel),
+ NewLIR4(cUnit, kMipsDelta, rMIPS_ARG1, 0, reinterpret_cast<uintptr_t>(baseLabel),
reinterpret_cast<uintptr_t>(tabRec));
// And go...
- oatClobberCalleeSave(cUnit);
- LIR* callInst = opReg(cUnit, kOpBlx, rTgt); // ( array*, fill_data* )
- markSafepointPC(cUnit, callInst);
+ ClobberCalleeSave(cUnit);
+ LIR* callInst = OpReg(cUnit, kOpBlx, rTgt); // ( array*, fill_data* )
+ MarkSafepointPC(cUnit, callInst);
}
/*
* TODO: implement fast path to short-circuit thin-lock case
*/
-void genMonitorEnter(CompilationUnit* cUnit, int optFlags, RegLocation rlSrc)
+void GenMonitorEnter(CompilationUnit* cUnit, int optFlags, RegLocation rlSrc)
{
- oatFlushAllRegs(cUnit);
- loadValueDirectFixed(cUnit, rlSrc, rMIPS_ARG0); // Get obj
- oatLockCallTemps(cUnit); // Prepare for explicit register usage
- genNullCheck(cUnit, rlSrc.sRegLow, rMIPS_ARG0, optFlags);
+ FlushAllRegs(cUnit);
+ LoadValueDirectFixed(cUnit, rlSrc, rMIPS_ARG0); // Get obj
+ LockCallTemps(cUnit); // Prepare for explicit register usage
+ GenNullCheck(cUnit, rlSrc.sRegLow, rMIPS_ARG0, optFlags);
// Go expensive route - artLockObjectFromCode(self, obj);
- int rTgt = loadHelper(cUnit, ENTRYPOINT_OFFSET(pLockObjectFromCode));
- oatClobberCalleeSave(cUnit);
- LIR* callInst = opReg(cUnit, kOpBlx, rTgt);
- markSafepointPC(cUnit, callInst);
+ int rTgt = LoadHelper(cUnit, ENTRYPOINT_OFFSET(pLockObjectFromCode));
+ ClobberCalleeSave(cUnit);
+ LIR* callInst = OpReg(cUnit, kOpBlx, rTgt);
+ MarkSafepointPC(cUnit, callInst);
}
/*
* TODO: implement fast path to short-circuit thin-lock case
*/
-void genMonitorExit(CompilationUnit* cUnit, int optFlags, RegLocation rlSrc)
+void GenMonitorExit(CompilationUnit* cUnit, int optFlags, RegLocation rlSrc)
{
- oatFlushAllRegs(cUnit);
- loadValueDirectFixed(cUnit, rlSrc, rMIPS_ARG0); // Get obj
- oatLockCallTemps(cUnit); // Prepare for explicit register usage
- genNullCheck(cUnit, rlSrc.sRegLow, rMIPS_ARG0, optFlags);
+ FlushAllRegs(cUnit);
+ LoadValueDirectFixed(cUnit, rlSrc, rMIPS_ARG0); // Get obj
+ LockCallTemps(cUnit); // Prepare for explicit register usage
+ GenNullCheck(cUnit, rlSrc.sRegLow, rMIPS_ARG0, optFlags);
// Go expensive route - UnlockObjectFromCode(obj);
- int rTgt = loadHelper(cUnit, ENTRYPOINT_OFFSET(pUnlockObjectFromCode));
- oatClobberCalleeSave(cUnit);
- LIR* callInst = opReg(cUnit, kOpBlx, rTgt);
- markSafepointPC(cUnit, callInst);
+ int rTgt = LoadHelper(cUnit, ENTRYPOINT_OFFSET(pUnlockObjectFromCode));
+ ClobberCalleeSave(cUnit);
+ LIR* callInst = OpReg(cUnit, kOpBlx, rTgt);
+ MarkSafepointPC(cUnit, callInst);
}
/*
* Mark garbage collection card. Skip if the value we're storing is null.
*/
-void markGCCard(CompilationUnit* cUnit, int valReg, int tgtAddrReg)
+void MarkGCCard(CompilationUnit* cUnit, int valReg, int tgtAddrReg)
{
- int regCardBase = oatAllocTemp(cUnit);
- int regCardNo = oatAllocTemp(cUnit);
- LIR* branchOver = opCmpImmBranch(cUnit, kCondEq, valReg, 0, NULL);
- loadWordDisp(cUnit, rMIPS_SELF, Thread::CardTableOffset().Int32Value(), regCardBase);
- opRegRegImm(cUnit, kOpLsr, regCardNo, tgtAddrReg, CardTable::kCardShift);
- storeBaseIndexed(cUnit, regCardBase, regCardNo, regCardBase, 0,
+ int regCardBase = AllocTemp(cUnit);
+ int regCardNo = AllocTemp(cUnit);
+ LIR* branchOver = OpCmpImmBranch(cUnit, kCondEq, valReg, 0, NULL);
+ LoadWordDisp(cUnit, rMIPS_SELF, Thread::CardTableOffset().Int32Value(), regCardBase);
+ OpRegRegImm(cUnit, kOpLsr, regCardNo, tgtAddrReg, CardTable::kCardShift);
+ StoreBaseIndexed(cUnit, regCardBase, regCardNo, regCardBase, 0,
kUnsignedByte);
- LIR* target = newLIR0(cUnit, kPseudoTargetLabel);
+ LIR* target = NewLIR0(cUnit, kPseudoTargetLabel);
branchOver->target = target;
- oatFreeTemp(cUnit, regCardBase);
- oatFreeTemp(cUnit, regCardNo);
+ FreeTemp(cUnit, regCardBase);
+ FreeTemp(cUnit, regCardNo);
}
-void genEntrySequence(CompilationUnit* cUnit, RegLocation* argLocs,
+void GenEntrySequence(CompilationUnit* cUnit, RegLocation* ArgLocs,
RegLocation rlMethod)
{
int spillCount = cUnit->numCoreSpills + cUnit->numFPSpills;
@@ -323,10 +323,10 @@
* expanding the frame or flushing. This leaves the utility
* code with a single temp: r12. This should be enough.
*/
- oatLockTemp(cUnit, rMIPS_ARG0);
- oatLockTemp(cUnit, rMIPS_ARG1);
- oatLockTemp(cUnit, rMIPS_ARG2);
- oatLockTemp(cUnit, rMIPS_ARG3);
+ LockTemp(cUnit, rMIPS_ARG0);
+ LockTemp(cUnit, rMIPS_ARG1);
+ LockTemp(cUnit, rMIPS_ARG2);
+ LockTemp(cUnit, rMIPS_ARG3);
/*
* We can safely skip the stack overflow check if we're
@@ -334,45 +334,45 @@
*/
bool skipOverflowCheck = ((cUnit->attrs & METHOD_IS_LEAF) &&
(static_cast<size_t>(cUnit->frameSize) < Thread::kStackOverflowReservedBytes));
- newLIR0(cUnit, kPseudoMethodEntry);
- int checkReg = oatAllocTemp(cUnit);
- int newSP = oatAllocTemp(cUnit);
+ NewLIR0(cUnit, kPseudoMethodEntry);
+ int checkReg = AllocTemp(cUnit);
+ int newSP = AllocTemp(cUnit);
if (!skipOverflowCheck) {
/* Load stack limit */
- loadWordDisp(cUnit, rMIPS_SELF, Thread::StackEndOffset().Int32Value(), checkReg);
+ LoadWordDisp(cUnit, rMIPS_SELF, Thread::StackEndOffset().Int32Value(), checkReg);
}
/* Spill core callee saves */
- spillCoreRegs(cUnit);
+ SpillCoreRegs(cUnit);
/* NOTE: promotion of FP regs currently unsupported, thus no FP spill */
DCHECK_EQ(cUnit->numFPSpills, 0);
if (!skipOverflowCheck) {
- opRegRegImm(cUnit, kOpSub, newSP, rMIPS_SP, cUnit->frameSize - (spillCount * 4));
- genRegRegCheck(cUnit, kCondCc, newSP, checkReg, kThrowStackOverflow);
- opRegCopy(cUnit, rMIPS_SP, newSP); // Establish stack
+ OpRegRegImm(cUnit, kOpSub, newSP, rMIPS_SP, cUnit->frameSize - (spillCount * 4));
+ GenRegRegCheck(cUnit, kCondCc, newSP, checkReg, kThrowStackOverflow);
+ OpRegCopy(cUnit, rMIPS_SP, newSP); // Establish stack
} else {
- opRegImm(cUnit, kOpSub, rMIPS_SP, cUnit->frameSize - (spillCount * 4));
+ OpRegImm(cUnit, kOpSub, rMIPS_SP, cUnit->frameSize - (spillCount * 4));
}
- flushIns(cUnit, argLocs, rlMethod);
+ FlushIns(cUnit, ArgLocs, rlMethod);
- oatFreeTemp(cUnit, rMIPS_ARG0);
- oatFreeTemp(cUnit, rMIPS_ARG1);
- oatFreeTemp(cUnit, rMIPS_ARG2);
- oatFreeTemp(cUnit, rMIPS_ARG3);
+ FreeTemp(cUnit, rMIPS_ARG0);
+ FreeTemp(cUnit, rMIPS_ARG1);
+ FreeTemp(cUnit, rMIPS_ARG2);
+ FreeTemp(cUnit, rMIPS_ARG3);
}
-void genExitSequence(CompilationUnit* cUnit)
+void GenExitSequence(CompilationUnit* cUnit)
{
/*
* In the exit path, rMIPS_RET0/rMIPS_RET1 are live - make sure they aren't
* allocated by the register utilities as temps.
*/
- oatLockTemp(cUnit, rMIPS_RET0);
- oatLockTemp(cUnit, rMIPS_RET1);
+ LockTemp(cUnit, rMIPS_RET0);
+ LockTemp(cUnit, rMIPS_RET1);
- newLIR0(cUnit, kPseudoMethodExit);
- unSpillCoreRegs(cUnit);
- opReg(cUnit, kOpBx, r_RA);
+ NewLIR0(cUnit, kPseudoMethodExit);
+ UnSpillCoreRegs(cUnit);
+ OpReg(cUnit, kOpBx, r_RA);
}
} // namespace art
diff --git a/src/compiler/codegen/mips/fp_mips.cc b/src/compiler/codegen/mips/fp_mips.cc
index 268a88d..942259d 100644
--- a/src/compiler/codegen/mips/fp_mips.cc
+++ b/src/compiler/codegen/mips/fp_mips.cc
@@ -21,7 +21,7 @@
namespace art {
-bool genArithOpFloat(CompilationUnit *cUnit, Instruction::Code opcode, RegLocation rlDest,
+bool GenArithOpFloat(CompilationUnit *cUnit, Instruction::Code opcode, RegLocation rlDest,
RegLocation rlSrc1, RegLocation rlSrc2)
{
#ifdef __mips_hard_float
@@ -52,24 +52,24 @@
case Instruction::REM_FLOAT_2ADDR:
case Instruction::REM_FLOAT:
case Instruction::NEG_FLOAT: {
- return genArithOpFloatPortable(cUnit, opcode, rlDest, rlSrc1, rlSrc2);
+ return GenArithOpFloatPortable(cUnit, opcode, rlDest, rlSrc1, rlSrc2);
}
default:
return true;
}
- rlSrc1 = loadValue(cUnit, rlSrc1, kFPReg);
- rlSrc2 = loadValue(cUnit, rlSrc2, kFPReg);
- rlResult = oatEvalLoc(cUnit, rlDest, kFPReg, true);
- newLIR3(cUnit, op, rlResult.lowReg, rlSrc1.lowReg, rlSrc2.lowReg);
- storeValue(cUnit, rlDest, rlResult);
+ rlSrc1 = LoadValue(cUnit, rlSrc1, kFPReg);
+ rlSrc2 = LoadValue(cUnit, rlSrc2, kFPReg);
+ rlResult = EvalLoc(cUnit, rlDest, kFPReg, true);
+ NewLIR3(cUnit, op, rlResult.lowReg, rlSrc1.lowReg, rlSrc2.lowReg);
+ StoreValue(cUnit, rlDest, rlResult);
return false;
#else
- return genArithOpFloatPortable(cUnit, opcode, rlDest, rlSrc1, rlSrc2);
+ return GenArithOpFloatPortable(cUnit, opcode, rlDest, rlSrc1, rlSrc2);
#endif
}
-bool genArithOpDouble(CompilationUnit *cUnit, Instruction::Code opcode,
+bool GenArithOpDouble(CompilationUnit *cUnit, Instruction::Code opcode,
RegLocation rlDest, RegLocation rlSrc1, RegLocation rlSrc2)
{
#ifdef __mips_hard_float
@@ -96,28 +96,28 @@
case Instruction::REM_DOUBLE_2ADDR:
case Instruction::REM_DOUBLE:
case Instruction::NEG_DOUBLE: {
- return genArithOpDoublePortable(cUnit, opcode, rlDest, rlSrc1, rlSrc2);
+ return GenArithOpDoublePortable(cUnit, opcode, rlDest, rlSrc1, rlSrc2);
}
default:
return true;
}
- rlSrc1 = loadValueWide(cUnit, rlSrc1, kFPReg);
+ rlSrc1 = LoadValueWide(cUnit, rlSrc1, kFPReg);
DCHECK(rlSrc1.wide);
- rlSrc2 = loadValueWide(cUnit, rlSrc2, kFPReg);
+ rlSrc2 = LoadValueWide(cUnit, rlSrc2, kFPReg);
DCHECK(rlSrc2.wide);
- rlResult = oatEvalLoc(cUnit, rlDest, kFPReg, true);
+ rlResult = EvalLoc(cUnit, rlDest, kFPReg, true);
DCHECK(rlDest.wide);
DCHECK(rlResult.wide);
- newLIR3(cUnit, op, s2d(rlResult.lowReg, rlResult.highReg), s2d(rlSrc1.lowReg, rlSrc1.highReg),
- s2d(rlSrc2.lowReg, rlSrc2.highReg));
- storeValueWide(cUnit, rlDest, rlResult);
+ NewLIR3(cUnit, op, S2d(rlResult.lowReg, rlResult.highReg), S2d(rlSrc1.lowReg, rlSrc1.highReg),
+ S2d(rlSrc2.lowReg, rlSrc2.highReg));
+ StoreValueWide(cUnit, rlDest, rlResult);
return false;
#else
- return genArithOpDoublePortable(cUnit, opcode, rlDest, rlSrc1, rlSrc2);
+ return GenArithOpDoublePortable(cUnit, opcode, rlDest, rlSrc1, rlSrc2);
#endif
}
-bool genConversion(CompilationUnit *cUnit, Instruction::Code opcode, RegLocation rlDest,
+bool GenConversion(CompilationUnit *cUnit, Instruction::Code opcode, RegLocation rlDest,
RegLocation rlSrc)
{
#ifdef __mips_hard_float
@@ -143,33 +143,33 @@
case Instruction::FLOAT_TO_LONG:
case Instruction::LONG_TO_FLOAT:
case Instruction::DOUBLE_TO_LONG:
- return genConversionPortable(cUnit, opcode, rlDest, rlSrc);
+ return GenConversionPortable(cUnit, opcode, rlDest, rlSrc);
default:
return true;
}
if (rlSrc.wide) {
- rlSrc = loadValueWide(cUnit, rlSrc, kFPReg);
- srcReg = s2d(rlSrc.lowReg, rlSrc.highReg);
+ rlSrc = LoadValueWide(cUnit, rlSrc, kFPReg);
+ srcReg = S2d(rlSrc.lowReg, rlSrc.highReg);
} else {
- rlSrc = loadValue(cUnit, rlSrc, kFPReg);
+ rlSrc = LoadValue(cUnit, rlSrc, kFPReg);
srcReg = rlSrc.lowReg;
}
if (rlDest.wide) {
- rlResult = oatEvalLoc(cUnit, rlDest, kFPReg, true);
- newLIR2(cUnit, op, s2d(rlResult.lowReg, rlResult.highReg), srcReg);
- storeValueWide(cUnit, rlDest, rlResult);
+ rlResult = EvalLoc(cUnit, rlDest, kFPReg, true);
+ NewLIR2(cUnit, op, S2d(rlResult.lowReg, rlResult.highReg), srcReg);
+ StoreValueWide(cUnit, rlDest, rlResult);
} else {
- rlResult = oatEvalLoc(cUnit, rlDest, kFPReg, true);
- newLIR2(cUnit, op, rlResult.lowReg, srcReg);
- storeValue(cUnit, rlDest, rlResult);
+ rlResult = EvalLoc(cUnit, rlDest, kFPReg, true);
+ NewLIR2(cUnit, op, rlResult.lowReg, srcReg);
+ StoreValue(cUnit, rlDest, rlResult);
}
return false;
#else
- return genConversionPortable(cUnit, opcode, rlDest, rlSrc);
+ return GenConversionPortable(cUnit, opcode, rlDest, rlSrc);
#endif
}
-bool genCmpFP(CompilationUnit *cUnit, Instruction::Code opcode, RegLocation rlDest,
+bool GenCmpFP(CompilationUnit *cUnit, Instruction::Code opcode, RegLocation rlDest,
RegLocation rlSrc1, RegLocation rlSrc2)
{
bool wide = true;
@@ -193,49 +193,49 @@
default:
return true;
}
- oatFlushAllRegs(cUnit);
- oatLockCallTemps(cUnit);
+ FlushAllRegs(cUnit);
+ LockCallTemps(cUnit);
if (wide) {
- loadValueDirectWideFixed(cUnit, rlSrc1, rMIPS_FARG0, rMIPS_FARG1);
- loadValueDirectWideFixed(cUnit, rlSrc2, rMIPS_FARG2, rMIPS_FARG3);
+ LoadValueDirectWideFixed(cUnit, rlSrc1, rMIPS_FARG0, rMIPS_FARG1);
+ LoadValueDirectWideFixed(cUnit, rlSrc2, rMIPS_FARG2, rMIPS_FARG3);
} else {
- loadValueDirectFixed(cUnit, rlSrc1, rMIPS_FARG0);
- loadValueDirectFixed(cUnit, rlSrc2, rMIPS_FARG2);
+ LoadValueDirectFixed(cUnit, rlSrc1, rMIPS_FARG0);
+ LoadValueDirectFixed(cUnit, rlSrc2, rMIPS_FARG2);
}
- int rTgt = loadHelper(cUnit, offset);
+ int rTgt = LoadHelper(cUnit, offset);
// NOTE: not a safepoint
- opReg(cUnit, kOpBlx, rTgt);
- RegLocation rlResult = oatGetReturn(cUnit, false);
- storeValue(cUnit, rlDest, rlResult);
+ OpReg(cUnit, kOpBlx, rTgt);
+ RegLocation rlResult = GetReturn(cUnit, false);
+ StoreValue(cUnit, rlDest, rlResult);
return false;
}
-void genFusedFPCmpBranch(CompilationUnit* cUnit, BasicBlock* bb, MIR* mir,
+void GenFusedFPCmpBranch(CompilationUnit* cUnit, BasicBlock* bb, MIR* mir,
bool gtBias, bool isDouble)
{
UNIMPLEMENTED(FATAL) << "Need codegen for fused fp cmp branch";
}
-void genNegFloat(CompilationUnit *cUnit, RegLocation rlDest, RegLocation rlSrc)
+void GenNegFloat(CompilationUnit *cUnit, RegLocation rlDest, RegLocation rlSrc)
{
RegLocation rlResult;
- rlSrc = loadValue(cUnit, rlSrc, kCoreReg);
- rlResult = oatEvalLoc(cUnit, rlDest, kCoreReg, true);
- opRegRegImm(cUnit, kOpAdd, rlResult.lowReg, rlSrc.lowReg, 0x80000000);
- storeValue(cUnit, rlDest, rlResult);
+ rlSrc = LoadValue(cUnit, rlSrc, kCoreReg);
+ rlResult = EvalLoc(cUnit, rlDest, kCoreReg, true);
+ OpRegRegImm(cUnit, kOpAdd, rlResult.lowReg, rlSrc.lowReg, 0x80000000);
+ StoreValue(cUnit, rlDest, rlResult);
}
-void genNegDouble(CompilationUnit *cUnit, RegLocation rlDest, RegLocation rlSrc)
+void GenNegDouble(CompilationUnit *cUnit, RegLocation rlDest, RegLocation rlSrc)
{
RegLocation rlResult;
- rlSrc = loadValueWide(cUnit, rlSrc, kCoreReg);
- rlResult = oatEvalLoc(cUnit, rlDest, kCoreReg, true);
- opRegRegImm(cUnit, kOpAdd, rlResult.highReg, rlSrc.highReg, 0x80000000);
- opRegCopy(cUnit, rlResult.lowReg, rlSrc.lowReg);
- storeValueWide(cUnit, rlDest, rlResult);
+ rlSrc = LoadValueWide(cUnit, rlSrc, kCoreReg);
+ rlResult = EvalLoc(cUnit, rlDest, kCoreReg, true);
+ OpRegRegImm(cUnit, kOpAdd, rlResult.highReg, rlSrc.highReg, 0x80000000);
+ OpRegCopy(cUnit, rlResult.lowReg, rlSrc.lowReg);
+ StoreValueWide(cUnit, rlDest, rlResult);
}
-bool genInlinedMinMaxInt(CompilationUnit *cUnit, CallInfo* info, bool isMin)
+bool GenInlinedMinMaxInt(CompilationUnit *cUnit, CallInfo* info, bool isMin)
{
// TODO: need Mips implementation
return false;
diff --git a/src/compiler/codegen/mips/int_mips.cc b/src/compiler/codegen/mips/int_mips.cc
index 297a5d92..29b08ed 100644
--- a/src/compiler/codegen/mips/int_mips.cc
+++ b/src/compiler/codegen/mips/int_mips.cc
@@ -39,29 +39,29 @@
* finish:
*
*/
-void genCmpLong(CompilationUnit* cUnit, RegLocation rlDest,
+void GenCmpLong(CompilationUnit* cUnit, RegLocation rlDest,
RegLocation rlSrc1, RegLocation rlSrc2)
{
- rlSrc1 = loadValueWide(cUnit, rlSrc1, kCoreReg);
- rlSrc2 = loadValueWide(cUnit, rlSrc2, kCoreReg);
- int t0 = oatAllocTemp(cUnit);
- int t1 = oatAllocTemp(cUnit);
- RegLocation rlResult = oatEvalLoc(cUnit, rlDest, kCoreReg, true);
- newLIR3(cUnit, kMipsSlt, t0, rlSrc1.highReg, rlSrc2.highReg);
- newLIR3(cUnit, kMipsSlt, t1, rlSrc2.highReg, rlSrc1.highReg);
- newLIR3(cUnit, kMipsSubu, rlResult.lowReg, t1, t0);
- LIR* branch = opCmpImmBranch(cUnit, kCondNe, rlResult.lowReg, 0, NULL);
- newLIR3(cUnit, kMipsSltu, t0, rlSrc1.lowReg, rlSrc2.lowReg);
- newLIR3(cUnit, kMipsSltu, t1, rlSrc2.lowReg, rlSrc1.lowReg);
- newLIR3(cUnit, kMipsSubu, rlResult.lowReg, t1, t0);
- oatFreeTemp(cUnit, t0);
- oatFreeTemp(cUnit, t1);
- LIR* target = newLIR0(cUnit, kPseudoTargetLabel);
+ rlSrc1 = LoadValueWide(cUnit, rlSrc1, kCoreReg);
+ rlSrc2 = LoadValueWide(cUnit, rlSrc2, kCoreReg);
+ int t0 = AllocTemp(cUnit);
+ int t1 = AllocTemp(cUnit);
+ RegLocation rlResult = EvalLoc(cUnit, rlDest, kCoreReg, true);
+ NewLIR3(cUnit, kMipsSlt, t0, rlSrc1.highReg, rlSrc2.highReg);
+ NewLIR3(cUnit, kMipsSlt, t1, rlSrc2.highReg, rlSrc1.highReg);
+ NewLIR3(cUnit, kMipsSubu, rlResult.lowReg, t1, t0);
+ LIR* branch = OpCmpImmBranch(cUnit, kCondNe, rlResult.lowReg, 0, NULL);
+ NewLIR3(cUnit, kMipsSltu, t0, rlSrc1.lowReg, rlSrc2.lowReg);
+ NewLIR3(cUnit, kMipsSltu, t1, rlSrc2.lowReg, rlSrc1.lowReg);
+ NewLIR3(cUnit, kMipsSubu, rlResult.lowReg, t1, t0);
+ FreeTemp(cUnit, t0);
+ FreeTemp(cUnit, t1);
+ LIR* target = NewLIR0(cUnit, kPseudoTargetLabel);
branch->target = target;
- storeValue(cUnit, rlDest, rlResult);
+ StoreValue(cUnit, rlDest, rlResult);
}
-LIR* opCmpBranch(CompilationUnit* cUnit, ConditionCode cond, int src1,
+LIR* OpCmpBranch(CompilationUnit* cUnit, ConditionCode cond, int src1,
int src2, LIR* target)
{
LIR* branch;
@@ -114,31 +114,31 @@
return NULL;
}
if (cmpZero) {
- branch = newLIR2(cUnit, brOp, src1, src2);
+ branch = NewLIR2(cUnit, brOp, src1, src2);
} else {
- int tReg = oatAllocTemp(cUnit);
+ int tReg = AllocTemp(cUnit);
if (swapped) {
- newLIR3(cUnit, sltOp, tReg, src2, src1);
+ NewLIR3(cUnit, sltOp, tReg, src2, src1);
} else {
- newLIR3(cUnit, sltOp, tReg, src1, src2);
+ NewLIR3(cUnit, sltOp, tReg, src1, src2);
}
- branch = newLIR1(cUnit, brOp, tReg);
- oatFreeTemp(cUnit, tReg);
+ branch = NewLIR1(cUnit, brOp, tReg);
+ FreeTemp(cUnit, tReg);
}
branch->target = target;
return branch;
}
-LIR* opCmpImmBranch(CompilationUnit* cUnit, ConditionCode cond, int reg,
+LIR* OpCmpImmBranch(CompilationUnit* cUnit, ConditionCode cond, int reg,
int checkValue, LIR* target)
{
LIR* branch;
if (checkValue != 0) {
// TUNING: handle s16 & kCondLt/Mi case using slti
- int tReg = oatAllocTemp(cUnit);
- loadConstant(cUnit, tReg, checkValue);
- branch = opCmpBranch(cUnit, cond, reg, tReg, target);
- oatFreeTemp(cUnit, tReg);
+ int tReg = AllocTemp(cUnit);
+ LoadConstant(cUnit, tReg, checkValue);
+ branch = OpCmpBranch(cUnit, cond, reg, tReg, target);
+ FreeTemp(cUnit, tReg);
return branch;
}
MipsOpCode opc;
@@ -152,24 +152,24 @@
case kCondNe: opc = kMipsBnez; break;
default:
// Tuning: use slti when applicable
- int tReg = oatAllocTemp(cUnit);
- loadConstant(cUnit, tReg, checkValue);
- branch = opCmpBranch(cUnit, cond, reg, tReg, target);
- oatFreeTemp(cUnit, tReg);
+ int tReg = AllocTemp(cUnit);
+ LoadConstant(cUnit, tReg, checkValue);
+ branch = OpCmpBranch(cUnit, cond, reg, tReg, target);
+ FreeTemp(cUnit, tReg);
return branch;
}
- branch = newLIR1(cUnit, opc, reg);
+ branch = NewLIR1(cUnit, opc, reg);
branch->target = target;
return branch;
}
-LIR* opRegCopyNoInsert(CompilationUnit *cUnit, int rDest, int rSrc)
+LIR* OpRegCopyNoInsert(CompilationUnit *cUnit, int rDest, int rSrc)
{
#ifdef __mips_hard_float
if (MIPS_FPREG(rDest) || MIPS_FPREG(rSrc))
- return fpRegCopy(cUnit, rDest, rSrc);
+ return FpRegCopy(cUnit, rDest, rSrc);
#endif
- LIR* res = rawLIR(cUnit, cUnit->currentDalvikOffset, kMipsMove,
+ LIR* res = RawLIR(cUnit, cUnit->currentDalvikOffset, kMipsMove,
rDest, rSrc);
if (!(cUnit->disableOpt & (1 << kSafeOptimizations)) && rDest == rSrc) {
res->flags.isNop = true;
@@ -177,14 +177,14 @@
return res;
}
-LIR* opRegCopy(CompilationUnit *cUnit, int rDest, int rSrc)
+LIR* OpRegCopy(CompilationUnit *cUnit, int rDest, int rSrc)
{
- LIR *res = opRegCopyNoInsert(cUnit, rDest, rSrc);
- oatAppendLIR(cUnit, res);
+ LIR *res = OpRegCopyNoInsert(cUnit, rDest, rSrc);
+ AppendLIR(cUnit, res);
return res;
}
-void opRegCopyWide(CompilationUnit *cUnit, int destLo, int destHi,
+void OpRegCopyWide(CompilationUnit *cUnit, int destLo, int destHi,
int srcLo, int srcHi)
{
#ifdef __mips_hard_float
@@ -194,169 +194,169 @@
assert(MIPS_FPREG(destLo) == MIPS_FPREG(destHi));
if (destFP) {
if (srcFP) {
- opRegCopy(cUnit, s2d(destLo, destHi), s2d(srcLo, srcHi));
+ OpRegCopy(cUnit, S2d(destLo, destHi), S2d(srcLo, srcHi));
} else {
/* note the operands are swapped for the mtc1 instr */
- newLIR2(cUnit, kMipsMtc1, srcLo, destLo);
- newLIR2(cUnit, kMipsMtc1, srcHi, destHi);
+ NewLIR2(cUnit, kMipsMtc1, srcLo, destLo);
+ NewLIR2(cUnit, kMipsMtc1, srcHi, destHi);
}
} else {
if (srcFP) {
- newLIR2(cUnit, kMipsMfc1, destLo, srcLo);
- newLIR2(cUnit, kMipsMfc1, destHi, srcHi);
+ NewLIR2(cUnit, kMipsMfc1, destLo, srcLo);
+ NewLIR2(cUnit, kMipsMfc1, destHi, srcHi);
} else {
// Handle overlap
if (srcHi == destLo) {
- opRegCopy(cUnit, destHi, srcHi);
- opRegCopy(cUnit, destLo, srcLo);
+ OpRegCopy(cUnit, destHi, srcHi);
+ OpRegCopy(cUnit, destLo, srcLo);
} else {
- opRegCopy(cUnit, destLo, srcLo);
- opRegCopy(cUnit, destHi, srcHi);
+ OpRegCopy(cUnit, destLo, srcLo);
+ OpRegCopy(cUnit, destHi, srcHi);
}
}
}
#else
// Handle overlap
if (srcHi == destLo) {
- opRegCopy(cUnit, destHi, srcHi);
- opRegCopy(cUnit, destLo, srcLo);
+ OpRegCopy(cUnit, destHi, srcHi);
+ OpRegCopy(cUnit, destLo, srcLo);
} else {
- opRegCopy(cUnit, destLo, srcLo);
- opRegCopy(cUnit, destHi, srcHi);
+ OpRegCopy(cUnit, destLo, srcLo);
+ OpRegCopy(cUnit, destHi, srcHi);
}
#endif
}
-void genFusedLongCmpBranch(CompilationUnit* cUnit, BasicBlock* bb, MIR* mir)
+void GenFusedLongCmpBranch(CompilationUnit* cUnit, BasicBlock* bb, MIR* mir)
{
UNIMPLEMENTED(FATAL) << "Need codegen for fused long cmp branch";
}
-LIR* genRegMemCheck(CompilationUnit* cUnit, ConditionCode cCode,
+LIR* GenRegMemCheck(CompilationUnit* cUnit, ConditionCode cCode,
int reg1, int base, int offset, ThrowKind kind)
{
- LOG(FATAL) << "Unexpected use of genRegMemCheck for Arm";
+ LOG(FATAL) << "Unexpected use of GenRegMemCheck for Arm";
return NULL;
}
-RegLocation genDivRem(CompilationUnit* cUnit, RegLocation rlDest, int reg1, int reg2, bool isDiv)
+RegLocation GenDivRem(CompilationUnit* cUnit, RegLocation rlDest, int reg1, int reg2, bool isDiv)
{
- newLIR4(cUnit, kMipsDiv, r_HI, r_LO, reg1, reg2);
- RegLocation rlResult = oatEvalLoc(cUnit, rlDest, kCoreReg, true);
+ NewLIR4(cUnit, kMipsDiv, r_HI, r_LO, reg1, reg2);
+ RegLocation rlResult = EvalLoc(cUnit, rlDest, kCoreReg, true);
if (isDiv) {
- newLIR2(cUnit, kMipsMflo, rlResult.lowReg, r_LO);
+ NewLIR2(cUnit, kMipsMflo, rlResult.lowReg, r_LO);
} else {
- newLIR2(cUnit, kMipsMfhi, rlResult.lowReg, r_HI);
+ NewLIR2(cUnit, kMipsMfhi, rlResult.lowReg, r_HI);
}
return rlResult;
}
-RegLocation genDivRemLit(CompilationUnit* cUnit, RegLocation rlDest, int reg1, int lit, bool isDiv)
+RegLocation GenDivRemLit(CompilationUnit* cUnit, RegLocation rlDest, int reg1, int lit, bool isDiv)
{
- int tReg = oatAllocTemp(cUnit);
- newLIR3(cUnit, kMipsAddiu, tReg, r_ZERO, lit);
- newLIR4(cUnit, kMipsDiv, r_HI, r_LO, reg1, tReg);
- RegLocation rlResult = oatEvalLoc(cUnit, rlDest, kCoreReg, true);
+ int tReg = AllocTemp(cUnit);
+ NewLIR3(cUnit, kMipsAddiu, tReg, r_ZERO, lit);
+ NewLIR4(cUnit, kMipsDiv, r_HI, r_LO, reg1, tReg);
+ RegLocation rlResult = EvalLoc(cUnit, rlDest, kCoreReg, true);
if (isDiv) {
- newLIR2(cUnit, kMipsMflo, rlResult.lowReg, r_LO);
+ NewLIR2(cUnit, kMipsMflo, rlResult.lowReg, r_LO);
} else {
- newLIR2(cUnit, kMipsMfhi, rlResult.lowReg, r_HI);
+ NewLIR2(cUnit, kMipsMfhi, rlResult.lowReg, r_HI);
}
- oatFreeTemp(cUnit, tReg);
+ FreeTemp(cUnit, tReg);
return rlResult;
}
-void opLea(CompilationUnit* cUnit, int rBase, int reg1, int reg2, int scale, int offset)
+void OpLea(CompilationUnit* cUnit, int rBase, int reg1, int reg2, int scale, int offset)
{
- LOG(FATAL) << "Unexpected use of opLea for Arm";
+ LOG(FATAL) << "Unexpected use of OpLea for Arm";
}
-void opTlsCmp(CompilationUnit* cUnit, int offset, int val)
+void OpTlsCmp(CompilationUnit* cUnit, int offset, int val)
{
- LOG(FATAL) << "Unexpected use of opTlsCmp for Arm";
+ LOG(FATAL) << "Unexpected use of OpTlsCmp for Arm";
}
-bool genInlinedCas32(CompilationUnit* cUnit, CallInfo* info, bool need_write_barrier) {
+bool GenInlinedCas32(CompilationUnit* cUnit, CallInfo* info, bool need_write_barrier) {
DCHECK_NE(cUnit->instructionSet, kThumb2);
return false;
}
-bool genInlinedSqrt(CompilationUnit* cUnit, CallInfo* info) {
+bool GenInlinedSqrt(CompilationUnit* cUnit, CallInfo* info) {
DCHECK_NE(cUnit->instructionSet, kThumb2);
return false;
}
-LIR* opPcRelLoad(CompilationUnit* cUnit, int reg, LIR* target) {
- LOG(FATAL) << "Unexpected use of opPcRelLoad for Mips";
+LIR* OpPcRelLoad(CompilationUnit* cUnit, int reg, LIR* target) {
+ LOG(FATAL) << "Unexpected use of OpPcRelLoad for Mips";
return NULL;
}
-LIR* opVldm(CompilationUnit* cUnit, int rBase, int count)
+LIR* OpVldm(CompilationUnit* cUnit, int rBase, int count)
{
- LOG(FATAL) << "Unexpected use of opVldm for Mips";
+ LOG(FATAL) << "Unexpected use of OpVldm for Mips";
return NULL;
}
-LIR* opVstm(CompilationUnit* cUnit, int rBase, int count)
+LIR* OpVstm(CompilationUnit* cUnit, int rBase, int count)
{
- LOG(FATAL) << "Unexpected use of opVstm for Mips";
+ LOG(FATAL) << "Unexpected use of OpVstm for Mips";
return NULL;
}
-void genMultiplyByTwoBitMultiplier(CompilationUnit* cUnit, RegLocation rlSrc,
+void GenMultiplyByTwoBitMultiplier(CompilationUnit* cUnit, RegLocation rlSrc,
RegLocation rlResult, int lit,
int firstBit, int secondBit)
{
- int tReg = oatAllocTemp(cUnit);
- opRegRegImm(cUnit, kOpLsl, tReg, rlSrc.lowReg, secondBit - firstBit);
- opRegRegReg(cUnit, kOpAdd, rlResult.lowReg, rlSrc.lowReg, tReg);
- oatFreeTemp(cUnit, tReg);
+ int tReg = AllocTemp(cUnit);
+ OpRegRegImm(cUnit, kOpLsl, tReg, rlSrc.lowReg, secondBit - firstBit);
+ OpRegRegReg(cUnit, kOpAdd, rlResult.lowReg, rlSrc.lowReg, tReg);
+ FreeTemp(cUnit, tReg);
if (firstBit != 0) {
- opRegRegImm(cUnit, kOpLsl, rlResult.lowReg, rlResult.lowReg, firstBit);
+ OpRegRegImm(cUnit, kOpLsl, rlResult.lowReg, rlResult.lowReg, firstBit);
}
}
-void genDivZeroCheck(CompilationUnit* cUnit, int regLo, int regHi)
+void GenDivZeroCheck(CompilationUnit* cUnit, int regLo, int regHi)
{
- int tReg = oatAllocTemp(cUnit);
- opRegRegReg(cUnit, kOpOr, tReg, regLo, regHi);
- genImmedCheck(cUnit, kCondEq, tReg, 0, kThrowDivZero);
- oatFreeTemp(cUnit, tReg);
+ int tReg = AllocTemp(cUnit);
+ OpRegRegReg(cUnit, kOpOr, tReg, regLo, regHi);
+ GenImmedCheck(cUnit, kCondEq, tReg, 0, kThrowDivZero);
+ FreeTemp(cUnit, tReg);
}
// Test suspend flag, return target of taken suspend branch
-LIR* opTestSuspend(CompilationUnit* cUnit, LIR* target)
+LIR* OpTestSuspend(CompilationUnit* cUnit, LIR* target)
{
- opRegImm(cUnit, kOpSub, rMIPS_SUSPEND, 1);
- return opCmpImmBranch(cUnit, (target == NULL) ? kCondEq : kCondNe, rMIPS_SUSPEND, 0, target);
+ OpRegImm(cUnit, kOpSub, rMIPS_SUSPEND, 1);
+ return OpCmpImmBranch(cUnit, (target == NULL) ? kCondEq : kCondNe, rMIPS_SUSPEND, 0, target);
}
// Decrement register and branch on condition
-LIR* opDecAndBranch(CompilationUnit* cUnit, ConditionCode cCode, int reg, LIR* target)
+LIR* OpDecAndBranch(CompilationUnit* cUnit, ConditionCode cCode, int reg, LIR* target)
{
- opRegImm(cUnit, kOpSub, reg, 1);
- return opCmpImmBranch(cUnit, cCode, reg, 0, target);
+ OpRegImm(cUnit, kOpSub, reg, 1);
+ return OpCmpImmBranch(cUnit, cCode, reg, 0, target);
}
-bool smallLiteralDivide(CompilationUnit* cUnit, Instruction::Code dalvikOpcode,
+bool SmallLiteralDivide(CompilationUnit* cUnit, Instruction::Code dalvikOpcode,
RegLocation rlSrc, RegLocation rlDest, int lit)
{
LOG(FATAL) << "Unexpected use of smallLiteralDive in Mips";
return false;
}
-LIR* opIT(CompilationUnit* cUnit, ArmConditionCode cond, const char* guide)
+LIR* OpIT(CompilationUnit* cUnit, ArmConditionCode cond, const char* guide)
{
- LOG(FATAL) << "Unexpected use of opIT in Mips";
+ LOG(FATAL) << "Unexpected use of OpIT in Mips";
return NULL;
}
-bool genAddLong(CompilationUnit* cUnit, RegLocation rlDest,
+bool GenAddLong(CompilationUnit* cUnit, RegLocation rlDest,
RegLocation rlSrc1, RegLocation rlSrc2)
{
- rlSrc1 = loadValueWide(cUnit, rlSrc1, kCoreReg);
- rlSrc2 = loadValueWide(cUnit, rlSrc2, kCoreReg);
- RegLocation rlResult = oatEvalLoc(cUnit, rlDest, kCoreReg, true);
+ rlSrc1 = LoadValueWide(cUnit, rlSrc1, kCoreReg);
+ rlSrc2 = LoadValueWide(cUnit, rlSrc2, kCoreReg);
+ RegLocation rlResult = EvalLoc(cUnit, rlDest, kCoreReg, true);
/*
* [v1 v0] = [a1 a0] + [a3 a2];
* addu v0,a2,a0
@@ -365,22 +365,22 @@
* addu v1,v1,t1
*/
- opRegRegReg(cUnit, kOpAdd, rlResult.lowReg, rlSrc2.lowReg, rlSrc1.lowReg);
- int tReg = oatAllocTemp(cUnit);
- opRegRegReg(cUnit, kOpAdd, tReg, rlSrc2.highReg, rlSrc1.highReg);
- newLIR3(cUnit, kMipsSltu, rlResult.highReg, rlResult.lowReg, rlSrc2.lowReg);
- opRegRegReg(cUnit, kOpAdd, rlResult.highReg, rlResult.highReg, tReg);
- oatFreeTemp(cUnit, tReg);
- storeValueWide(cUnit, rlDest, rlResult);
+ OpRegRegReg(cUnit, kOpAdd, rlResult.lowReg, rlSrc2.lowReg, rlSrc1.lowReg);
+ int tReg = AllocTemp(cUnit);
+ OpRegRegReg(cUnit, kOpAdd, tReg, rlSrc2.highReg, rlSrc1.highReg);
+ NewLIR3(cUnit, kMipsSltu, rlResult.highReg, rlResult.lowReg, rlSrc2.lowReg);
+ OpRegRegReg(cUnit, kOpAdd, rlResult.highReg, rlResult.highReg, tReg);
+ FreeTemp(cUnit, tReg);
+ StoreValueWide(cUnit, rlDest, rlResult);
return false;
}
-bool genSubLong(CompilationUnit* cUnit, RegLocation rlDest,
+bool GenSubLong(CompilationUnit* cUnit, RegLocation rlDest,
RegLocation rlSrc1, RegLocation rlSrc2)
{
- rlSrc1 = loadValueWide(cUnit, rlSrc1, kCoreReg);
- rlSrc2 = loadValueWide(cUnit, rlSrc2, kCoreReg);
- RegLocation rlResult = oatEvalLoc(cUnit, rlDest, kCoreReg, true);
+ rlSrc1 = LoadValueWide(cUnit, rlSrc1, kCoreReg);
+ rlSrc2 = LoadValueWide(cUnit, rlSrc2, kCoreReg);
+ RegLocation rlResult = EvalLoc(cUnit, rlDest, kCoreReg, true);
/*
* [v1 v0] = [a1 a0] - [a3 a2];
* sltu t1,a0,a2
@@ -389,21 +389,21 @@
* subu v1,v1,t1
*/
- int tReg = oatAllocTemp(cUnit);
- newLIR3(cUnit, kMipsSltu, tReg, rlSrc1.lowReg, rlSrc2.lowReg);
- opRegRegReg(cUnit, kOpSub, rlResult.lowReg, rlSrc1.lowReg, rlSrc2.lowReg);
- opRegRegReg(cUnit, kOpSub, rlResult.highReg, rlSrc1.highReg, rlSrc2.highReg);
- opRegRegReg(cUnit, kOpSub, rlResult.highReg, rlResult.highReg, tReg);
- oatFreeTemp(cUnit, tReg);
- storeValueWide(cUnit, rlDest, rlResult);
+ int tReg = AllocTemp(cUnit);
+ NewLIR3(cUnit, kMipsSltu, tReg, rlSrc1.lowReg, rlSrc2.lowReg);
+ OpRegRegReg(cUnit, kOpSub, rlResult.lowReg, rlSrc1.lowReg, rlSrc2.lowReg);
+ OpRegRegReg(cUnit, kOpSub, rlResult.highReg, rlSrc1.highReg, rlSrc2.highReg);
+ OpRegRegReg(cUnit, kOpSub, rlResult.highReg, rlResult.highReg, tReg);
+ FreeTemp(cUnit, tReg);
+ StoreValueWide(cUnit, rlDest, rlResult);
return false;
}
-bool genNegLong(CompilationUnit* cUnit, RegLocation rlDest,
+bool GenNegLong(CompilationUnit* cUnit, RegLocation rlDest,
RegLocation rlSrc)
{
- rlSrc = loadValueWide(cUnit, rlSrc, kCoreReg);
- RegLocation rlResult = oatEvalLoc(cUnit, rlDest, kCoreReg, true);
+ rlSrc = LoadValueWide(cUnit, rlSrc, kCoreReg);
+ RegLocation rlResult = EvalLoc(cUnit, rlDest, kCoreReg, true);
/*
* [v1 v0] = -[a1 a0]
* negu v0,a0
@@ -412,34 +412,34 @@
* subu v1,v1,t1
*/
- opRegReg(cUnit, kOpNeg, rlResult.lowReg, rlSrc.lowReg);
- opRegReg(cUnit, kOpNeg, rlResult.highReg, rlSrc.highReg);
- int tReg = oatAllocTemp(cUnit);
- newLIR3(cUnit, kMipsSltu, tReg, r_ZERO, rlResult.lowReg);
- opRegRegReg(cUnit, kOpSub, rlResult.highReg, rlResult.highReg, tReg);
- oatFreeTemp(cUnit, tReg);
- storeValueWide(cUnit, rlDest, rlResult);
+ OpRegReg(cUnit, kOpNeg, rlResult.lowReg, rlSrc.lowReg);
+ OpRegReg(cUnit, kOpNeg, rlResult.highReg, rlSrc.highReg);
+ int tReg = AllocTemp(cUnit);
+ NewLIR3(cUnit, kMipsSltu, tReg, r_ZERO, rlResult.lowReg);
+ OpRegRegReg(cUnit, kOpSub, rlResult.highReg, rlResult.highReg, tReg);
+ FreeTemp(cUnit, tReg);
+ StoreValueWide(cUnit, rlDest, rlResult);
return false;
}
-bool genAndLong(CompilationUnit* cUnit, RegLocation rlDest,
+bool GenAndLong(CompilationUnit* cUnit, RegLocation rlDest,
RegLocation rlSrc1, RegLocation rlSrc2)
{
- LOG(FATAL) << "Unexpected use of genAndLong for Mips";
+ LOG(FATAL) << "Unexpected use of GenAndLong for Mips";
return false;
}
-bool genOrLong(CompilationUnit* cUnit, RegLocation rlDest,
+bool GenOrLong(CompilationUnit* cUnit, RegLocation rlDest,
RegLocation rlSrc1, RegLocation rlSrc2)
{
- LOG(FATAL) << "Unexpected use of genOrLong for Mips";
+ LOG(FATAL) << "Unexpected use of GenOrLong for Mips";
return false;
}
-bool genXorLong(CompilationUnit* cUnit, RegLocation rlDest,
+bool GenXorLong(CompilationUnit* cUnit, RegLocation rlDest,
RegLocation rlSrc1, RegLocation rlSrc2)
{
- LOG(FATAL) << "Unexpected use of genXorLong for Mips";
+ LOG(FATAL) << "Unexpected use of GenXorLong for Mips";
return false;
}
diff --git a/src/compiler/codegen/mips/target_mips.cc b/src/compiler/codegen/mips/target_mips.cc
index a3621f5..3623800 100644
--- a/src/compiler/codegen/mips/target_mips.cc
+++ b/src/compiler/codegen/mips/target_mips.cc
@@ -27,43 +27,43 @@
r_T0, r_T1, r_T2, r_T3, r_T4, r_T5, r_T6, r_T7,
r_S0, r_S1, r_S2, r_S3, r_S4, r_S5, r_S6, r_S7, r_T8,
r_T9, r_K0, r_K1, r_GP, r_SP, r_FP, r_RA};
-static int reservedRegs[] = {r_ZERO, r_AT, r_S0, r_S1, r_K0, r_K1, r_GP, r_SP,
+static int ReservedRegs[] = {r_ZERO, r_AT, r_S0, r_S1, r_K0, r_K1, r_GP, r_SP,
r_RA};
static int coreTemps[] = {r_V0, r_V1, r_A0, r_A1, r_A2, r_A3, r_T0, r_T1, r_T2,
r_T3, r_T4, r_T5, r_T6, r_T7, r_T8};
#ifdef __mips_hard_float
-static int fpRegs[] = {r_F0, r_F1, r_F2, r_F3, r_F4, r_F5, r_F6, r_F7,
+static int FpRegs[] = {r_F0, r_F1, r_F2, r_F3, r_F4, r_F5, r_F6, r_F7,
r_F8, r_F9, r_F10, r_F11, r_F12, r_F13, r_F14, r_F15};
static int fpTemps[] = {r_F0, r_F1, r_F2, r_F3, r_F4, r_F5, r_F6, r_F7,
r_F8, r_F9, r_F10, r_F11, r_F12, r_F13, r_F14, r_F15};
#endif
-RegLocation locCReturn()
+RegLocation LocCReturn()
{
RegLocation res = MIPS_LOC_C_RETURN;
return res;
}
-RegLocation locCReturnWide()
+RegLocation LocCReturnWide()
{
RegLocation res = MIPS_LOC_C_RETURN_WIDE;
return res;
}
-RegLocation locCReturnFloat()
+RegLocation LocCReturnFloat()
{
RegLocation res = MIPS_LOC_C_RETURN_FLOAT;
return res;
}
-RegLocation locCReturnDouble()
+RegLocation LocCReturnDouble()
{
RegLocation res = MIPS_LOC_C_RETURN_DOUBLE;
return res;
}
// Return a target-dependent special register.
-int targetReg(SpecialTargetRegister reg) {
+int TargetReg(SpecialTargetRegister reg) {
int res = INVALID_REG;
switch (reg) {
case kSelf: res = rMIPS_SELF; break;
@@ -88,37 +88,37 @@
}
// Create a double from a pair of singles.
-int s2d(int lowReg, int highReg)
+int S2d(int lowReg, int highReg)
{
return MIPS_S2D(lowReg, highReg);
}
// Is reg a single or double?
-bool fpReg(int reg)
+bool FpReg(int reg)
{
return MIPS_FPREG(reg);
}
// Is reg a single?
-bool singleReg(int reg)
+bool SingleReg(int reg)
{
return MIPS_SINGLEREG(reg);
}
// Is reg a double?
-bool doubleReg(int reg)
+bool DoubleReg(int reg)
{
return MIPS_DOUBLEREG(reg);
}
// Return mask to strip off fp reg flags and bias.
-uint32_t fpRegMask()
+uint32_t FpRegMask()
{
return MIPS_FP_REG_MASK;
}
// True if both regs single, both core or both double.
-bool sameRegType(int reg1, int reg2)
+bool SameRegType(int reg1, int reg2)
{
return (MIPS_REGTYPE(reg1) == MIPS_REGTYPE(reg2));
}
@@ -126,7 +126,7 @@
/*
* Decode the register id.
*/
-uint64_t getRegMaskCommon(CompilationUnit* cUnit, int reg)
+uint64_t GetRegMaskCommon(CompilationUnit* cUnit, int reg)
{
uint64_t seed;
int shift;
@@ -143,13 +143,13 @@
return (seed << shift);
}
-uint64_t getPCUseDefEncoding()
+uint64_t GetPCUseDefEncoding()
{
return ENCODE_MIPS_REG_PC;
}
-void setupTargetResourceMasks(CompilationUnit* cUnit, LIR* lir)
+void SetupTargetResourceMasks(CompilationUnit* cUnit, LIR* lir)
{
DCHECK_EQ(cUnit->instructionSet, kMips);
@@ -182,7 +182,7 @@
* Interpret a format string and build a string no longer than size
* See format key in Assemble.c.
*/
-std::string buildInsnString(const char *fmt, LIR *lir, unsigned char* baseAddr)
+std::string BuildInsnString(const char *fmt, LIR *lir, unsigned char* baseAddr)
{
std::string buf;
int i;
@@ -275,7 +275,7 @@
}
// FIXME: need to redo resource maps for MIPS - fix this at that time
-void oatDumpResourceMask(LIR *mipsLIR, uint64_t mask, const char *prefix)
+void DumpResourceMask(LIR *mipsLIR, uint64_t mask, const char *prefix)
{
char buf[256];
buf[0] = 0;
@@ -326,7 +326,7 @@
* machinery is in place, always spill lr.
*/
-void oatAdjustSpillMask(CompilationUnit* cUnit)
+void AdjustSpillMask(CompilationUnit* cUnit)
{
cUnit->coreSpillMask |= (1 << r_RA);
cUnit->numCoreSpills++;
@@ -338,15 +338,15 @@
* include any holes in the mask. Associate holes with
* Dalvik register INVALID_VREG (0xFFFFU).
*/
-void oatMarkPreservedSingle(CompilationUnit* cUnit, int sReg, int reg)
+void MarkPreservedSingle(CompilationUnit* cUnit, int sReg, int reg)
{
LOG(FATAL) << "No support yet for promoted FP regs";
}
-void oatFlushRegWide(CompilationUnit* cUnit, int reg1, int reg2)
+void FlushRegWide(CompilationUnit* cUnit, int reg1, int reg2)
{
- RegisterInfo* info1 = oatGetRegInfo(cUnit, reg1);
- RegisterInfo* info2 = oatGetRegInfo(cUnit, reg2);
+ RegisterInfo* info1 = GetRegInfo(cUnit, reg1);
+ RegisterInfo* info2 = GetRegInfo(cUnit, reg2);
DCHECK(info1 && info2 && info1->pair && info2->pair &&
(info1->partner == info2->reg) &&
(info2->partner == info1->reg));
@@ -361,130 +361,117 @@
if (SRegToVReg(cUnit, info2->sReg) < SRegToVReg(cUnit, info1->sReg))
info1 = info2;
int vReg = SRegToVReg(cUnit, info1->sReg);
- storeBaseDispWide(cUnit, rMIPS_SP, oatVRegOffset(cUnit, vReg), info1->reg, info1->partner);
+ StoreBaseDispWide(cUnit, rMIPS_SP, VRegOffset(cUnit, vReg), info1->reg, info1->partner);
}
}
-void oatFlushReg(CompilationUnit* cUnit, int reg)
+void FlushReg(CompilationUnit* cUnit, int reg)
{
- RegisterInfo* info = oatGetRegInfo(cUnit, reg);
+ RegisterInfo* info = GetRegInfo(cUnit, reg);
if (info->live && info->dirty) {
info->dirty = false;
int vReg = SRegToVReg(cUnit, info->sReg);
- storeBaseDisp(cUnit, rMIPS_SP, oatVRegOffset(cUnit, vReg), reg, kWord);
+ StoreBaseDisp(cUnit, rMIPS_SP, VRegOffset(cUnit, vReg), reg, kWord);
}
}
/* Give access to the target-dependent FP register encoding to common code */
-bool oatIsFpReg(int reg) {
+bool IsFpReg(int reg) {
return MIPS_FPREG(reg);
}
-uint32_t oatFpRegMask() {
- return MIPS_FP_REG_MASK;
-}
-
/* Clobber all regs that might be used by an external C call */
-extern void oatClobberCalleeSave(CompilationUnit *cUnit)
+extern void ClobberCalleeSave(CompilationUnit *cUnit)
{
- oatClobber(cUnit, r_ZERO);
- oatClobber(cUnit, r_AT);
- oatClobber(cUnit, r_V0);
- oatClobber(cUnit, r_V1);
- oatClobber(cUnit, r_A0);
- oatClobber(cUnit, r_A1);
- oatClobber(cUnit, r_A2);
- oatClobber(cUnit, r_A3);
- oatClobber(cUnit, r_T0);
- oatClobber(cUnit, r_T1);
- oatClobber(cUnit, r_T2);
- oatClobber(cUnit, r_T3);
- oatClobber(cUnit, r_T4);
- oatClobber(cUnit, r_T5);
- oatClobber(cUnit, r_T6);
- oatClobber(cUnit, r_T7);
- oatClobber(cUnit, r_T8);
- oatClobber(cUnit, r_T9);
- oatClobber(cUnit, r_K0);
- oatClobber(cUnit, r_K1);
- oatClobber(cUnit, r_GP);
- oatClobber(cUnit, r_FP);
- oatClobber(cUnit, r_RA);
- oatClobber(cUnit, r_F0);
- oatClobber(cUnit, r_F1);
- oatClobber(cUnit, r_F2);
- oatClobber(cUnit, r_F3);
- oatClobber(cUnit, r_F4);
- oatClobber(cUnit, r_F5);
- oatClobber(cUnit, r_F6);
- oatClobber(cUnit, r_F7);
- oatClobber(cUnit, r_F8);
- oatClobber(cUnit, r_F9);
- oatClobber(cUnit, r_F10);
- oatClobber(cUnit, r_F11);
- oatClobber(cUnit, r_F12);
- oatClobber(cUnit, r_F13);
- oatClobber(cUnit, r_F14);
- oatClobber(cUnit, r_F15);
+ Clobber(cUnit, r_ZERO);
+ Clobber(cUnit, r_AT);
+ Clobber(cUnit, r_V0);
+ Clobber(cUnit, r_V1);
+ Clobber(cUnit, r_A0);
+ Clobber(cUnit, r_A1);
+ Clobber(cUnit, r_A2);
+ Clobber(cUnit, r_A3);
+ Clobber(cUnit, r_T0);
+ Clobber(cUnit, r_T1);
+ Clobber(cUnit, r_T2);
+ Clobber(cUnit, r_T3);
+ Clobber(cUnit, r_T4);
+ Clobber(cUnit, r_T5);
+ Clobber(cUnit, r_T6);
+ Clobber(cUnit, r_T7);
+ Clobber(cUnit, r_T8);
+ Clobber(cUnit, r_T9);
+ Clobber(cUnit, r_K0);
+ Clobber(cUnit, r_K1);
+ Clobber(cUnit, r_GP);
+ Clobber(cUnit, r_FP);
+ Clobber(cUnit, r_RA);
+ Clobber(cUnit, r_F0);
+ Clobber(cUnit, r_F1);
+ Clobber(cUnit, r_F2);
+ Clobber(cUnit, r_F3);
+ Clobber(cUnit, r_F4);
+ Clobber(cUnit, r_F5);
+ Clobber(cUnit, r_F6);
+ Clobber(cUnit, r_F7);
+ Clobber(cUnit, r_F8);
+ Clobber(cUnit, r_F9);
+ Clobber(cUnit, r_F10);
+ Clobber(cUnit, r_F11);
+ Clobber(cUnit, r_F12);
+ Clobber(cUnit, r_F13);
+ Clobber(cUnit, r_F14);
+ Clobber(cUnit, r_F15);
}
-extern RegLocation oatGetReturnWideAlt(CompilationUnit* cUnit)
+extern RegLocation GetReturnWideAlt(CompilationUnit* cUnit)
{
- UNIMPLEMENTED(FATAL) << "No oatGetReturnWideAlt for MIPS";
- RegLocation res = locCReturnWide();
+ UNIMPLEMENTED(FATAL) << "No GetReturnWideAlt for MIPS";
+ RegLocation res = LocCReturnWide();
return res;
}
-extern RegLocation oatGetReturnAlt(CompilationUnit* cUnit)
+extern RegLocation GetReturnAlt(CompilationUnit* cUnit)
{
- UNIMPLEMENTED(FATAL) << "No oatGetReturnAlt for MIPS";
- RegLocation res = locCReturn();
+ UNIMPLEMENTED(FATAL) << "No GetReturnAlt for MIPS";
+ RegLocation res = LocCReturn();
return res;
}
-extern RegisterInfo* oatGetRegInfo(CompilationUnit* cUnit, int reg)
+extern RegisterInfo* GetRegInfo(CompilationUnit* cUnit, int reg)
{
return MIPS_FPREG(reg) ? &cUnit->regPool->FPRegs[reg & MIPS_FP_REG_MASK]
: &cUnit->regPool->coreRegs[reg];
}
/* To be used when explicitly managing register use */
-extern void oatLockCallTemps(CompilationUnit* cUnit)
+extern void LockCallTemps(CompilationUnit* cUnit)
{
- oatLockTemp(cUnit, rMIPS_ARG0);
- oatLockTemp(cUnit, rMIPS_ARG1);
- oatLockTemp(cUnit, rMIPS_ARG2);
- oatLockTemp(cUnit, rMIPS_ARG3);
+ LockTemp(cUnit, rMIPS_ARG0);
+ LockTemp(cUnit, rMIPS_ARG1);
+ LockTemp(cUnit, rMIPS_ARG2);
+ LockTemp(cUnit, rMIPS_ARG3);
}
/* To be used when explicitly managing register use */
-extern void oatFreeCallTemps(CompilationUnit* cUnit)
+extern void FreeCallTemps(CompilationUnit* cUnit)
{
- oatFreeTemp(cUnit, rMIPS_ARG0);
- oatFreeTemp(cUnit, rMIPS_ARG1);
- oatFreeTemp(cUnit, rMIPS_ARG2);
- oatFreeTemp(cUnit, rMIPS_ARG3);
-}
-
-/*
- * Determine the initial instruction set to be used for this trace.
- * Later components may decide to change this.
- */
-InstructionSet oatInstructionSet()
-{
- return kMips;
+ FreeTemp(cUnit, rMIPS_ARG0);
+ FreeTemp(cUnit, rMIPS_ARG1);
+ FreeTemp(cUnit, rMIPS_ARG2);
+ FreeTemp(cUnit, rMIPS_ARG3);
}
/* Architecture-specific initializations and checks go here */
-bool oatArchVariantInit(void)
+bool ArchVariantInit(void)
{
return true;
}
-void oatGenMemBarrier(CompilationUnit *cUnit, MemBarrierKind barrierKind)
+void GenMemBarrier(CompilationUnit *cUnit, MemBarrierKind barrierKind)
{
#if ANDROID_SMP != 0
- newLIR1(cUnit, kMipsSync, 0 /* Only stype currently supported */);
+ NewLIR1(cUnit, kMipsSync, 0 /* Only stype currently supported */);
#endif
}
@@ -492,7 +479,7 @@
* Alloc a pair of core registers, or a double. Low reg in low byte,
* high reg in next byte.
*/
-int oatAllocTypedTempPair(CompilationUnit *cUnit, bool fpHint,
+int AllocTypedTempPair(CompilationUnit *cUnit, bool fpHint,
int regClass)
{
int highReg;
@@ -501,71 +488,71 @@
#ifdef __mips_hard_float
if (((regClass == kAnyReg) && fpHint) || (regClass == kFPReg)) {
- lowReg = oatAllocTempDouble(cUnit);
+ lowReg = AllocTempDouble(cUnit);
highReg = lowReg + 1;
res = (lowReg & 0xff) | ((highReg & 0xff) << 8);
return res;
}
#endif
- lowReg = oatAllocTemp(cUnit);
- highReg = oatAllocTemp(cUnit);
+ lowReg = AllocTemp(cUnit);
+ highReg = AllocTemp(cUnit);
res = (lowReg & 0xff) | ((highReg & 0xff) << 8);
return res;
}
-int oatAllocTypedTemp(CompilationUnit *cUnit, bool fpHint, int regClass)
+int AllocTypedTemp(CompilationUnit *cUnit, bool fpHint, int regClass)
{
#ifdef __mips_hard_float
if (((regClass == kAnyReg) && fpHint) || (regClass == kFPReg))
{
- return oatAllocTempFloat(cUnit);
+ return AllocTempFloat(cUnit);
}
#endif
- return oatAllocTemp(cUnit);
+ return AllocTemp(cUnit);
}
-void oatInitializeRegAlloc(CompilationUnit* cUnit)
+void CompilerInitializeRegAlloc(CompilationUnit* cUnit)
{
int numRegs = sizeof(coreRegs)/sizeof(*coreRegs);
- int numReserved = sizeof(reservedRegs)/sizeof(*reservedRegs);
+ int numReserved = sizeof(ReservedRegs)/sizeof(*ReservedRegs);
int numTemps = sizeof(coreTemps)/sizeof(*coreTemps);
#ifdef __mips_hard_float
- int numFPRegs = sizeof(fpRegs)/sizeof(*fpRegs);
+ int numFPRegs = sizeof(FpRegs)/sizeof(*FpRegs);
int numFPTemps = sizeof(fpTemps)/sizeof(*fpTemps);
#else
int numFPRegs = 0;
int numFPTemps = 0;
#endif
RegisterPool *pool =
- static_cast<RegisterPool*>(oatNew(cUnit, sizeof(*pool), true, kAllocRegAlloc));
+ static_cast<RegisterPool*>(NewMem(cUnit, sizeof(*pool), true, kAllocRegAlloc));
cUnit->regPool = pool;
pool->numCoreRegs = numRegs;
pool->coreRegs = static_cast<RegisterInfo*>
- (oatNew(cUnit, numRegs * sizeof(*cUnit->regPool->coreRegs), true, kAllocRegAlloc));
+ (NewMem(cUnit, numRegs * sizeof(*cUnit->regPool->coreRegs), true, kAllocRegAlloc));
pool->numFPRegs = numFPRegs;
pool->FPRegs = static_cast<RegisterInfo*>
- (oatNew(cUnit, numFPRegs * sizeof(*cUnit->regPool->FPRegs), true, kAllocRegAlloc));
- oatInitPool(pool->coreRegs, coreRegs, pool->numCoreRegs);
- oatInitPool(pool->FPRegs, fpRegs, pool->numFPRegs);
+ (NewMem(cUnit, numFPRegs * sizeof(*cUnit->regPool->FPRegs), true, kAllocRegAlloc));
+ CompilerInitPool(pool->coreRegs, coreRegs, pool->numCoreRegs);
+ CompilerInitPool(pool->FPRegs, FpRegs, pool->numFPRegs);
// Keep special registers from being allocated
for (int i = 0; i < numReserved; i++) {
- if (NO_SUSPEND && (reservedRegs[i] == rMIPS_SUSPEND)) {
+ if (NO_SUSPEND && (ReservedRegs[i] == rMIPS_SUSPEND)) {
//To measure cost of suspend check
continue;
}
- oatMarkInUse(cUnit, reservedRegs[i]);
+ MarkInUse(cUnit, ReservedRegs[i]);
}
// Mark temp regs - all others not in use can be used for promotion
for (int i = 0; i < numTemps; i++) {
- oatMarkTemp(cUnit, coreTemps[i]);
+ MarkTemp(cUnit, coreTemps[i]);
}
for (int i = 0; i < numFPTemps; i++) {
- oatMarkTemp(cUnit, fpTemps[i]);
+ MarkTemp(cUnit, fpTemps[i]);
}
// Construct the alias map.
cUnit->phiAliasMap = static_cast<int*>
- (oatNew(cUnit, cUnit->numSSARegs * sizeof(cUnit->phiAliasMap[0]), false, kAllocDFInfo));
+ (NewMem(cUnit, cUnit->numSSARegs * sizeof(cUnit->phiAliasMap[0]), false, kAllocDFInfo));
for (int i = 0; i < cUnit->numSSARegs; i++) {
cUnit->phiAliasMap[i] = i;
}
@@ -581,14 +568,14 @@
}
}
-void freeRegLocTemps(CompilationUnit* cUnit, RegLocation rlKeep,
+void FreeRegLocTemps(CompilationUnit* cUnit, RegLocation rlKeep,
RegLocation rlFree)
{
if ((rlFree.lowReg != rlKeep.lowReg) && (rlFree.lowReg != rlKeep.highReg) &&
(rlFree.highReg != rlKeep.lowReg) && (rlFree.highReg != rlKeep.highReg)) {
// No overlap, free both
- oatFreeTemp(cUnit, rlFree.lowReg);
- oatFreeTemp(cUnit, rlFree.highReg);
+ FreeTemp(cUnit, rlFree.lowReg);
+ FreeTemp(cUnit, rlFree.highReg);
}
}
/*
@@ -597,29 +584,29 @@
* ensure that all branch instructions can be restarted if
* there is a trap in the shadow. Allocate a temp register.
*/
-int loadHelper(CompilationUnit* cUnit, int offset)
+int LoadHelper(CompilationUnit* cUnit, int offset)
{
- loadWordDisp(cUnit, rMIPS_SELF, offset, r_T9);
+ LoadWordDisp(cUnit, rMIPS_SELF, offset, r_T9);
return r_T9;
}
-void spillCoreRegs(CompilationUnit* cUnit)
+void SpillCoreRegs(CompilationUnit* cUnit)
{
if (cUnit->numCoreSpills == 0) {
return;
}
uint32_t mask = cUnit->coreSpillMask;
int offset = cUnit->numCoreSpills * 4;
- opRegImm(cUnit, kOpSub, rMIPS_SP, offset);
+ OpRegImm(cUnit, kOpSub, rMIPS_SP, offset);
for (int reg = 0; mask; mask >>= 1, reg++) {
if (mask & 0x1) {
offset -= 4;
- storeWordDisp(cUnit, rMIPS_SP, offset, reg);
+ StoreWordDisp(cUnit, rMIPS_SP, offset, reg);
}
}
}
-void unSpillCoreRegs(CompilationUnit* cUnit)
+void UnSpillCoreRegs(CompilationUnit* cUnit)
{
if (cUnit->numCoreSpills == 0) {
return;
@@ -629,19 +616,19 @@
for (int reg = 0; mask; mask >>= 1, reg++) {
if (mask & 0x1) {
offset -= 4;
- loadWordDisp(cUnit, rMIPS_SP, offset, reg);
+ LoadWordDisp(cUnit, rMIPS_SP, offset, reg);
}
}
- opRegImm(cUnit, kOpAdd, rMIPS_SP, cUnit->frameSize);
+ OpRegImm(cUnit, kOpAdd, rMIPS_SP, cUnit->frameSize);
}
-bool branchUnconditional(LIR* lir)
+bool BranchUnconditional(LIR* lir)
{
return (lir->opcode == kMipsB);
}
/* Common initialization routine for an architecture family */
-bool oatArchInit()
+bool ArchInit()
{
int i;
@@ -652,20 +639,20 @@
}
}
- return oatArchVariantInit();
+ return ArchVariantInit();
}
-uint64_t getTargetInstFlags(int opcode)
+uint64_t GetTargetInstFlags(int opcode)
{
return EncodingMap[opcode].flags;
}
-const char* getTargetInstName(int opcode)
+const char* GetTargetInstName(int opcode)
{
return EncodingMap[opcode].name;
}
-const char* getTargetInstFmt(int opcode)
+const char* GetTargetInstFmt(int opcode)
{
return EncodingMap[opcode].fmt;
}
diff --git a/src/compiler/codegen/mips/utility_mips.cc b/src/compiler/codegen/mips/utility_mips.cc
index 7a018c5..011fc34 100644
--- a/src/compiler/codegen/mips/utility_mips.cc
+++ b/src/compiler/codegen/mips/utility_mips.cc
@@ -22,16 +22,16 @@
/* This file contains codegen for the MIPS32 ISA. */
-void genBarrier(CompilationUnit *cUnit);
-void loadPair(CompilationUnit *cUnit, int base, int lowReg, int highReg);
-LIR *loadWordDisp(CompilationUnit *cUnit, int rBase, int displacement,
+void GenBarrier(CompilationUnit *cUnit);
+void LoadPair(CompilationUnit *cUnit, int base, int lowReg, int highReg);
+LIR *LoadWordDisp(CompilationUnit *cUnit, int rBase, int displacement,
int rDest);
-LIR *storeWordDisp(CompilationUnit *cUnit, int rBase,
+LIR *StoreWordDisp(CompilationUnit *cUnit, int rBase,
int displacement, int rSrc);
-LIR *loadConstant(CompilationUnit *cUnit, int rDest, int value);
+LIR *LoadConstant(CompilationUnit *cUnit, int rDest, int value);
#ifdef __mips_hard_float
-LIR *fpRegCopy(CompilationUnit *cUnit, int rDest, int rSrc)
+LIR *FpRegCopy(CompilationUnit *cUnit, int rDest, int rSrc)
{
int opcode;
/* must be both DOUBLE or both not DOUBLE */
@@ -54,7 +54,7 @@
opcode = kMipsMfc1;
}
}
- LIR* res = rawLIR(cUnit, cUnit->currentDalvikOffset, opcode, rSrc, rDest);
+ LIR* res = RawLIR(cUnit, cUnit->currentDalvikOffset, opcode, rSrc, rDest);
if (!(cUnit->disableOpt & (1 << kSafeOptimizations)) && rDest == rSrc) {
res->flags.isNop = true;
}
@@ -68,10 +68,10 @@
* a high register, build constant into a low register and copy.
*
* No additional register clobbering operation performed. Use this version when
- * 1) rDest is freshly returned from oatAllocTemp or
+ * 1) rDest is freshly returned from AllocTemp or
* 2) The codegen is under fixed register usage
*/
-LIR *loadConstantNoClobber(CompilationUnit *cUnit, int rDest, int value)
+LIR *LoadConstantNoClobber(CompilationUnit *cUnit, int rDest, int value)
{
LIR *res;
@@ -80,42 +80,42 @@
int isFpReg = MIPS_FPREG(rDest);
if (isFpReg) {
DCHECK(MIPS_SINGLEREG(rDest));
- rDest = oatAllocTemp(cUnit);
+ rDest = AllocTemp(cUnit);
}
#endif
/* See if the value can be constructed cheaply */
if (value == 0) {
- res = newLIR2(cUnit, kMipsMove, rDest, r_ZERO);
+ res = NewLIR2(cUnit, kMipsMove, rDest, r_ZERO);
} else if ((value > 0) && (value <= 65535)) {
- res = newLIR3(cUnit, kMipsOri, rDest, r_ZERO, value);
+ res = NewLIR3(cUnit, kMipsOri, rDest, r_ZERO, value);
} else if ((value < 0) && (value >= -32768)) {
- res = newLIR3(cUnit, kMipsAddiu, rDest, r_ZERO, value);
+ res = NewLIR3(cUnit, kMipsAddiu, rDest, r_ZERO, value);
} else {
- res = newLIR2(cUnit, kMipsLui, rDest, value>>16);
+ res = NewLIR2(cUnit, kMipsLui, rDest, value>>16);
if (value & 0xffff)
- newLIR3(cUnit, kMipsOri, rDest, rDest, value);
+ NewLIR3(cUnit, kMipsOri, rDest, rDest, value);
}
#ifdef __mips_hard_float
if (isFpReg) {
- newLIR2(cUnit, kMipsMtc1, rDest, rDestSave);
- oatFreeTemp(cUnit, rDest);
+ NewLIR2(cUnit, kMipsMtc1, rDest, rDestSave);
+ FreeTemp(cUnit, rDest);
}
#endif
return res;
}
-LIR *opBranchUnconditional(CompilationUnit *cUnit, OpKind op)
+LIR *OpBranchUnconditional(CompilationUnit *cUnit, OpKind op)
{
DCHECK_EQ(op, kOpUncondBr);
- return newLIR1(cUnit, kMipsB, 0 /* offset to be patched */ );
+ return NewLIR1(cUnit, kMipsB, 0 /* offset to be patched */ );
}
-LIR *loadMultiple(CompilationUnit *cUnit, int rBase, int rMask);
+LIR *LoadMultiple(CompilationUnit *cUnit, int rBase, int rMask);
-LIR *opReg(CompilationUnit *cUnit, OpKind op, int rDestSrc)
+LIR *OpReg(CompilationUnit *cUnit, OpKind op, int rDestSrc)
{
MipsOpCode opcode = kMipsNop;
switch (op) {
@@ -123,17 +123,17 @@
opcode = kMipsJalr;
break;
case kOpBx:
- return newLIR1(cUnit, kMipsJr, rDestSrc);
+ return NewLIR1(cUnit, kMipsJr, rDestSrc);
break;
default:
- LOG(FATAL) << "Bad case in opReg";
+ LOG(FATAL) << "Bad case in OpReg";
}
- return newLIR2(cUnit, opcode, r_RA, rDestSrc);
+ return NewLIR2(cUnit, opcode, r_RA, rDestSrc);
}
-LIR *opRegRegImm(CompilationUnit *cUnit, OpKind op, int rDest,
+LIR *OpRegRegImm(CompilationUnit *cUnit, OpKind op, int rDest,
int rSrc1, int value);
-LIR *opRegImm(CompilationUnit *cUnit, OpKind op, int rDestSrc1,
+LIR *OpRegImm(CompilationUnit *cUnit, OpKind op, int rDestSrc1,
int value)
{
LIR *res;
@@ -143,29 +143,29 @@
MipsOpCode opcode = kMipsNop;
switch (op) {
case kOpAdd:
- return opRegRegImm(cUnit, op, rDestSrc1, rDestSrc1, value);
+ return OpRegRegImm(cUnit, op, rDestSrc1, rDestSrc1, value);
break;
case kOpSub:
- return opRegRegImm(cUnit, op, rDestSrc1, rDestSrc1, value);
+ return OpRegRegImm(cUnit, op, rDestSrc1, rDestSrc1, value);
break;
default:
- LOG(FATAL) << "Bad case in opRegImm";
+ LOG(FATAL) << "Bad case in OpRegImm";
break;
}
if (shortForm)
- res = newLIR2(cUnit, opcode, rDestSrc1, absValue);
+ res = NewLIR2(cUnit, opcode, rDestSrc1, absValue);
else {
- int rScratch = oatAllocTemp(cUnit);
- res = loadConstant(cUnit, rScratch, value);
+ int rScratch = AllocTemp(cUnit);
+ res = LoadConstant(cUnit, rScratch, value);
if (op == kOpCmp)
- newLIR2(cUnit, opcode, rDestSrc1, rScratch);
+ NewLIR2(cUnit, opcode, rDestSrc1, rScratch);
else
- newLIR3(cUnit, opcode, rDestSrc1, rDestSrc1, rScratch);
+ NewLIR3(cUnit, opcode, rDestSrc1, rDestSrc1, rScratch);
}
return res;
}
-LIR *opRegRegReg(CompilationUnit *cUnit, OpKind op, int rDest,
+LIR *OpRegRegReg(CompilationUnit *cUnit, OpKind op, int rDest,
int rSrc1, int rSrc2)
{
MipsOpCode opcode = kMipsNop;
@@ -202,13 +202,13 @@
LOG(FATAL) << "No carry bit on MIPS";
break;
default:
- LOG(FATAL) << "bad case in opRegRegReg";
+ LOG(FATAL) << "bad case in OpRegRegReg";
break;
}
- return newLIR3(cUnit, opcode, rDest, rSrc1, rSrc2);
+ return NewLIR3(cUnit, opcode, rDest, rSrc1, rSrc2);
}
-LIR *opRegRegImm(CompilationUnit *cUnit, OpKind op, int rDest,
+LIR *OpRegRegImm(CompilationUnit *cUnit, OpKind op, int rDest,
int rSrc1, int value)
{
LIR *res;
@@ -279,26 +279,26 @@
opcode = kMipsMul;
break;
default:
- LOG(FATAL) << "Bad case in opRegRegImm";
+ LOG(FATAL) << "Bad case in OpRegRegImm";
break;
}
if (shortForm)
- res = newLIR3(cUnit, opcode, rDest, rSrc1, value);
+ res = NewLIR3(cUnit, opcode, rDest, rSrc1, value);
else {
if (rDest != rSrc1) {
- res = loadConstant(cUnit, rDest, value);
- newLIR3(cUnit, opcode, rDest, rSrc1, rDest);
+ res = LoadConstant(cUnit, rDest, value);
+ NewLIR3(cUnit, opcode, rDest, rSrc1, rDest);
} else {
- int rScratch = oatAllocTemp(cUnit);
- res = loadConstant(cUnit, rScratch, value);
- newLIR3(cUnit, opcode, rDest, rSrc1, rScratch);
+ int rScratch = AllocTemp(cUnit);
+ res = LoadConstant(cUnit, rScratch, value);
+ NewLIR3(cUnit, opcode, rDest, rSrc1, rScratch);
}
}
return res;
}
-LIR *opRegReg(CompilationUnit *cUnit, OpKind op, int rDestSrc1, int rSrc2)
+LIR *OpRegReg(CompilationUnit *cUnit, OpKind op, int rDestSrc1, int rSrc2)
{
MipsOpCode opcode = kMipsNop;
LIR *res;
@@ -307,58 +307,58 @@
opcode = kMipsMove;
break;
case kOpMvn:
- return newLIR3(cUnit, kMipsNor, rDestSrc1, rSrc2, r_ZERO);
+ return NewLIR3(cUnit, kMipsNor, rDestSrc1, rSrc2, r_ZERO);
case kOpNeg:
- return newLIR3(cUnit, kMipsSubu, rDestSrc1, r_ZERO, rSrc2);
+ return NewLIR3(cUnit, kMipsSubu, rDestSrc1, r_ZERO, rSrc2);
case kOpAdd:
case kOpAnd:
case kOpMul:
case kOpOr:
case kOpSub:
case kOpXor:
- return opRegRegReg(cUnit, op, rDestSrc1, rDestSrc1, rSrc2);
+ return OpRegRegReg(cUnit, op, rDestSrc1, rDestSrc1, rSrc2);
case kOp2Byte:
#if __mips_isa_rev>=2
- res = newLIR2(cUnit, kMipsSeb, rDestSrc1, rSrc2);
+ res = NewLIR2(cUnit, kMipsSeb, rDestSrc1, rSrc2);
#else
- res = opRegRegImm(cUnit, kOpLsl, rDestSrc1, rSrc2, 24);
- opRegRegImm(cUnit, kOpAsr, rDestSrc1, rDestSrc1, 24);
+ res = OpRegRegImm(cUnit, kOpLsl, rDestSrc1, rSrc2, 24);
+ OpRegRegImm(cUnit, kOpAsr, rDestSrc1, rDestSrc1, 24);
#endif
return res;
case kOp2Short:
#if __mips_isa_rev>=2
- res = newLIR2(cUnit, kMipsSeh, rDestSrc1, rSrc2);
+ res = NewLIR2(cUnit, kMipsSeh, rDestSrc1, rSrc2);
#else
- res = opRegRegImm(cUnit, kOpLsl, rDestSrc1, rSrc2, 16);
- opRegRegImm(cUnit, kOpAsr, rDestSrc1, rDestSrc1, 16);
+ res = OpRegRegImm(cUnit, kOpLsl, rDestSrc1, rSrc2, 16);
+ OpRegRegImm(cUnit, kOpAsr, rDestSrc1, rDestSrc1, 16);
#endif
return res;
case kOp2Char:
- return newLIR3(cUnit, kMipsAndi, rDestSrc1, rSrc2, 0xFFFF);
+ return NewLIR3(cUnit, kMipsAndi, rDestSrc1, rSrc2, 0xFFFF);
default:
- LOG(FATAL) << "Bad case in opRegReg";
+ LOG(FATAL) << "Bad case in OpRegReg";
break;
}
- return newLIR2(cUnit, opcode, rDestSrc1, rSrc2);
+ return NewLIR2(cUnit, opcode, rDestSrc1, rSrc2);
}
-LIR *loadConstantValueWide(CompilationUnit *cUnit, int rDestLo,
+LIR *LoadConstantValueWide(CompilationUnit *cUnit, int rDestLo,
int rDestHi, int valLo, int valHi)
{
LIR *res;
- res = loadConstantNoClobber(cUnit, rDestLo, valLo);
- loadConstantNoClobber(cUnit, rDestHi, valHi);
+ res = LoadConstantNoClobber(cUnit, rDestLo, valLo);
+ LoadConstantNoClobber(cUnit, rDestHi, valHi);
return res;
}
/* Load value from base + scaled index. */
-LIR *loadBaseIndexed(CompilationUnit *cUnit, int rBase,
+LIR *LoadBaseIndexed(CompilationUnit *cUnit, int rBase,
int rIndex, int rDest, int scale, OpSize size)
{
LIR *first = NULL;
LIR *res;
MipsOpCode opcode = kMipsNop;
- int tReg = oatAllocTemp(cUnit);
+ int tReg = AllocTemp(cUnit);
#ifdef __mips_hard_float
if (MIPS_FPREG(rDest)) {
@@ -372,10 +372,10 @@
#endif
if (!scale) {
- first = newLIR3(cUnit, kMipsAddu, tReg , rBase, rIndex);
+ first = NewLIR3(cUnit, kMipsAddu, tReg , rBase, rIndex);
} else {
- first = opRegRegImm(cUnit, kOpLsl, tReg, rIndex, scale);
- newLIR3(cUnit, kMipsAddu, tReg , rBase, tReg);
+ first = OpRegRegImm(cUnit, kOpLsl, tReg, rIndex, scale);
+ NewLIR3(cUnit, kMipsAddu, tReg , rBase, tReg);
}
switch (size) {
@@ -400,22 +400,22 @@
opcode = kMipsLb;
break;
default:
- LOG(FATAL) << "Bad case in loadBaseIndexed";
+ LOG(FATAL) << "Bad case in LoadBaseIndexed";
}
- res = newLIR3(cUnit, opcode, rDest, 0, tReg);
- oatFreeTemp(cUnit, tReg);
+ res = NewLIR3(cUnit, opcode, rDest, 0, tReg);
+ FreeTemp(cUnit, tReg);
return (first) ? first : res;
}
/* store value base base + scaled index. */
-LIR *storeBaseIndexed(CompilationUnit *cUnit, int rBase,
+LIR *StoreBaseIndexed(CompilationUnit *cUnit, int rBase,
int rIndex, int rSrc, int scale, OpSize size)
{
LIR *first = NULL;
MipsOpCode opcode = kMipsNop;
int rNewIndex = rIndex;
- int tReg = oatAllocTemp(cUnit);
+ int tReg = AllocTemp(cUnit);
#ifdef __mips_hard_float
if (MIPS_FPREG(rSrc)) {
@@ -429,10 +429,10 @@
#endif
if (!scale) {
- first = newLIR3(cUnit, kMipsAddu, tReg , rBase, rIndex);
+ first = NewLIR3(cUnit, kMipsAddu, tReg , rBase, rIndex);
} else {
- first = opRegRegImm(cUnit, kOpLsl, tReg, rIndex, scale);
- newLIR3(cUnit, kMipsAddu, tReg , rBase, tReg);
+ first = OpRegRegImm(cUnit, kOpLsl, tReg, rIndex, scale);
+ NewLIR3(cUnit, kMipsAddu, tReg , rBase, tReg);
}
switch (size) {
@@ -453,58 +453,58 @@
opcode = kMipsSb;
break;
default:
- LOG(FATAL) << "Bad case in storeBaseIndexed";
+ LOG(FATAL) << "Bad case in StoreBaseIndexed";
}
- newLIR3(cUnit, opcode, rSrc, 0, tReg);
- oatFreeTemp(cUnit, rNewIndex);
+ NewLIR3(cUnit, opcode, rSrc, 0, tReg);
+ FreeTemp(cUnit, rNewIndex);
return first;
}
-LIR *loadMultiple(CompilationUnit *cUnit, int rBase, int rMask)
+LIR *LoadMultiple(CompilationUnit *cUnit, int rBase, int rMask)
{
int i;
int loadCnt = 0;
LIR *res = NULL ;
- genBarrier(cUnit);
+ GenBarrier(cUnit);
for (i = 0; i < 8; i++, rMask >>= 1) {
if (rMask & 0x1) { /* map r0 to MIPS r_A0 */
- newLIR3(cUnit, kMipsLw, i+r_A0, loadCnt*4, rBase);
+ NewLIR3(cUnit, kMipsLw, i+r_A0, loadCnt*4, rBase);
loadCnt++;
}
}
if (loadCnt) {/* increment after */
- newLIR3(cUnit, kMipsAddiu, rBase, rBase, loadCnt*4);
+ NewLIR3(cUnit, kMipsAddiu, rBase, rBase, loadCnt*4);
}
- genBarrier(cUnit);
+ GenBarrier(cUnit);
return res; /* NULL always returned which should be ok since no callers use it */
}
-LIR *storeMultiple(CompilationUnit *cUnit, int rBase, int rMask)
+LIR *StoreMultiple(CompilationUnit *cUnit, int rBase, int rMask)
{
int i;
int storeCnt = 0;
LIR *res = NULL ;
- genBarrier(cUnit);
+ GenBarrier(cUnit);
for (i = 0; i < 8; i++, rMask >>= 1) {
if (rMask & 0x1) { /* map r0 to MIPS r_A0 */
- newLIR3(cUnit, kMipsSw, i+r_A0, storeCnt*4, rBase);
+ NewLIR3(cUnit, kMipsSw, i+r_A0, storeCnt*4, rBase);
storeCnt++;
}
}
if (storeCnt) { /* increment after */
- newLIR3(cUnit, kMipsAddiu, rBase, rBase, storeCnt*4);
+ NewLIR3(cUnit, kMipsAddiu, rBase, rBase, storeCnt*4);
}
- genBarrier(cUnit);
+ GenBarrier(cUnit);
return res; /* NULL always returned which should be ok since no callers use it */
}
-LIR *loadBaseDispBody(CompilationUnit *cUnit, int rBase,
+LIR *LoadBaseDispBody(CompilationUnit *cUnit, int rBase,
int displacement, int rDest, int rDestHi,
OpSize size, int sReg)
/*
@@ -569,61 +569,61 @@
opcode = kMipsLb;
break;
default:
- LOG(FATAL) << "Bad case in loadBaseIndexedBody";
+ LOG(FATAL) << "Bad case in LoadBaseIndexedBody";
}
if (shortForm) {
if (!pair) {
- load = res = newLIR3(cUnit, opcode, rDest, displacement, rBase);
+ load = res = NewLIR3(cUnit, opcode, rDest, displacement, rBase);
} else {
- load = res = newLIR3(cUnit, opcode, rDest,
+ load = res = NewLIR3(cUnit, opcode, rDest,
displacement + LOWORD_OFFSET, rBase);
- load2 = newLIR3(cUnit, opcode, rDestHi,
+ load2 = NewLIR3(cUnit, opcode, rDestHi,
displacement + HIWORD_OFFSET, rBase);
}
} else {
if (pair) {
- int rTmp = oatAllocFreeTemp(cUnit);
- res = opRegRegImm(cUnit, kOpAdd, rTmp, rBase, displacement);
- load = newLIR3(cUnit, opcode, rDest, LOWORD_OFFSET, rTmp);
- load2 = newLIR3(cUnit, opcode, rDestHi, HIWORD_OFFSET, rTmp);
- oatFreeTemp(cUnit, rTmp);
+ int rTmp = AllocFreeTemp(cUnit);
+ res = OpRegRegImm(cUnit, kOpAdd, rTmp, rBase, displacement);
+ load = NewLIR3(cUnit, opcode, rDest, LOWORD_OFFSET, rTmp);
+ load2 = NewLIR3(cUnit, opcode, rDestHi, HIWORD_OFFSET, rTmp);
+ FreeTemp(cUnit, rTmp);
} else {
- int rTmp = (rBase == rDest) ? oatAllocFreeTemp(cUnit) : rDest;
- res = opRegRegImm(cUnit, kOpAdd, rTmp, rBase, displacement);
- load = newLIR3(cUnit, opcode, rDest, 0, rTmp);
+ int rTmp = (rBase == rDest) ? AllocFreeTemp(cUnit) : rDest;
+ res = OpRegRegImm(cUnit, kOpAdd, rTmp, rBase, displacement);
+ load = NewLIR3(cUnit, opcode, rDest, 0, rTmp);
if (rTmp != rDest)
- oatFreeTemp(cUnit, rTmp);
+ FreeTemp(cUnit, rTmp);
}
}
if (rBase == rMIPS_SP) {
- annotateDalvikRegAccess(load,
+ AnnotateDalvikRegAccess(load,
(displacement + (pair ? LOWORD_OFFSET : 0)) >> 2,
true /* isLoad */, pair /* is64bit */);
if (pair) {
- annotateDalvikRegAccess(load2, (displacement + HIWORD_OFFSET) >> 2,
+ AnnotateDalvikRegAccess(load2, (displacement + HIWORD_OFFSET) >> 2,
true /* isLoad */, pair /* is64bit */);
}
}
return load;
}
-LIR *loadBaseDisp(CompilationUnit *cUnit, int rBase,
+LIR *LoadBaseDisp(CompilationUnit *cUnit, int rBase,
int displacement, int rDest, OpSize size, int sReg)
{
- return loadBaseDispBody(cUnit, rBase, displacement, rDest, -1,
+ return LoadBaseDispBody(cUnit, rBase, displacement, rDest, -1,
size, sReg);
}
-LIR *loadBaseDispWide(CompilationUnit *cUnit, int rBase,
+LIR *LoadBaseDispWide(CompilationUnit *cUnit, int rBase,
int displacement, int rDestLo, int rDestHi, int sReg)
{
- return loadBaseDispBody(cUnit, rBase, displacement, rDestLo, rDestHi,
+ return LoadBaseDispBody(cUnit, rBase, displacement, rDestLo, rDestHi,
kLong, sReg);
}
-LIR *storeBaseDispBody(CompilationUnit *cUnit, int rBase,
+LIR *StoreBaseDispBody(CompilationUnit *cUnit, int rBase,
int displacement, int rSrc, int rSrcHi, OpSize size)
{
LIR *res;
@@ -674,35 +674,35 @@
opcode = kMipsSb;
break;
default:
- LOG(FATAL) << "Bad case in storeBaseIndexedBody";
+ LOG(FATAL) << "Bad case in StoreBaseIndexedBody";
}
if (shortForm) {
if (!pair) {
- store = res = newLIR3(cUnit, opcode, rSrc, displacement, rBase);
+ store = res = NewLIR3(cUnit, opcode, rSrc, displacement, rBase);
} else {
- store = res = newLIR3(cUnit, opcode, rSrc, displacement + LOWORD_OFFSET,
+ store = res = NewLIR3(cUnit, opcode, rSrc, displacement + LOWORD_OFFSET,
rBase);
- store2 = newLIR3(cUnit, opcode, rSrcHi, displacement + HIWORD_OFFSET,
+ store2 = NewLIR3(cUnit, opcode, rSrcHi, displacement + HIWORD_OFFSET,
rBase);
}
} else {
- int rScratch = oatAllocTemp(cUnit);
- res = opRegRegImm(cUnit, kOpAdd, rScratch, rBase, displacement);
+ int rScratch = AllocTemp(cUnit);
+ res = OpRegRegImm(cUnit, kOpAdd, rScratch, rBase, displacement);
if (!pair) {
- store = newLIR3(cUnit, opcode, rSrc, 0, rScratch);
+ store = NewLIR3(cUnit, opcode, rSrc, 0, rScratch);
} else {
- store = newLIR3(cUnit, opcode, rSrc, LOWORD_OFFSET, rScratch);
- store2 = newLIR3(cUnit, opcode, rSrcHi, HIWORD_OFFSET, rScratch);
+ store = NewLIR3(cUnit, opcode, rSrc, LOWORD_OFFSET, rScratch);
+ store2 = NewLIR3(cUnit, opcode, rSrcHi, HIWORD_OFFSET, rScratch);
}
- oatFreeTemp(cUnit, rScratch);
+ FreeTemp(cUnit, rScratch);
}
if (rBase == rMIPS_SP) {
- annotateDalvikRegAccess(store, (displacement + (pair ? LOWORD_OFFSET : 0))
+ AnnotateDalvikRegAccess(store, (displacement + (pair ? LOWORD_OFFSET : 0))
>> 2, false /* isLoad */, pair /* is64bit */);
if (pair) {
- annotateDalvikRegAccess(store2, (displacement + HIWORD_OFFSET) >> 2,
+ AnnotateDalvikRegAccess(store2, (displacement + HIWORD_OFFSET) >> 2,
false /* isLoad */, pair /* is64bit */);
}
}
@@ -710,64 +710,64 @@
return res;
}
-LIR *storeBaseDisp(CompilationUnit *cUnit, int rBase,
+LIR *StoreBaseDisp(CompilationUnit *cUnit, int rBase,
int displacement, int rSrc, OpSize size)
{
- return storeBaseDispBody(cUnit, rBase, displacement, rSrc, -1, size);
+ return StoreBaseDispBody(cUnit, rBase, displacement, rSrc, -1, size);
}
-LIR *storeBaseDispWide(CompilationUnit *cUnit, int rBase,
+LIR *StoreBaseDispWide(CompilationUnit *cUnit, int rBase,
int displacement, int rSrcLo, int rSrcHi)
{
- return storeBaseDispBody(cUnit, rBase, displacement, rSrcLo, rSrcHi, kLong);
+ return StoreBaseDispBody(cUnit, rBase, displacement, rSrcLo, rSrcHi, kLong);
}
-void loadPair(CompilationUnit *cUnit, int base, int lowReg, int highReg)
+void LoadPair(CompilationUnit *cUnit, int base, int lowReg, int highReg)
{
- loadWordDisp(cUnit, base, LOWORD_OFFSET , lowReg);
- loadWordDisp(cUnit, base, HIWORD_OFFSET , highReg);
+ LoadWordDisp(cUnit, base, LOWORD_OFFSET , lowReg);
+ LoadWordDisp(cUnit, base, HIWORD_OFFSET , highReg);
}
-LIR* opThreadMem(CompilationUnit* cUnit, OpKind op, int threadOffset)
+LIR* OpThreadMem(CompilationUnit* cUnit, OpKind op, int threadOffset)
{
- LOG(FATAL) << "Unexpected use of opThreadMem for MIPS";
+ LOG(FATAL) << "Unexpected use of OpThreadMem for MIPS";
return NULL;
}
-LIR* opMem(CompilationUnit* cUnit, OpKind op, int rBase, int disp)
+LIR* OpMem(CompilationUnit* cUnit, OpKind op, int rBase, int disp)
{
- LOG(FATAL) << "Unexpected use of opMem for MIPS";
+ LOG(FATAL) << "Unexpected use of OpMem for MIPS";
return NULL;
}
-LIR* storeBaseIndexedDisp(CompilationUnit *cUnit,
+LIR* StoreBaseIndexedDisp(CompilationUnit *cUnit,
int rBase, int rIndex, int scale, int displacement,
int rSrc, int rSrcHi,
OpSize size, int sReg)
{
- LOG(FATAL) << "Unexpected use of storeBaseIndexedDisp for MIPS";
+ LOG(FATAL) << "Unexpected use of StoreBaseIndexedDisp for MIPS";
return NULL;
}
-LIR* opRegMem(CompilationUnit *cUnit, OpKind op, int rDest, int rBase,
+LIR* OpRegMem(CompilationUnit *cUnit, OpKind op, int rDest, int rBase,
int offset)
{
- LOG(FATAL) << "Unexpected use of opRegMem for MIPS";
+ LOG(FATAL) << "Unexpected use of OpRegMem for MIPS";
return NULL;
}
-LIR* loadBaseIndexedDisp(CompilationUnit *cUnit,
+LIR* LoadBaseIndexedDisp(CompilationUnit *cUnit,
int rBase, int rIndex, int scale, int displacement,
int rDest, int rDestHi,
OpSize size, int sReg)
{
- LOG(FATAL) << "Unexpected use of loadBaseIndexedDisp for MIPS";
+ LOG(FATAL) << "Unexpected use of LoadBaseIndexedDisp for MIPS";
return NULL;
}
-LIR* opCondBranch(CompilationUnit* cUnit, ConditionCode cc, LIR* target)
+LIR* OpCondBranch(CompilationUnit* cUnit, ConditionCode cc, LIR* target)
{
- LOG(FATAL) << "Unexpected use of opCondBranch for MIPS";
+ LOG(FATAL) << "Unexpected use of OpCondBranch for MIPS";
return NULL;
}